src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /**
  24  * @file iris_screen.c
  25  *
  26  * Screen related driver hooks and capability lists.
  27  *
  28  * A program may use multiple rendering contexts (iris_context), but
  29  * they all share a common screen (iris_screen).  Global driver state
  30  * can be stored in the screen; it may be accessed by multiple threads.
  31  */
  32
  33 #include <stdio.h>
  34 #include <errno.h>
  35 #include <sys/ioctl.h>
  36 #include "pipe/p_defines.h"
  37 #include "pipe/p_state.h"
  38 #include "pipe/p_context.h"
  39 #include "pipe/p_screen.h"
  40 #include "util/debug.h"
  41 #include "util/u_inlines.h"
  42 #include "util/u_format.h"
  43 #include "util/u_transfer_helper.h"
  44 #include "util/u_upload_mgr.h"
  45 #include "util/ralloc.h"
  46 #include "util/xmlconfig.h"
  47 #include "drm-uapi/i915_drm.h"
  48 #include "iris_context.h"
  49 #include "iris_defines.h"
  50 #include "iris_fence.h"
  51 #include "iris_pipe.h"
  52 #include "iris_resource.h"
  53 #include "iris_screen.h"
  54 #include "intel/compiler/brw_compiler.h"
  55
  56 static void
  57 iris_flush_frontbuffer(struct pipe_screen *_screen,
  58                        struct pipe_resource *resource,
  59                        unsigned level, unsigned layer,
  60                        void *context_private, struct pipe_box *box)
  61 {
  62 }
  63
  64 static const char *
  65 iris_get_vendor(struct pipe_screen *pscreen)
  66 {
  67    return "Intel";
  68 }
  69
  70 static const char *
  71 iris_get_device_vendor(struct pipe_screen *pscreen)
  72 {
  73    return "Intel";
  74 }
  75
  76 static const char *
  77 iris_get_name(struct pipe_screen *pscreen)
  78 {
  79    struct iris_screen *screen = (struct iris_screen *)pscreen;
  80    static char buf[128];
  81    const char *chipset;
  82
  83    switch (screen->pci_id) {
  84 #undef CHIPSET
  85 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
  86 #include "pci_ids/i965_pci_ids.h"
  87    default:
  88       chipset = "Unknown Intel Chipset";
  89       break;
  90    }
  91
  92    snprintf(buf, sizeof(buf), "Mesa %s", chipset);
  93    return buf;
  94 }
  95
  96 static int
  97 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  98 {
  99    struct iris_screen *screen = (struct iris_screen *)pscreen;
 100    const struct gen_device_info *devinfo = &screen->devinfo;
 101
 102    switch (param) {
 103    case PIPE_CAP_NPOT_TEXTURES:
 104    case PIPE_CAP_ANISOTROPIC_FILTER:
 105    case PIPE_CAP_POINT_SPRITE:
 106    case PIPE_CAP_OCCLUSION_QUERY:
 107    case PIPE_CAP_QUERY_TIME_ELAPSED:
 108    case PIPE_CAP_TEXTURE_SWIZZLE:
 109    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 110    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 111    case PIPE_CAP_SM3:
 112    case PIPE_CAP_PRIMITIVE_RESTART:
 113    case PIPE_CAP_INDEP_BLEND_ENABLE:
 114    case PIPE_CAP_INDEP_BLEND_FUNC:
 115    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 116    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 117    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 118    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 119    case PIPE_CAP_TGSI_INSTANCEID:
 120    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 121    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 122    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 123    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 124    case PIPE_CAP_CONDITIONAL_RENDER:
 125    case PIPE_CAP_TEXTURE_BARRIER:
 126    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 127    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 128    case PIPE_CAP_COMPUTE:
 129    case PIPE_CAP_START_INSTANCE:
 130    case PIPE_CAP_QUERY_TIMESTAMP:
 131    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 132    case PIPE_CAP_CUBE_MAP_ARRAY:
 133    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 134    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 135    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 136    case PIPE_CAP_TEXTURE_QUERY_LOD:
 137    case PIPE_CAP_SAMPLE_SHADING:
 138    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 139    case PIPE_CAP_DRAW_INDIRECT:
 140    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 141    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 142    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 143    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 144    case PIPE_CAP_ACCELERATED:
 145    case PIPE_CAP_UMA:
 146    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 147    case PIPE_CAP_CLIP_HALFZ:
 148    case PIPE_CAP_TGSI_TEXCOORD:
 149    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 150    case PIPE_CAP_DOUBLES:
 151    case PIPE_CAP_INT64:
 152    case PIPE_CAP_INT64_DIVMOD:
 153    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 154    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 155    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 156    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 157    case PIPE_CAP_CULL_DISTANCE:
 158    case PIPE_CAP_PACKED_UNIFORMS:
 159    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 160    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 161    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 162    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 163    case PIPE_CAP_QUERY_SO_OVERFLOW:
 164    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 165    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 166    case PIPE_CAP_TGSI_TXQS:
 167    case PIPE_CAP_TGSI_CLOCK:
 168    case PIPE_CAP_TGSI_BALLOT:
 169    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 170    case PIPE_CAP_CLEAR_TEXTURE:
 171    case PIPE_CAP_TGSI_VOTE:
 172    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 173    case PIPE_CAP_TEXTURE_GATHER_SM5:
 174    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 175    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 176    case PIPE_CAP_LOAD_CONSTBUF:
 177    case PIPE_CAP_NIR_COMPACT_ARRAYS:
 178    case PIPE_CAP_DRAW_PARAMETERS:
 179    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 180    case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
 181    case PIPE_CAP_INVALIDATE_BUFFER:
 182       return true;
 183    case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
 184    case PIPE_CAP_TGSI_FS_FBFETCH:
 185    case PIPE_CAP_POST_DEPTH_COVERAGE:
 186    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 187       return devinfo->gen >= 9;
 188    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 189       return 1;
 190    case PIPE_CAP_MAX_RENDER_TARGETS:
 191       return BRW_MAX_DRAW_BUFFERS;
 192    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 193    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 194       return IRIS_MAX_MIPLEVELS; /* 16384x16384 */
 195    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 196       return 12; /* 2048x2048 */
 197    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 198       return 4;
 199    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 200       return 2048;
 201    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 202       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 203    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 204       return BRW_MAX_SOL_BINDINGS;
 205    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 206       return 460;
 207    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 208       return 140;
 209    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 210       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 211       return 32;
 212    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 213       return IRIS_MAP_BUFFER_ALIGNMENT;
 214    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 215       /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
 216        * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
 217        * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
 218        * GPU and the CPU can be updating disjoint regions of the buffer
 219        * simultaneously and that will break if the regions overlap the same
 220        * cacheline.
 221        */
 222       return 64;
 223    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 224       return 1 << 27;
 225    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 226       return 16; // XXX: u_screen says 256 is the minimum value...
 227    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 228       return true; // XXX: ?????
 229    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 230       return IRIS_MAX_TEXTURE_BUFFER_SIZE;
 231    case PIPE_CAP_MAX_VIEWPORTS:
 232       return 16;
 233    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 234       return 256;
 235    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 236       return 1024;
 237    case PIPE_CAP_MAX_GS_INVOCATIONS:
 238       return 32;
 239    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 240       return 4;
 241    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 242       return -32;
 243    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 244       return 31;
 245    case PIPE_CAP_MAX_VERTEX_STREAMS:
 246       return 4;
 247    case PIPE_CAP_VENDOR_ID:
 248       return 0x8086;
 249    case PIPE_CAP_DEVICE_ID:
 250       return screen->pci_id;
 251    case PIPE_CAP_VIDEO_MEMORY:
 252       return INT_MAX; // XXX: bogus
 253    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 254    case PIPE_CAP_MAX_VARYINGS:
 255       return 32;
 256    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 257       /* AMD_pinned_memory assumes the flexibility of using client memory
 258        * for any buffer (incl. vertex buffers) which rules out the prospect
 259        * of using snooped buffers, as using snooped buffers without
 260        * cogniscience is likely to be detrimental to performance and require
 261        * extensive checking in the driver for correctness, e.g. to prevent
 262        * illegal snoop <-> snoop transfers.
 263        */
 264       return devinfo->has_llc;
 265
 266    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 267       return PIPE_CONTEXT_PRIORITY_LOW |
 268              PIPE_CONTEXT_PRIORITY_MEDIUM |
 269              PIPE_CONTEXT_PRIORITY_HIGH;
 270
 271    // XXX: don't hardcode 00:00:02.0 PCI here
 272    case PIPE_CAP_PCI_GROUP:
 273       return 0;
 274    case PIPE_CAP_PCI_BUS:
 275       return 0;
 276    case PIPE_CAP_PCI_DEVICE:
 277       return 2;
 278    case PIPE_CAP_PCI_FUNCTION:
 279       return 0;
 280
 281    default:
 282       return u_pipe_screen_get_param_defaults(pscreen, param);
 283    }
 284    return 0;
 285 }
 286
 287 static float
 288 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 289 {
 290    switch (param) {
 291    case PIPE_CAPF_MAX_LINE_WIDTH:
 292    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 293       return 7.375f;
 294
 295    case PIPE_CAPF_MAX_POINT_WIDTH:
 296    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 297       return 255.0f;
 298
 299    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 300       return 16.0f;
 301    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 302       return 15.0f;
 303    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 304    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 305    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 306       return 0.0f;
 307    default:
 308       unreachable("unknown param");
 309    }
 310 }
 311
 312 static int
 313 iris_get_shader_param(struct pipe_screen *pscreen,
 314                       enum pipe_shader_type p_stage,
 315                       enum pipe_shader_cap param)
 316 {
 317    gl_shader_stage stage = stage_from_pipe(p_stage);
 318
 319    /* this is probably not totally correct.. but it's a start: */
 320    switch (param) {
 321    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 322       return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
 323    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 324    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 325    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 326       return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
 327
 328    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 329       return UINT_MAX;
 330
 331    case PIPE_SHADER_CAP_MAX_INPUTS:
 332       return stage == MESA_SHADER_VERTEX ? 16 : 32;
 333    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 334       return 32;
 335    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 336       return 16 * 1024 * sizeof(float);
 337    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 338       return 16;
 339    case PIPE_SHADER_CAP_MAX_TEMPS:
 340       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 341    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 342       return 0;
 343    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 344    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 345    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 346    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 347       /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
 348        * which we don't want.  Our compiler backend will check brw_compiler's
 349        * options and call nir_lower_indirect_derefs appropriately anyway.
 350        */
 351       return true;
 352    case PIPE_SHADER_CAP_SUBROUTINES:
 353       return 0;
 354    case PIPE_SHADER_CAP_INTEGERS:
 355    case PIPE_SHADER_CAP_SCALAR_ISA:
 356       return 1;
 357    case PIPE_SHADER_CAP_INT64_ATOMICS:
 358    case PIPE_SHADER_CAP_FP16:
 359       return 0;
 360    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 361    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 362    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 363       return IRIS_MAX_TEXTURE_SAMPLERS;
 364    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 365       return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
 366    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 367    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 368       return 0;
 369    case PIPE_SHADER_CAP_PREFERRED_IR:
 370       return PIPE_SHADER_IR_NIR;
 371    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 372       return 1 << PIPE_SHADER_IR_NIR;
 373    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 374       return 32;
 375    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 376    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 377    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 378    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 379    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 380    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 381    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 382    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 383       return 0;
 384    default:
 385       unreachable("unknown shader param");
 386    }
 387 }
 388
 389 static int
 390 iris_get_compute_param(struct pipe_screen *pscreen,
 391                        enum pipe_shader_ir ir_type,
 392                        enum pipe_compute_cap param,
 393                        void *ret)
 394 {
 395    struct iris_screen *screen = (struct iris_screen *)pscreen;
 396    const struct gen_device_info *devinfo = &screen->devinfo;
 397
 398    const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
 399    const uint32_t max_invocations = 32 * max_threads;
 400
 401 #define RET(x) do {                  \
 402    if (ret)                          \
 403       memcpy(ret, x, sizeof(x));     \
 404    return sizeof(x);                 \
 405 } while (0)
 406
 407    switch (param) {
 408    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 409       RET((uint32_t []){ 32 });
 410
 411    case PIPE_COMPUTE_CAP_IR_TARGET:
 412       if (ret)
 413          strcpy(ret, "gen");
 414       return 4;
 415
 416    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 417       RET((uint64_t []) { 3 });
 418
 419    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 420       RET(((uint64_t []) { 65535, 65535, 65535 }));
 421
 422    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 423       /* MaxComputeWorkGroupSize[0..2] */
 424       RET(((uint64_t []) {max_invocations, max_invocations, max_invocations}));
 425
 426    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 427       /* MaxComputeWorkGroupInvocations */
 428       RET((uint64_t []) { max_invocations });
 429
 430    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 431       /* MaxComputeSharedMemorySize */
 432       RET((uint64_t []) { 64 * 1024 });
 433
 434    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 435       RET((uint32_t []) { 1 });
 436
 437    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 438       RET((uint32_t []) { BRW_SUBGROUP_SIZE });
 439
 440    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 441    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 442    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 443    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 444    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 445    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 446    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 447       // XXX: I think these are for Clover...
 448       return 0;
 449
 450    default:
 451       unreachable("unknown compute param");
 452    }
 453 }
 454
 455 static uint64_t
 456 iris_get_timestamp(struct pipe_screen *pscreen)
 457 {
 458    struct iris_screen *screen = (struct iris_screen *) pscreen;
 459    const unsigned TIMESTAMP = 0x2358;
 460    uint64_t result;
 461
 462    iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
 463
 464    result = iris_timebase_scale(&screen->devinfo, result);
 465    result &= (1ull << TIMESTAMP_BITS) - 1;
 466
 467    return result;
 468 }
 469
 470 static void
 471 iris_destroy_screen(struct pipe_screen *pscreen)
 472 {
 473    struct iris_screen *screen = (struct iris_screen *) pscreen;
 474    iris_bo_unreference(screen->workaround_bo);
 475    u_transfer_helper_destroy(pscreen->transfer_helper);
 476    iris_bufmgr_destroy(screen->bufmgr);
 477    ralloc_free(screen);
 478 }
 479
 480 static void
 481 iris_query_memory_info(struct pipe_screen *pscreen,
 482                        struct pipe_memory_info *info)
 483 {
 484 }
 485
 486 static const void *
 487 iris_get_compiler_options(struct pipe_screen *pscreen,
 488                           enum pipe_shader_ir ir,
 489                           enum pipe_shader_type pstage)
 490 {
 491    struct iris_screen *screen = (struct iris_screen *) pscreen;
 492    gl_shader_stage stage = stage_from_pipe(pstage);
 493    assert(ir == PIPE_SHADER_IR_NIR);
 494
 495    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 496 }
 497
 498 static int
 499 iris_getparam(struct iris_screen *screen, int param, int *value)
 500 {
 501    struct drm_i915_getparam gp = { .param = param, .value = value };
 502
 503    if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 504       return -errno;
 505
 506    return 0;
 507 }
 508
 509 static int
 510 iris_getparam_integer(struct iris_screen *screen, int param)
 511 {
 512    int value = -1;
 513
 514    if (iris_getparam(screen, param, &value) == 0)
 515       return value;
 516
 517    return -1;
 518 }
 519
 520 static void
 521 iris_shader_debug_log(void *data, const char *fmt, ...)
 522 {
 523    struct pipe_debug_callback *dbg = data;
 524    unsigned id = 0;
 525    va_list args;
 526
 527    if (!dbg->debug_message)
 528       return;
 529
 530    va_start(args, fmt);
 531    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
 532    va_end(args);
 533 }
 534
 535 static void
 536 iris_shader_perf_log(void *data, const char *fmt, ...)
 537 {
 538    struct pipe_debug_callback *dbg = data;
 539    unsigned id = 0;
 540    va_list args;
 541    va_start(args, fmt);
 542
 543    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
 544       va_list args_copy;
 545       va_copy(args_copy, args);
 546       vfprintf(stderr, fmt, args_copy);
 547       va_end(args_copy);
 548    }
 549
 550    if (dbg->debug_message) {
 551       dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
 552    }
 553
 554    va_end(args);
 555 }
 556
 557 struct pipe_screen *
 558 iris_screen_create(int fd, const struct pipe_screen_config *config)
 559 {
 560    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 561    if (!screen)
 562       return NULL;
 563
 564    screen->fd = fd;
 565    screen->pci_id = iris_getparam_integer(screen, I915_PARAM_CHIPSET_ID);
 566
 567    if (!gen_get_device_info(screen->pci_id, &screen->devinfo))
 568       return NULL;
 569
 570    if (screen->devinfo.gen < 8 || screen->devinfo.is_cherryview)
 571       return NULL;
 572
 573    screen->devinfo.timestamp_frequency =
 574       iris_getparam_integer(screen, I915_PARAM_CS_TIMESTAMP_FREQUENCY);
 575
 576    if (getenv("INTEL_NO_HW") != NULL)
 577       screen->no_hw = true;
 578
 579    screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
 580    if (!screen->bufmgr)
 581       return NULL;
 582
 583    screen->workaround_bo =
 584       iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
 585    if (!screen->workaround_bo)
 586       return NULL;
 587
 588    brw_process_intel_debug_variable();
 589
 590    screen->driconf.dual_color_blend_by_location =
 591       driQueryOptionb(config->options, "dual_color_blend_by_location");
 592
 593    screen->precompile = env_var_as_boolean("shader_precompile", true);
 594
 595    isl_device_init(&screen->isl_dev, &screen->devinfo, false);
 596
 597    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 598    screen->compiler->shader_debug_log = iris_shader_debug_log;
 599    screen->compiler->shader_perf_log = iris_shader_perf_log;
 600    screen->compiler->supports_pull_constants = false;
 601
 602    slab_create_parent(&screen->transfer_pool,
 603                       sizeof(struct iris_transfer), 64);
 604
 605    screen->subslice_total =
 606       iris_getparam_integer(screen, I915_PARAM_SUBSLICE_TOTAL);
 607    assert(screen->subslice_total >= 1);
 608
 609    struct pipe_screen *pscreen = &screen->base;
 610
 611    iris_init_screen_fence_functions(pscreen);
 612    iris_init_screen_resource_functions(pscreen);
 613
 614    pscreen->destroy = iris_destroy_screen;
 615    pscreen->get_name = iris_get_name;
 616    pscreen->get_vendor = iris_get_vendor;
 617    pscreen->get_device_vendor = iris_get_device_vendor;
 618    pscreen->get_param = iris_get_param;
 619    pscreen->get_shader_param = iris_get_shader_param;
 620    pscreen->get_compute_param = iris_get_compute_param;
 621    pscreen->get_paramf = iris_get_paramf;
 622    pscreen->get_compiler_options = iris_get_compiler_options;
 623    pscreen->is_format_supported = iris_is_format_supported;
 624    pscreen->context_create = iris_create_context;
 625    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 626    pscreen->get_timestamp = iris_get_timestamp;
 627    pscreen->query_memory_info = iris_query_memory_info;
 628
 629    return pscreen;
 630 }