src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /**
  24  * @file iris_screen.c
  25  *
  26  * Screen related driver hooks and capability lists.
  27  *
  28  * A program may use multiple rendering contexts (iris_context), but
  29  * they all share a common screen (iris_screen).  Global driver state
  30  * can be stored in the screen; it may be accessed by multiple threads.
  31  */
  32
  33 #include <stdio.h>
  34 #include <errno.h>
  35 #include <sys/ioctl.h>
  36 #include "pipe/p_defines.h"
  37 #include "pipe/p_state.h"
  38 #include "pipe/p_context.h"
  39 #include "pipe/p_screen.h"
  40 #include "util/u_inlines.h"
  41 #include "util/u_format.h"
  42 #include "util/u_upload_mgr.h"
  43 #include "util/ralloc.h"
  44 #include "drm-uapi/i915_drm.h"
  45 #include "iris_context.h"
  46 #include "iris_pipe.h"
  47 #include "iris_resource.h"
  48 #include "iris_screen.h"
  49 #include "intel/compiler/brw_compiler.h"
  50
  51 static void
  52 iris_flush_frontbuffer(struct pipe_screen *_screen,
  53                        struct pipe_resource *resource,
  54                        unsigned level, unsigned layer,
  55                        void *context_private, struct pipe_box *box)
  56 {
  57 }
  58
  59 static const char *
  60 iris_get_vendor(struct pipe_screen *pscreen)
  61 {
  62    return "Mesa Project";
  63 }
  64
  65 static const char *
  66 iris_get_device_vendor(struct pipe_screen *pscreen)
  67 {
  68    return "Intel";
  69 }
  70
  71 static const char *
  72 iris_get_name(struct pipe_screen *pscreen)
  73 {
  74    struct iris_screen *screen = (struct iris_screen *)pscreen;
  75    const char *chipset;
  76
  77    switch (screen->pci_id) {
  78 #undef CHIPSET
  79 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
  80 #include "pci_ids/i965_pci_ids.h"
  81    default:
  82       chipset = "Unknown Intel Chipset";
  83       break;
  84    }
  85    return &chipset[9];
  86 }
  87
  88 static int
  89 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  90 {
  91    struct iris_screen *screen = (struct iris_screen *)pscreen;
  92    const struct gen_device_info *devinfo = &screen->devinfo;
  93
  94    switch (param) {
  95    case PIPE_CAP_NPOT_TEXTURES:
  96    case PIPE_CAP_ANISOTROPIC_FILTER:
  97    case PIPE_CAP_POINT_SPRITE:
  98    case PIPE_CAP_OCCLUSION_QUERY:
  99    case PIPE_CAP_QUERY_TIME_ELAPSED:
 100    case PIPE_CAP_TEXTURE_SWIZZLE:
 101    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 102    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 103    case PIPE_CAP_SM3:
 104    case PIPE_CAP_PRIMITIVE_RESTART:
 105    case PIPE_CAP_INDEP_BLEND_ENABLE:
 106    case PIPE_CAP_INDEP_BLEND_FUNC:
 107    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 108    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 109    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 110    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 111    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 112    case PIPE_CAP_TGSI_INSTANCEID:
 113    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 114    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 115    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 116    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 117    case PIPE_CAP_CONDITIONAL_RENDER:
 118    case PIPE_CAP_TEXTURE_BARRIER:
 119    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 120    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 121    case PIPE_CAP_COMPUTE:
 122    case PIPE_CAP_START_INSTANCE:
 123    case PIPE_CAP_QUERY_TIMESTAMP:
 124    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 125    case PIPE_CAP_CUBE_MAP_ARRAY:
 126    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 127    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 128    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 129    case PIPE_CAP_TEXTURE_QUERY_LOD:
 130    case PIPE_CAP_SAMPLE_SHADING:
 131    case PIPE_CAP_DRAW_INDIRECT:
 132    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 133    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 134    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 135    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 136    case PIPE_CAP_ACCELERATED:
 137    case PIPE_CAP_UMA:
 138    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 139    case PIPE_CAP_CLIP_HALFZ:
 140    case PIPE_CAP_TGSI_TEXCOORD:
 141    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 142    case PIPE_CAP_DOUBLES:
 143    case PIPE_CAP_INT64:
 144    case PIPE_CAP_INT64_DIVMOD:
 145    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 146    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 147    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 148    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 149    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 150    case PIPE_CAP_CULL_DISTANCE:
 151    case PIPE_CAP_PACKED_UNIFORMS:
 152    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 153    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 154    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 155    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 156    case PIPE_CAP_POST_DEPTH_COVERAGE:
 157    case PIPE_CAP_QUERY_SO_OVERFLOW:
 158    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 159    case PIPE_CAP_TGSI_CLOCK:
 160    case PIPE_CAP_TGSI_BALLOT:
 161    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 162    case PIPE_CAP_CLEAR_TEXTURE:
 163    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 164    case PIPE_CAP_TEXTURE_GATHER_SM5:
 165    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 166       return true;
 167
 168    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 169       return 1;
 170    case PIPE_CAP_MAX_RENDER_TARGETS:
 171       return BRW_MAX_DRAW_BUFFERS;
 172    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 173    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 174       return 15; /* 16384x16384 */
 175    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 176       return 12; /* 2048x2048 */
 177    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 178       return 4;
 179    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 180       return 2048;
 181    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 182       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 183    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 184       return BRW_MAX_SOL_BINDINGS;
 185    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 186       return 460;
 187    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 188       return 140;
 189    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 190       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 191       return 32;
 192    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 193       /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
 194        * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
 195        * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
 196        * GPU and the CPU can be updating disjoint regions of the buffer
 197        * simultaneously and that will break if the regions overlap the same
 198        * cacheline.
 199        */
 200       return 64;
 201    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 202       return 1 << 27;
 203    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 204       return 16; // XXX: u_screen says 256 is the minimum value...
 205    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 206       return true; // XXX: ?????
 207    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 208       return 1 << 27; /* 128MB */
 209    case PIPE_CAP_MAX_VIEWPORTS:
 210       return 16;
 211    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 212       return 256;
 213    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 214       return 1024;
 215    case PIPE_CAP_MAX_GS_INVOCATIONS:
 216       return 32;
 217    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 218       return 4;
 219    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 220       return -32;
 221    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 222       return 31;
 223    case PIPE_CAP_MAX_VERTEX_STREAMS:
 224       return 4;
 225    case PIPE_CAP_VENDOR_ID:
 226       return 0x8086;
 227    case PIPE_CAP_DEVICE_ID:
 228       return screen->pci_id;
 229    case PIPE_CAP_VIDEO_MEMORY:
 230       return 0xffffffff; // XXX: bogus
 231    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 232       return 32;
 233    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 234       /* AMD_pinned_memory assumes the flexibility of using client memory
 235        * for any buffer (incl. vertex buffers) which rules out the prospect
 236        * of using snooped buffers, as using snooped buffers without
 237        * cogniscience is likely to be detrimental to performance and require
 238        * extensive checking in the driver for correctness, e.g. to prevent
 239        * illegal snoop <-> snoop transfers.
 240        */
 241       return devinfo->has_llc;
 242
 243    // XXX: don't hardcode 00:00:02.0 PCI here
 244    case PIPE_CAP_PCI_GROUP:
 245       return 0;
 246    case PIPE_CAP_PCI_BUS:
 247       return 0;
 248    case PIPE_CAP_PCI_DEVICE:
 249       return 2;
 250    case PIPE_CAP_PCI_FUNCTION:
 251       return 0;
 252
 253    default:
 254       return u_pipe_screen_get_param_defaults(pscreen, param);
 255    }
 256    return 0;
 257 }
 258
 259 static float
 260 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 261 {
 262    switch (param) {
 263    case PIPE_CAPF_MAX_LINE_WIDTH:
 264    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 265       return 7.375f;
 266
 267    case PIPE_CAPF_MAX_POINT_WIDTH:
 268    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 269       return 255.0f;
 270
 271    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 272       return 16.0f;
 273    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 274       return 15.0f;
 275    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 276    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 277    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 278       return 0.0f;
 279    default:
 280       unreachable("unknown param");
 281    }
 282 }
 283
 284 static int
 285 iris_get_shader_param(struct pipe_screen *pscreen,
 286                       enum pipe_shader_type p_stage,
 287                       enum pipe_shader_cap param)
 288 {
 289    struct iris_screen *screen = (struct iris_screen *)pscreen;
 290    struct brw_compiler *compiler = screen->compiler;
 291    gl_shader_stage stage = stage_from_pipe(p_stage);
 292
 293    /* this is probably not totally correct.. but it's a start: */
 294    switch (param) {
 295    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 296       return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
 297    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 298    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 299    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 300       return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
 301
 302    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 303       return UINT_MAX;
 304
 305    case PIPE_SHADER_CAP_MAX_INPUTS:
 306       return stage == MESA_SHADER_VERTEX ? 16 : 32;
 307    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 308       return 32;
 309    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 310       return 16 * 1024 * sizeof(float);
 311    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 312       return 16;
 313    case PIPE_SHADER_CAP_MAX_TEMPS:
 314       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 315    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 316       return 0;
 317    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 318       return !compiler->glsl_compiler_options[stage].EmitNoIndirectInput;
 319    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 320       return !compiler->glsl_compiler_options[stage].EmitNoIndirectOutput;
 321    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 322       return !compiler->glsl_compiler_options[stage].EmitNoIndirectTemp;
 323    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 324       return 1;
 325    case PIPE_SHADER_CAP_SUBROUTINES:
 326       return 0;
 327    case PIPE_SHADER_CAP_INTEGERS:
 328    case PIPE_SHADER_CAP_SCALAR_ISA:
 329       return 1;
 330    case PIPE_SHADER_CAP_INT64_ATOMICS:
 331    case PIPE_SHADER_CAP_FP16:
 332       return 0;
 333    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 334    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 335    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 336       return IRIS_MAX_TEXTURE_SAMPLERS;
 337    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 338       return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
 339    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 340    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 341       return 0;
 342    case PIPE_SHADER_CAP_PREFERRED_IR:
 343       return PIPE_SHADER_IR_NIR;
 344    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 345       return 0;
 346    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 347       return 32;
 348    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 349    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 350    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 351    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 352    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 353    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 354    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 355    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 356       return 0;
 357    default:
 358       unreachable("unknown shader param");
 359    }
 360 }
 361
 362 static int
 363 iris_get_compute_param(struct pipe_screen *pscreen,
 364                        enum pipe_shader_ir ir_type,
 365                        enum pipe_compute_cap param,
 366                        void *ret)
 367 {
 368    /* TODO: compute shaders */
 369    return 0;
 370 }
 371
 372 static uint64_t
 373 iris_get_timestamp(struct pipe_screen *pscreen)
 374 {
 375    return 0;
 376 }
 377
 378 static void
 379 iris_destroy_screen(struct pipe_screen *pscreen)
 380 {
 381    struct iris_screen *screen = (struct iris_screen *) pscreen;
 382    iris_bo_unreference(screen->workaround_bo);
 383    ralloc_free(screen);
 384 }
 385
 386 static void
 387 iris_fence_reference(struct pipe_screen *screen,
 388                      struct pipe_fence_handle **ptr,
 389                      struct pipe_fence_handle *fence)
 390 {
 391 }
 392
 393 static boolean
 394 iris_fence_finish(struct pipe_screen *screen,
 395                   struct pipe_context *ctx,
 396                   struct pipe_fence_handle *fence,
 397                   uint64_t timeout)
 398 {
 399    return true;
 400 }
 401
 402 static void
 403 iris_query_memory_info(struct pipe_screen *pscreen,
 404                        struct pipe_memory_info *info)
 405 {
 406 }
 407
 408 static const void *
 409 iris_get_compiler_options(struct pipe_screen *pscreen,
 410                           enum pipe_shader_ir ir,
 411                           enum pipe_shader_type pstage)
 412 {
 413    struct iris_screen *screen = (struct iris_screen *) pscreen;
 414    gl_shader_stage stage = stage_from_pipe(pstage);
 415    assert(ir == PIPE_SHADER_IR_NIR);
 416
 417    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 418 }
 419
 420 static int
 421 iris_getparam(struct iris_screen *screen, int param, int *value)
 422 {
 423    struct drm_i915_getparam gp = { .param = param, .value = value };
 424
 425    if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 426       return -errno;
 427
 428    return 0;
 429 }
 430
 431 static bool
 432 iris_getparam_boolean(struct iris_screen *screen, int param)
 433 {
 434    int value = 0;
 435    return (iris_getparam(screen, param, &value) == 0) && value;
 436 }
 437
 438 static int
 439 iris_getparam_integer(struct iris_screen *screen, int param)
 440 {
 441    int value = -1;
 442
 443    if (iris_getparam(screen, param, &value) == 0)
 444       return value;
 445
 446    return -1;
 447 }
 448
 449 static void
 450 iris_shader_debug_log(void *data, const char *fmt, ...)
 451 {
 452    struct pipe_debug_callback *dbg = data;
 453    unsigned id = 0;
 454    va_list args;
 455
 456    if (!dbg->debug_message)
 457       return;
 458
 459    va_start(args, fmt);
 460    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
 461    va_end(args);
 462 }
 463
 464 static void
 465 iris_shader_perf_log(void *data, const char *fmt, ...)
 466 {
 467    struct pipe_debug_callback *dbg = data;
 468    unsigned id = 0;
 469    va_list args;
 470
 471    if (!dbg->debug_message)
 472       return;
 473
 474    va_start(args, fmt);
 475    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
 476    va_end(args);
 477 }
 478
 479 struct pipe_screen *
 480 iris_screen_create(int fd)
 481 {
 482    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 483    if (!screen)
 484       return NULL;
 485
 486    screen->fd = fd;
 487    screen->pci_id = iris_getparam_integer(screen, I915_PARAM_CHIPSET_ID);
 488
 489    if (!gen_get_device_info(screen->pci_id, &screen->devinfo))
 490       return NULL;
 491
 492    screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
 493    if (!screen->bufmgr)
 494       return NULL;
 495
 496    screen->workaround_bo =
 497       iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
 498    if (!screen->workaround_bo)
 499       return NULL;
 500
 501    brw_process_intel_debug_variable();
 502
 503    bool hw_has_swizzling = false; // XXX: detect?
 504    isl_device_init(&screen->isl_dev, &screen->devinfo, hw_has_swizzling);
 505
 506    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 507    screen->compiler->shader_debug_log = iris_shader_debug_log;
 508    screen->compiler->shader_perf_log = iris_shader_perf_log;
 509
 510    slab_create_parent(&screen->transfer_pool,
 511                       sizeof(struct iris_transfer), 64);
 512
 513    struct pipe_screen *pscreen = &screen->base;
 514
 515    iris_init_screen_resource_functions(pscreen);
 516
 517    pscreen->destroy = iris_destroy_screen;
 518    pscreen->get_name = iris_get_name;
 519    pscreen->get_vendor = iris_get_vendor;
 520    pscreen->get_device_vendor = iris_get_device_vendor;
 521    pscreen->get_param = iris_get_param;
 522    pscreen->get_shader_param = iris_get_shader_param;
 523    pscreen->get_compute_param = iris_get_compute_param;
 524    pscreen->get_paramf = iris_get_paramf;
 525    pscreen->get_compiler_options = iris_get_compiler_options;
 526    pscreen->is_format_supported = iris_is_format_supported;
 527    pscreen->context_create = iris_create_context;
 528    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 529    pscreen->get_timestamp = iris_get_timestamp;
 530    pscreen->fence_reference = iris_fence_reference;
 531    pscreen->fence_finish = iris_fence_finish;
 532    pscreen->query_memory_info = iris_query_memory_info;
 533
 534    return pscreen;
 535 }