src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include <sys/ioctl.h>
  26 #include "pipe/p_defines.h"
  27 #include "pipe/p_state.h"
  28 #include "pipe/p_context.h"
  29 #include "pipe/p_screen.h"
  30 #include "util/u_inlines.h"
  31 #include "util/u_format.h"
  32 #include "util/u_upload_mgr.h"
  33 #include "util/ralloc.h"
  34 #include "drm-uapi/i915_drm.h"
  35 #include "iris_context.h"
  36 #include "iris_pipe.h"
  37 #include "iris_resource.h"
  38 #include "iris_screen.h"
  39 #include "intel/compiler/brw_compiler.h"
  40
  41 static void
  42 iris_flush_frontbuffer(struct pipe_screen *_screen,
  43                        struct pipe_resource *resource,
  44                        unsigned level, unsigned layer,
  45                        void *context_private, struct pipe_box *box)
  46 {
  47 }
  48
  49 static const char *
  50 iris_get_vendor(struct pipe_screen *pscreen)
  51 {
  52    return "Mesa Project";
  53 }
  54
  55 static const char *
  56 iris_get_device_vendor(struct pipe_screen *pscreen)
  57 {
  58    return "Intel";
  59 }
  60
  61 static const char *
  62 iris_get_name(struct pipe_screen *pscreen)
  63 {
  64    struct iris_screen *screen = (struct iris_screen *)pscreen;
  65    const char *chipset;
  66
  67    switch (screen->pci_id) {
  68 #undef CHIPSET
  69 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
  70 #include "pci_ids/i965_pci_ids.h"
  71    default:
  72       chipset = "Unknown Intel Chipset";
  73       break;
  74    }
  75    return &chipset[9];
  76 }
  77
  78 static int
  79 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  80 {
  81    struct iris_screen *screen = (struct iris_screen *)pscreen;
  82
  83    switch (param) {
  84    case PIPE_CAP_NPOT_TEXTURES:
  85    case PIPE_CAP_ANISOTROPIC_FILTER:
  86    case PIPE_CAP_POINT_SPRITE:
  87    case PIPE_CAP_OCCLUSION_QUERY:
  88    case PIPE_CAP_QUERY_TIME_ELAPSED:
  89    case PIPE_CAP_TEXTURE_SWIZZLE:
  90    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  91    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  92    case PIPE_CAP_SM3:
  93    case PIPE_CAP_PRIMITIVE_RESTART:
  94    case PIPE_CAP_INDEP_BLEND_ENABLE:
  95    case PIPE_CAP_INDEP_BLEND_FUNC:
  96    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
  97    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  98    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  99    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 100    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 101    case PIPE_CAP_TGSI_INSTANCEID:
 102    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 103    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 104    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 105    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 106    case PIPE_CAP_CONDITIONAL_RENDER:
 107    case PIPE_CAP_TEXTURE_BARRIER:
 108    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 109    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 110    case PIPE_CAP_COMPUTE:
 111    case PIPE_CAP_START_INSTANCE:
 112    case PIPE_CAP_QUERY_TIMESTAMP:
 113    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 114    case PIPE_CAP_CUBE_MAP_ARRAY:
 115    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 116    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 117    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 118    case PIPE_CAP_TEXTURE_QUERY_LOD:
 119    case PIPE_CAP_SAMPLE_SHADING:
 120    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 121    case PIPE_CAP_DRAW_INDIRECT:
 122    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 123    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 124    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 125    case PIPE_CAP_ACCELERATED:
 126    case PIPE_CAP_UMA:
 127    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 128    case PIPE_CAP_CLIP_HALFZ:
 129    case PIPE_CAP_TGSI_TEXCOORD:
 130    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 131    case PIPE_CAP_DOUBLES:
 132    case PIPE_CAP_INT64:
 133    case PIPE_CAP_INT64_DIVMOD:
 134    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 135    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 136    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 137    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 138    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 139    case PIPE_CAP_CULL_DISTANCE:
 140    case PIPE_CAP_PACKED_UNIFORMS:
 141    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 142    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 143    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 144    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 145    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 146       return true;
 147
 148    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 149    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 150    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 151    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 152    case PIPE_CAP_USER_VERTEX_BUFFERS:
 153    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 154    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 155    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 156    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 157    case PIPE_CAP_FAKE_SW_MSAA:
 158    case PIPE_CAP_VERTEXID_NOBASE:
 159    case PIPE_CAP_FENCE_SIGNAL:
 160    case PIPE_CAP_CONSTBUF0_FLAGS:
 161    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 162    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 163    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 164    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 165    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 166    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 167    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 168    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 169    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 170    case PIPE_CAP_GENERATE_MIPMAP:
 171    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 172       return false;
 173
 174    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 175       /* Intel GPUs don't support PIPE_TEX_WRAP_MIRROR_CLAMP or
 176        * PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER.
 177        */
 178       return false;
 179
 180    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 181       return 1;
 182    case PIPE_CAP_MAX_RENDER_TARGETS:
 183       return BRW_MAX_DRAW_BUFFERS;
 184    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 185    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 186       return 15; /* 16384x16384 */
 187    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 188       return 12; /* 2048x2048 */
 189    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 190       return 4;
 191    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 192       return 2048;
 193    case PIPE_CAP_MIN_TEXEL_OFFSET:
 194       return -8;
 195    case PIPE_CAP_MAX_TEXEL_OFFSET:
 196       return 7;
 197    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 198       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 199    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 200       return BRW_MAX_SOL_BINDINGS;
 201    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 202       return 460;
 203    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 204       return 140;
 205    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 206       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 207       return 32;
 208    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 209       /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
 210        * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
 211        * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
 212        * GPU and the CPU can be updating disjoint regions of the buffer
 213        * simultaneously and that will break if the regions overlap the same
 214        * cacheline.
 215        */
 216       return 64;
 217    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 218       return 64; // XXX: ?
 219    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 220       return 16;
 221    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 222       return true; // XXX: ?????
 223    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 224       return 1 << 27; /* 128MB */
 225    case PIPE_CAP_MAX_VIEWPORTS:
 226       return 16;
 227    case PIPE_CAP_ENDIANNESS:
 228       return PIPE_ENDIAN_LITTLE;
 229    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 230       return 256;
 231    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 232       return 128;
 233    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 234    case PIPE_CAP_TEXTURE_GATHER_SM5:
 235       return 0; // XXX:
 236    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 237       return -32;
 238    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 239       return 31;
 240    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 241    case PIPE_CAP_MAX_VERTEX_STREAMS:
 242       return 4;
 243    case PIPE_CAP_VENDOR_ID:
 244       return 0x8086;
 245    case PIPE_CAP_DEVICE_ID:
 246       return screen->pci_id;
 247    case PIPE_CAP_VIDEO_MEMORY:
 248       return 0xffffffff; // XXX: bogus
 249    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 250       return 2048;
 251    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 252       return 32;
 253    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 254    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 255    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 256    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 257    case PIPE_CAP_TGSI_TXQS:
 258    case PIPE_CAP_SHAREABLE_SHADERS:
 259    case PIPE_CAP_CLEAR_TEXTURE:
 260    case PIPE_CAP_DRAW_PARAMETERS:
 261    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 262    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 263    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 264    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 265    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 266    case PIPE_CAP_INVALIDATE_BUFFER:
 267    case PIPE_CAP_STRING_MARKER:
 268    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 269    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 270    case PIPE_CAP_QUERY_MEMORY_INFO:
 271    case PIPE_CAP_PCI_GROUP:
 272    case PIPE_CAP_PCI_BUS:
 273    case PIPE_CAP_PCI_DEVICE:
 274    case PIPE_CAP_PCI_FUNCTION:
 275    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 276    case PIPE_CAP_TGSI_VOTE:
 277    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 278    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 279    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 280    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 281    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 282    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 283    case PIPE_CAP_NATIVE_FENCE_FD:
 284    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 285    case PIPE_CAP_TGSI_FS_FBFETCH:
 286    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 287    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 288    case PIPE_CAP_TGSI_CLOCK:
 289    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 290    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 291    case PIPE_CAP_TGSI_BALLOT:
 292    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 293    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 294    case PIPE_CAP_POST_DEPTH_COVERAGE:
 295    case PIPE_CAP_BINDLESS_TEXTURE:
 296    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 297    case PIPE_CAP_QUERY_SO_OVERFLOW:
 298    case PIPE_CAP_MEMOBJ:
 299    case PIPE_CAP_LOAD_CONSTBUF:
 300    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 301    case PIPE_CAP_TILE_RASTER_ORDER:
 302    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 303    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 304       // XXX: TODO: fill these out
 305       break;
 306    }
 307    return 0;
 308 }
 309
 310 static float
 311 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 312 {
 313    switch (param) {
 314    case PIPE_CAPF_MAX_LINE_WIDTH:
 315    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 316       return 7.375f;
 317
 318    case PIPE_CAPF_MAX_POINT_WIDTH:
 319    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 320       return 255.0f;
 321
 322    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 323       return 16.0f;
 324    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 325       return 15.0f;
 326    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 327    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 328    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 329       return 0.0f;
 330    default:
 331       unreachable("unknown param");
 332    }
 333 }
 334
 335 static int
 336 iris_get_shader_param(struct pipe_screen *pscreen,
 337                       enum pipe_shader_type p_stage,
 338                       enum pipe_shader_cap param)
 339 {
 340    struct iris_screen *screen = (struct iris_screen *)pscreen;
 341    struct brw_compiler *compiler = screen->compiler;
 342    gl_shader_stage stage = stage_from_pipe(p_stage);
 343
 344    /* this is probably not totally correct.. but it's a start: */
 345    switch (param) {
 346    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 347       return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
 348    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 349    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 350    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 351       return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
 352
 353    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 354       return UINT_MAX;
 355
 356    case PIPE_SHADER_CAP_MAX_INPUTS:
 357       return stage == MESA_SHADER_VERTEX ? 16 : 32;
 358    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 359       return 32;
 360    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 361       return 16 * 1024 * sizeof(float);
 362    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 363       return 16;
 364    case PIPE_SHADER_CAP_MAX_TEMPS:
 365       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 366    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 367       return 0;
 368    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 369       return !compiler->glsl_compiler_options[stage].EmitNoIndirectInput;
 370    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 371       return !compiler->glsl_compiler_options[stage].EmitNoIndirectOutput;
 372    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 373       return !compiler->glsl_compiler_options[stage].EmitNoIndirectTemp;
 374    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 375       return 1;
 376    case PIPE_SHADER_CAP_SUBROUTINES:
 377       return 0;
 378    case PIPE_SHADER_CAP_INTEGERS:
 379    case PIPE_SHADER_CAP_SCALAR_ISA:
 380       return 1;
 381    case PIPE_SHADER_CAP_INT64_ATOMICS:
 382    case PIPE_SHADER_CAP_FP16:
 383       return 0;
 384    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 385    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 386    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 387    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 388       return IRIS_MAX_TEXTURE_SAMPLERS;
 389    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 390    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 391       return 0;
 392    case PIPE_SHADER_CAP_PREFERRED_IR:
 393       return PIPE_SHADER_IR_NIR;
 394    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 395       return 0;
 396    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 397       return 32;
 398    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 399    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 400    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 401    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 402    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 403    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 404    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 405    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 406       return 0;
 407    default:
 408       unreachable("unknown shader param");
 409    }
 410 }
 411
 412 static int
 413 iris_get_compute_param(struct pipe_screen *pscreen,
 414                        enum pipe_shader_ir ir_type,
 415                        enum pipe_compute_cap param,
 416                        void *ret)
 417 {
 418    /* TODO: compute shaders */
 419    return 0;
 420 }
 421
 422 static uint64_t
 423 iris_get_timestamp(struct pipe_screen *pscreen)
 424 {
 425    return 0;
 426 }
 427
 428 static void
 429 iris_destroy_screen(struct pipe_screen *pscreen)
 430 {
 431    struct iris_screen *screen = (struct iris_screen *) pscreen;
 432    iris_bo_unreference(screen->workaround_bo);
 433    ralloc_free(screen);
 434 }
 435
 436 static void
 437 iris_fence_reference(struct pipe_screen *screen,
 438                      struct pipe_fence_handle **ptr,
 439                      struct pipe_fence_handle *fence)
 440 {
 441 }
 442
 443 static boolean
 444 iris_fence_finish(struct pipe_screen *screen,
 445                   struct pipe_context *ctx,
 446                   struct pipe_fence_handle *fence,
 447                   uint64_t timeout)
 448 {
 449    return true;
 450 }
 451
 452 static void
 453 iris_query_memory_info(struct pipe_screen *pscreen,
 454                        struct pipe_memory_info *info)
 455 {
 456 }
 457
 458 static const void *
 459 iris_get_compiler_options(struct pipe_screen *pscreen,
 460                           enum pipe_shader_ir ir,
 461                           enum pipe_shader_type pstage)
 462 {
 463    struct iris_screen *screen = (struct iris_screen *) pscreen;
 464    gl_shader_stage stage = stage_from_pipe(pstage);
 465    assert(ir == PIPE_SHADER_IR_NIR);
 466
 467    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 468 }
 469
 470 static int
 471 iris_getparam(struct iris_screen *screen, int param, int *value)
 472 {
 473    struct drm_i915_getparam gp = { .param = param, .value = value };
 474
 475    if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 476       return -errno;
 477
 478    return 0;
 479 }
 480
 481 static bool
 482 iris_getparam_boolean(struct iris_screen *screen, int param)
 483 {
 484    int value = 0;
 485    return (iris_getparam(screen, param, &value) == 0) && value;
 486 }
 487
 488 static int
 489 iris_getparam_integer(struct iris_screen *screen, int param)
 490 {
 491    int value = -1;
 492
 493    if (iris_getparam(screen, param, &value) == 0)
 494       return value;
 495
 496    return -1;
 497 }
 498
 499 static void
 500 iris_shader_debug_log(void *data, const char *fmt, ...)
 501 {
 502    struct pipe_debug_callback *dbg = data;
 503    unsigned id = 0;
 504    va_list args;
 505
 506    if (!dbg->debug_message)
 507       return;
 508
 509    va_start(args, fmt);
 510    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
 511    va_end(args);
 512 }
 513
 514 static void
 515 iris_shader_perf_log(void *data, const char *fmt, ...)
 516 {
 517    struct pipe_debug_callback *dbg = data;
 518    unsigned id = 0;
 519    va_list args;
 520
 521    if (!dbg->debug_message)
 522       return;
 523
 524    va_start(args, fmt);
 525    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
 526    va_end(args);
 527 }
 528
 529 struct pipe_screen *
 530 iris_screen_create(int fd)
 531 {
 532    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 533    if (!screen)
 534       return NULL;
 535
 536    screen->fd = fd;
 537    screen->pci_id = iris_getparam_integer(screen, I915_PARAM_CHIPSET_ID);
 538
 539    if (!gen_get_device_info(screen->pci_id, &screen->devinfo))
 540       return NULL;
 541
 542    screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
 543    if (!screen->bufmgr)
 544       return NULL;
 545
 546    screen->workaround_bo =
 547       iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
 548    if (!screen->workaround_bo)
 549       return NULL;
 550
 551    brw_process_intel_debug_variable();
 552
 553    bool hw_has_swizzling = false; // XXX: detect?
 554    isl_device_init(&screen->isl_dev, &screen->devinfo, hw_has_swizzling);
 555
 556    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 557    screen->compiler->shader_debug_log = iris_shader_debug_log;
 558    screen->compiler->shader_perf_log = iris_shader_perf_log;
 559
 560    slab_create_parent(&screen->transfer_pool,
 561                       sizeof(struct iris_transfer), 64);
 562
 563    struct pipe_screen *pscreen = &screen->base;
 564
 565    iris_init_screen_resource_functions(pscreen);
 566
 567    pscreen->destroy = iris_destroy_screen;
 568    pscreen->get_name = iris_get_name;
 569    pscreen->get_vendor = iris_get_vendor;
 570    pscreen->get_device_vendor = iris_get_device_vendor;
 571    pscreen->get_param = iris_get_param;
 572    pscreen->get_shader_param = iris_get_shader_param;
 573    pscreen->get_compute_param = iris_get_compute_param;
 574    pscreen->get_paramf = iris_get_paramf;
 575    pscreen->get_compiler_options = iris_get_compiler_options;
 576    pscreen->is_format_supported = iris_is_format_supported;
 577    pscreen->context_create = iris_create_context;
 578    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 579    pscreen->get_timestamp = iris_get_timestamp;
 580    pscreen->fence_reference = iris_fence_reference;
 581    pscreen->fence_finish = iris_fence_finish;
 582    pscreen->query_memory_info = iris_query_memory_info;
 583
 584    return pscreen;
 585 }