src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /**
  24  * @file iris_screen.c
  25  *
  26  * Screen related driver hooks and capability lists.
  27  *
  28  * A program may use multiple rendering contexts (iris_context), but
  29  * they all share a common screen (iris_screen).  Global driver state
  30  * can be stored in the screen; it may be accessed by multiple threads.
  31  */
  32
  33 #include <stdio.h>
  34 #include <errno.h>
  35 #include <sys/ioctl.h>
  36 #include "pipe/p_defines.h"
  37 #include "pipe/p_state.h"
  38 #include "pipe/p_context.h"
  39 #include "pipe/p_screen.h"
  40 #include "util/u_inlines.h"
  41 #include "util/u_format.h"
  42 #include "util/u_upload_mgr.h"
  43 #include "util/ralloc.h"
  44 #include "drm-uapi/i915_drm.h"
  45 #include "iris_context.h"
  46 #include "iris_defines.h"
  47 #include "iris_pipe.h"
  48 #include "iris_resource.h"
  49 #include "iris_screen.h"
  50 #include "intel/compiler/brw_compiler.h"
  51
  52 static void
  53 iris_flush_frontbuffer(struct pipe_screen *_screen,
  54                        struct pipe_resource *resource,
  55                        unsigned level, unsigned layer,
  56                        void *context_private, struct pipe_box *box)
  57 {
  58 }
  59
  60 static const char *
  61 iris_get_vendor(struct pipe_screen *pscreen)
  62 {
  63    return "Mesa Project";
  64 }
  65
  66 static const char *
  67 iris_get_device_vendor(struct pipe_screen *pscreen)
  68 {
  69    return "Intel";
  70 }
  71
  72 static const char *
  73 iris_get_name(struct pipe_screen *pscreen)
  74 {
  75    struct iris_screen *screen = (struct iris_screen *)pscreen;
  76    const char *chipset;
  77
  78    switch (screen->pci_id) {
  79 #undef CHIPSET
  80 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
  81 #include "pci_ids/i965_pci_ids.h"
  82    default:
  83       chipset = "Unknown Intel Chipset";
  84       break;
  85    }
  86    return &chipset[9];
  87 }
  88
  89 static int
  90 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  91 {
  92    struct iris_screen *screen = (struct iris_screen *)pscreen;
  93    const struct gen_device_info *devinfo = &screen->devinfo;
  94
  95    switch (param) {
  96    case PIPE_CAP_NPOT_TEXTURES:
  97    case PIPE_CAP_ANISOTROPIC_FILTER:
  98    case PIPE_CAP_POINT_SPRITE:
  99    case PIPE_CAP_OCCLUSION_QUERY:
 100    case PIPE_CAP_QUERY_TIME_ELAPSED:
 101    case PIPE_CAP_TEXTURE_SWIZZLE:
 102    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 103    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 104    case PIPE_CAP_SM3:
 105    case PIPE_CAP_PRIMITIVE_RESTART:
 106    case PIPE_CAP_INDEP_BLEND_ENABLE:
 107    case PIPE_CAP_INDEP_BLEND_FUNC:
 108    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 109    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 110    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 111    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 112    case PIPE_CAP_TGSI_INSTANCEID:
 113    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 114    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 115    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 116    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 117    case PIPE_CAP_CONDITIONAL_RENDER:
 118    case PIPE_CAP_TEXTURE_BARRIER:
 119    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 120    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 121    case PIPE_CAP_COMPUTE:
 122    case PIPE_CAP_START_INSTANCE:
 123    case PIPE_CAP_QUERY_TIMESTAMP:
 124    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 125    case PIPE_CAP_CUBE_MAP_ARRAY:
 126    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 127    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 128    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 129    case PIPE_CAP_TEXTURE_QUERY_LOD:
 130    case PIPE_CAP_SAMPLE_SHADING:
 131    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 132    case PIPE_CAP_DRAW_INDIRECT:
 133    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 134    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 135    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 136    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 137    case PIPE_CAP_ACCELERATED:
 138    case PIPE_CAP_UMA:
 139    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 140    case PIPE_CAP_CLIP_HALFZ:
 141    case PIPE_CAP_TGSI_TEXCOORD:
 142    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 143    case PIPE_CAP_DOUBLES:
 144    case PIPE_CAP_INT64:
 145    case PIPE_CAP_INT64_DIVMOD:
 146    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 147    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 148    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 149    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 150    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 151    case PIPE_CAP_CULL_DISTANCE:
 152    case PIPE_CAP_PACKED_UNIFORMS:
 153    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 154    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 155    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 156    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 157    case PIPE_CAP_POST_DEPTH_COVERAGE:
 158    case PIPE_CAP_QUERY_SO_OVERFLOW:
 159    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 160    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 161    case PIPE_CAP_TGSI_TXQS:
 162    case PIPE_CAP_TGSI_FS_FBFETCH:
 163    case PIPE_CAP_TGSI_CLOCK:
 164    case PIPE_CAP_TGSI_BALLOT:
 165    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 166    case PIPE_CAP_CLEAR_TEXTURE:
 167    case PIPE_CAP_TGSI_VOTE:
 168    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 169    case PIPE_CAP_TEXTURE_GATHER_SM5:
 170    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 171    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 172       return true;
 173
 174    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 175       return 1;
 176    case PIPE_CAP_MAX_RENDER_TARGETS:
 177       return BRW_MAX_DRAW_BUFFERS;
 178    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 179    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 180       return 15; /* 16384x16384 */
 181    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 182       return 12; /* 2048x2048 */
 183    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 184       return 4;
 185    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 186       return 2048;
 187    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 188       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 189    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 190       return BRW_MAX_SOL_BINDINGS;
 191    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 192       return 460;
 193    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 194       return 140;
 195    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 196       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 197       return 32;
 198    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 199       /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
 200        * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
 201        * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
 202        * GPU and the CPU can be updating disjoint regions of the buffer
 203        * simultaneously and that will break if the regions overlap the same
 204        * cacheline.
 205        */
 206       return 64;
 207    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 208       return 1 << 27;
 209    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 210       return 16; // XXX: u_screen says 256 is the minimum value...
 211    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 212       return true; // XXX: ?????
 213    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 214       return 1 << 27; /* 128MB */
 215    case PIPE_CAP_MAX_VIEWPORTS:
 216       return 16;
 217    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 218       return 256;
 219    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 220       return 1024;
 221    case PIPE_CAP_MAX_GS_INVOCATIONS:
 222       return 32;
 223    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 224       return 4;
 225    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 226       return -32;
 227    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 228       return 31;
 229    case PIPE_CAP_MAX_VERTEX_STREAMS:
 230       return 4;
 231    case PIPE_CAP_VENDOR_ID:
 232       return 0x8086;
 233    case PIPE_CAP_DEVICE_ID:
 234       return screen->pci_id;
 235    case PIPE_CAP_VIDEO_MEMORY:
 236       return 0xffffffff; // XXX: bogus
 237    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 238       return 32;
 239    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 240       /* AMD_pinned_memory assumes the flexibility of using client memory
 241        * for any buffer (incl. vertex buffers) which rules out the prospect
 242        * of using snooped buffers, as using snooped buffers without
 243        * cogniscience is likely to be detrimental to performance and require
 244        * extensive checking in the driver for correctness, e.g. to prevent
 245        * illegal snoop <-> snoop transfers.
 246        */
 247       return devinfo->has_llc;
 248
 249    // XXX: don't hardcode 00:00:02.0 PCI here
 250    case PIPE_CAP_PCI_GROUP:
 251       return 0;
 252    case PIPE_CAP_PCI_BUS:
 253       return 0;
 254    case PIPE_CAP_PCI_DEVICE:
 255       return 2;
 256    case PIPE_CAP_PCI_FUNCTION:
 257       return 0;
 258
 259    default:
 260       return u_pipe_screen_get_param_defaults(pscreen, param);
 261    }
 262    return 0;
 263 }
 264
 265 static float
 266 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 267 {
 268    switch (param) {
 269    case PIPE_CAPF_MAX_LINE_WIDTH:
 270    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 271       return 7.375f;
 272
 273    case PIPE_CAPF_MAX_POINT_WIDTH:
 274    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 275       return 255.0f;
 276
 277    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 278       return 16.0f;
 279    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 280       return 15.0f;
 281    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 282    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 283    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 284       return 0.0f;
 285    default:
 286       unreachable("unknown param");
 287    }
 288 }
 289
 290 static int
 291 iris_get_shader_param(struct pipe_screen *pscreen,
 292                       enum pipe_shader_type p_stage,
 293                       enum pipe_shader_cap param)
 294 {
 295    struct iris_screen *screen = (struct iris_screen *)pscreen;
 296    struct brw_compiler *compiler = screen->compiler;
 297    gl_shader_stage stage = stage_from_pipe(p_stage);
 298
 299    /* this is probably not totally correct.. but it's a start: */
 300    switch (param) {
 301    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 302       return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
 303    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 304    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 305    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 306       return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
 307
 308    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 309       return UINT_MAX;
 310
 311    case PIPE_SHADER_CAP_MAX_INPUTS:
 312       return stage == MESA_SHADER_VERTEX ? 16 : 32;
 313    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 314       return 32;
 315    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 316       return 16 * 1024 * sizeof(float);
 317    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 318       return 16;
 319    case PIPE_SHADER_CAP_MAX_TEMPS:
 320       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 321    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 322       return 0;
 323    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 324       return !compiler->glsl_compiler_options[stage].EmitNoIndirectInput;
 325    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 326       return !compiler->glsl_compiler_options[stage].EmitNoIndirectOutput;
 327    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 328       return !compiler->glsl_compiler_options[stage].EmitNoIndirectTemp;
 329    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 330       return 1;
 331    case PIPE_SHADER_CAP_SUBROUTINES:
 332       return 0;
 333    case PIPE_SHADER_CAP_INTEGERS:
 334    case PIPE_SHADER_CAP_SCALAR_ISA:
 335       return 1;
 336    case PIPE_SHADER_CAP_INT64_ATOMICS:
 337    case PIPE_SHADER_CAP_FP16:
 338       return 0;
 339    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 340    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 341    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 342       return IRIS_MAX_TEXTURE_SAMPLERS;
 343    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 344       return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
 345    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 346    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 347       return 0;
 348    case PIPE_SHADER_CAP_PREFERRED_IR:
 349       return PIPE_SHADER_IR_NIR;
 350    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 351       return 1 << PIPE_SHADER_IR_NIR;
 352    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 353       return 32;
 354    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 355    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 356    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 357    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 358    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 359    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 360    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 361    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 362       return 0;
 363    default:
 364       unreachable("unknown shader param");
 365    }
 366 }
 367
 368 static int
 369 iris_get_compute_param(struct pipe_screen *pscreen,
 370                        enum pipe_shader_ir ir_type,
 371                        enum pipe_compute_cap param,
 372                        void *ret)
 373 {
 374    struct iris_screen *screen = (struct iris_screen *)pscreen;
 375    struct brw_compiler *compiler = screen->compiler;
 376    const struct gen_device_info *devinfo = &screen->devinfo;
 377
 378    // XXX: cherryview fusing
 379
 380    const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
 381    const uint32_t max_invocations = 32 * max_threads;
 382
 383 #define RET(x) do {                  \
 384    if (ret)                          \
 385       memcpy(ret, x, sizeof(x));     \
 386    return sizeof(x);                 \
 387 } while (0)
 388
 389    switch (param) {
 390    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 391       RET((uint32_t []){ 32 });
 392
 393    case PIPE_COMPUTE_CAP_IR_TARGET:
 394       if (ret)
 395          strcpy(ret, "gen");
 396       return 4;
 397
 398    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 399       RET((uint64_t []) { 3 });
 400
 401    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 402       RET(((uint64_t []) { 65535, 65535, 65535 }));
 403
 404    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 405       /* MaxComputeWorkGroupSize[0..2] */
 406       RET(((uint64_t []) {max_invocations, max_invocations, max_invocations}));
 407
 408    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 409       /* MaxComputeWorkGroupInvocations */
 410       RET((uint64_t []) { max_invocations });
 411
 412    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 413       /* MaxComputeSharedMemorySize */
 414       RET((uint64_t []) { 64 * 1024 });
 415
 416    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 417       RET((uint32_t []) { 1 });
 418
 419    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 420       RET((uint32_t []) { BRW_SUBGROUP_SIZE });
 421
 422    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 423    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 424    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 425    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 426    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 427    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 428    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 429       // XXX: I think these are for Clover...
 430       return 0;
 431
 432    default:
 433       unreachable("unknown compute param");
 434    }
 435 }
 436
 437 static uint64_t
 438 iris_get_timestamp(struct pipe_screen *pscreen)
 439 {
 440    struct iris_screen *screen = (struct iris_screen *) pscreen;
 441    const unsigned TIMESTAMP = 0x2358;
 442    uint64_t result;
 443
 444    iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
 445
 446    result = iris_timebase_scale(&screen->devinfo, result);
 447    result &= (1ull << TIMESTAMP_BITS) - 1;
 448
 449    return result;
 450 }
 451
 452 static void
 453 iris_destroy_screen(struct pipe_screen *pscreen)
 454 {
 455    struct iris_screen *screen = (struct iris_screen *) pscreen;
 456    iris_bo_unreference(screen->workaround_bo);
 457    ralloc_free(screen);
 458 }
 459
 460 static void
 461 iris_fence_reference(struct pipe_screen *screen,
 462                      struct pipe_fence_handle **ptr,
 463                      struct pipe_fence_handle *fence)
 464 {
 465 }
 466
 467 static boolean
 468 iris_fence_finish(struct pipe_screen *screen,
 469                   struct pipe_context *ctx,
 470                   struct pipe_fence_handle *fence,
 471                   uint64_t timeout)
 472 {
 473    return true;
 474 }
 475
 476 static void
 477 iris_query_memory_info(struct pipe_screen *pscreen,
 478                        struct pipe_memory_info *info)
 479 {
 480 }
 481
 482 static const void *
 483 iris_get_compiler_options(struct pipe_screen *pscreen,
 484                           enum pipe_shader_ir ir,
 485                           enum pipe_shader_type pstage)
 486 {
 487    struct iris_screen *screen = (struct iris_screen *) pscreen;
 488    gl_shader_stage stage = stage_from_pipe(pstage);
 489    assert(ir == PIPE_SHADER_IR_NIR);
 490
 491    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 492 }
 493
 494 static int
 495 iris_getparam(struct iris_screen *screen, int param, int *value)
 496 {
 497    struct drm_i915_getparam gp = { .param = param, .value = value };
 498
 499    if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 500       return -errno;
 501
 502    return 0;
 503 }
 504
 505 static bool
 506 iris_getparam_boolean(struct iris_screen *screen, int param)
 507 {
 508    int value = 0;
 509    return (iris_getparam(screen, param, &value) == 0) && value;
 510 }
 511
 512 static int
 513 iris_getparam_integer(struct iris_screen *screen, int param)
 514 {
 515    int value = -1;
 516
 517    if (iris_getparam(screen, param, &value) == 0)
 518       return value;
 519
 520    return -1;
 521 }
 522
 523 static void
 524 iris_shader_debug_log(void *data, const char *fmt, ...)
 525 {
 526    struct pipe_debug_callback *dbg = data;
 527    unsigned id = 0;
 528    va_list args;
 529
 530    if (!dbg->debug_message)
 531       return;
 532
 533    va_start(args, fmt);
 534    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
 535    va_end(args);
 536 }
 537
 538 static void
 539 iris_shader_perf_log(void *data, const char *fmt, ...)
 540 {
 541    struct pipe_debug_callback *dbg = data;
 542    unsigned id = 0;
 543    va_list args;
 544
 545    if (!dbg->debug_message)
 546       return;
 547
 548    va_start(args, fmt);
 549    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
 550    va_end(args);
 551 }
 552
 553 struct pipe_screen *
 554 iris_screen_create(int fd)
 555 {
 556    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 557    if (!screen)
 558       return NULL;
 559
 560    screen->fd = fd;
 561    screen->pci_id = iris_getparam_integer(screen, I915_PARAM_CHIPSET_ID);
 562
 563    if (!gen_get_device_info(screen->pci_id, &screen->devinfo))
 564       return NULL;
 565
 566    screen->devinfo.timestamp_frequency =
 567       iris_getparam_integer(screen, I915_PARAM_CS_TIMESTAMP_FREQUENCY);
 568
 569    screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
 570    if (!screen->bufmgr)
 571       return NULL;
 572
 573    screen->workaround_bo =
 574       iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
 575    if (!screen->workaround_bo)
 576       return NULL;
 577
 578    brw_process_intel_debug_variable();
 579
 580    bool hw_has_swizzling = false; // XXX: detect?
 581    isl_device_init(&screen->isl_dev, &screen->devinfo, hw_has_swizzling);
 582
 583    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 584    screen->compiler->shader_debug_log = iris_shader_debug_log;
 585    screen->compiler->shader_perf_log = iris_shader_perf_log;
 586
 587    slab_create_parent(&screen->transfer_pool,
 588                       sizeof(struct iris_transfer), 64);
 589
 590    struct pipe_screen *pscreen = &screen->base;
 591
 592    iris_init_screen_resource_functions(pscreen);
 593
 594    pscreen->destroy = iris_destroy_screen;
 595    pscreen->get_name = iris_get_name;
 596    pscreen->get_vendor = iris_get_vendor;
 597    pscreen->get_device_vendor = iris_get_device_vendor;
 598    pscreen->get_param = iris_get_param;
 599    pscreen->get_shader_param = iris_get_shader_param;
 600    pscreen->get_compute_param = iris_get_compute_param;
 601    pscreen->get_paramf = iris_get_paramf;
 602    pscreen->get_compiler_options = iris_get_compiler_options;
 603    pscreen->is_format_supported = iris_is_format_supported;
 604    pscreen->context_create = iris_create_context;
 605    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 606    pscreen->get_timestamp = iris_get_timestamp;
 607    pscreen->fence_reference = iris_fence_reference;
 608    pscreen->fence_finish = iris_fence_finish;
 609    pscreen->query_memory_info = iris_query_memory_info;
 610
 611    return pscreen;
 612 }