src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file iris_screen.c
  26  *
  27  * Screen related driver hooks and capability lists.
  28  *
  29  * A program may use multiple rendering contexts (iris_context), but
  30  * they all share a common screen (iris_screen).  Global driver state
  31  * can be stored in the screen; it may be accessed by multiple threads.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <sys/ioctl.h>
  37 #include "pipe/p_defines.h"
  38 #include "pipe/p_state.h"
  39 #include "pipe/p_context.h"
  40 #include "pipe/p_screen.h"
  41 #include "util/u_inlines.h"
  42 #include "util/u_format.h"
  43 #include "util/u_upload_mgr.h"
  44 #include "util/ralloc.h"
  45 #include "drm-uapi/i915_drm.h"
  46 #include "iris_context.h"
  47 #include "iris_pipe.h"
  48 #include "iris_resource.h"
  49 #include "iris_screen.h"
  50 #include "intel/compiler/brw_compiler.h"
  51
  52 static void
  53 iris_flush_frontbuffer(struct pipe_screen *_screen,
  54                        struct pipe_resource *resource,
  55                        unsigned level, unsigned layer,
  56                        void *context_private, struct pipe_box *box)
  57 {
  58 }
  59
  60 static const char *
  61 iris_get_vendor(struct pipe_screen *pscreen)
  62 {
  63    return "Mesa Project";
  64 }
  65
  66 static const char *
  67 iris_get_device_vendor(struct pipe_screen *pscreen)
  68 {
  69    return "Intel";
  70 }
  71
  72 static const char *
  73 iris_get_name(struct pipe_screen *pscreen)
  74 {
  75    struct iris_screen *screen = (struct iris_screen *)pscreen;
  76    const char *chipset;
  77
  78    switch (screen->pci_id) {
  79 #undef CHIPSET
  80 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
  81 #include "pci_ids/i965_pci_ids.h"
  82    default:
  83       chipset = "Unknown Intel Chipset";
  84       break;
  85    }
  86    return &chipset[9];
  87 }
  88
  89 static int
  90 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  91 {
  92    struct iris_screen *screen = (struct iris_screen *)pscreen;
  93
  94    switch (param) {
  95    case PIPE_CAP_NPOT_TEXTURES:
  96    case PIPE_CAP_ANISOTROPIC_FILTER:
  97    case PIPE_CAP_POINT_SPRITE:
  98    case PIPE_CAP_OCCLUSION_QUERY:
  99    case PIPE_CAP_QUERY_TIME_ELAPSED:
 100    case PIPE_CAP_TEXTURE_SWIZZLE:
 101    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 102    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 103    case PIPE_CAP_SM3:
 104    case PIPE_CAP_PRIMITIVE_RESTART:
 105    case PIPE_CAP_INDEP_BLEND_ENABLE:
 106    case PIPE_CAP_INDEP_BLEND_FUNC:
 107    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 108    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 109    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 110    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 111    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 112    case PIPE_CAP_TGSI_INSTANCEID:
 113    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 114    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 115    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 116    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 117    case PIPE_CAP_CONDITIONAL_RENDER:
 118    case PIPE_CAP_TEXTURE_BARRIER:
 119    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 120    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 121    case PIPE_CAP_COMPUTE:
 122    case PIPE_CAP_START_INSTANCE:
 123    case PIPE_CAP_QUERY_TIMESTAMP:
 124    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 125    case PIPE_CAP_CUBE_MAP_ARRAY:
 126    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 127    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 128    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 129    case PIPE_CAP_TEXTURE_QUERY_LOD:
 130    case PIPE_CAP_SAMPLE_SHADING:
 131    case PIPE_CAP_DRAW_INDIRECT:
 132    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 133    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 134    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 135    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 136    case PIPE_CAP_ACCELERATED:
 137    case PIPE_CAP_UMA:
 138    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 139    case PIPE_CAP_CLIP_HALFZ:
 140    case PIPE_CAP_TGSI_TEXCOORD:
 141    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 142    case PIPE_CAP_DOUBLES:
 143    case PIPE_CAP_INT64:
 144    case PIPE_CAP_INT64_DIVMOD:
 145    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 146    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 147    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 148    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 149    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 150    case PIPE_CAP_CULL_DISTANCE:
 151    case PIPE_CAP_PACKED_UNIFORMS:
 152    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 153    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 154    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 155    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 156    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 157    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 158    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 159    case PIPE_CAP_POST_DEPTH_COVERAGE:
 160    case PIPE_CAP_QUERY_SO_OVERFLOW:
 161    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 162    case PIPE_CAP_TGSI_CLOCK:
 163    case PIPE_CAP_TGSI_BALLOT:
 164       return true;
 165
 166    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 167    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 168    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 169    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 170    case PIPE_CAP_USER_VERTEX_BUFFERS:
 171    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 172    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 173    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 174    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 175    case PIPE_CAP_FAKE_SW_MSAA:
 176    case PIPE_CAP_VERTEXID_NOBASE:
 177    case PIPE_CAP_FENCE_SIGNAL:
 178    case PIPE_CAP_CONSTBUF0_FLAGS:
 179    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 180    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 181    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 182    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 183    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 184    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 185    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 186    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 187    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 188    case PIPE_CAP_GENERATE_MIPMAP:
 189    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 190    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 191    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 192    case PIPE_CAP_TILE_RASTER_ORDER:
 193    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 194    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 195    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 196    case PIPE_CAP_BINDLESS_TEXTURE:
 197    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 198       return false;
 199
 200    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 201       /* Intel GPUs don't support PIPE_TEX_WRAP_MIRROR_CLAMP or
 202        * PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER.
 203        */
 204       return false;
 205
 206    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 207       return 1;
 208    case PIPE_CAP_MAX_RENDER_TARGETS:
 209       return BRW_MAX_DRAW_BUFFERS;
 210    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 211    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 212       return 15; /* 16384x16384 */
 213    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 214       return 12; /* 2048x2048 */
 215    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 216       return 4;
 217    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 218       return 2048;
 219    case PIPE_CAP_MIN_TEXEL_OFFSET:
 220       return -8;
 221    case PIPE_CAP_MAX_TEXEL_OFFSET:
 222       return 7;
 223    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 224       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 225    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 226       return BRW_MAX_SOL_BINDINGS;
 227    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 228       return 460;
 229    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 230       return 140;
 231    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 232       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 233       return 32;
 234    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 235       /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
 236        * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
 237        * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
 238        * GPU and the CPU can be updating disjoint regions of the buffer
 239        * simultaneously and that will break if the regions overlap the same
 240        * cacheline.
 241        */
 242       return 64;
 243    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 244       return 64; // XXX: ?
 245    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 246       return 16;
 247    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 248       return true; // XXX: ?????
 249    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 250       return 1 << 27; /* 128MB */
 251    case PIPE_CAP_MAX_VIEWPORTS:
 252       return 16;
 253    case PIPE_CAP_ENDIANNESS:
 254       return PIPE_ENDIAN_LITTLE;
 255    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 256       return 256;
 257    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 258       return 1024;
 259    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 260       return 4;
 261    case PIPE_CAP_TEXTURE_GATHER_SM5:
 262       return 1;
 263    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 264       return -32;
 265    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 266       return 31;
 267    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 268    case PIPE_CAP_MAX_VERTEX_STREAMS:
 269       return 4;
 270    case PIPE_CAP_VENDOR_ID:
 271       return 0x8086;
 272    case PIPE_CAP_DEVICE_ID:
 273       return screen->pci_id;
 274    case PIPE_CAP_VIDEO_MEMORY:
 275       return 0xffffffff; // XXX: bogus
 276    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 277       return 2048;
 278    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 279       return 32;
 280    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 281       return 0;
 282    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 283    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 284    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 285    case PIPE_CAP_TGSI_TXQS:
 286    case PIPE_CAP_SHAREABLE_SHADERS:
 287    case PIPE_CAP_CLEAR_TEXTURE:
 288    case PIPE_CAP_DRAW_PARAMETERS:
 289    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 290    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 291    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 292    case PIPE_CAP_INVALIDATE_BUFFER:
 293    case PIPE_CAP_STRING_MARKER:
 294    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 295    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 296    case PIPE_CAP_QUERY_MEMORY_INFO:
 297    case PIPE_CAP_PCI_GROUP:
 298    case PIPE_CAP_PCI_BUS:
 299    case PIPE_CAP_PCI_DEVICE:
 300    case PIPE_CAP_PCI_FUNCTION:
 301    case PIPE_CAP_TGSI_VOTE:
 302    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 303    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 304    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 305    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 306    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 307    case PIPE_CAP_NATIVE_FENCE_FD:
 308    case PIPE_CAP_TGSI_FS_FBFETCH:
 309    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 310    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 311    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 312    case PIPE_CAP_MEMOBJ:
 313    case PIPE_CAP_LOAD_CONSTBUF:
 314    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 315    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 316    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 317       // XXX: TODO: fill these out
 318       break;
 319    }
 320    return 0;
 321 }
 322
 323 static float
 324 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 325 {
 326    switch (param) {
 327    case PIPE_CAPF_MAX_LINE_WIDTH:
 328    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 329       return 7.375f;
 330
 331    case PIPE_CAPF_MAX_POINT_WIDTH:
 332    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 333       return 255.0f;
 334
 335    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 336       return 16.0f;
 337    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 338       return 15.0f;
 339    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 340    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 341    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 342       return 0.0f;
 343    default:
 344       unreachable("unknown param");
 345    }
 346 }
 347
 348 static int
 349 iris_get_shader_param(struct pipe_screen *pscreen,
 350                       enum pipe_shader_type p_stage,
 351                       enum pipe_shader_cap param)
 352 {
 353    struct iris_screen *screen = (struct iris_screen *)pscreen;
 354    struct brw_compiler *compiler = screen->compiler;
 355    gl_shader_stage stage = stage_from_pipe(p_stage);
 356
 357    /* this is probably not totally correct.. but it's a start: */
 358    switch (param) {
 359    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 360       return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
 361    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 362    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 363    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 364       return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
 365
 366    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 367       return UINT_MAX;
 368
 369    case PIPE_SHADER_CAP_MAX_INPUTS:
 370       return stage == MESA_SHADER_VERTEX ? 16 : 32;
 371    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 372       return 32;
 373    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 374       return 16 * 1024 * sizeof(float);
 375    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 376       return 16;
 377    case PIPE_SHADER_CAP_MAX_TEMPS:
 378       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 379    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 380       return 0;
 381    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 382       return !compiler->glsl_compiler_options[stage].EmitNoIndirectInput;
 383    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 384       return !compiler->glsl_compiler_options[stage].EmitNoIndirectOutput;
 385    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 386       return !compiler->glsl_compiler_options[stage].EmitNoIndirectTemp;
 387    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 388       return 1;
 389    case PIPE_SHADER_CAP_SUBROUTINES:
 390       return 0;
 391    case PIPE_SHADER_CAP_INTEGERS:
 392    case PIPE_SHADER_CAP_SCALAR_ISA:
 393       return 1;
 394    case PIPE_SHADER_CAP_INT64_ATOMICS:
 395    case PIPE_SHADER_CAP_FP16:
 396       return 0;
 397    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 398    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 399    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 400       return IRIS_MAX_TEXTURE_SAMPLERS;
 401    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 402       return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
 403    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 404    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 405       return 0;
 406    case PIPE_SHADER_CAP_PREFERRED_IR:
 407       return PIPE_SHADER_IR_NIR;
 408    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 409       return 0;
 410    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 411       return 32;
 412    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 413    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 414    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 415    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 416    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 417    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 418    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 419    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 420       return 0;
 421    default:
 422       unreachable("unknown shader param");
 423    }
 424 }
 425
 426 static int
 427 iris_get_compute_param(struct pipe_screen *pscreen,
 428                        enum pipe_shader_ir ir_type,
 429                        enum pipe_compute_cap param,
 430                        void *ret)
 431 {
 432    /* TODO: compute shaders */
 433    return 0;
 434 }
 435
 436 static uint64_t
 437 iris_get_timestamp(struct pipe_screen *pscreen)
 438 {
 439    return 0;
 440 }
 441
 442 static void
 443 iris_destroy_screen(struct pipe_screen *pscreen)
 444 {
 445    struct iris_screen *screen = (struct iris_screen *) pscreen;
 446    iris_bo_unreference(screen->workaround_bo);
 447    ralloc_free(screen);
 448 }
 449
 450 static void
 451 iris_fence_reference(struct pipe_screen *screen,
 452                      struct pipe_fence_handle **ptr,
 453                      struct pipe_fence_handle *fence)
 454 {
 455 }
 456
 457 static boolean
 458 iris_fence_finish(struct pipe_screen *screen,
 459                   struct pipe_context *ctx,
 460                   struct pipe_fence_handle *fence,
 461                   uint64_t timeout)
 462 {
 463    return true;
 464 }
 465
 466 static void
 467 iris_query_memory_info(struct pipe_screen *pscreen,
 468                        struct pipe_memory_info *info)
 469 {
 470 }
 471
 472 static const void *
 473 iris_get_compiler_options(struct pipe_screen *pscreen,
 474                           enum pipe_shader_ir ir,
 475                           enum pipe_shader_type pstage)
 476 {
 477    struct iris_screen *screen = (struct iris_screen *) pscreen;
 478    gl_shader_stage stage = stage_from_pipe(pstage);
 479    assert(ir == PIPE_SHADER_IR_NIR);
 480
 481    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 482 }
 483
 484 static int
 485 iris_getparam(struct iris_screen *screen, int param, int *value)
 486 {
 487    struct drm_i915_getparam gp = { .param = param, .value = value };
 488
 489    if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 490       return -errno;
 491
 492    return 0;
 493 }
 494
 495 static bool
 496 iris_getparam_boolean(struct iris_screen *screen, int param)
 497 {
 498    int value = 0;
 499    return (iris_getparam(screen, param, &value) == 0) && value;
 500 }
 501
 502 static int
 503 iris_getparam_integer(struct iris_screen *screen, int param)
 504 {
 505    int value = -1;
 506
 507    if (iris_getparam(screen, param, &value) == 0)
 508       return value;
 509
 510    return -1;
 511 }
 512
 513 static void
 514 iris_shader_debug_log(void *data, const char *fmt, ...)
 515 {
 516    struct pipe_debug_callback *dbg = data;
 517    unsigned id = 0;
 518    va_list args;
 519
 520    if (!dbg->debug_message)
 521       return;
 522
 523    va_start(args, fmt);
 524    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
 525    va_end(args);
 526 }
 527
 528 static void
 529 iris_shader_perf_log(void *data, const char *fmt, ...)
 530 {
 531    struct pipe_debug_callback *dbg = data;
 532    unsigned id = 0;
 533    va_list args;
 534
 535    if (!dbg->debug_message)
 536       return;
 537
 538    va_start(args, fmt);
 539    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
 540    va_end(args);
 541 }
 542
 543 struct pipe_screen *
 544 iris_screen_create(int fd)
 545 {
 546    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 547    if (!screen)
 548       return NULL;
 549
 550    screen->fd = fd;
 551    screen->pci_id = iris_getparam_integer(screen, I915_PARAM_CHIPSET_ID);
 552
 553    if (!gen_get_device_info(screen->pci_id, &screen->devinfo))
 554       return NULL;
 555
 556    screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
 557    if (!screen->bufmgr)
 558       return NULL;
 559
 560    screen->workaround_bo =
 561       iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
 562    if (!screen->workaround_bo)
 563       return NULL;
 564
 565    brw_process_intel_debug_variable();
 566
 567    bool hw_has_swizzling = false; // XXX: detect?
 568    isl_device_init(&screen->isl_dev, &screen->devinfo, hw_has_swizzling);
 569
 570    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 571    screen->compiler->shader_debug_log = iris_shader_debug_log;
 572    screen->compiler->shader_perf_log = iris_shader_perf_log;
 573
 574    slab_create_parent(&screen->transfer_pool,
 575                       sizeof(struct iris_transfer), 64);
 576
 577    struct pipe_screen *pscreen = &screen->base;
 578
 579    iris_init_screen_resource_functions(pscreen);
 580
 581    pscreen->destroy = iris_destroy_screen;
 582    pscreen->get_name = iris_get_name;
 583    pscreen->get_vendor = iris_get_vendor;
 584    pscreen->get_device_vendor = iris_get_device_vendor;
 585    pscreen->get_param = iris_get_param;
 586    pscreen->get_shader_param = iris_get_shader_param;
 587    pscreen->get_compute_param = iris_get_compute_param;
 588    pscreen->get_paramf = iris_get_paramf;
 589    pscreen->get_compiler_options = iris_get_compiler_options;
 590    pscreen->is_format_supported = iris_is_format_supported;
 591    pscreen->context_create = iris_create_context;
 592    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 593    pscreen->get_timestamp = iris_get_timestamp;
 594    pscreen->fence_reference = iris_fence_reference;
 595    pscreen->fence_finish = iris_fence_finish;
 596    pscreen->query_memory_info = iris_query_memory_info;
 597
 598    return pscreen;
 599 }