src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include <sys/ioctl.h>
  26 #include "pipe/p_defines.h"
  27 #include "pipe/p_state.h"
  28 #include "pipe/p_context.h"
  29 #include "pipe/p_screen.h"
  30 #include "util/u_inlines.h"
  31 #include "util/u_format.h"
  32 #include "util/u_upload_mgr.h"
  33 #include "util/ralloc.h"
  34 #include "drm-uapi/i915_drm.h"
  35 #include "iris_context.h"
  36 #include "iris_pipe.h"
  37 #include "iris_resource.h"
  38 #include "iris_screen.h"
  39 #include "intel/compiler/brw_compiler.h"
  40
  41 static void
  42 iris_flush_frontbuffer(struct pipe_screen *_screen,
  43                        struct pipe_resource *resource,
  44                        unsigned level, unsigned layer,
  45                        void *context_private, struct pipe_box *box)
  46 {
  47 }
  48
  49 static const char *
  50 iris_get_vendor(struct pipe_screen *pscreen)
  51 {
  52    return "Mesa Project";
  53 }
  54
  55 static const char *
  56 iris_get_device_vendor(struct pipe_screen *pscreen)
  57 {
  58    return "Intel";
  59 }
  60
  61 static const char *
  62 iris_get_name(struct pipe_screen *pscreen)
  63 {
  64    struct iris_screen *screen = (struct iris_screen *)pscreen;
  65    const char *chipset;
  66
  67    switch (screen->pci_id) {
  68 #undef CHIPSET
  69 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
  70 #include "pci_ids/i965_pci_ids.h"
  71    default:
  72       chipset = "Unknown Intel Chipset";
  73       break;
  74    }
  75    return &chipset[9];
  76 }
  77
  78 static int
  79 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  80 {
  81    struct iris_screen *screen = (struct iris_screen *)pscreen;
  82
  83    switch (param) {
  84    case PIPE_CAP_NPOT_TEXTURES:
  85    case PIPE_CAP_ANISOTROPIC_FILTER:
  86    case PIPE_CAP_POINT_SPRITE:
  87    case PIPE_CAP_OCCLUSION_QUERY:
  88    case PIPE_CAP_QUERY_TIME_ELAPSED:
  89    case PIPE_CAP_TEXTURE_SWIZZLE:
  90    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  91    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  92    case PIPE_CAP_SM3:
  93    case PIPE_CAP_PRIMITIVE_RESTART:
  94    case PIPE_CAP_INDEP_BLEND_ENABLE:
  95    case PIPE_CAP_INDEP_BLEND_FUNC:
  96    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
  97    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  98    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  99    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 100    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 101    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 102    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 103    case PIPE_CAP_TGSI_INSTANCEID:
 104    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 105    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 106    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 107    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 108    case PIPE_CAP_CONDITIONAL_RENDER:
 109    case PIPE_CAP_TEXTURE_BARRIER:
 110    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 111    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 112    case PIPE_CAP_COMPUTE:
 113    case PIPE_CAP_START_INSTANCE:
 114    case PIPE_CAP_QUERY_TIMESTAMP:
 115    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 116    case PIPE_CAP_CUBE_MAP_ARRAY:
 117    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 118    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 119    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 120    case PIPE_CAP_TEXTURE_QUERY_LOD:
 121    case PIPE_CAP_SAMPLE_SHADING:
 122    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 123    case PIPE_CAP_DRAW_INDIRECT:
 124    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 125    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 126    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 127    case PIPE_CAP_ACCELERATED:
 128    case PIPE_CAP_UMA:
 129    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 130    case PIPE_CAP_CLIP_HALFZ:
 131       return true;
 132
 133    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 134    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 135    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 136    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 137    case PIPE_CAP_USER_VERTEX_BUFFERS:
 138    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 139    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 140    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 141    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 142    case PIPE_CAP_TGSI_TEXCOORD:
 143    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 144    case PIPE_CAP_FAKE_SW_MSAA:
 145    case PIPE_CAP_VERTEXID_NOBASE:
 146       return false;
 147
 148    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 149       return 1;
 150    case PIPE_CAP_MAX_RENDER_TARGETS:
 151       return BRW_MAX_DRAW_BUFFERS;
 152    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 153    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 154       return 15; /* 16384x16384 */
 155    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 156       return 12; /* 2048x2048 */
 157    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 158       return 4;
 159    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 160       return 2048;
 161    case PIPE_CAP_MIN_TEXEL_OFFSET:
 162       return -8;
 163    case PIPE_CAP_MAX_TEXEL_OFFSET:
 164       return 7;
 165    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 166       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 167    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 168       return BRW_MAX_SOL_BINDINGS;
 169    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 170       return 460;
 171    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 172       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 173       return 32;
 174    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 175       return 64; // XXX: ?
 176    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 177       return 1;
 178    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 179       return true; // XXX: ?????
 180    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 181       return 1 << 27; /* 128MB */
 182    case PIPE_CAP_MAX_VIEWPORTS:
 183       return 16;
 184    case PIPE_CAP_ENDIANNESS:
 185       return PIPE_ENDIAN_LITTLE;
 186    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 187       return 256;
 188    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 189       return 128;
 190    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 191    case PIPE_CAP_TEXTURE_GATHER_SM5:
 192       return 0; // XXX:
 193    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 194       return -32;
 195    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 196       return 31;
 197    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 198    case PIPE_CAP_MAX_VERTEX_STREAMS:
 199       return 4;
 200    case PIPE_CAP_VENDOR_ID:
 201       return 0x8086;
 202    case PIPE_CAP_DEVICE_ID:
 203       return screen->pci_id;
 204    case PIPE_CAP_VIDEO_MEMORY:
 205       return 0xffffffff; // XXX: bogus
 206    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 207       return 2048;
 208    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 209       return false; // XXX: what is this?
 210    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 211    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 212    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 213    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 214    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 215    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 216    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 217    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 218    case PIPE_CAP_TGSI_TXQS:
 219    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 220    case PIPE_CAP_SHAREABLE_SHADERS:
 221    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 222    case PIPE_CAP_CLEAR_TEXTURE:
 223    case PIPE_CAP_DRAW_PARAMETERS:
 224    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 225    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 226    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 227    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 228    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 229    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 230    case PIPE_CAP_INVALIDATE_BUFFER:
 231    case PIPE_CAP_GENERATE_MIPMAP:
 232    case PIPE_CAP_STRING_MARKER:
 233    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 234    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 235    case PIPE_CAP_QUERY_MEMORY_INFO:
 236    case PIPE_CAP_PCI_GROUP:
 237    case PIPE_CAP_PCI_BUS:
 238    case PIPE_CAP_PCI_DEVICE:
 239    case PIPE_CAP_PCI_FUNCTION:
 240    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 241    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 242    case PIPE_CAP_CULL_DISTANCE:
 243    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 244    case PIPE_CAP_TGSI_VOTE:
 245    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 246    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 247    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 248    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 249    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 250    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 251    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 252    case PIPE_CAP_NATIVE_FENCE_FD:
 253    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 254    case PIPE_CAP_TGSI_FS_FBFETCH:
 255    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 256    case PIPE_CAP_DOUBLES:
 257    case PIPE_CAP_INT64:
 258    case PIPE_CAP_INT64_DIVMOD:
 259    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 260    case PIPE_CAP_TGSI_CLOCK:
 261    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 262    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 263    case PIPE_CAP_TGSI_BALLOT:
 264    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 265    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 266    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 267    case PIPE_CAP_POST_DEPTH_COVERAGE:
 268    case PIPE_CAP_BINDLESS_TEXTURE:
 269    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 270    case PIPE_CAP_QUERY_SO_OVERFLOW:
 271    case PIPE_CAP_MEMOBJ:
 272    case PIPE_CAP_LOAD_CONSTBUF:
 273    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 274    case PIPE_CAP_TILE_RASTER_ORDER:
 275    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 276    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 277    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 278       // XXX: TODO: fill these out
 279       break;
 280    }
 281    return 0;
 282 }
 283
 284 static float
 285 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 286 {
 287    switch (param) {
 288    case PIPE_CAPF_MAX_LINE_WIDTH:
 289    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 290       return 7.375f;
 291
 292    case PIPE_CAPF_MAX_POINT_WIDTH:
 293    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 294       return 255.0f;
 295
 296    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 297       return 16.0f;
 298    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 299       return 15.0f;
 300    default:
 301       unreachable("unknown param");
 302    }
 303 }
 304
 305 static int
 306 iris_get_shader_param(struct pipe_screen *pscreen,
 307                       enum pipe_shader_type shader,
 308                       enum pipe_shader_cap param)
 309 {
 310    struct iris_screen *screen = (struct iris_screen *)pscreen;
 311    struct brw_compiler *compiler = screen->compiler;
 312
 313    /* this is probably not totally correct.. but it's a start: */
 314    switch (param) {
 315    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 316       return shader == PIPE_SHADER_FRAGMENT ? 1024 : 16384;
 317    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 318    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 319    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 320       return shader == PIPE_SHADER_FRAGMENT ? 1024 : 0;
 321
 322    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 323       return UINT_MAX;
 324
 325    case PIPE_SHADER_CAP_MAX_INPUTS:
 326       return shader == PIPE_SHADER_VERTEX ? 16 : 32;
 327    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 328       return 32;
 329    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 330       return 16 * 1024 * sizeof(float);
 331    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 332       return 16;
 333    case PIPE_SHADER_CAP_MAX_TEMPS:
 334       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 335    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 336       return 0;
 337    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 338       return !compiler->glsl_compiler_options[shader].EmitNoIndirectInput;
 339    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 340       return !compiler->glsl_compiler_options[shader].EmitNoIndirectOutput;
 341    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 342       return !compiler->glsl_compiler_options[shader].EmitNoIndirectTemp;
 343    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 344       return 1;
 345    case PIPE_SHADER_CAP_SUBROUTINES:
 346       return 0;
 347    case PIPE_SHADER_CAP_INTEGERS:
 348    case PIPE_SHADER_CAP_SCALAR_ISA:
 349       return 1;
 350    case PIPE_SHADER_CAP_INT64_ATOMICS:
 351    case PIPE_SHADER_CAP_FP16:
 352       return 0;
 353    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 354    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 355    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 356    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 357       return IRIS_MAX_TEXTURE_SAMPLERS;
 358    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 359    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 360       return 0;
 361    case PIPE_SHADER_CAP_PREFERRED_IR:
 362       return PIPE_SHADER_IR_NIR;
 363    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 364       return 0;
 365    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 366       return 32;
 367    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 368    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 369    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 370    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 371    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 372    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 373    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 374    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 375       return 0;
 376    default:
 377       unreachable("unknown shader param");
 378    }
 379 }
 380
 381 static int
 382 iris_get_compute_param(struct pipe_screen *pscreen,
 383                        enum pipe_shader_ir ir_type,
 384                        enum pipe_compute_cap param,
 385                        void *ret)
 386 {
 387    /* TODO: compute shaders */
 388    return 0;
 389 }
 390
 391 static uint64_t
 392 iris_get_timestamp(struct pipe_screen *pscreen)
 393 {
 394    return 0;
 395 }
 396
 397 static void
 398 iris_destroy_screen(struct pipe_screen *pscreen)
 399 {
 400    struct iris_screen *screen = (struct iris_screen *) pscreen;
 401    ralloc_free(screen);
 402 }
 403
 404 static void
 405 iris_fence_reference(struct pipe_screen *screen,
 406                      struct pipe_fence_handle **ptr,
 407                      struct pipe_fence_handle *fence)
 408 {
 409 }
 410
 411 static boolean
 412 iris_fence_finish(struct pipe_screen *screen,
 413                   struct pipe_context *ctx,
 414                   struct pipe_fence_handle *fence,
 415                   uint64_t timeout)
 416 {
 417    return true;
 418 }
 419
 420 static void
 421 iris_query_memory_info(struct pipe_screen *pscreen,
 422                        struct pipe_memory_info *info)
 423 {
 424 }
 425
 426 static const void *
 427 iris_get_compiler_options(struct pipe_screen *pscreen,
 428                           enum pipe_shader_ir ir,
 429                           enum pipe_shader_type pstage)
 430 {
 431    struct iris_screen *screen = (struct iris_screen *) pscreen;
 432    gl_shader_stage stage = stage_from_pipe(pstage);
 433    assert(ir == PIPE_SHADER_IR_NIR);
 434
 435    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 436 }
 437
 438 static int
 439 iris_getparam(struct iris_screen *screen, int param, int *value)
 440 {
 441    struct drm_i915_getparam gp = { .param = param, .value = value };
 442
 443    if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 444       return -errno;
 445
 446    return 0;
 447 }
 448
 449 static bool
 450 iris_getparam_boolean(struct iris_screen *screen, int param)
 451 {
 452    int value = 0;
 453    return (iris_getparam(screen, param, &value) == 0) && value;
 454 }
 455
 456 static int
 457 iris_getparam_integer(struct iris_screen *screen, int param)
 458 {
 459    int value = -1;
 460
 461    if (iris_getparam(screen, param, &value) == 0)
 462       return value;
 463
 464    return -1;
 465 }
 466
 467 struct pipe_screen *
 468 iris_screen_create(int fd)
 469 {
 470    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 471    if (!screen)
 472       return NULL;
 473
 474    screen->fd = fd;
 475    screen->pci_id = iris_getparam_integer(screen, I915_PARAM_CHIPSET_ID);
 476
 477    if (!gen_get_device_info(screen->pci_id, &screen->devinfo))
 478       return NULL;
 479
 480    screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
 481    if (!screen->bufmgr)
 482       return NULL;
 483
 484    bool hw_has_swizzling = false; // XXX: detect?
 485    isl_device_init(&screen->isl_dev, &screen->devinfo, hw_has_swizzling);
 486
 487    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 488
 489    struct pipe_screen *pscreen = &screen->base;
 490
 491    iris_init_screen_resource_functions(pscreen);
 492
 493    pscreen->destroy = iris_destroy_screen;
 494    pscreen->get_name = iris_get_name;
 495    pscreen->get_vendor = iris_get_vendor;
 496    pscreen->get_device_vendor = iris_get_device_vendor;
 497    pscreen->get_param = iris_get_param;
 498    pscreen->get_shader_param = iris_get_shader_param;
 499    pscreen->get_compute_param = iris_get_compute_param;
 500    pscreen->get_paramf = iris_get_paramf;
 501    pscreen->get_compiler_options = iris_get_compiler_options;
 502    pscreen->is_format_supported = iris_is_format_supported;
 503    pscreen->context_create = iris_create_context;
 504    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 505    pscreen->get_timestamp = iris_get_timestamp;
 506    pscreen->fence_reference = iris_fence_reference;
 507    pscreen->fence_finish = iris_fence_finish;
 508    pscreen->query_memory_info = iris_query_memory_info;
 509
 510    return pscreen;
 511 }