src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /**
  24  * @file iris_screen.c
  25  *
  26  * Screen related driver hooks and capability lists.
  27  *
  28  * A program may use multiple rendering contexts (iris_context), but
  29  * they all share a common screen (iris_screen).  Global driver state
  30  * can be stored in the screen; it may be accessed by multiple threads.
  31  */
  32
  33 #include <stdio.h>
  34 #include <errno.h>
  35 #include <sys/ioctl.h>
  36 #include "pipe/p_defines.h"
  37 #include "pipe/p_state.h"
  38 #include "pipe/p_context.h"
  39 #include "pipe/p_screen.h"
  40 #include "util/debug.h"
  41 #include "util/u_inlines.h"
  42 #include "util/u_format.h"
  43 #include "util/u_transfer_helper.h"
  44 #include "util/u_upload_mgr.h"
  45 #include "util/ralloc.h"
  46 #include "drm-uapi/i915_drm.h"
  47 #include "iris_context.h"
  48 #include "iris_defines.h"
  49 #include "iris_fence.h"
  50 #include "iris_pipe.h"
  51 #include "iris_resource.h"
  52 #include "iris_screen.h"
  53 #include "intel/compiler/brw_compiler.h"
  54
  55 static void
  56 iris_flush_frontbuffer(struct pipe_screen *_screen,
  57                        struct pipe_resource *resource,
  58                        unsigned level, unsigned layer,
  59                        void *context_private, struct pipe_box *box)
  60 {
  61 }
  62
  63 static const char *
  64 iris_get_vendor(struct pipe_screen *pscreen)
  65 {
  66    return "Mesa Project";
  67 }
  68
  69 static const char *
  70 iris_get_device_vendor(struct pipe_screen *pscreen)
  71 {
  72    return "Intel";
  73 }
  74
  75 static const char *
  76 iris_get_name(struct pipe_screen *pscreen)
  77 {
  78    struct iris_screen *screen = (struct iris_screen *)pscreen;
  79    const char *chipset;
  80
  81    switch (screen->pci_id) {
  82 #undef CHIPSET
  83 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
  84 #include "pci_ids/i965_pci_ids.h"
  85    default:
  86       chipset = "Unknown Intel Chipset";
  87       break;
  88    }
  89    return chipset;
  90 }
  91
  92 static int
  93 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  94 {
  95    struct iris_screen *screen = (struct iris_screen *)pscreen;
  96    const struct gen_device_info *devinfo = &screen->devinfo;
  97
  98    switch (param) {
  99    case PIPE_CAP_NPOT_TEXTURES:
 100    case PIPE_CAP_ANISOTROPIC_FILTER:
 101    case PIPE_CAP_POINT_SPRITE:
 102    case PIPE_CAP_OCCLUSION_QUERY:
 103    case PIPE_CAP_QUERY_TIME_ELAPSED:
 104    case PIPE_CAP_TEXTURE_SWIZZLE:
 105    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 106    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 107    case PIPE_CAP_SM3:
 108    case PIPE_CAP_PRIMITIVE_RESTART:
 109    case PIPE_CAP_INDEP_BLEND_ENABLE:
 110    case PIPE_CAP_INDEP_BLEND_FUNC:
 111    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 112    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 113    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 114    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 115    case PIPE_CAP_TGSI_INSTANCEID:
 116    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 117    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 118    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 119    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 120    case PIPE_CAP_CONDITIONAL_RENDER:
 121    case PIPE_CAP_TEXTURE_BARRIER:
 122    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 123    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 124    case PIPE_CAP_COMPUTE:
 125    case PIPE_CAP_START_INSTANCE:
 126    case PIPE_CAP_QUERY_TIMESTAMP:
 127    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 128    case PIPE_CAP_CUBE_MAP_ARRAY:
 129    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 130    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 131    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 132    case PIPE_CAP_TEXTURE_QUERY_LOD:
 133    case PIPE_CAP_SAMPLE_SHADING:
 134    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 135    case PIPE_CAP_DRAW_INDIRECT:
 136    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 137    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 138    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 139    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 140    case PIPE_CAP_ACCELERATED:
 141    case PIPE_CAP_UMA:
 142    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 143    case PIPE_CAP_CLIP_HALFZ:
 144    case PIPE_CAP_TGSI_TEXCOORD:
 145    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 146    case PIPE_CAP_DOUBLES:
 147    case PIPE_CAP_INT64:
 148    case PIPE_CAP_INT64_DIVMOD:
 149    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 150    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 151    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 152    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 153    case PIPE_CAP_CULL_DISTANCE:
 154    case PIPE_CAP_PACKED_UNIFORMS:
 155    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 156    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 157    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 158    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 159    case PIPE_CAP_QUERY_SO_OVERFLOW:
 160    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 161    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 162    case PIPE_CAP_TGSI_TXQS:
 163    case PIPE_CAP_TGSI_CLOCK:
 164    case PIPE_CAP_TGSI_BALLOT:
 165    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 166    case PIPE_CAP_CLEAR_TEXTURE:
 167    case PIPE_CAP_TGSI_VOTE:
 168    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 169    case PIPE_CAP_TEXTURE_GATHER_SM5:
 170    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 171    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 172    case PIPE_CAP_LOAD_CONSTBUF:
 173    case PIPE_CAP_NIR_COMPACT_ARRAYS:
 174    case PIPE_CAP_DRAW_PARAMETERS:
 175    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 176    case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
 177       return true;
 178    case PIPE_CAP_TGSI_FS_FBFETCH:
 179    case PIPE_CAP_POST_DEPTH_COVERAGE:
 180    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 181       return devinfo->gen >= 9;
 182    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 183       return 1;
 184    case PIPE_CAP_MAX_RENDER_TARGETS:
 185       return BRW_MAX_DRAW_BUFFERS;
 186    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 187    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 188       return IRIS_MAX_MIPLEVELS; /* 16384x16384 */
 189    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 190       return 12; /* 2048x2048 */
 191    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 192       return 4;
 193    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 194       return 2048;
 195    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 196       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 197    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 198       return BRW_MAX_SOL_BINDINGS;
 199    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 200       return 460;
 201    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 202       return 140;
 203    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 204       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 205       return 32;
 206    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 207       return IRIS_MAP_BUFFER_ALIGNMENT;
 208    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 209       /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
 210        * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
 211        * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
 212        * GPU and the CPU can be updating disjoint regions of the buffer
 213        * simultaneously and that will break if the regions overlap the same
 214        * cacheline.
 215        */
 216       return 64;
 217    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 218       return 1 << 27;
 219    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 220       return 16; // XXX: u_screen says 256 is the minimum value...
 221    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 222       return true; // XXX: ?????
 223    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 224       return IRIS_MAX_TEXTURE_BUFFER_SIZE;
 225    case PIPE_CAP_MAX_VIEWPORTS:
 226       return 16;
 227    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 228       return 256;
 229    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 230       return 1024;
 231    case PIPE_CAP_MAX_GS_INVOCATIONS:
 232       return 32;
 233    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 234       return 4;
 235    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 236       return -32;
 237    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 238       return 31;
 239    case PIPE_CAP_MAX_VERTEX_STREAMS:
 240       return 4;
 241    case PIPE_CAP_VENDOR_ID:
 242       return 0x8086;
 243    case PIPE_CAP_DEVICE_ID:
 244       return screen->pci_id;
 245    case PIPE_CAP_VIDEO_MEMORY:
 246       return INT_MAX; // XXX: bogus
 247    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 248    case PIPE_CAP_MAX_VARYINGS:
 249       return 32;
 250    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 251       /* AMD_pinned_memory assumes the flexibility of using client memory
 252        * for any buffer (incl. vertex buffers) which rules out the prospect
 253        * of using snooped buffers, as using snooped buffers without
 254        * cogniscience is likely to be detrimental to performance and require
 255        * extensive checking in the driver for correctness, e.g. to prevent
 256        * illegal snoop <-> snoop transfers.
 257        */
 258       return devinfo->has_llc;
 259
 260    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 261       return PIPE_CONTEXT_PRIORITY_LOW |
 262              PIPE_CONTEXT_PRIORITY_MEDIUM |
 263              PIPE_CONTEXT_PRIORITY_HIGH;
 264
 265    // XXX: don't hardcode 00:00:02.0 PCI here
 266    case PIPE_CAP_PCI_GROUP:
 267       return 0;
 268    case PIPE_CAP_PCI_BUS:
 269       return 0;
 270    case PIPE_CAP_PCI_DEVICE:
 271       return 2;
 272    case PIPE_CAP_PCI_FUNCTION:
 273       return 0;
 274
 275    default:
 276       return u_pipe_screen_get_param_defaults(pscreen, param);
 277    }
 278    return 0;
 279 }
 280
 281 static float
 282 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 283 {
 284    switch (param) {
 285    case PIPE_CAPF_MAX_LINE_WIDTH:
 286    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 287       return 7.375f;
 288
 289    case PIPE_CAPF_MAX_POINT_WIDTH:
 290    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 291       return 255.0f;
 292
 293    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 294       return 16.0f;
 295    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 296       return 15.0f;
 297    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 298    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 299    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 300       return 0.0f;
 301    default:
 302       unreachable("unknown param");
 303    }
 304 }
 305
 306 static int
 307 iris_get_shader_param(struct pipe_screen *pscreen,
 308                       enum pipe_shader_type p_stage,
 309                       enum pipe_shader_cap param)
 310 {
 311    gl_shader_stage stage = stage_from_pipe(p_stage);
 312
 313    /* this is probably not totally correct.. but it's a start: */
 314    switch (param) {
 315    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 316       return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
 317    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 318    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 319    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 320       return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
 321
 322    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 323       return UINT_MAX;
 324
 325    case PIPE_SHADER_CAP_MAX_INPUTS:
 326       return stage == MESA_SHADER_VERTEX ? 16 : 32;
 327    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 328       return 32;
 329    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 330       return 16 * 1024 * sizeof(float);
 331    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 332       return 16;
 333    case PIPE_SHADER_CAP_MAX_TEMPS:
 334       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 335    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 336       return 0;
 337    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 338    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 339    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 340    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 341       /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
 342        * which we don't want.  Our compiler backend will check brw_compiler's
 343        * options and call nir_lower_indirect_derefs appropriately anyway.
 344        */
 345       return true;
 346    case PIPE_SHADER_CAP_SUBROUTINES:
 347       return 0;
 348    case PIPE_SHADER_CAP_INTEGERS:
 349    case PIPE_SHADER_CAP_SCALAR_ISA:
 350       return 1;
 351    case PIPE_SHADER_CAP_INT64_ATOMICS:
 352    case PIPE_SHADER_CAP_FP16:
 353       return 0;
 354    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 355    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 356    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 357       return IRIS_MAX_TEXTURE_SAMPLERS;
 358    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 359       return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
 360    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 361    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 362       return 0;
 363    case PIPE_SHADER_CAP_PREFERRED_IR:
 364       return PIPE_SHADER_IR_NIR;
 365    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 366       return 1 << PIPE_SHADER_IR_NIR;
 367    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 368       return 32;
 369    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 370    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 371    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 372    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 373    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 374    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 375    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 376    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 377       return 0;
 378    default:
 379       unreachable("unknown shader param");
 380    }
 381 }
 382
 383 static int
 384 iris_get_compute_param(struct pipe_screen *pscreen,
 385                        enum pipe_shader_ir ir_type,
 386                        enum pipe_compute_cap param,
 387                        void *ret)
 388 {
 389    struct iris_screen *screen = (struct iris_screen *)pscreen;
 390    const struct gen_device_info *devinfo = &screen->devinfo;
 391
 392    const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
 393    const uint32_t max_invocations = 32 * max_threads;
 394
 395 #define RET(x) do {                  \
 396    if (ret)                          \
 397       memcpy(ret, x, sizeof(x));     \
 398    return sizeof(x);                 \
 399 } while (0)
 400
 401    switch (param) {
 402    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 403       RET((uint32_t []){ 32 });
 404
 405    case PIPE_COMPUTE_CAP_IR_TARGET:
 406       if (ret)
 407          strcpy(ret, "gen");
 408       return 4;
 409
 410    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 411       RET((uint64_t []) { 3 });
 412
 413    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 414       RET(((uint64_t []) { 65535, 65535, 65535 }));
 415
 416    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 417       /* MaxComputeWorkGroupSize[0..2] */
 418       RET(((uint64_t []) {max_invocations, max_invocations, max_invocations}));
 419
 420    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 421       /* MaxComputeWorkGroupInvocations */
 422       RET((uint64_t []) { max_invocations });
 423
 424    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 425       /* MaxComputeSharedMemorySize */
 426       RET((uint64_t []) { 64 * 1024 });
 427
 428    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 429       RET((uint32_t []) { 1 });
 430
 431    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 432       RET((uint32_t []) { BRW_SUBGROUP_SIZE });
 433
 434    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 435    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 436    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 437    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 438    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 439    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 440    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 441       // XXX: I think these are for Clover...
 442       return 0;
 443
 444    default:
 445       unreachable("unknown compute param");
 446    }
 447 }
 448
 449 static uint64_t
 450 iris_get_timestamp(struct pipe_screen *pscreen)
 451 {
 452    struct iris_screen *screen = (struct iris_screen *) pscreen;
 453    const unsigned TIMESTAMP = 0x2358;
 454    uint64_t result;
 455
 456    iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
 457
 458    result = iris_timebase_scale(&screen->devinfo, result);
 459    result &= (1ull << TIMESTAMP_BITS) - 1;
 460
 461    return result;
 462 }
 463
 464 static void
 465 iris_destroy_screen(struct pipe_screen *pscreen)
 466 {
 467    struct iris_screen *screen = (struct iris_screen *) pscreen;
 468    iris_bo_unreference(screen->workaround_bo);
 469    u_transfer_helper_destroy(pscreen->transfer_helper);
 470    iris_bufmgr_destroy(screen->bufmgr);
 471    ralloc_free(screen);
 472 }
 473
 474 static void
 475 iris_query_memory_info(struct pipe_screen *pscreen,
 476                        struct pipe_memory_info *info)
 477 {
 478 }
 479
 480 static const void *
 481 iris_get_compiler_options(struct pipe_screen *pscreen,
 482                           enum pipe_shader_ir ir,
 483                           enum pipe_shader_type pstage)
 484 {
 485    struct iris_screen *screen = (struct iris_screen *) pscreen;
 486    gl_shader_stage stage = stage_from_pipe(pstage);
 487    assert(ir == PIPE_SHADER_IR_NIR);
 488
 489    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 490 }
 491
 492 static int
 493 iris_getparam(struct iris_screen *screen, int param, int *value)
 494 {
 495    struct drm_i915_getparam gp = { .param = param, .value = value };
 496
 497    if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 498       return -errno;
 499
 500    return 0;
 501 }
 502
 503 static int
 504 iris_getparam_integer(struct iris_screen *screen, int param)
 505 {
 506    int value = -1;
 507
 508    if (iris_getparam(screen, param, &value) == 0)
 509       return value;
 510
 511    return -1;
 512 }
 513
 514 static void
 515 iris_shader_debug_log(void *data, const char *fmt, ...)
 516 {
 517    struct pipe_debug_callback *dbg = data;
 518    unsigned id = 0;
 519    va_list args;
 520
 521    if (!dbg->debug_message)
 522       return;
 523
 524    va_start(args, fmt);
 525    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
 526    va_end(args);
 527 }
 528
 529 static void
 530 iris_shader_perf_log(void *data, const char *fmt, ...)
 531 {
 532    struct pipe_debug_callback *dbg = data;
 533    unsigned id = 0;
 534    va_list args;
 535
 536    if (!dbg->debug_message)
 537       return;
 538
 539    va_start(args, fmt);
 540    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
 541    va_end(args);
 542 }
 543
 544 struct pipe_screen *
 545 iris_screen_create(int fd)
 546 {
 547    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 548    if (!screen)
 549       return NULL;
 550
 551    screen->fd = fd;
 552    screen->pci_id = iris_getparam_integer(screen, I915_PARAM_CHIPSET_ID);
 553
 554    if (!gen_get_device_info(screen->pci_id, &screen->devinfo))
 555       return NULL;
 556
 557    if (screen->devinfo.gen < 8 || screen->devinfo.is_cherryview)
 558       return NULL;
 559
 560    screen->devinfo.timestamp_frequency =
 561       iris_getparam_integer(screen, I915_PARAM_CS_TIMESTAMP_FREQUENCY);
 562
 563    screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
 564    if (!screen->bufmgr)
 565       return NULL;
 566
 567    screen->workaround_bo =
 568       iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
 569    if (!screen->workaround_bo)
 570       return NULL;
 571
 572    brw_process_intel_debug_variable();
 573
 574    screen->precompile = env_var_as_boolean("shader_precompile", true);
 575
 576    isl_device_init(&screen->isl_dev, &screen->devinfo, false);
 577
 578    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 579    screen->compiler->shader_debug_log = iris_shader_debug_log;
 580    screen->compiler->shader_perf_log = iris_shader_perf_log;
 581    screen->compiler->supports_pull_constants = false;
 582
 583    slab_create_parent(&screen->transfer_pool,
 584                       sizeof(struct iris_transfer), 64);
 585
 586    screen->subslice_total =
 587       iris_getparam_integer(screen, I915_PARAM_SUBSLICE_TOTAL);
 588    assert(screen->subslice_total >= 1);
 589
 590    struct pipe_screen *pscreen = &screen->base;
 591
 592    iris_init_screen_fence_functions(pscreen);
 593    iris_init_screen_resource_functions(pscreen);
 594
 595    pscreen->destroy = iris_destroy_screen;
 596    pscreen->get_name = iris_get_name;
 597    pscreen->get_vendor = iris_get_vendor;
 598    pscreen->get_device_vendor = iris_get_device_vendor;
 599    pscreen->get_param = iris_get_param;
 600    pscreen->get_shader_param = iris_get_shader_param;
 601    pscreen->get_compute_param = iris_get_compute_param;
 602    pscreen->get_paramf = iris_get_paramf;
 603    pscreen->get_compiler_options = iris_get_compiler_options;
 604    pscreen->is_format_supported = iris_is_format_supported;
 605    pscreen->context_create = iris_create_context;
 606    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 607    pscreen->get_timestamp = iris_get_timestamp;
 608    pscreen->query_memory_info = iris_query_memory_info;
 609
 610    return pscreen;
 611 }