src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include <sys/ioctl.h>
  26 #include "pipe/p_defines.h"
  27 #include "pipe/p_state.h"
  28 #include "pipe/p_context.h"
  29 #include "pipe/p_screen.h"
  30 #include "util/u_inlines.h"
  31 #include "util/u_format.h"
  32 #include "util/u_upload_mgr.h"
  33 #include "util/ralloc.h"
  34 #include "drm-uapi/i915_drm.h"
  35 #include "iris_context.h"
  36 #include "iris_pipe.h"
  37 #include "iris_resource.h"
  38 #include "iris_screen.h"
  39 #include "intel/compiler/brw_compiler.h"
  40
  41 static void
  42 iris_flush_frontbuffer(struct pipe_screen *_screen,
  43                        struct pipe_resource *resource,
  44                        unsigned level, unsigned layer,
  45                        void *context_private, struct pipe_box *box)
  46 {
  47 }
  48
  49 static const char *
  50 iris_get_vendor(struct pipe_screen *pscreen)
  51 {
  52    return "Mesa Project";
  53 }
  54
  55 static const char *
  56 iris_get_device_vendor(struct pipe_screen *pscreen)
  57 {
  58    return "Intel";
  59 }
  60
  61 static const char *
  62 iris_get_name(struct pipe_screen *pscreen)
  63 {
  64    struct iris_screen *screen = (struct iris_screen *)pscreen;
  65    const char *chipset;
  66
  67    switch (screen->pci_id) {
  68 #undef CHIPSET
  69 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
  70 #include "pci_ids/i965_pci_ids.h"
  71    default:
  72       chipset = "Unknown Intel Chipset";
  73       break;
  74    }
  75    return &chipset[9];
  76 }
  77
  78 static int
  79 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  80 {
  81    struct iris_screen *screen = (struct iris_screen *)pscreen;
  82
  83    switch (param) {
  84    case PIPE_CAP_NPOT_TEXTURES:
  85    case PIPE_CAP_ANISOTROPIC_FILTER:
  86    case PIPE_CAP_POINT_SPRITE:
  87    case PIPE_CAP_OCCLUSION_QUERY:
  88    case PIPE_CAP_QUERY_TIME_ELAPSED:
  89    case PIPE_CAP_TEXTURE_SWIZZLE:
  90    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  91    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  92    case PIPE_CAP_SM3:
  93    case PIPE_CAP_PRIMITIVE_RESTART:
  94    case PIPE_CAP_INDEP_BLEND_ENABLE:
  95    case PIPE_CAP_INDEP_BLEND_FUNC:
  96    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
  97    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  98    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  99    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 100    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 101    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 102    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 103    case PIPE_CAP_TGSI_INSTANCEID:
 104    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 105    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 106    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 107    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 108    case PIPE_CAP_CONDITIONAL_RENDER:
 109    case PIPE_CAP_TEXTURE_BARRIER:
 110    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 111    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 112    case PIPE_CAP_COMPUTE:
 113    case PIPE_CAP_START_INSTANCE:
 114    case PIPE_CAP_QUERY_TIMESTAMP:
 115    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 116    case PIPE_CAP_CUBE_MAP_ARRAY:
 117    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 118    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 119    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 120    case PIPE_CAP_TEXTURE_QUERY_LOD:
 121    case PIPE_CAP_SAMPLE_SHADING:
 122    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 123    case PIPE_CAP_DRAW_INDIRECT:
 124    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 125    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 126    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 127    case PIPE_CAP_ACCELERATED:
 128    case PIPE_CAP_UMA:
 129    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 130    case PIPE_CAP_CLIP_HALFZ:
 131    case PIPE_CAP_TGSI_TEXCOORD:
 132    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 133    case PIPE_CAP_DOUBLES:
 134    case PIPE_CAP_INT64:
 135    case PIPE_CAP_INT64_DIVMOD:
 136    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 137    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 138    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 139    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 140    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 141    case PIPE_CAP_CULL_DISTANCE:
 142    case PIPE_CAP_PACKED_UNIFORMS:
 143    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 144    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 145       return true;
 146
 147    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 148    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 149    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 150    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 151    case PIPE_CAP_USER_VERTEX_BUFFERS:
 152    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 153    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 154    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 155    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 156    case PIPE_CAP_FAKE_SW_MSAA:
 157    case PIPE_CAP_VERTEXID_NOBASE:
 158    case PIPE_CAP_FENCE_SIGNAL:
 159    case PIPE_CAP_CONSTBUF0_FLAGS:
 160    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 161    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 162    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 163    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 164    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 165    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 166    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 167       return false;
 168
 169    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 170       return 1;
 171    case PIPE_CAP_MAX_RENDER_TARGETS:
 172       return BRW_MAX_DRAW_BUFFERS;
 173    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 174    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 175       return 15; /* 16384x16384 */
 176    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 177       return 12; /* 2048x2048 */
 178    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 179       return 4;
 180    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 181       return 2048;
 182    case PIPE_CAP_MIN_TEXEL_OFFSET:
 183       return -8;
 184    case PIPE_CAP_MAX_TEXEL_OFFSET:
 185       return 7;
 186    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 187       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 188    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 189       return BRW_MAX_SOL_BINDINGS;
 190    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 191       return 460;
 192    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 193       return 140;
 194    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 195       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 196       return 32;
 197    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 198       return 64; // XXX: ?
 199    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 200       return 1;
 201    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 202       return true; // XXX: ?????
 203    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 204       return 1 << 27; /* 128MB */
 205    case PIPE_CAP_MAX_VIEWPORTS:
 206       return 16;
 207    case PIPE_CAP_ENDIANNESS:
 208       return PIPE_ENDIAN_LITTLE;
 209    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 210       return 256;
 211    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 212       return 128;
 213    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 214    case PIPE_CAP_TEXTURE_GATHER_SM5:
 215       return 0; // XXX:
 216    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 217       return -32;
 218    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 219       return 31;
 220    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 221    case PIPE_CAP_MAX_VERTEX_STREAMS:
 222       return 4;
 223    case PIPE_CAP_VENDOR_ID:
 224       return 0x8086;
 225    case PIPE_CAP_DEVICE_ID:
 226       return screen->pci_id;
 227    case PIPE_CAP_VIDEO_MEMORY:
 228       return 0xffffffff; // XXX: bogus
 229    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 230       return 2048;
 231    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 232    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 233    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 234    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 235    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 236    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 237    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 238    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 239    case PIPE_CAP_TGSI_TXQS:
 240    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 241    case PIPE_CAP_SHAREABLE_SHADERS:
 242    case PIPE_CAP_CLEAR_TEXTURE:
 243    case PIPE_CAP_DRAW_PARAMETERS:
 244    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 245    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 246    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 247    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 248    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 249    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 250    case PIPE_CAP_INVALIDATE_BUFFER:
 251    case PIPE_CAP_GENERATE_MIPMAP:
 252    case PIPE_CAP_STRING_MARKER:
 253    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 254    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 255    case PIPE_CAP_QUERY_MEMORY_INFO:
 256    case PIPE_CAP_PCI_GROUP:
 257    case PIPE_CAP_PCI_BUS:
 258    case PIPE_CAP_PCI_DEVICE:
 259    case PIPE_CAP_PCI_FUNCTION:
 260    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 261    case PIPE_CAP_TGSI_VOTE:
 262    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 263    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 264    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 265    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 266    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 267    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 268    case PIPE_CAP_NATIVE_FENCE_FD:
 269    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 270    case PIPE_CAP_TGSI_FS_FBFETCH:
 271    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 272    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 273    case PIPE_CAP_TGSI_CLOCK:
 274    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 275    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 276    case PIPE_CAP_TGSI_BALLOT:
 277    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 278    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 279    case PIPE_CAP_POST_DEPTH_COVERAGE:
 280    case PIPE_CAP_BINDLESS_TEXTURE:
 281    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 282    case PIPE_CAP_QUERY_SO_OVERFLOW:
 283    case PIPE_CAP_MEMOBJ:
 284    case PIPE_CAP_LOAD_CONSTBUF:
 285    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 286    case PIPE_CAP_TILE_RASTER_ORDER:
 287    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 288    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 289       // XXX: TODO: fill these out
 290       break;
 291    }
 292    return 0;
 293 }
 294
 295 static float
 296 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 297 {
 298    switch (param) {
 299    case PIPE_CAPF_MAX_LINE_WIDTH:
 300    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 301       return 7.375f;
 302
 303    case PIPE_CAPF_MAX_POINT_WIDTH:
 304    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 305       return 255.0f;
 306
 307    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 308       return 16.0f;
 309    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 310       return 15.0f;
 311    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 312    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 313    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 314       return 0.0f;
 315    default:
 316       unreachable("unknown param");
 317    }
 318 }
 319
 320 static int
 321 iris_get_shader_param(struct pipe_screen *pscreen,
 322                       enum pipe_shader_type shader,
 323                       enum pipe_shader_cap param)
 324 {
 325    struct iris_screen *screen = (struct iris_screen *)pscreen;
 326    struct brw_compiler *compiler = screen->compiler;
 327
 328    /* this is probably not totally correct.. but it's a start: */
 329    switch (param) {
 330    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 331       return shader == PIPE_SHADER_FRAGMENT ? 1024 : 16384;
 332    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 333    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 334    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 335       return shader == PIPE_SHADER_FRAGMENT ? 1024 : 0;
 336
 337    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 338       return UINT_MAX;
 339
 340    case PIPE_SHADER_CAP_MAX_INPUTS:
 341       return shader == PIPE_SHADER_VERTEX ? 16 : 32;
 342    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 343       return 32;
 344    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 345       return 16 * 1024 * sizeof(float);
 346    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 347       return 16;
 348    case PIPE_SHADER_CAP_MAX_TEMPS:
 349       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 350    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 351       return 0;
 352    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 353       return !compiler->glsl_compiler_options[shader].EmitNoIndirectInput;
 354    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 355       return !compiler->glsl_compiler_options[shader].EmitNoIndirectOutput;
 356    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 357       return !compiler->glsl_compiler_options[shader].EmitNoIndirectTemp;
 358    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 359       return 1;
 360    case PIPE_SHADER_CAP_SUBROUTINES:
 361       return 0;
 362    case PIPE_SHADER_CAP_INTEGERS:
 363    case PIPE_SHADER_CAP_SCALAR_ISA:
 364       return 1;
 365    case PIPE_SHADER_CAP_INT64_ATOMICS:
 366    case PIPE_SHADER_CAP_FP16:
 367       return 0;
 368    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 369    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 370    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 371    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 372       return IRIS_MAX_TEXTURE_SAMPLERS;
 373    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 374    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 375       return 0;
 376    case PIPE_SHADER_CAP_PREFERRED_IR:
 377       return PIPE_SHADER_IR_NIR;
 378    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 379       return 0;
 380    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 381       return 32;
 382    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 383    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 384    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 385    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 386    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 387    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 388    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 389    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 390       return 0;
 391    default:
 392       unreachable("unknown shader param");
 393    }
 394 }
 395
 396 static int
 397 iris_get_compute_param(struct pipe_screen *pscreen,
 398                        enum pipe_shader_ir ir_type,
 399                        enum pipe_compute_cap param,
 400                        void *ret)
 401 {
 402    /* TODO: compute shaders */
 403    return 0;
 404 }
 405
 406 static uint64_t
 407 iris_get_timestamp(struct pipe_screen *pscreen)
 408 {
 409    return 0;
 410 }
 411
 412 static void
 413 iris_destroy_screen(struct pipe_screen *pscreen)
 414 {
 415    struct iris_screen *screen = (struct iris_screen *) pscreen;
 416    iris_bo_unreference(screen->workaround_bo);
 417    ralloc_free(screen);
 418 }
 419
 420 static void
 421 iris_fence_reference(struct pipe_screen *screen,
 422                      struct pipe_fence_handle **ptr,
 423                      struct pipe_fence_handle *fence)
 424 {
 425 }
 426
 427 static boolean
 428 iris_fence_finish(struct pipe_screen *screen,
 429                   struct pipe_context *ctx,
 430                   struct pipe_fence_handle *fence,
 431                   uint64_t timeout)
 432 {
 433    return true;
 434 }
 435
 436 static void
 437 iris_query_memory_info(struct pipe_screen *pscreen,
 438                        struct pipe_memory_info *info)
 439 {
 440 }
 441
 442 static const void *
 443 iris_get_compiler_options(struct pipe_screen *pscreen,
 444                           enum pipe_shader_ir ir,
 445                           enum pipe_shader_type pstage)
 446 {
 447    struct iris_screen *screen = (struct iris_screen *) pscreen;
 448    gl_shader_stage stage = stage_from_pipe(pstage);
 449    assert(ir == PIPE_SHADER_IR_NIR);
 450
 451    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 452 }
 453
 454 static int
 455 iris_getparam(struct iris_screen *screen, int param, int *value)
 456 {
 457    struct drm_i915_getparam gp = { .param = param, .value = value };
 458
 459    if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 460       return -errno;
 461
 462    return 0;
 463 }
 464
 465 static bool
 466 iris_getparam_boolean(struct iris_screen *screen, int param)
 467 {
 468    int value = 0;
 469    return (iris_getparam(screen, param, &value) == 0) && value;
 470 }
 471
 472 static int
 473 iris_getparam_integer(struct iris_screen *screen, int param)
 474 {
 475    int value = -1;
 476
 477    if (iris_getparam(screen, param, &value) == 0)
 478       return value;
 479
 480    return -1;
 481 }
 482
 483 static void
 484 iris_shader_debug_log(void *data, const char *fmt, ...)
 485 {
 486    struct pipe_debug_callback *dbg = data;
 487    unsigned id = 0;
 488    va_list args;
 489
 490    if (!dbg->debug_message)
 491       return;
 492
 493    va_start(args, fmt);
 494
 495    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
 496    va_end(args);
 497 }
 498
 499 struct pipe_screen *
 500 iris_screen_create(int fd)
 501 {
 502    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 503    if (!screen)
 504       return NULL;
 505
 506    screen->fd = fd;
 507    screen->pci_id = iris_getparam_integer(screen, I915_PARAM_CHIPSET_ID);
 508
 509    if (!gen_get_device_info(screen->pci_id, &screen->devinfo))
 510       return NULL;
 511
 512    screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
 513    if (!screen->bufmgr)
 514       return NULL;
 515
 516    screen->workaround_bo =
 517       iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
 518    if (!screen->workaround_bo)
 519       return NULL;
 520
 521    brw_process_intel_debug_variable();
 522
 523    bool hw_has_swizzling = false; // XXX: detect?
 524    isl_device_init(&screen->isl_dev, &screen->devinfo, hw_has_swizzling);
 525
 526    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 527    screen->compiler->shader_debug_log = iris_shader_debug_log;
 528
 529    struct pipe_screen *pscreen = &screen->base;
 530
 531    iris_init_screen_resource_functions(pscreen);
 532
 533    pscreen->destroy = iris_destroy_screen;
 534    pscreen->get_name = iris_get_name;
 535    pscreen->get_vendor = iris_get_vendor;
 536    pscreen->get_device_vendor = iris_get_device_vendor;
 537    pscreen->get_param = iris_get_param;
 538    pscreen->get_shader_param = iris_get_shader_param;
 539    pscreen->get_compute_param = iris_get_compute_param;
 540    pscreen->get_paramf = iris_get_paramf;
 541    pscreen->get_compiler_options = iris_get_compiler_options;
 542    pscreen->is_format_supported = iris_is_format_supported;
 543    pscreen->context_create = iris_create_context;
 544    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 545    pscreen->get_timestamp = iris_get_timestamp;
 546    pscreen->fence_reference = iris_fence_reference;
 547    pscreen->fence_finish = iris_fence_finish;
 548    pscreen->query_memory_info = iris_query_memory_info;
 549
 550    return pscreen;
 551 }