src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file iris_screen.c
  26  *
  27  * Screen related driver hooks and capability lists.
  28  *
  29  * A program may use multiple rendering contexts (iris_context), but
  30  * they all share a common screen (iris_screen).  Global driver state
  31  * can be stored in the screen; it may be accessed by multiple threads.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <sys/ioctl.h>
  37 #include "pipe/p_defines.h"
  38 #include "pipe/p_state.h"
  39 #include "pipe/p_context.h"
  40 #include "pipe/p_screen.h"
  41 #include "util/u_inlines.h"
  42 #include "util/u_format.h"
  43 #include "util/u_upload_mgr.h"
  44 #include "util/ralloc.h"
  45 #include "drm-uapi/i915_drm.h"
  46 #include "iris_context.h"
  47 #include "iris_pipe.h"
  48 #include "iris_resource.h"
  49 #include "iris_screen.h"
  50 #include "intel/compiler/brw_compiler.h"
  51
  52 static void
  53 iris_flush_frontbuffer(struct pipe_screen *_screen,
  54                        struct pipe_resource *resource,
  55                        unsigned level, unsigned layer,
  56                        void *context_private, struct pipe_box *box)
  57 {
  58 }
  59
  60 static const char *
  61 iris_get_vendor(struct pipe_screen *pscreen)
  62 {
  63    return "Mesa Project";
  64 }
  65
  66 static const char *
  67 iris_get_device_vendor(struct pipe_screen *pscreen)
  68 {
  69    return "Intel";
  70 }
  71
  72 static const char *
  73 iris_get_name(struct pipe_screen *pscreen)
  74 {
  75    struct iris_screen *screen = (struct iris_screen *)pscreen;
  76    const char *chipset;
  77
  78    switch (screen->pci_id) {
  79 #undef CHIPSET
  80 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
  81 #include "pci_ids/i965_pci_ids.h"
  82    default:
  83       chipset = "Unknown Intel Chipset";
  84       break;
  85    }
  86    return &chipset[9];
  87 }
  88
  89 static int
  90 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  91 {
  92    struct iris_screen *screen = (struct iris_screen *)pscreen;
  93
  94    switch (param) {
  95    case PIPE_CAP_NPOT_TEXTURES:
  96    case PIPE_CAP_ANISOTROPIC_FILTER:
  97    case PIPE_CAP_POINT_SPRITE:
  98    case PIPE_CAP_OCCLUSION_QUERY:
  99    case PIPE_CAP_QUERY_TIME_ELAPSED:
 100    case PIPE_CAP_TEXTURE_SWIZZLE:
 101    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 102    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 103    case PIPE_CAP_SM3:
 104    case PIPE_CAP_PRIMITIVE_RESTART:
 105    case PIPE_CAP_INDEP_BLEND_ENABLE:
 106    case PIPE_CAP_INDEP_BLEND_FUNC:
 107    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 108    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 109    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 110    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 111    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 112    case PIPE_CAP_TGSI_INSTANCEID:
 113    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 114    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 115    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 116    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 117    case PIPE_CAP_CONDITIONAL_RENDER:
 118    case PIPE_CAP_TEXTURE_BARRIER:
 119    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 120    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 121    case PIPE_CAP_COMPUTE:
 122    case PIPE_CAP_START_INSTANCE:
 123    case PIPE_CAP_QUERY_TIMESTAMP:
 124    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 125    case PIPE_CAP_CUBE_MAP_ARRAY:
 126    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 127    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 128    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 129    case PIPE_CAP_TEXTURE_QUERY_LOD:
 130    case PIPE_CAP_SAMPLE_SHADING:
 131    case PIPE_CAP_DRAW_INDIRECT:
 132    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 133    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 134    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 135    case PIPE_CAP_ACCELERATED:
 136    case PIPE_CAP_UMA:
 137    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 138    case PIPE_CAP_CLIP_HALFZ:
 139    case PIPE_CAP_TGSI_TEXCOORD:
 140    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 141    case PIPE_CAP_DOUBLES:
 142    case PIPE_CAP_INT64:
 143    case PIPE_CAP_INT64_DIVMOD:
 144    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 145    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 146    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 147    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 148    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 149    case PIPE_CAP_CULL_DISTANCE:
 150    case PIPE_CAP_PACKED_UNIFORMS:
 151    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 152    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 153    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 154    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 155    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 156       return true;
 157
 158    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 159    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 160    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 161    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 162    case PIPE_CAP_USER_VERTEX_BUFFERS:
 163    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 164    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 165    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 166    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 167    case PIPE_CAP_FAKE_SW_MSAA:
 168    case PIPE_CAP_VERTEXID_NOBASE:
 169    case PIPE_CAP_FENCE_SIGNAL:
 170    case PIPE_CAP_CONSTBUF0_FLAGS:
 171    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 172    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 173    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 174    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 175    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 176    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 177    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 178    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 179    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 180    case PIPE_CAP_GENERATE_MIPMAP:
 181    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 182    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 183       return false;
 184
 185    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 186       /* Intel GPUs don't support PIPE_TEX_WRAP_MIRROR_CLAMP or
 187        * PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER.
 188        */
 189       return false;
 190
 191    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 192       return 1;
 193    case PIPE_CAP_MAX_RENDER_TARGETS:
 194       return BRW_MAX_DRAW_BUFFERS;
 195    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 196    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 197       return 15; /* 16384x16384 */
 198    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 199       return 12; /* 2048x2048 */
 200    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 201       return 4;
 202    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 203       return 2048;
 204    case PIPE_CAP_MIN_TEXEL_OFFSET:
 205       return -8;
 206    case PIPE_CAP_MAX_TEXEL_OFFSET:
 207       return 7;
 208    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 209       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 210    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 211       return BRW_MAX_SOL_BINDINGS;
 212    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 213       return 460;
 214    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 215       return 140;
 216    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 217       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 218       return 32;
 219    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 220       /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
 221        * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
 222        * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
 223        * GPU and the CPU can be updating disjoint regions of the buffer
 224        * simultaneously and that will break if the regions overlap the same
 225        * cacheline.
 226        */
 227       return 64;
 228    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 229       return 64; // XXX: ?
 230    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 231       return 16;
 232    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 233       return true; // XXX: ?????
 234    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 235       return 1 << 27; /* 128MB */
 236    case PIPE_CAP_MAX_VIEWPORTS:
 237       return 16;
 238    case PIPE_CAP_ENDIANNESS:
 239       return PIPE_ENDIAN_LITTLE;
 240    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 241       return 256;
 242    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 243       return 1024;
 244    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 245       return 4;
 246    case PIPE_CAP_TEXTURE_GATHER_SM5:
 247       return 1;
 248    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 249       return -32;
 250    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 251       return 31;
 252    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 253    case PIPE_CAP_MAX_VERTEX_STREAMS:
 254       return 4;
 255    case PIPE_CAP_VENDOR_ID:
 256       return 0x8086;
 257    case PIPE_CAP_DEVICE_ID:
 258       return screen->pci_id;
 259    case PIPE_CAP_VIDEO_MEMORY:
 260       return 0xffffffff; // XXX: bogus
 261    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 262       return 2048;
 263    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 264       return 32;
 265    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 266    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 267    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 268    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 269    case PIPE_CAP_TGSI_TXQS:
 270    case PIPE_CAP_SHAREABLE_SHADERS:
 271    case PIPE_CAP_CLEAR_TEXTURE:
 272    case PIPE_CAP_DRAW_PARAMETERS:
 273    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 274    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 275    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 276    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 277    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 278    case PIPE_CAP_INVALIDATE_BUFFER:
 279    case PIPE_CAP_STRING_MARKER:
 280    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 281    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 282    case PIPE_CAP_QUERY_MEMORY_INFO:
 283    case PIPE_CAP_PCI_GROUP:
 284    case PIPE_CAP_PCI_BUS:
 285    case PIPE_CAP_PCI_DEVICE:
 286    case PIPE_CAP_PCI_FUNCTION:
 287    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 288    case PIPE_CAP_TGSI_VOTE:
 289    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 290    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 291    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 292    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 293    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 294    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 295    case PIPE_CAP_NATIVE_FENCE_FD:
 296    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 297    case PIPE_CAP_TGSI_FS_FBFETCH:
 298    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 299    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 300    case PIPE_CAP_TGSI_CLOCK:
 301    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 302    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 303    case PIPE_CAP_TGSI_BALLOT:
 304    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 305    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 306    case PIPE_CAP_POST_DEPTH_COVERAGE:
 307    case PIPE_CAP_BINDLESS_TEXTURE:
 308    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 309    case PIPE_CAP_QUERY_SO_OVERFLOW:
 310    case PIPE_CAP_MEMOBJ:
 311    case PIPE_CAP_LOAD_CONSTBUF:
 312    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 313    case PIPE_CAP_TILE_RASTER_ORDER:
 314    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 315    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 316       // XXX: TODO: fill these out
 317       break;
 318    }
 319    return 0;
 320 }
 321
 322 static float
 323 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 324 {
 325    switch (param) {
 326    case PIPE_CAPF_MAX_LINE_WIDTH:
 327    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 328       return 7.375f;
 329
 330    case PIPE_CAPF_MAX_POINT_WIDTH:
 331    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 332       return 255.0f;
 333
 334    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 335       return 16.0f;
 336    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 337       return 15.0f;
 338    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 339    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 340    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 341       return 0.0f;
 342    default:
 343       unreachable("unknown param");
 344    }
 345 }
 346
 347 static int
 348 iris_get_shader_param(struct pipe_screen *pscreen,
 349                       enum pipe_shader_type p_stage,
 350                       enum pipe_shader_cap param)
 351 {
 352    struct iris_screen *screen = (struct iris_screen *)pscreen;
 353    struct brw_compiler *compiler = screen->compiler;
 354    gl_shader_stage stage = stage_from_pipe(p_stage);
 355
 356    /* this is probably not totally correct.. but it's a start: */
 357    switch (param) {
 358    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 359       return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
 360    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 361    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 362    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 363       return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
 364
 365    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 366       return UINT_MAX;
 367
 368    case PIPE_SHADER_CAP_MAX_INPUTS:
 369       return stage == MESA_SHADER_VERTEX ? 16 : 32;
 370    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 371       return 32;
 372    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 373       return 16 * 1024 * sizeof(float);
 374    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 375       return 16;
 376    case PIPE_SHADER_CAP_MAX_TEMPS:
 377       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 378    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 379       return 0;
 380    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 381       return !compiler->glsl_compiler_options[stage].EmitNoIndirectInput;
 382    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 383       return !compiler->glsl_compiler_options[stage].EmitNoIndirectOutput;
 384    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 385       return !compiler->glsl_compiler_options[stage].EmitNoIndirectTemp;
 386    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 387       return 1;
 388    case PIPE_SHADER_CAP_SUBROUTINES:
 389       return 0;
 390    case PIPE_SHADER_CAP_INTEGERS:
 391    case PIPE_SHADER_CAP_SCALAR_ISA:
 392       return 1;
 393    case PIPE_SHADER_CAP_INT64_ATOMICS:
 394    case PIPE_SHADER_CAP_FP16:
 395       return 0;
 396    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 397    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 398    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 399       return IRIS_MAX_TEXTURE_SAMPLERS;
 400    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 401       return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
 402    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 403    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 404       return 0;
 405    case PIPE_SHADER_CAP_PREFERRED_IR:
 406       return PIPE_SHADER_IR_NIR;
 407    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 408       return 0;
 409    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 410       return 32;
 411    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 412    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 413    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 414    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 415    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 416    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 417    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 418    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 419       return 0;
 420    default:
 421       unreachable("unknown shader param");
 422    }
 423 }
 424
 425 static int
 426 iris_get_compute_param(struct pipe_screen *pscreen,
 427                        enum pipe_shader_ir ir_type,
 428                        enum pipe_compute_cap param,
 429                        void *ret)
 430 {
 431    /* TODO: compute shaders */
 432    return 0;
 433 }
 434
 435 static uint64_t
 436 iris_get_timestamp(struct pipe_screen *pscreen)
 437 {
 438    return 0;
 439 }
 440
 441 static void
 442 iris_destroy_screen(struct pipe_screen *pscreen)
 443 {
 444    struct iris_screen *screen = (struct iris_screen *) pscreen;
 445    iris_bo_unreference(screen->workaround_bo);
 446    ralloc_free(screen);
 447 }
 448
 449 static void
 450 iris_fence_reference(struct pipe_screen *screen,
 451                      struct pipe_fence_handle **ptr,
 452                      struct pipe_fence_handle *fence)
 453 {
 454 }
 455
 456 static boolean
 457 iris_fence_finish(struct pipe_screen *screen,
 458                   struct pipe_context *ctx,
 459                   struct pipe_fence_handle *fence,
 460                   uint64_t timeout)
 461 {
 462    return true;
 463 }
 464
 465 static void
 466 iris_query_memory_info(struct pipe_screen *pscreen,
 467                        struct pipe_memory_info *info)
 468 {
 469 }
 470
 471 static const void *
 472 iris_get_compiler_options(struct pipe_screen *pscreen,
 473                           enum pipe_shader_ir ir,
 474                           enum pipe_shader_type pstage)
 475 {
 476    struct iris_screen *screen = (struct iris_screen *) pscreen;
 477    gl_shader_stage stage = stage_from_pipe(pstage);
 478    assert(ir == PIPE_SHADER_IR_NIR);
 479
 480    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 481 }
 482
 483 static int
 484 iris_getparam(struct iris_screen *screen, int param, int *value)
 485 {
 486    struct drm_i915_getparam gp = { .param = param, .value = value };
 487
 488    if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 489       return -errno;
 490
 491    return 0;
 492 }
 493
 494 static bool
 495 iris_getparam_boolean(struct iris_screen *screen, int param)
 496 {
 497    int value = 0;
 498    return (iris_getparam(screen, param, &value) == 0) && value;
 499 }
 500
 501 static int
 502 iris_getparam_integer(struct iris_screen *screen, int param)
 503 {
 504    int value = -1;
 505
 506    if (iris_getparam(screen, param, &value) == 0)
 507       return value;
 508
 509    return -1;
 510 }
 511
 512 static void
 513 iris_shader_debug_log(void *data, const char *fmt, ...)
 514 {
 515    struct pipe_debug_callback *dbg = data;
 516    unsigned id = 0;
 517    va_list args;
 518
 519    if (!dbg->debug_message)
 520       return;
 521
 522    va_start(args, fmt);
 523    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
 524    va_end(args);
 525 }
 526
 527 static void
 528 iris_shader_perf_log(void *data, const char *fmt, ...)
 529 {
 530    struct pipe_debug_callback *dbg = data;
 531    unsigned id = 0;
 532    va_list args;
 533
 534    if (!dbg->debug_message)
 535       return;
 536
 537    va_start(args, fmt);
 538    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
 539    va_end(args);
 540 }
 541
 542 struct pipe_screen *
 543 iris_screen_create(int fd)
 544 {
 545    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 546    if (!screen)
 547       return NULL;
 548
 549    screen->fd = fd;
 550    screen->pci_id = iris_getparam_integer(screen, I915_PARAM_CHIPSET_ID);
 551
 552    if (!gen_get_device_info(screen->pci_id, &screen->devinfo))
 553       return NULL;
 554
 555    screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
 556    if (!screen->bufmgr)
 557       return NULL;
 558
 559    screen->workaround_bo =
 560       iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
 561    if (!screen->workaround_bo)
 562       return NULL;
 563
 564    brw_process_intel_debug_variable();
 565
 566    bool hw_has_swizzling = false; // XXX: detect?
 567    isl_device_init(&screen->isl_dev, &screen->devinfo, hw_has_swizzling);
 568
 569    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 570    screen->compiler->shader_debug_log = iris_shader_debug_log;
 571    screen->compiler->shader_perf_log = iris_shader_perf_log;
 572
 573    slab_create_parent(&screen->transfer_pool,
 574                       sizeof(struct iris_transfer), 64);
 575
 576    struct pipe_screen *pscreen = &screen->base;
 577
 578    iris_init_screen_resource_functions(pscreen);
 579
 580    pscreen->destroy = iris_destroy_screen;
 581    pscreen->get_name = iris_get_name;
 582    pscreen->get_vendor = iris_get_vendor;
 583    pscreen->get_device_vendor = iris_get_device_vendor;
 584    pscreen->get_param = iris_get_param;
 585    pscreen->get_shader_param = iris_get_shader_param;
 586    pscreen->get_compute_param = iris_get_compute_param;
 587    pscreen->get_paramf = iris_get_paramf;
 588    pscreen->get_compiler_options = iris_get_compiler_options;
 589    pscreen->is_format_supported = iris_is_format_supported;
 590    pscreen->context_create = iris_create_context;
 591    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 592    pscreen->get_timestamp = iris_get_timestamp;
 593    pscreen->fence_reference = iris_fence_reference;
 594    pscreen->fence_finish = iris_fence_finish;
 595    pscreen->query_memory_info = iris_query_memory_info;
 596
 597    return pscreen;
 598 }