src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /**
  24  * @file iris_screen.c
  25  *
  26  * Screen related driver hooks and capability lists.
  27  *
  28  * A program may use multiple rendering contexts (iris_context), but
  29  * they all share a common screen (iris_screen).  Global driver state
  30  * can be stored in the screen; it may be accessed by multiple threads.
  31  */
  32
  33 #include <stdio.h>
  34 #include <errno.h>
  35 #include <sys/ioctl.h>
  36 #include "pipe/p_defines.h"
  37 #include "pipe/p_state.h"
  38 #include "pipe/p_context.h"
  39 #include "pipe/p_screen.h"
  40 #include "util/u_inlines.h"
  41 #include "util/u_format.h"
  42 #include "util/u_upload_mgr.h"
  43 #include "util/ralloc.h"
  44 #include "drm-uapi/i915_drm.h"
  45 #include "iris_context.h"
  46 #include "iris_defines.h"
  47 #include "iris_fence.h"
  48 #include "iris_pipe.h"
  49 #include "iris_resource.h"
  50 #include "iris_screen.h"
  51 #include "intel/compiler/brw_compiler.h"
  52
  53 static void
  54 iris_flush_frontbuffer(struct pipe_screen *_screen,
  55                        struct pipe_resource *resource,
  56                        unsigned level, unsigned layer,
  57                        void *context_private, struct pipe_box *box)
  58 {
  59 }
  60
  61 static const char *
  62 iris_get_vendor(struct pipe_screen *pscreen)
  63 {
  64    return "Mesa Project";
  65 }
  66
  67 static const char *
  68 iris_get_device_vendor(struct pipe_screen *pscreen)
  69 {
  70    return "Intel";
  71 }
  72
  73 static const char *
  74 iris_get_name(struct pipe_screen *pscreen)
  75 {
  76    struct iris_screen *screen = (struct iris_screen *)pscreen;
  77    const char *chipset;
  78
  79    switch (screen->pci_id) {
  80 #undef CHIPSET
  81 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
  82 #include "pci_ids/i965_pci_ids.h"
  83    default:
  84       chipset = "Unknown Intel Chipset";
  85       break;
  86    }
  87    return &chipset[9];
  88 }
  89
  90 static int
  91 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  92 {
  93    struct iris_screen *screen = (struct iris_screen *)pscreen;
  94    const struct gen_device_info *devinfo = &screen->devinfo;
  95
  96    switch (param) {
  97    case PIPE_CAP_NPOT_TEXTURES:
  98    case PIPE_CAP_ANISOTROPIC_FILTER:
  99    case PIPE_CAP_POINT_SPRITE:
 100    case PIPE_CAP_OCCLUSION_QUERY:
 101    case PIPE_CAP_QUERY_TIME_ELAPSED:
 102    case PIPE_CAP_TEXTURE_SWIZZLE:
 103    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 104    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 105    case PIPE_CAP_SM3:
 106    case PIPE_CAP_PRIMITIVE_RESTART:
 107    case PIPE_CAP_INDEP_BLEND_ENABLE:
 108    case PIPE_CAP_INDEP_BLEND_FUNC:
 109    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 110    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 111    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 112    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 113    case PIPE_CAP_TGSI_INSTANCEID:
 114    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 115    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 116    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 117    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 118    case PIPE_CAP_CONDITIONAL_RENDER:
 119    case PIPE_CAP_TEXTURE_BARRIER:
 120    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 121    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 122    case PIPE_CAP_COMPUTE:
 123    case PIPE_CAP_START_INSTANCE:
 124    case PIPE_CAP_QUERY_TIMESTAMP:
 125    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 126    case PIPE_CAP_CUBE_MAP_ARRAY:
 127    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 128    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 129    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 130    case PIPE_CAP_TEXTURE_QUERY_LOD:
 131    case PIPE_CAP_SAMPLE_SHADING:
 132    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 133    case PIPE_CAP_DRAW_INDIRECT:
 134    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 135    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 136    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 137    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 138    case PIPE_CAP_ACCELERATED:
 139    case PIPE_CAP_UMA:
 140    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 141    case PIPE_CAP_CLIP_HALFZ:
 142    case PIPE_CAP_TGSI_TEXCOORD:
 143    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 144    case PIPE_CAP_DOUBLES:
 145    case PIPE_CAP_INT64:
 146    case PIPE_CAP_INT64_DIVMOD:
 147    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 148    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 149    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 150    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 151    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 152    case PIPE_CAP_CULL_DISTANCE:
 153    case PIPE_CAP_PACKED_UNIFORMS:
 154    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 155    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 156    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 157    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 158    case PIPE_CAP_POST_DEPTH_COVERAGE:
 159    case PIPE_CAP_QUERY_SO_OVERFLOW:
 160    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 161    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 162    case PIPE_CAP_TGSI_TXQS:
 163    case PIPE_CAP_TGSI_FS_FBFETCH:
 164    case PIPE_CAP_TGSI_CLOCK:
 165    case PIPE_CAP_TGSI_BALLOT:
 166    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 167    case PIPE_CAP_CLEAR_TEXTURE:
 168    case PIPE_CAP_TGSI_VOTE:
 169    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 170    case PIPE_CAP_TEXTURE_GATHER_SM5:
 171    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 172    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 173    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 174       return true;
 175
 176    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 177       return 1;
 178    case PIPE_CAP_MAX_RENDER_TARGETS:
 179       return BRW_MAX_DRAW_BUFFERS;
 180    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 181    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 182       return 15; /* 16384x16384 */
 183    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 184       return 12; /* 2048x2048 */
 185    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 186       return 4;
 187    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 188       return 2048;
 189    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 190       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 191    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 192       return BRW_MAX_SOL_BINDINGS;
 193    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 194       return 460;
 195    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 196       return 140;
 197    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 198       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 199       return 32;
 200    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 201       /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
 202        * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
 203        * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
 204        * GPU and the CPU can be updating disjoint regions of the buffer
 205        * simultaneously and that will break if the regions overlap the same
 206        * cacheline.
 207        */
 208       return 64;
 209    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 210       return 1 << 27;
 211    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 212       return 16; // XXX: u_screen says 256 is the minimum value...
 213    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 214       return true; // XXX: ?????
 215    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 216       return IRIS_MAX_TEXTURE_BUFFER_SIZE;
 217    case PIPE_CAP_MAX_VIEWPORTS:
 218       return 16;
 219    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 220       return 256;
 221    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 222       return 1024;
 223    case PIPE_CAP_MAX_GS_INVOCATIONS:
 224       return 32;
 225    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 226       return 4;
 227    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 228       return -32;
 229    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 230       return 31;
 231    case PIPE_CAP_MAX_VERTEX_STREAMS:
 232       return 4;
 233    case PIPE_CAP_VENDOR_ID:
 234       return 0x8086;
 235    case PIPE_CAP_DEVICE_ID:
 236       return screen->pci_id;
 237    case PIPE_CAP_VIDEO_MEMORY:
 238       return 0xffffffff; // XXX: bogus
 239    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 240       return 32;
 241    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 242       /* AMD_pinned_memory assumes the flexibility of using client memory
 243        * for any buffer (incl. vertex buffers) which rules out the prospect
 244        * of using snooped buffers, as using snooped buffers without
 245        * cogniscience is likely to be detrimental to performance and require
 246        * extensive checking in the driver for correctness, e.g. to prevent
 247        * illegal snoop <-> snoop transfers.
 248        */
 249       return devinfo->has_llc;
 250
 251    // XXX: don't hardcode 00:00:02.0 PCI here
 252    case PIPE_CAP_PCI_GROUP:
 253       return 0;
 254    case PIPE_CAP_PCI_BUS:
 255       return 0;
 256    case PIPE_CAP_PCI_DEVICE:
 257       return 2;
 258    case PIPE_CAP_PCI_FUNCTION:
 259       return 0;
 260
 261    default:
 262       return u_pipe_screen_get_param_defaults(pscreen, param);
 263    }
 264    return 0;
 265 }
 266
 267 static float
 268 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 269 {
 270    switch (param) {
 271    case PIPE_CAPF_MAX_LINE_WIDTH:
 272    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 273       return 7.375f;
 274
 275    case PIPE_CAPF_MAX_POINT_WIDTH:
 276    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 277       return 255.0f;
 278
 279    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 280       return 16.0f;
 281    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 282       return 15.0f;
 283    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 284    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 285    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 286       return 0.0f;
 287    default:
 288       unreachable("unknown param");
 289    }
 290 }
 291
 292 static int
 293 iris_get_shader_param(struct pipe_screen *pscreen,
 294                       enum pipe_shader_type p_stage,
 295                       enum pipe_shader_cap param)
 296 {
 297    struct iris_screen *screen = (struct iris_screen *)pscreen;
 298    struct brw_compiler *compiler = screen->compiler;
 299    gl_shader_stage stage = stage_from_pipe(p_stage);
 300
 301    /* this is probably not totally correct.. but it's a start: */
 302    switch (param) {
 303    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 304       return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
 305    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 306    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 307    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 308       return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
 309
 310    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 311       return UINT_MAX;
 312
 313    case PIPE_SHADER_CAP_MAX_INPUTS:
 314       return stage == MESA_SHADER_VERTEX ? 16 : 32;
 315    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 316       return 32;
 317    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 318       return 16 * 1024 * sizeof(float);
 319    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 320       return 16;
 321    case PIPE_SHADER_CAP_MAX_TEMPS:
 322       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 323    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 324       return 0;
 325    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 326       return !compiler->glsl_compiler_options[stage].EmitNoIndirectInput;
 327    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 328       return !compiler->glsl_compiler_options[stage].EmitNoIndirectOutput;
 329    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 330       return !compiler->glsl_compiler_options[stage].EmitNoIndirectTemp;
 331    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 332       return 1;
 333    case PIPE_SHADER_CAP_SUBROUTINES:
 334       return 0;
 335    case PIPE_SHADER_CAP_INTEGERS:
 336    case PIPE_SHADER_CAP_SCALAR_ISA:
 337       return 1;
 338    case PIPE_SHADER_CAP_INT64_ATOMICS:
 339    case PIPE_SHADER_CAP_FP16:
 340       return 0;
 341    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 342    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 343    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 344       return IRIS_MAX_TEXTURE_SAMPLERS;
 345    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 346       return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
 347    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 348    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 349       return 0;
 350    case PIPE_SHADER_CAP_PREFERRED_IR:
 351       return PIPE_SHADER_IR_NIR;
 352    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 353       return 1 << PIPE_SHADER_IR_NIR;
 354    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 355       return 32;
 356    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 357    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 358    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 359    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 360    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 361    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 362    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 363    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 364       return 0;
 365    default:
 366       unreachable("unknown shader param");
 367    }
 368 }
 369
 370 static int
 371 iris_get_compute_param(struct pipe_screen *pscreen,
 372                        enum pipe_shader_ir ir_type,
 373                        enum pipe_compute_cap param,
 374                        void *ret)
 375 {
 376    struct iris_screen *screen = (struct iris_screen *)pscreen;
 377    struct brw_compiler *compiler = screen->compiler;
 378    const struct gen_device_info *devinfo = &screen->devinfo;
 379
 380    // XXX: cherryview fusing
 381
 382    const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
 383    const uint32_t max_invocations = 32 * max_threads;
 384
 385 #define RET(x) do {                  \
 386    if (ret)                          \
 387       memcpy(ret, x, sizeof(x));     \
 388    return sizeof(x);                 \
 389 } while (0)
 390
 391    switch (param) {
 392    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 393       RET((uint32_t []){ 32 });
 394
 395    case PIPE_COMPUTE_CAP_IR_TARGET:
 396       if (ret)
 397          strcpy(ret, "gen");
 398       return 4;
 399
 400    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 401       RET((uint64_t []) { 3 });
 402
 403    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 404       RET(((uint64_t []) { 65535, 65535, 65535 }));
 405
 406    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 407       /* MaxComputeWorkGroupSize[0..2] */
 408       RET(((uint64_t []) {max_invocations, max_invocations, max_invocations}));
 409
 410    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 411       /* MaxComputeWorkGroupInvocations */
 412       RET((uint64_t []) { max_invocations });
 413
 414    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 415       /* MaxComputeSharedMemorySize */
 416       RET((uint64_t []) { 64 * 1024 });
 417
 418    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 419       RET((uint32_t []) { 1 });
 420
 421    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 422       RET((uint32_t []) { BRW_SUBGROUP_SIZE });
 423
 424    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 425    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 426    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 427    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 428    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 429    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 430    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 431       // XXX: I think these are for Clover...
 432       return 0;
 433
 434    default:
 435       unreachable("unknown compute param");
 436    }
 437 }
 438
 439 static uint64_t
 440 iris_get_timestamp(struct pipe_screen *pscreen)
 441 {
 442    struct iris_screen *screen = (struct iris_screen *) pscreen;
 443    const unsigned TIMESTAMP = 0x2358;
 444    uint64_t result;
 445
 446    iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
 447
 448    result = iris_timebase_scale(&screen->devinfo, result);
 449    result &= (1ull << TIMESTAMP_BITS) - 1;
 450
 451    return result;
 452 }
 453
 454 static void
 455 iris_destroy_screen(struct pipe_screen *pscreen)
 456 {
 457    struct iris_screen *screen = (struct iris_screen *) pscreen;
 458    iris_bo_unreference(screen->workaround_bo);
 459    ralloc_free(screen);
 460 }
 461
 462 static void
 463 iris_query_memory_info(struct pipe_screen *pscreen,
 464                        struct pipe_memory_info *info)
 465 {
 466 }
 467
 468 static const void *
 469 iris_get_compiler_options(struct pipe_screen *pscreen,
 470                           enum pipe_shader_ir ir,
 471                           enum pipe_shader_type pstage)
 472 {
 473    struct iris_screen *screen = (struct iris_screen *) pscreen;
 474    gl_shader_stage stage = stage_from_pipe(pstage);
 475    assert(ir == PIPE_SHADER_IR_NIR);
 476
 477    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 478 }
 479
 480 static int
 481 iris_getparam(struct iris_screen *screen, int param, int *value)
 482 {
 483    struct drm_i915_getparam gp = { .param = param, .value = value };
 484
 485    if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 486       return -errno;
 487
 488    return 0;
 489 }
 490
 491 static bool
 492 iris_getparam_boolean(struct iris_screen *screen, int param)
 493 {
 494    int value = 0;
 495    return (iris_getparam(screen, param, &value) == 0) && value;
 496 }
 497
 498 static int
 499 iris_getparam_integer(struct iris_screen *screen, int param)
 500 {
 501    int value = -1;
 502
 503    if (iris_getparam(screen, param, &value) == 0)
 504       return value;
 505
 506    return -1;
 507 }
 508
 509 static void
 510 iris_shader_debug_log(void *data, const char *fmt, ...)
 511 {
 512    struct pipe_debug_callback *dbg = data;
 513    unsigned id = 0;
 514    va_list args;
 515
 516    if (!dbg->debug_message)
 517       return;
 518
 519    va_start(args, fmt);
 520    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
 521    va_end(args);
 522 }
 523
 524 static void
 525 iris_shader_perf_log(void *data, const char *fmt, ...)
 526 {
 527    struct pipe_debug_callback *dbg = data;
 528    unsigned id = 0;
 529    va_list args;
 530
 531    if (!dbg->debug_message)
 532       return;
 533
 534    va_start(args, fmt);
 535    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
 536    va_end(args);
 537 }
 538
 539 struct pipe_screen *
 540 iris_screen_create(int fd)
 541 {
 542    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 543    if (!screen)
 544       return NULL;
 545
 546    screen->fd = fd;
 547    screen->pci_id = iris_getparam_integer(screen, I915_PARAM_CHIPSET_ID);
 548
 549    if (!gen_get_device_info(screen->pci_id, &screen->devinfo))
 550       return NULL;
 551
 552    screen->devinfo.timestamp_frequency =
 553       iris_getparam_integer(screen, I915_PARAM_CS_TIMESTAMP_FREQUENCY);
 554
 555    screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
 556    if (!screen->bufmgr)
 557       return NULL;
 558
 559    screen->workaround_bo =
 560       iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
 561    if (!screen->workaround_bo)
 562       return NULL;
 563
 564    brw_process_intel_debug_variable();
 565
 566    bool hw_has_swizzling = false; // XXX: detect?
 567    isl_device_init(&screen->isl_dev, &screen->devinfo, hw_has_swizzling);
 568
 569    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 570    screen->compiler->shader_debug_log = iris_shader_debug_log;
 571    screen->compiler->shader_perf_log = iris_shader_perf_log;
 572    screen->compiler->supports_pull_constants = false;
 573
 574    slab_create_parent(&screen->transfer_pool,
 575                       sizeof(struct iris_transfer), 64);
 576
 577    screen->subslice_total =
 578       iris_getparam_integer(screen, I915_PARAM_SUBSLICE_TOTAL);
 579    assert(screen->subslice_total >= 1);
 580
 581    struct pipe_screen *pscreen = &screen->base;
 582
 583    iris_init_screen_fence_functions(pscreen);
 584    iris_init_screen_resource_functions(pscreen);
 585
 586    pscreen->destroy = iris_destroy_screen;
 587    pscreen->get_name = iris_get_name;
 588    pscreen->get_vendor = iris_get_vendor;
 589    pscreen->get_device_vendor = iris_get_device_vendor;
 590    pscreen->get_param = iris_get_param;
 591    pscreen->get_shader_param = iris_get_shader_param;
 592    pscreen->get_compute_param = iris_get_compute_param;
 593    pscreen->get_paramf = iris_get_paramf;
 594    pscreen->get_compiler_options = iris_get_compiler_options;
 595    pscreen->is_format_supported = iris_is_format_supported;
 596    pscreen->context_create = iris_create_context;
 597    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 598    pscreen->get_timestamp = iris_get_timestamp;
 599    pscreen->query_memory_info = iris_query_memory_info;
 600
 601    return pscreen;
 602 }