src/gallium/drivers/iris/iris_screen.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 /**
  24  * @file iris_screen.c
  25  *
  26  * Screen related driver hooks and capability lists.
  27  *
  28  * A program may use multiple rendering contexts (iris_context), but
  29  * they all share a common screen (iris_screen).  Global driver state
  30  * can be stored in the screen; it may be accessed by multiple threads.
  31  */
  32
  33 #include <stdio.h>
  34 #include <errno.h>
  35 #include <sys/ioctl.h>
  36 #include "pipe/p_defines.h"
  37 #include "pipe/p_state.h"
  38 #include "pipe/p_context.h"
  39 #include "pipe/p_screen.h"
  40 #include "util/debug.h"
  41 #include "util/u_inlines.h"
  42 #include "util/u_format.h"
  43 #include "util/u_transfer_helper.h"
  44 #include "util/u_upload_mgr.h"
  45 #include "util/ralloc.h"
  46 #include "drm-uapi/i915_drm.h"
  47 #include "iris_context.h"
  48 #include "iris_defines.h"
  49 #include "iris_fence.h"
  50 #include "iris_pipe.h"
  51 #include "iris_resource.h"
  52 #include "iris_screen.h"
  53 #include "intel/compiler/brw_compiler.h"
  54
  55 static void
  56 iris_flush_frontbuffer(struct pipe_screen *_screen,
  57                        struct pipe_resource *resource,
  58                        unsigned level, unsigned layer,
  59                        void *context_private, struct pipe_box *box)
  60 {
  61 }
  62
  63 static const char *
  64 iris_get_vendor(struct pipe_screen *pscreen)
  65 {
  66    return "Intel";
  67 }
  68
  69 static const char *
  70 iris_get_device_vendor(struct pipe_screen *pscreen)
  71 {
  72    return "Intel";
  73 }
  74
  75 static const char *
  76 iris_get_name(struct pipe_screen *pscreen)
  77 {
  78    struct iris_screen *screen = (struct iris_screen *)pscreen;
  79    static char buf[128];
  80    const char *chipset;
  81
  82    switch (screen->pci_id) {
  83 #undef CHIPSET
  84 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
  85 #include "pci_ids/i965_pci_ids.h"
  86    default:
  87       chipset = "Unknown Intel Chipset";
  88       break;
  89    }
  90
  91    snprintf(buf, sizeof(buf), "Mesa %s", chipset);
  92    return chipset;
  93 }
  94
  95 static int
  96 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  97 {
  98    struct iris_screen *screen = (struct iris_screen *)pscreen;
  99    const struct gen_device_info *devinfo = &screen->devinfo;
 100
 101    switch (param) {
 102    case PIPE_CAP_NPOT_TEXTURES:
 103    case PIPE_CAP_ANISOTROPIC_FILTER:
 104    case PIPE_CAP_POINT_SPRITE:
 105    case PIPE_CAP_OCCLUSION_QUERY:
 106    case PIPE_CAP_QUERY_TIME_ELAPSED:
 107    case PIPE_CAP_TEXTURE_SWIZZLE:
 108    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 109    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 110    case PIPE_CAP_SM3:
 111    case PIPE_CAP_PRIMITIVE_RESTART:
 112    case PIPE_CAP_INDEP_BLEND_ENABLE:
 113    case PIPE_CAP_INDEP_BLEND_FUNC:
 114    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 115    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 116    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 117    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 118    case PIPE_CAP_TGSI_INSTANCEID:
 119    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 120    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 121    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 122    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 123    case PIPE_CAP_CONDITIONAL_RENDER:
 124    case PIPE_CAP_TEXTURE_BARRIER:
 125    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 126    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 127    case PIPE_CAP_COMPUTE:
 128    case PIPE_CAP_START_INSTANCE:
 129    case PIPE_CAP_QUERY_TIMESTAMP:
 130    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 131    case PIPE_CAP_CUBE_MAP_ARRAY:
 132    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 133    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 134    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 135    case PIPE_CAP_TEXTURE_QUERY_LOD:
 136    case PIPE_CAP_SAMPLE_SHADING:
 137    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 138    case PIPE_CAP_DRAW_INDIRECT:
 139    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 140    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 141    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 142    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 143    case PIPE_CAP_ACCELERATED:
 144    case PIPE_CAP_UMA:
 145    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 146    case PIPE_CAP_CLIP_HALFZ:
 147    case PIPE_CAP_TGSI_TEXCOORD:
 148    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 149    case PIPE_CAP_DOUBLES:
 150    case PIPE_CAP_INT64:
 151    case PIPE_CAP_INT64_DIVMOD:
 152    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 153    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 154    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 155    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 156    case PIPE_CAP_CULL_DISTANCE:
 157    case PIPE_CAP_PACKED_UNIFORMS:
 158    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 159    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 160    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 161    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 162    case PIPE_CAP_QUERY_SO_OVERFLOW:
 163    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 164    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 165    case PIPE_CAP_TGSI_TXQS:
 166    case PIPE_CAP_TGSI_CLOCK:
 167    case PIPE_CAP_TGSI_BALLOT:
 168    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 169    case PIPE_CAP_CLEAR_TEXTURE:
 170    case PIPE_CAP_TGSI_VOTE:
 171    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 172    case PIPE_CAP_TEXTURE_GATHER_SM5:
 173    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 174    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 175    case PIPE_CAP_LOAD_CONSTBUF:
 176    case PIPE_CAP_NIR_COMPACT_ARRAYS:
 177    case PIPE_CAP_DRAW_PARAMETERS:
 178    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 179    case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
 180       return true;
 181    case PIPE_CAP_TGSI_FS_FBFETCH:
 182    case PIPE_CAP_POST_DEPTH_COVERAGE:
 183    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 184       return devinfo->gen >= 9;
 185    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 186       return 1;
 187    case PIPE_CAP_MAX_RENDER_TARGETS:
 188       return BRW_MAX_DRAW_BUFFERS;
 189    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 190    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 191       return IRIS_MAX_MIPLEVELS; /* 16384x16384 */
 192    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 193       return 12; /* 2048x2048 */
 194    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 195       return 4;
 196    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 197       return 2048;
 198    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 199       return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
 200    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 201       return BRW_MAX_SOL_BINDINGS;
 202    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 203       return 460;
 204    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 205       return 140;
 206    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 207       /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
 208       return 32;
 209    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 210       return IRIS_MAP_BUFFER_ALIGNMENT;
 211    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 212       /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
 213        * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
 214        * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
 215        * GPU and the CPU can be updating disjoint regions of the buffer
 216        * simultaneously and that will break if the regions overlap the same
 217        * cacheline.
 218        */
 219       return 64;
 220    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 221       return 1 << 27;
 222    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 223       return 16; // XXX: u_screen says 256 is the minimum value...
 224    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 225       return true; // XXX: ?????
 226    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 227       return IRIS_MAX_TEXTURE_BUFFER_SIZE;
 228    case PIPE_CAP_MAX_VIEWPORTS:
 229       return 16;
 230    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 231       return 256;
 232    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 233       return 1024;
 234    case PIPE_CAP_MAX_GS_INVOCATIONS:
 235       return 32;
 236    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 237       return 4;
 238    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 239       return -32;
 240    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 241       return 31;
 242    case PIPE_CAP_MAX_VERTEX_STREAMS:
 243       return 4;
 244    case PIPE_CAP_VENDOR_ID:
 245       return 0x8086;
 246    case PIPE_CAP_DEVICE_ID:
 247       return screen->pci_id;
 248    case PIPE_CAP_VIDEO_MEMORY:
 249       return INT_MAX; // XXX: bogus
 250    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 251    case PIPE_CAP_MAX_VARYINGS:
 252       return 32;
 253    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 254       /* AMD_pinned_memory assumes the flexibility of using client memory
 255        * for any buffer (incl. vertex buffers) which rules out the prospect
 256        * of using snooped buffers, as using snooped buffers without
 257        * cogniscience is likely to be detrimental to performance and require
 258        * extensive checking in the driver for correctness, e.g. to prevent
 259        * illegal snoop <-> snoop transfers.
 260        */
 261       return devinfo->has_llc;
 262
 263    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 264       return PIPE_CONTEXT_PRIORITY_LOW |
 265              PIPE_CONTEXT_PRIORITY_MEDIUM |
 266              PIPE_CONTEXT_PRIORITY_HIGH;
 267
 268    // XXX: don't hardcode 00:00:02.0 PCI here
 269    case PIPE_CAP_PCI_GROUP:
 270       return 0;
 271    case PIPE_CAP_PCI_BUS:
 272       return 0;
 273    case PIPE_CAP_PCI_DEVICE:
 274       return 2;
 275    case PIPE_CAP_PCI_FUNCTION:
 276       return 0;
 277
 278    default:
 279       return u_pipe_screen_get_param_defaults(pscreen, param);
 280    }
 281    return 0;
 282 }
 283
 284 static float
 285 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 286 {
 287    switch (param) {
 288    case PIPE_CAPF_MAX_LINE_WIDTH:
 289    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 290       return 7.375f;
 291
 292    case PIPE_CAPF_MAX_POINT_WIDTH:
 293    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 294       return 255.0f;
 295
 296    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 297       return 16.0f;
 298    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 299       return 15.0f;
 300    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 301    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 302    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 303       return 0.0f;
 304    default:
 305       unreachable("unknown param");
 306    }
 307 }
 308
 309 static int
 310 iris_get_shader_param(struct pipe_screen *pscreen,
 311                       enum pipe_shader_type p_stage,
 312                       enum pipe_shader_cap param)
 313 {
 314    gl_shader_stage stage = stage_from_pipe(p_stage);
 315
 316    /* this is probably not totally correct.. but it's a start: */
 317    switch (param) {
 318    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 319       return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
 320    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 321    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 322    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 323       return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
 324
 325    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 326       return UINT_MAX;
 327
 328    case PIPE_SHADER_CAP_MAX_INPUTS:
 329       return stage == MESA_SHADER_VERTEX ? 16 : 32;
 330    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 331       return 32;
 332    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 333       return 16 * 1024 * sizeof(float);
 334    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 335       return 16;
 336    case PIPE_SHADER_CAP_MAX_TEMPS:
 337       return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 338    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 339       return 0;
 340    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 341    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 342    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 343    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 344       /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
 345        * which we don't want.  Our compiler backend will check brw_compiler's
 346        * options and call nir_lower_indirect_derefs appropriately anyway.
 347        */
 348       return true;
 349    case PIPE_SHADER_CAP_SUBROUTINES:
 350       return 0;
 351    case PIPE_SHADER_CAP_INTEGERS:
 352    case PIPE_SHADER_CAP_SCALAR_ISA:
 353       return 1;
 354    case PIPE_SHADER_CAP_INT64_ATOMICS:
 355    case PIPE_SHADER_CAP_FP16:
 356       return 0;
 357    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 358    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 359    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 360       return IRIS_MAX_TEXTURE_SAMPLERS;
 361    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 362       return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
 363    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 364    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 365       return 0;
 366    case PIPE_SHADER_CAP_PREFERRED_IR:
 367       return PIPE_SHADER_IR_NIR;
 368    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 369       return 1 << PIPE_SHADER_IR_NIR;
 370    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 371       return 32;
 372    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 373    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 374    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 375    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 376    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 377    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 378    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 379    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 380       return 0;
 381    default:
 382       unreachable("unknown shader param");
 383    }
 384 }
 385
 386 static int
 387 iris_get_compute_param(struct pipe_screen *pscreen,
 388                        enum pipe_shader_ir ir_type,
 389                        enum pipe_compute_cap param,
 390                        void *ret)
 391 {
 392    struct iris_screen *screen = (struct iris_screen *)pscreen;
 393    const struct gen_device_info *devinfo = &screen->devinfo;
 394
 395    const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
 396    const uint32_t max_invocations = 32 * max_threads;
 397
 398 #define RET(x) do {                  \
 399    if (ret)                          \
 400       memcpy(ret, x, sizeof(x));     \
 401    return sizeof(x);                 \
 402 } while (0)
 403
 404    switch (param) {
 405    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 406       RET((uint32_t []){ 32 });
 407
 408    case PIPE_COMPUTE_CAP_IR_TARGET:
 409       if (ret)
 410          strcpy(ret, "gen");
 411       return 4;
 412
 413    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 414       RET((uint64_t []) { 3 });
 415
 416    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 417       RET(((uint64_t []) { 65535, 65535, 65535 }));
 418
 419    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 420       /* MaxComputeWorkGroupSize[0..2] */
 421       RET(((uint64_t []) {max_invocations, max_invocations, max_invocations}));
 422
 423    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 424       /* MaxComputeWorkGroupInvocations */
 425       RET((uint64_t []) { max_invocations });
 426
 427    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 428       /* MaxComputeSharedMemorySize */
 429       RET((uint64_t []) { 64 * 1024 });
 430
 431    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 432       RET((uint32_t []) { 1 });
 433
 434    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 435       RET((uint32_t []) { BRW_SUBGROUP_SIZE });
 436
 437    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 438    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 439    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 440    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 441    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 442    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 443    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 444       // XXX: I think these are for Clover...
 445       return 0;
 446
 447    default:
 448       unreachable("unknown compute param");
 449    }
 450 }
 451
 452 static uint64_t
 453 iris_get_timestamp(struct pipe_screen *pscreen)
 454 {
 455    struct iris_screen *screen = (struct iris_screen *) pscreen;
 456    const unsigned TIMESTAMP = 0x2358;
 457    uint64_t result;
 458
 459    iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
 460
 461    result = iris_timebase_scale(&screen->devinfo, result);
 462    result &= (1ull << TIMESTAMP_BITS) - 1;
 463
 464    return result;
 465 }
 466
 467 static void
 468 iris_destroy_screen(struct pipe_screen *pscreen)
 469 {
 470    struct iris_screen *screen = (struct iris_screen *) pscreen;
 471    iris_bo_unreference(screen->workaround_bo);
 472    u_transfer_helper_destroy(pscreen->transfer_helper);
 473    iris_bufmgr_destroy(screen->bufmgr);
 474    ralloc_free(screen);
 475 }
 476
 477 static void
 478 iris_query_memory_info(struct pipe_screen *pscreen,
 479                        struct pipe_memory_info *info)
 480 {
 481 }
 482
 483 static const void *
 484 iris_get_compiler_options(struct pipe_screen *pscreen,
 485                           enum pipe_shader_ir ir,
 486                           enum pipe_shader_type pstage)
 487 {
 488    struct iris_screen *screen = (struct iris_screen *) pscreen;
 489    gl_shader_stage stage = stage_from_pipe(pstage);
 490    assert(ir == PIPE_SHADER_IR_NIR);
 491
 492    return screen->compiler->glsl_compiler_options[stage].NirOptions;
 493 }
 494
 495 static int
 496 iris_getparam(struct iris_screen *screen, int param, int *value)
 497 {
 498    struct drm_i915_getparam gp = { .param = param, .value = value };
 499
 500    if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
 501       return -errno;
 502
 503    return 0;
 504 }
 505
 506 static int
 507 iris_getparam_integer(struct iris_screen *screen, int param)
 508 {
 509    int value = -1;
 510
 511    if (iris_getparam(screen, param, &value) == 0)
 512       return value;
 513
 514    return -1;
 515 }
 516
 517 static void
 518 iris_shader_debug_log(void *data, const char *fmt, ...)
 519 {
 520    struct pipe_debug_callback *dbg = data;
 521    unsigned id = 0;
 522    va_list args;
 523
 524    if (!dbg->debug_message)
 525       return;
 526
 527    va_start(args, fmt);
 528    dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
 529    va_end(args);
 530 }
 531
 532 static void
 533 iris_shader_perf_log(void *data, const char *fmt, ...)
 534 {
 535    struct pipe_debug_callback *dbg = data;
 536    unsigned id = 0;
 537    va_list args;
 538    va_start(args, fmt);
 539
 540    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
 541       va_list args_copy;
 542       va_copy(args_copy, args);
 543       vfprintf(stderr, fmt, args_copy);
 544       va_end(args_copy);
 545    }
 546
 547    if (dbg->debug_message) {
 548       dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
 549    }
 550
 551    va_end(args);
 552 }
 553
 554 struct pipe_screen *
 555 iris_screen_create(int fd, const struct pipe_screen_config *config)
 556 {
 557    struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
 558    if (!screen)
 559       return NULL;
 560
 561    screen->fd = fd;
 562    screen->pci_id = iris_getparam_integer(screen, I915_PARAM_CHIPSET_ID);
 563
 564    if (!gen_get_device_info(screen->pci_id, &screen->devinfo))
 565       return NULL;
 566
 567    if (screen->devinfo.gen < 8 || screen->devinfo.is_cherryview)
 568       return NULL;
 569
 570    screen->devinfo.timestamp_frequency =
 571       iris_getparam_integer(screen, I915_PARAM_CS_TIMESTAMP_FREQUENCY);
 572
 573    if (getenv("INTEL_NO_HW") != NULL)
 574       screen->no_hw = true;
 575
 576    screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
 577    if (!screen->bufmgr)
 578       return NULL;
 579
 580    screen->workaround_bo =
 581       iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
 582    if (!screen->workaround_bo)
 583       return NULL;
 584
 585    brw_process_intel_debug_variable();
 586
 587    screen->precompile = env_var_as_boolean("shader_precompile", true);
 588
 589    isl_device_init(&screen->isl_dev, &screen->devinfo, false);
 590
 591    screen->compiler = brw_compiler_create(screen, &screen->devinfo);
 592    screen->compiler->shader_debug_log = iris_shader_debug_log;
 593    screen->compiler->shader_perf_log = iris_shader_perf_log;
 594    screen->compiler->supports_pull_constants = false;
 595
 596    slab_create_parent(&screen->transfer_pool,
 597                       sizeof(struct iris_transfer), 64);
 598
 599    screen->subslice_total =
 600       iris_getparam_integer(screen, I915_PARAM_SUBSLICE_TOTAL);
 601    assert(screen->subslice_total >= 1);
 602
 603    struct pipe_screen *pscreen = &screen->base;
 604
 605    iris_init_screen_fence_functions(pscreen);
 606    iris_init_screen_resource_functions(pscreen);
 607
 608    pscreen->destroy = iris_destroy_screen;
 609    pscreen->get_name = iris_get_name;
 610    pscreen->get_vendor = iris_get_vendor;
 611    pscreen->get_device_vendor = iris_get_device_vendor;
 612    pscreen->get_param = iris_get_param;
 613    pscreen->get_shader_param = iris_get_shader_param;
 614    pscreen->get_compute_param = iris_get_compute_param;
 615    pscreen->get_paramf = iris_get_paramf;
 616    pscreen->get_compiler_options = iris_get_compiler_options;
 617    pscreen->is_format_supported = iris_is_format_supported;
 618    pscreen->context_create = iris_create_context;
 619    pscreen->flush_frontbuffer = iris_flush_frontbuffer;
 620    pscreen->get_timestamp = iris_get_timestamp;
 621    pscreen->query_memory_info = iris_query_memory_info;
 622
 623    return pscreen;
 624 }