src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp

   1 /*
   2  * Copyright 2011 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "codegen/nv50_ir_target_nvc0.h"
  24
  25 namespace nv50_ir {
  26
  27 Target *getTargetNVC0(unsigned int chipset)
  28 {
  29    return new TargetNVC0(chipset);
  30 }
  31
  32 TargetNVC0::TargetNVC0(unsigned int card) : Target(false, card >= 0xe4)
  33 {
  34    chipset = card;
  35    initOpInfo();
  36 }
  37
  38 // BULTINS / LIBRARY FUNCTIONS:
  39
  40 // lazyness -> will just hardcode everything for the time being
  41
  42 #include "lib/gf100.asm.h"
  43 #include "lib/gk104.asm.h"
  44 #include "lib/gk110.asm.h"
  45
  46 void
  47 TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const
  48 {
  49    switch (chipset & ~0xf) {
  50    case 0xe0:
  51       *code = (const uint32_t *)&gk104_builtin_code[0];
  52       *size = sizeof(gk104_builtin_code);
  53       break;
  54    case 0xf0:
  55    case 0x100:
  56       *code = (const uint32_t *)&gk110_builtin_code[0];
  57       *size = sizeof(gk110_builtin_code);
  58       break;
  59    default:
  60       *code = (const uint32_t *)&gf100_builtin_code[0];
  61       *size = sizeof(gf100_builtin_code);
  62       break;
  63    }
  64 }
  65
  66 uint32_t
  67 TargetNVC0::getBuiltinOffset(int builtin) const
  68 {
  69    assert(builtin < NVC0_BUILTIN_COUNT);
  70
  71    switch (chipset & ~0xf) {
  72    case 0xe0:
  73       return gk104_builtin_offsets[builtin];
  74    case 0xf0:
  75    case 0x100:
  76       return gk110_builtin_offsets[builtin];
  77    default:
  78       return gf100_builtin_offsets[builtin];
  79    }
  80 }
  81
  82 struct opProperties
  83 {
  84    operation op;
  85    unsigned int mNeg   : 4;
  86    unsigned int mAbs   : 4;
  87    unsigned int mNot   : 4;
  88    unsigned int mSat   : 4;
  89    unsigned int fConst : 3;
  90    unsigned int fImmd  : 4; // last bit indicates if full immediate is suppoted
  91 };
  92
  93 static const struct opProperties _initProps[] =
  94 {
  95    //           neg  abs  not  sat  c[]  imm
  96    { OP_ADD,    0x3, 0x3, 0x0, 0x8, 0x2, 0x2 | 0x8 },
  97    { OP_SUB,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 | 0x8 },
  98    { OP_MUL,    0x3, 0x0, 0x0, 0x8, 0x2, 0x2 | 0x8 },
  99    { OP_MAX,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 100    { OP_MIN,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 101    { OP_MAD,    0x7, 0x0, 0x0, 0x8, 0x6, 0x2 | 0x8 }, // special c[] constraint
 102    { OP_MADSP,  0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
 103    { OP_ABS,    0x0, 0x0, 0x0, 0x0, 0x1, 0x0 },
 104    { OP_NEG,    0x0, 0x1, 0x0, 0x0, 0x1, 0x0 },
 105    { OP_CVT,    0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
 106    { OP_CEIL,   0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
 107    { OP_FLOOR,  0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
 108    { OP_TRUNC,  0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
 109    { OP_AND,    0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
 110    { OP_OR,     0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
 111    { OP_XOR,    0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
 112    { OP_SHL,    0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
 113    { OP_SHR,    0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
 114    { OP_SET,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 115    { OP_SLCT,   0x4, 0x0, 0x0, 0x0, 0x6, 0x2 }, // special c[] constraint
 116    { OP_PREEX2, 0x1, 0x1, 0x0, 0x0, 0x1, 0x1 },
 117    { OP_PRESIN, 0x1, 0x1, 0x0, 0x0, 0x1, 0x1 },
 118    { OP_COS,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 119    { OP_SIN,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 120    { OP_EX2,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 121    { OP_LG2,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 122    { OP_RCP,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 123    { OP_RSQ,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
 124    { OP_DFDX,   0x1, 0x0, 0x0, 0x0, 0x0, 0x0 },
 125    { OP_DFDY,   0x1, 0x0, 0x0, 0x0, 0x0, 0x0 },
 126    { OP_CALL,   0x0, 0x0, 0x0, 0x0, 0x1, 0x0 },
 127    { OP_POPCNT, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 },
 128    { OP_INSBF,  0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
 129    { OP_EXTBF,  0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
 130    { OP_BFIND,  0x0, 0x0, 0x1, 0x0, 0x1, 0x1 },
 131    { OP_PERMT,  0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
 132    { OP_SET_AND, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 133    { OP_SET_OR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 134    { OP_SET_XOR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
 135    // saturate only:
 136    { OP_LINTERP, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0 },
 137    { OP_PINTERP, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0 },
 138    // nve4 ops:
 139    { OP_SULDB,   0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
 140    { OP_SUSTB,   0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
 141    { OP_SUSTP,   0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
 142    { OP_SUCLAMP, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
 143    { OP_SUBFM,   0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
 144    { OP_SUEAU,   0x0, 0x0, 0x0, 0x0, 0x6, 0x2 }
 145 };
 146
 147 void TargetNVC0::initOpInfo()
 148 {
 149    unsigned int i, j;
 150
 151    static const uint32_t commutative[(OP_LAST + 31) / 32] =
 152    {
 153       // ADD, MAD, MUL, AND, OR, XOR, MAX, MIN
 154       0x0670ca00, 0x0000003f, 0x00000000, 0x00000000
 155    };
 156
 157    static const uint32_t shortForm[(OP_LAST + 31) / 32] =
 158    {
 159       // ADD, MAD, MUL, AND, OR, XOR, PRESIN, PREEX2, SFN, CVT, PINTERP, MOV
 160       0x0670ca00, 0x00000000, 0x00000000, 0x00000000
 161    };
 162
 163    static const operation noDest[] =
 164    {
 165       OP_STORE, OP_WRSV, OP_EXPORT, OP_BRA, OP_CALL, OP_RET, OP_EXIT,
 166       OP_DISCARD, OP_CONT, OP_BREAK, OP_PRECONT, OP_PREBREAK, OP_PRERET,
 167       OP_JOIN, OP_JOINAT, OP_BRKPT, OP_MEMBAR, OP_EMIT, OP_RESTART,
 168       OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP,
 169       OP_SUREDB, OP_BAR
 170    };
 171
 172    static const operation noPred[] =
 173    {
 174       OP_CALL, OP_PRERET, OP_QUADON, OP_QUADPOP,
 175       OP_JOINAT, OP_PREBREAK, OP_PRECONT, OP_BRKPT
 176    };
 177
 178    for (i = 0; i < DATA_FILE_COUNT; ++i)
 179       nativeFileMap[i] = (DataFile)i;
 180    nativeFileMap[FILE_ADDRESS] = FILE_GPR;
 181
 182    for (i = 0; i < OP_LAST; ++i) {
 183       opInfo[i].variants = NULL;
 184       opInfo[i].op = (operation)i;
 185       opInfo[i].srcTypes = 1 << (int)TYPE_F32;
 186       opInfo[i].dstTypes = 1 << (int)TYPE_F32;
 187       opInfo[i].immdBits = 0;
 188       opInfo[i].srcNr = operationSrcNr[i];
 189
 190       for (j = 0; j < opInfo[i].srcNr; ++j) {
 191          opInfo[i].srcMods[j] = 0;
 192          opInfo[i].srcFiles[j] = 1 << (int)FILE_GPR;
 193       }
 194       opInfo[i].dstMods = 0;
 195       opInfo[i].dstFiles = 1 << (int)FILE_GPR;
 196
 197       opInfo[i].hasDest = 1;
 198       opInfo[i].vector = (i >= OP_TEX && i <= OP_TEXCSAA);
 199       opInfo[i].commutative = (commutative[i / 32] >> (i % 32)) & 1;
 200       opInfo[i].pseudo = (i < OP_MOV);
 201       opInfo[i].predicate = !opInfo[i].pseudo;
 202       opInfo[i].flow = (i >= OP_BRA && i <= OP_JOIN);
 203       opInfo[i].minEncSize = (shortForm[i / 32] & (1 << (i % 32))) ? 4 : 8;
 204    }
 205    for (i = 0; i < sizeof(noDest) / sizeof(noDest[0]); ++i)
 206       opInfo[noDest[i]].hasDest = 0;
 207    for (i = 0; i < sizeof(noPred) / sizeof(noPred[0]); ++i)
 208       opInfo[noPred[i]].predicate = 0;
 209
 210    for (i = 0; i < sizeof(_initProps) / sizeof(_initProps[0]); ++i) {
 211       const struct opProperties *prop = &_initProps[i];
 212
 213       for (int s = 0; s < 3; ++s) {
 214          if (prop->mNeg & (1 << s))
 215             opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_NEG;
 216          if (prop->mAbs & (1 << s))
 217             opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_ABS;
 218          if (prop->mNot & (1 << s))
 219             opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_NOT;
 220          if (prop->fConst & (1 << s))
 221             opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_MEMORY_CONST;
 222          if (prop->fImmd & (1 << s))
 223             opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_IMMEDIATE;
 224          if (prop->fImmd & 8)
 225             opInfo[prop->op].immdBits = 0xffffffff;
 226       }
 227       if (prop->mSat & 8)
 228          opInfo[prop->op].dstMods = NV50_IR_MOD_SAT;
 229    }
 230 }
 231
 232 unsigned int
 233 TargetNVC0::getFileSize(DataFile file) const
 234 {
 235    switch (file) {
 236    case FILE_NULL:          return 0;
 237    case FILE_GPR:           return (chipset >= NVISA_GK110_CHIPSET) ? 255 : 63;
 238    case FILE_PREDICATE:     return 7;
 239    case FILE_FLAGS:         return 1;
 240    case FILE_ADDRESS:       return 0;
 241    case FILE_IMMEDIATE:     return 0;
 242    case FILE_MEMORY_CONST:  return 65536;
 243    case FILE_SHADER_INPUT:  return 0x400;
 244    case FILE_SHADER_OUTPUT: return 0x400;
 245    case FILE_MEMORY_GLOBAL: return 0xffffffff;
 246    case FILE_MEMORY_SHARED: return 16 << 10;
 247    case FILE_MEMORY_LOCAL:  return 48 << 10;
 248    case FILE_SYSTEM_VALUE:  return 32;
 249    default:
 250       assert(!"invalid file");
 251       return 0;
 252    }
 253 }
 254
 255 unsigned int
 256 TargetNVC0::getFileUnit(DataFile file) const
 257 {
 258    if (file == FILE_GPR || file == FILE_ADDRESS || file == FILE_SYSTEM_VALUE)
 259       return 2;
 260    return 0;
 261 }
 262
 263 uint32_t
 264 TargetNVC0::getSVAddress(DataFile shaderFile, const Symbol *sym) const
 265 {
 266    const int idx = sym->reg.data.sv.index;
 267    const SVSemantic sv = sym->reg.data.sv.sv;
 268
 269    const bool isInput = shaderFile == FILE_SHADER_INPUT;
 270    const bool kepler = getChipset() >= NVISA_GK104_CHIPSET;
 271
 272    switch (sv) {
 273    case SV_POSITION:       return 0x070 + idx * 4;
 274    case SV_INSTANCE_ID:    return 0x2f8;
 275    case SV_VERTEX_ID:      return 0x2fc;
 276    case SV_PRIMITIVE_ID:   return isInput ? 0x060 : 0x040;
 277    case SV_LAYER:          return 0x064;
 278    case SV_VIEWPORT_INDEX: return 0x068;
 279    case SV_POINT_SIZE:     return 0x06c;
 280    case SV_CLIP_DISTANCE:  return 0x2c0 + idx * 4;
 281    case SV_POINT_COORD:    return 0x2e0 + idx * 4;
 282    case SV_FACE:           return 0x3fc;
 283    case SV_TESS_FACTOR:    return 0x000 + idx * 4;
 284    case SV_TESS_COORD:     return 0x2f0 + idx * 4;
 285    case SV_NTID:           return kepler ? (0x00 + idx * 4) : ~0;
 286    case SV_NCTAID:         return kepler ? (0x0c + idx * 4) : ~0;
 287    case SV_GRIDID:         return kepler ? 0x18 : ~0;
 288    case SV_SAMPLE_INDEX:   return 0;
 289    case SV_SAMPLE_POS:     return 0;
 290    case SV_SAMPLE_MASK:    return 0;
 291    default:
 292       return 0xffffffff;
 293    }
 294 }
 295
 296 bool
 297 TargetNVC0::insnCanLoad(const Instruction *i, int s,
 298                         const Instruction *ld) const
 299 {
 300    DataFile sf = ld->src(0).getFile();
 301
 302    // immediate 0 can be represented by GPR $r63/$r255
 303    if (sf == FILE_IMMEDIATE && ld->getSrc(0)->reg.data.u64 == 0)
 304       return (!i->isPseudo() &&
 305               !i->asTex() &&
 306               i->op != OP_EXPORT && i->op != OP_STORE);
 307
 308    if (s >= opInfo[i->op].srcNr)
 309       return false;
 310    if (!(opInfo[i->op].srcFiles[s] & (1 << (int)sf)))
 311       return false;
 312
 313    // indirect loads can only be done by OP_LOAD/VFETCH/INTERP on nvc0
 314    if (ld->src(0).isIndirect(0))
 315       return false;
 316
 317    for (int k = 0; i->srcExists(k); ++k) {
 318       if (i->src(k).getFile() == FILE_IMMEDIATE) {
 319          if (k == 2 && i->op == OP_SUCLAMP) // special case
 320             continue;
 321          if (i->getSrc(k)->reg.data.u64 != 0)
 322             return false;
 323       } else
 324       if (i->src(k).getFile() != FILE_GPR &&
 325           i->src(k).getFile() != FILE_PREDICATE) {
 326          return false;
 327       }
 328    }
 329
 330    // not all instructions support full 32 bit immediates
 331    if (sf == FILE_IMMEDIATE) {
 332       Storage &reg = ld->getSrc(0)->asImm()->reg;
 333
 334       if (opInfo[i->op].immdBits != 0xffffffff) {
 335          if (i->sType == TYPE_F32) {
 336             if (reg.data.u32 & 0xfff)
 337                return false;
 338          } else
 339          if (i->sType == TYPE_S32 || i->sType == TYPE_U32) {
 340             // with u32, 0xfffff counts as 0xffffffff as well
 341             if (reg.data.s32 > 0x7ffff || reg.data.s32 < -0x80000)
 342                return false;
 343          }
 344       } else
 345       if (i->op == OP_MAD || i->op == OP_FMA) {
 346          // requires src == dst, cannot decide before RA
 347          // (except if we implement more constraints)
 348          if (ld->getSrc(0)->asImm()->reg.data.u32 & 0xfff)
 349             return false;
 350       } else
 351       if (i->op == OP_ADD && i->sType == TYPE_F32) {
 352          // add f32 LIMM cannot saturate
 353          if (i->saturate && (reg.data.u32 & 0xfff))
 354             return false;
 355       }
 356    }
 357
 358    return true;
 359 }
 360
 361 bool
 362 TargetNVC0::isAccessSupported(DataFile file, DataType ty) const
 363 {
 364    if (ty == TYPE_NONE)
 365       return false;
 366    if (file == FILE_MEMORY_CONST && getChipset() >= 0xe0) // wrong encoding ?
 367       return typeSizeof(ty) <= 8;
 368    if (ty == TYPE_B96)
 369       return false;
 370    return true;
 371 }
 372
 373 bool
 374 TargetNVC0::isOpSupported(operation op, DataType ty) const
 375 {
 376    if ((op == OP_MAD || op == OP_FMA) && (ty != TYPE_F32))
 377       return false;
 378    if (op == OP_SAD && ty != TYPE_S32 && ty != TYPE_U32)
 379       return false;
 380    if (op == OP_POW || op == OP_SQRT || op == OP_DIV || op == OP_MOD)
 381       return false;
 382    return true;
 383 }
 384
 385 bool
 386 TargetNVC0::isModSupported(const Instruction *insn, int s, Modifier mod) const
 387 {
 388    if (!isFloatType(insn->dType)) {
 389       switch (insn->op) {
 390       case OP_ABS:
 391       case OP_NEG:
 392       case OP_CVT:
 393       case OP_CEIL:
 394       case OP_FLOOR:
 395       case OP_TRUNC:
 396       case OP_AND:
 397       case OP_OR:
 398       case OP_XOR:
 399       case OP_POPCNT:
 400       case OP_BFIND:
 401          break;
 402       case OP_SET:
 403          if (insn->sType != TYPE_F32)
 404             return false;
 405          break;
 406       case OP_ADD:
 407          if (mod.abs())
 408             return false;
 409          if (insn->src(s ? 0 : 1).mod.neg())
 410             return false;
 411          break;
 412       case OP_SUB:
 413          if (s == 0)
 414             return insn->src(1).mod.neg() ? false : true;
 415          break;
 416       default:
 417          return false;
 418       }
 419    }
 420    if (s > 3)
 421       return false;
 422    return (mod & Modifier(opInfo[insn->op].srcMods[s])) == mod;
 423 }
 424
 425 bool
 426 TargetNVC0::mayPredicate(const Instruction *insn, const Value *pred) const
 427 {
 428    if (insn->getPredicate())
 429       return false;
 430    return opInfo[insn->op].predicate;
 431 }
 432
 433 bool
 434 TargetNVC0::isSatSupported(const Instruction *insn) const
 435 {
 436    if (insn->op == OP_CVT)
 437       return true;
 438    if (!(opInfo[insn->op].dstMods & NV50_IR_MOD_SAT))
 439       return false;
 440
 441    if (insn->dType == TYPE_U32)
 442       return (insn->op == OP_ADD) || (insn->op == OP_MAD);
 443
 444    // add f32 LIMM cannot saturate
 445    if (insn->op == OP_ADD && insn->sType == TYPE_F32) {
 446       if (insn->getSrc(1)->asImm() &&
 447           insn->getSrc(1)->reg.data.u32 & 0xfff)
 448          return false;
 449    }
 450
 451    return insn->dType == TYPE_F32;
 452 }
 453
 454 bool
 455 TargetNVC0::isPostMultiplySupported(operation op, float f, int& e) const
 456 {
 457    if (op != OP_MUL)
 458       return false;
 459    f = fabsf(f);
 460    e = static_cast<int>(log2f(f));
 461    if (e < -3 || e > 3)
 462       return false;
 463    return f == exp2f(static_cast<float>(e));
 464 }
 465
 466 // TODO: better values
 467 // this could be more precise, e.g. depending on the issue-to-read/write delay
 468 // of the depending instruction, but it's good enough
 469 int TargetNVC0::getLatency(const Instruction *i) const
 470 {
 471    if (chipset >= 0xe4) {
 472       if (i->dType == TYPE_F64 || i->sType == TYPE_F64)
 473          return 20;
 474       switch (i->op) {
 475       case OP_LINTERP:
 476       case OP_PINTERP:
 477          return 15;
 478       case OP_LOAD:
 479          if (i->src(0).getFile() == FILE_MEMORY_CONST)
 480             return 9;
 481          // fall through
 482       case OP_VFETCH:
 483          return 24;
 484       default:
 485          if (Target::getOpClass(i->op) == OPCLASS_TEXTURE)
 486             return 17;
 487          if (i->op == OP_MUL && i->dType != TYPE_F32)
 488             return 15;
 489          return 9;
 490       }
 491    } else {
 492       if (i->op == OP_LOAD) {
 493          if (i->cache == CACHE_CV)
 494             return 700;
 495          return 48;
 496       }
 497       return 24;
 498    }
 499    return 32;
 500 }
 501
 502 // These are "inverse" throughput values, i.e. the number of cycles required
 503 // to issue a specific instruction for a full warp (32 threads).
 504 //
 505 // Assuming we have more than 1 warp in flight, a higher issue latency results
 506 // in a lower result latency since the MP will have spent more time with other
 507 // warps.
 508 // This also helps to determine the number of cycles between instructions in
 509 // a single warp.
 510 //
 511 int TargetNVC0::getThroughput(const Instruction *i) const
 512 {
 513    // TODO: better values
 514    if (i->dType == TYPE_F32) {
 515       switch (i->op) {
 516       case OP_ADD:
 517       case OP_MUL:
 518       case OP_MAD:
 519       case OP_FMA:
 520          return 1;
 521       case OP_CVT:
 522       case OP_CEIL:
 523       case OP_FLOOR:
 524       case OP_TRUNC:
 525       case OP_SET:
 526       case OP_SLCT:
 527       case OP_MIN:
 528       case OP_MAX:
 529          return 2;
 530       case OP_RCP:
 531       case OP_RSQ:
 532       case OP_LG2:
 533       case OP_SIN:
 534       case OP_COS:
 535       case OP_PRESIN:
 536       case OP_PREEX2:
 537       default:
 538          return 8;
 539       }
 540    } else
 541    if (i->dType == TYPE_U32 || i->dType == TYPE_S32) {
 542       switch (i->op) {
 543       case OP_ADD:
 544       case OP_AND:
 545       case OP_OR:
 546       case OP_XOR:
 547       case OP_NOT:
 548          return 1;
 549       case OP_MUL:
 550       case OP_MAD:
 551       case OP_CVT:
 552       case OP_SET:
 553       case OP_SLCT:
 554       case OP_SHL:
 555       case OP_SHR:
 556       case OP_NEG:
 557       case OP_ABS:
 558       case OP_MIN:
 559       case OP_MAX:
 560       default:
 561          return 2;
 562       }
 563    } else
 564    if (i->dType == TYPE_F64) {
 565       return 2;
 566    } else {
 567       return 1;
 568    }
 569 }
 570
 571 bool TargetNVC0::canDualIssue(const Instruction *a, const Instruction *b) const
 572 {
 573    const OpClass clA = operationClass[a->op];
 574    const OpClass clB = operationClass[b->op];
 575
 576    if (getChipset() >= 0xe4) {
 577       // not texturing
 578       // not if the 2nd instruction isn't necessarily executed
 579       if (clA == OPCLASS_TEXTURE || clA == OPCLASS_FLOW)
 580          return false;
 581       // anything with MOV
 582       if (a->op == OP_MOV || b->op == OP_MOV)
 583          return true;
 584       if (clA == clB) {
 585          // only F32 arith or integer additions
 586          if (clA != OPCLASS_ARITH)
 587             return false;
 588          return (a->dType == TYPE_F32 || a->op == OP_ADD ||
 589                  b->dType == TYPE_F32 || b->op == OP_ADD);
 590       }
 591       // nothing with TEXBAR
 592       if (a->op == OP_TEXBAR || b->op == OP_TEXBAR)
 593          return false;
 594       // no loads and stores accessing the the same space
 595       if ((clA == OPCLASS_LOAD && clB == OPCLASS_STORE) ||
 596           (clB == OPCLASS_LOAD && clA == OPCLASS_STORE))
 597          if (a->src(0).getFile() == b->src(0).getFile())
 598             return false;
 599       // no > 32-bit ops
 600       if (typeSizeof(a->dType) > 4 || typeSizeof(b->dType) > 4 ||
 601           typeSizeof(a->sType) > 4 || typeSizeof(b->sType) > 4)
 602          return false;
 603       return true;
 604    } else {
 605       return false; // info not needed (yet)
 606    }
 607 }
 608
 609 } // namespace nv50_ir