src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 static boolean
  45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  46                                 enum pipe_format format,
  47                                 enum pipe_texture_target target,
  48                                 unsigned sample_count,
  49                                 unsigned bindings)
  50 {
  51    if (sample_count > 8)
  52       return false;
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return false;
  55    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  56       return false;
  57
  58    switch (format) {
  59    case PIPE_FORMAT_Z16_UNORM:
  60       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  61          return false;
  62       break;
  63    default:
  64       break;
  65    }
  66
  67    if (bindings & PIPE_BIND_LINEAR)
  68       if (util_format_is_depth_or_stencil(format) ||
  69           (target != PIPE_TEXTURE_1D &&
  70            target != PIPE_TEXTURE_2D &&
  71            target != PIPE_TEXTURE_RECT) ||
  72           sample_count > 1)
  73          return false;
  74
  75    /* shared is always supported */
  76    bindings &= ~(PIPE_BIND_LINEAR |
  77                  PIPE_BIND_SHARED);
  78
  79    return (( nv50_format_table[format].usage |
  80             nv50_vertex_format[format].usage) & bindings) == bindings;
  81 }
  82
  83 static int
  84 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  85 {
  86    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  87    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  88
  89    switch (param) {
  90    /* non-boolean caps */
  91    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  92       return 14;
  93    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  94       return 12;
  95    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  96       return 14;
  97    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  98       return 512;
  99    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 100    case PIPE_CAP_MIN_TEXEL_OFFSET:
 101       return -8;
 102    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 103    case PIPE_CAP_MAX_TEXEL_OFFSET:
 104       return 7;
 105    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 106       return 128 * 1024 * 1024;
 107    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 108       return 330;
 109    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 110       return 140;
 111    case PIPE_CAP_MAX_RENDER_TARGETS:
 112       return 8;
 113    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 114       return 1;
 115    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 116       return 4;
 117    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 118    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 119       return 64;
 120    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 121    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 122       return 1024;
 123    case PIPE_CAP_MAX_VERTEX_STREAMS:
 124       return 1;
 125    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 126       return 2048;
 127    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 128       return 256;
 129    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 130       return 16; /* 256 for binding as RT, but that's not possible in GL */
 131    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 132       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 133    case PIPE_CAP_MAX_VIEWPORTS:
 134       return NV50_MAX_VIEWPORTS;
 135    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 136       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 137    case PIPE_CAP_ENDIANNESS:
 138       return PIPE_ENDIAN_LITTLE;
 139    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 140       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 141    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 142       return NV50_MAX_WINDOW_RECTANGLES;
 143
 144    /* supported caps */
 145    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 146    case PIPE_CAP_TEXTURE_SWIZZLE:
 147    case PIPE_CAP_NPOT_TEXTURES:
 148    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 149    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 150    case PIPE_CAP_ANISOTROPIC_FILTER:
 151    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 152    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 153    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 154    case PIPE_CAP_POINT_SPRITE:
 155    case PIPE_CAP_SM3:
 156    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 157    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 158    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 159    case PIPE_CAP_QUERY_TIMESTAMP:
 160    case PIPE_CAP_QUERY_TIME_ELAPSED:
 161    case PIPE_CAP_OCCLUSION_QUERY:
 162    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 163    case PIPE_CAP_INDEP_BLEND_ENABLE:
 164    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 165    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 166    case PIPE_CAP_PRIMITIVE_RESTART:
 167    case PIPE_CAP_TGSI_INSTANCEID:
 168    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 169    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 170    case PIPE_CAP_CONDITIONAL_RENDER:
 171    case PIPE_CAP_TEXTURE_BARRIER:
 172    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 173    case PIPE_CAP_START_INSTANCE:
 174    case PIPE_CAP_USER_VERTEX_BUFFERS:
 175    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 176    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 177    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 178    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 179    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 180    case PIPE_CAP_CLIP_HALFZ:
 181    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 182    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 183    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 184    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 185    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 186    case PIPE_CAP_TGSI_TXQS:
 187    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 188    case PIPE_CAP_SHAREABLE_SHADERS:
 189    case PIPE_CAP_CLEAR_TEXTURE:
 190    case PIPE_CAP_COMPUTE:
 191    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 192    case PIPE_CAP_INVALIDATE_BUFFER:
 193    case PIPE_CAP_STRING_MARKER:
 194    case PIPE_CAP_CULL_DISTANCE:
 195    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 196    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 197    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 198    case PIPE_CAP_TGSI_CLOCK:
 199    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 200    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 201       return 1;
 202    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 203       return 1; /* class_3d >= NVA0_3D_CLASS; */
 204    /* supported on nva0+ */
 205    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 206       return class_3d >= NVA0_3D_CLASS;
 207    /* supported on nva3+ */
 208    case PIPE_CAP_CUBE_MAP_ARRAY:
 209    case PIPE_CAP_INDEP_BLEND_FUNC:
 210    case PIPE_CAP_TEXTURE_QUERY_LOD:
 211    case PIPE_CAP_SAMPLE_SHADING:
 212    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 213       return class_3d >= NVA3_3D_CLASS;
 214
 215    /* unsupported caps */
 216    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 217    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 218    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 219    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 220    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 221    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 222    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 223    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 224    case PIPE_CAP_TGSI_TEXCOORD:
 225    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 226    case PIPE_CAP_TEXTURE_GATHER_SM5:
 227    case PIPE_CAP_FAKE_SW_MSAA:
 228    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 229    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 230    case PIPE_CAP_DRAW_INDIRECT:
 231    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 232    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 233    case PIPE_CAP_VERTEXID_NOBASE:
 234    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 235    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 236    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 237    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 238    case PIPE_CAP_DRAW_PARAMETERS:
 239    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 240    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 241    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 242    case PIPE_CAP_GENERATE_MIPMAP:
 243    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 244    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 245    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 246    case PIPE_CAP_QUERY_MEMORY_INFO:
 247    case PIPE_CAP_PCI_GROUP:
 248    case PIPE_CAP_PCI_BUS:
 249    case PIPE_CAP_PCI_DEVICE:
 250    case PIPE_CAP_PCI_FUNCTION:
 251    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 252    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 253    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 254    case PIPE_CAP_TGSI_VOTE:
 255    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 256    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 257    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 258    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 259    case PIPE_CAP_NATIVE_FENCE_FD:
 260    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 261    case PIPE_CAP_TGSI_FS_FBFETCH:
 262    case PIPE_CAP_DOUBLES:
 263    case PIPE_CAP_INT64:
 264    case PIPE_CAP_INT64_DIVMOD:
 265    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 266    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 267    case PIPE_CAP_TGSI_BALLOT:
 268    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 269    case PIPE_CAP_POST_DEPTH_COVERAGE:
 270    case PIPE_CAP_BINDLESS_TEXTURE:
 271    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 272    case PIPE_CAP_QUERY_SO_OVERFLOW:
 273    case PIPE_CAP_MEMOBJ:
 274    case PIPE_CAP_LOAD_CONSTBUF:
 275    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 276    case PIPE_CAP_TILE_RASTER_ORDER:
 277    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 278    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 279    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 280    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 281    case PIPE_CAP_FENCE_SIGNAL:
 282    case PIPE_CAP_CONSTBUF0_FLAGS:
 283    case PIPE_CAP_PACKED_UNIFORMS:
 284    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 285    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 286    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 287    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 288    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 289    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 290    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 291       return 0;
 292
 293    case PIPE_CAP_VENDOR_ID:
 294       return 0x10de;
 295    case PIPE_CAP_DEVICE_ID: {
 296       uint64_t device_id;
 297       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 298          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 299          return -1;
 300       }
 301       return device_id;
 302    }
 303    case PIPE_CAP_ACCELERATED:
 304       return 1;
 305    case PIPE_CAP_VIDEO_MEMORY:
 306       return dev->vram_size >> 20;
 307    case PIPE_CAP_UMA:
 308       return 0;
 309    }
 310
 311    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 312    return 0;
 313 }
 314
 315 static int
 316 nv50_screen_get_shader_param(struct pipe_screen *pscreen,
 317                              enum pipe_shader_type shader,
 318                              enum pipe_shader_cap param)
 319 {
 320    switch (shader) {
 321    case PIPE_SHADER_VERTEX:
 322    case PIPE_SHADER_GEOMETRY:
 323    case PIPE_SHADER_FRAGMENT:
 324       break;
 325    case PIPE_SHADER_COMPUTE:
 326    default:
 327       return 0;
 328    }
 329
 330    switch (param) {
 331    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 332    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 333    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 334    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 335       return 16384;
 336    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 337       return 4;
 338    case PIPE_SHADER_CAP_MAX_INPUTS:
 339       if (shader == PIPE_SHADER_VERTEX)
 340          return 32;
 341       return 15;
 342    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 343       return 16;
 344    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 345       return 65536;
 346    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 347       return NV50_MAX_PIPE_CONSTBUFS;
 348    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 349       return shader != PIPE_SHADER_FRAGMENT;
 350    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 351    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 352    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 353       return 1;
 354    case PIPE_SHADER_CAP_MAX_TEMPS:
 355       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 356    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 357       return 1;
 358    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 359       return 1;
 360    case PIPE_SHADER_CAP_INT64_ATOMICS:
 361    case PIPE_SHADER_CAP_FP16:
 362    case PIPE_SHADER_CAP_SUBROUTINES:
 363       return 0; /* please inline, or provide function declarations */
 364    case PIPE_SHADER_CAP_INTEGERS:
 365       return 1;
 366    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 367       return 1;
 368    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 369       /* The chip could handle more sampler views than samplers */
 370    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 371       return MIN2(16, PIPE_MAX_SAMPLERS);
 372    case PIPE_SHADER_CAP_PREFERRED_IR:
 373       return PIPE_SHADER_IR_TGSI;
 374    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 375       return 32;
 376    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 377    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 378    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 379    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 380    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 381    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 382    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 383    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 384    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 385    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 386    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 387       return 0;
 388    case PIPE_SHADER_CAP_SCALAR_ISA:
 389       return 1;
 390    default:
 391       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 392       return 0;
 393    }
 394 }
 395
 396 static float
 397 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 398 {
 399    switch (param) {
 400    case PIPE_CAPF_MAX_LINE_WIDTH:
 401    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 402       return 10.0f;
 403    case PIPE_CAPF_MAX_POINT_WIDTH:
 404    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 405       return 64.0f;
 406    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 407       return 16.0f;
 408    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 409       return 4.0f;
 410    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 411    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 412    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 413       return 0.0f;
 414    }
 415
 416    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 417    return 0.0f;
 418 }
 419
 420 static int
 421 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 422                               enum pipe_shader_ir ir_type,
 423                               enum pipe_compute_cap param, void *data)
 424 {
 425    struct nv50_screen *screen = nv50_screen(pscreen);
 426
 427 #define RET(x) do {                  \
 428    if (data)                         \
 429       memcpy(data, x, sizeof(x));    \
 430    return sizeof(x);                 \
 431 } while (0)
 432
 433    switch (param) {
 434    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 435       RET((uint64_t []) { 2 });
 436    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 437       RET(((uint64_t []) { 65535, 65535 }));
 438    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 439       RET(((uint64_t []) { 512, 512, 64 }));
 440    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 441       RET((uint64_t []) { 512 });
 442    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 443       RET((uint64_t []) { 1ULL << 32 });
 444    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 445       RET((uint64_t []) { 16 << 10 });
 446    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 447       RET((uint64_t []) { 16 << 10 });
 448    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 449       RET((uint64_t []) { 4096 });
 450    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 451       RET((uint32_t []) { 32 });
 452    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 453       RET((uint64_t []) { 1ULL << 40 });
 454    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 455       RET((uint32_t []) { 0 });
 456    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 457       RET((uint32_t []) { screen->mp_count });
 458    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 459       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 460    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 461       RET((uint32_t []) { 32 });
 462    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 463       RET((uint64_t []) { 0 });
 464    default:
 465       return 0;
 466    }
 467
 468 #undef RET
 469 }
 470
 471 static void
 472 nv50_screen_destroy(struct pipe_screen *pscreen)
 473 {
 474    struct nv50_screen *screen = nv50_screen(pscreen);
 475
 476    if (!nouveau_drm_screen_unref(&screen->base))
 477       return;
 478
 479    if (screen->base.fence.current) {
 480       struct nouveau_fence *current = NULL;
 481
 482       /* nouveau_fence_wait will create a new current fence, so wait on the
 483        * _current_ one, and remove both.
 484        */
 485       nouveau_fence_ref(screen->base.fence.current, &current);
 486       nouveau_fence_wait(current, NULL);
 487       nouveau_fence_ref(NULL, &current);
 488       nouveau_fence_ref(NULL, &screen->base.fence.current);
 489    }
 490    if (screen->base.pushbuf)
 491       screen->base.pushbuf->user_priv = NULL;
 492
 493    if (screen->blitter)
 494       nv50_blitter_destroy(screen);
 495    if (screen->pm.prog) {
 496       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 497       nv50_program_destroy(NULL, screen->pm.prog);
 498       FREE(screen->pm.prog);
 499    }
 500
 501    nouveau_bo_ref(NULL, &screen->code);
 502    nouveau_bo_ref(NULL, &screen->tls_bo);
 503    nouveau_bo_ref(NULL, &screen->stack_bo);
 504    nouveau_bo_ref(NULL, &screen->txc);
 505    nouveau_bo_ref(NULL, &screen->uniforms);
 506    nouveau_bo_ref(NULL, &screen->fence.bo);
 507
 508    nouveau_heap_destroy(&screen->vp_code_heap);
 509    nouveau_heap_destroy(&screen->gp_code_heap);
 510    nouveau_heap_destroy(&screen->fp_code_heap);
 511
 512    FREE(screen->tic.entries);
 513
 514    nouveau_object_del(&screen->tesla);
 515    nouveau_object_del(&screen->eng2d);
 516    nouveau_object_del(&screen->m2mf);
 517    nouveau_object_del(&screen->compute);
 518    nouveau_object_del(&screen->sync);
 519
 520    nouveau_screen_fini(&screen->base);
 521
 522    FREE(screen);
 523 }
 524
 525 static void
 526 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 527 {
 528    struct nv50_screen *screen = nv50_screen(pscreen);
 529    struct nouveau_pushbuf *push = screen->base.pushbuf;
 530
 531    /* we need to do it after possible flush in MARK_RING */
 532    *sequence = ++screen->base.fence.sequence;
 533
 534    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 535    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 536    PUSH_DATAh(push, screen->fence.bo->offset);
 537    PUSH_DATA (push, screen->fence.bo->offset);
 538    PUSH_DATA (push, *sequence);
 539    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 540                     NV50_3D_QUERY_GET_UNK4 |
 541                     NV50_3D_QUERY_GET_UNIT_CROP |
 542                     NV50_3D_QUERY_GET_TYPE_QUERY |
 543                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 544                     NV50_3D_QUERY_GET_SHORT);
 545 }
 546
 547 static u32
 548 nv50_screen_fence_update(struct pipe_screen *pscreen)
 549 {
 550    return nv50_screen(pscreen)->fence.map[0];
 551 }
 552
 553 static void
 554 nv50_screen_init_hwctx(struct nv50_screen *screen)
 555 {
 556    struct nouveau_pushbuf *push = screen->base.pushbuf;
 557    struct nv04_fifo *fifo;
 558    unsigned i;
 559
 560    fifo = (struct nv04_fifo *)screen->base.channel->data;
 561
 562    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 563    PUSH_DATA (push, screen->m2mf->handle);
 564    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 565    PUSH_DATA (push, screen->sync->handle);
 566    PUSH_DATA (push, fifo->vram);
 567    PUSH_DATA (push, fifo->vram);
 568
 569    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 570    PUSH_DATA (push, screen->eng2d->handle);
 571    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 572    PUSH_DATA (push, screen->sync->handle);
 573    PUSH_DATA (push, fifo->vram);
 574    PUSH_DATA (push, fifo->vram);
 575    PUSH_DATA (push, fifo->vram);
 576    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 577    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 578    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 579    PUSH_DATA (push, 0);
 580    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 581    PUSH_DATA (push, 0);
 582    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 583    PUSH_DATA (push, 1);
 584    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 585    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 586
 587    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 588    PUSH_DATA (push, screen->tesla->handle);
 589
 590    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 591    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 592
 593    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 594    PUSH_DATA (push, screen->sync->handle);
 595    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 596    for (i = 0; i < 11; ++i)
 597       PUSH_DATA(push, fifo->vram);
 598    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 599    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 600       PUSH_DATA(push, fifo->vram);
 601
 602    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 603    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 604    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 605    PUSH_DATA (push, 0xf);
 606
 607    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 608       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 609       PUSH_DATA (push, 0x18);
 610    }
 611
 612    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 613    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 614
 615    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 616    for (i = 0; i < 8; ++i)
 617       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 618
 619    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 620    PUSH_DATA (push, 1);
 621
 622    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 623    PUSH_DATA (push, 0);
 624    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 625    PUSH_DATA (push, 0);
 626    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 627    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 628    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 629    PUSH_DATA (push, 0);
 630    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 631    PUSH_DATA (push, 1);
 632    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 633    PUSH_DATA (push, 1);
 634
 635    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 636       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 637       PUSH_DATA (push, 0);
 638    }
 639
 640    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 641    PUSH_DATA (push, 0);
 642    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 643    PUSH_DATA (push, 0);
 644    PUSH_DATA (push, 0);
 645    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 646    PUSH_DATA (push, 0x3f);
 647
 648    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 649    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 650    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 651
 652    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 653    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 654    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 655
 656    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 657    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 658    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 659
 660    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 661    PUSH_DATAh(push, screen->tls_bo->offset);
 662    PUSH_DATA (push, screen->tls_bo->offset);
 663    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 664
 665    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 666    PUSH_DATAh(push, screen->stack_bo->offset);
 667    PUSH_DATA (push, screen->stack_bo->offset);
 668    PUSH_DATA (push, 4);
 669
 670    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 671    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 672    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 673    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 674
 675    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 676    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 677    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 678    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 679
 680    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 681    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 682    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 683    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 684
 685    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 686    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 687    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 688    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 689
 690    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 691    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 692    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 693    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 694
 695    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 696    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 697    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 698    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 699    PUSH_DATAf(push, 0.0f);
 700    PUSH_DATAf(push, 0.0f);
 701    PUSH_DATAf(push, 0.0f);
 702    PUSH_DATAf(push, 0.0f);
 703    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 704    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 705    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 706
 707    nv50_upload_ms_info(push);
 708
 709    /* max TIC (bits 4:8) & TSC bindings, per program type */
 710    for (i = 0; i < 3; ++i) {
 711       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 712       PUSH_DATA (push, 0x54);
 713    }
 714
 715    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 716    PUSH_DATAh(push, screen->txc->offset);
 717    PUSH_DATA (push, screen->txc->offset);
 718    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 719
 720    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 721    PUSH_DATAh(push, screen->txc->offset + 65536);
 722    PUSH_DATA (push, screen->txc->offset + 65536);
 723    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 724
 725    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 726    PUSH_DATA (push, 0);
 727
 728    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 729    PUSH_DATA (push, 0);
 730    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 731    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 732    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 733    for (i = 0; i < 8 * 2; ++i)
 734       PUSH_DATA(push, 0);
 735    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 736    PUSH_DATA (push, 0);
 737
 738    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 739    PUSH_DATA (push, 1);
 740    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 741       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 742       PUSH_DATAf(push, 0.0f);
 743       PUSH_DATAf(push, 1.0f);
 744       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 745       PUSH_DATA (push, 8192 << 16);
 746       PUSH_DATA (push, 8192 << 16);
 747    }
 748
 749    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 750 #ifdef NV50_SCISSORS_CLIPPING
 751    PUSH_DATA (push, 0x0000);
 752 #else
 753    PUSH_DATA (push, 0x1080);
 754 #endif
 755
 756    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 757    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 758
 759    /* We use scissors instead of exact view volume clipping,
 760     * so they're always enabled.
 761     */
 762    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 763       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 764       PUSH_DATA (push, 1);
 765       PUSH_DATA (push, 8192 << 16);
 766       PUSH_DATA (push, 8192 << 16);
 767    }
 768
 769    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 770    PUSH_DATA (push, 1);
 771    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 772    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 773    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 774    PUSH_DATA (push, 0x11111111);
 775    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 776    PUSH_DATA (push, 1);
 777
 778    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 779    PUSH_DATA (push, 0);
 780    if (screen->base.class_3d >= NV84_3D_CLASS) {
 781       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 782       PUSH_DATA (push, 0);
 783    }
 784
 785    BEGIN_NV04(push, NV50_3D(UNK0FDC), 1);
 786    PUSH_DATA (push, 1);
 787    BEGIN_NV04(push, NV50_3D(UNK19C0), 1);
 788    PUSH_DATA (push, 1);
 789
 790    PUSH_KICK (push);
 791 }
 792
 793 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 794       uint64_t *tls_size)
 795 {
 796    struct nouveau_device *dev = screen->base.device;
 797    int ret;
 798
 799    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 800          ONE_TEMP_SIZE;
 801    if (nouveau_mesa_debug)
 802       debug_printf("allocating space for %u temps\n",
 803             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 804    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 805          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 806
 807    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 808                         *tls_size, NULL, &screen->tls_bo);
 809    if (ret) {
 810       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 811       return ret;
 812    }
 813
 814    return 0;
 815 }
 816
 817 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 818 {
 819    struct nouveau_pushbuf *push = screen->base.pushbuf;
 820    int ret;
 821    uint64_t tls_size;
 822
 823    if (tls_space < screen->cur_tls_space)
 824       return 0;
 825    if (tls_space > screen->max_tls_space) {
 826       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 827        * LOCAL_WARPS_NO_CLAMP) */
 828       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 829             (unsigned)(tls_space / ONE_TEMP_SIZE),
 830             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 831       return -ENOMEM;
 832    }
 833
 834    nouveau_bo_ref(NULL, &screen->tls_bo);
 835    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 836    if (ret)
 837       return ret;
 838
 839    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 840    PUSH_DATAh(push, screen->tls_bo->offset);
 841    PUSH_DATA (push, screen->tls_bo->offset);
 842    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 843
 844    return 1;
 845 }
 846
 847 struct nouveau_screen *
 848 nv50_screen_create(struct nouveau_device *dev)
 849 {
 850    struct nv50_screen *screen;
 851    struct pipe_screen *pscreen;
 852    struct nouveau_object *chan;
 853    uint64_t value;
 854    uint32_t tesla_class;
 855    unsigned stack_size;
 856    int ret;
 857
 858    screen = CALLOC_STRUCT(nv50_screen);
 859    if (!screen)
 860       return NULL;
 861    pscreen = &screen->base.base;
 862    pscreen->destroy = nv50_screen_destroy;
 863
 864    ret = nouveau_screen_init(&screen->base, dev);
 865    if (ret) {
 866       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 867       goto fail;
 868    }
 869
 870    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 871     *  admit them to VRAM.
 872     */
 873    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 874       PIPE_BIND_VERTEX_BUFFER;
 875    screen->base.sysmem_bindings |=
 876       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 877
 878    screen->base.pushbuf->user_priv = screen;
 879    screen->base.pushbuf->rsvd_kick = 5;
 880
 881    chan = screen->base.channel;
 882
 883    pscreen->context_create = nv50_create;
 884    pscreen->is_format_supported = nv50_screen_is_format_supported;
 885    pscreen->get_param = nv50_screen_get_param;
 886    pscreen->get_shader_param = nv50_screen_get_shader_param;
 887    pscreen->get_paramf = nv50_screen_get_paramf;
 888    pscreen->get_compute_param = nv50_screen_get_compute_param;
 889    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 890    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 891
 892    nv50_screen_init_resource_functions(pscreen);
 893
 894    if (screen->base.device->chipset < 0x84 ||
 895        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 896       /* PMPEG */
 897       nouveau_screen_init_vdec(&screen->base);
 898    } else if (screen->base.device->chipset < 0x98 ||
 899               screen->base.device->chipset == 0xa0) {
 900       /* VP2 */
 901       screen->base.base.get_video_param = nv84_screen_get_video_param;
 902       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 903    } else {
 904       /* VP3/4 */
 905       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 906       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 907    }
 908
 909    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 910                         NULL, &screen->fence.bo);
 911    if (ret) {
 912       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 913       goto fail;
 914    }
 915
 916    nouveau_bo_map(screen->fence.bo, 0, NULL);
 917    screen->fence.map = screen->fence.bo->map;
 918    screen->base.fence.emit = nv50_screen_fence_emit;
 919    screen->base.fence.update = nv50_screen_fence_update;
 920
 921    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 922                             &(struct nv04_notify){ .length = 32 },
 923                             sizeof(struct nv04_notify), &screen->sync);
 924    if (ret) {
 925       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 926       goto fail;
 927    }
 928
 929    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 930                             NULL, 0, &screen->m2mf);
 931    if (ret) {
 932       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 933       goto fail;
 934    }
 935
 936    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 937                             NULL, 0, &screen->eng2d);
 938    if (ret) {
 939       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 940       goto fail;
 941    }
 942
 943    switch (dev->chipset & 0xf0) {
 944    case 0x50:
 945       tesla_class = NV50_3D_CLASS;
 946       break;
 947    case 0x80:
 948    case 0x90:
 949       tesla_class = NV84_3D_CLASS;
 950       break;
 951    case 0xa0:
 952       switch (dev->chipset) {
 953       case 0xa0:
 954       case 0xaa:
 955       case 0xac:
 956          tesla_class = NVA0_3D_CLASS;
 957          break;
 958       case 0xaf:
 959          tesla_class = NVAF_3D_CLASS;
 960          break;
 961       default:
 962          tesla_class = NVA3_3D_CLASS;
 963          break;
 964       }
 965       break;
 966    default:
 967       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 968       goto fail;
 969    }
 970    screen->base.class_3d = tesla_class;
 971
 972    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 973                             NULL, 0, &screen->tesla);
 974    if (ret) {
 975       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 976       goto fail;
 977    }
 978
 979    /* This over-allocates by a page. The GP, which would execute at the end of
 980     * the last page, would trigger faults. The going theory is that it
 981     * prefetches up to a certain amount.
 982     */
 983    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 984                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 985                         NULL, &screen->code);
 986    if (ret) {
 987       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 988       goto fail;
 989    }
 990
 991    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 992    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 993    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 994
 995    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 996
 997    screen->TPs = util_bitcount(value & 0xffff);
 998    screen->MPsInTP = util_bitcount(value & 0x0f000000);
 999
1000    screen->mp_count = screen->TPs * screen->MPsInTP;
1001
1002    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
1003          STACK_WARPS_ALLOC * 64 * 8;
1004
1005    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
1006                         &screen->stack_bo);
1007    if (ret) {
1008       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
1009       goto fail;
1010    }
1011
1012    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
1013          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
1014          ONE_TEMP_SIZE;
1015    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
1016    screen->max_tls_space /= 2; /* half of vram */
1017
1018    /* hw can address max 64 KiB */
1019    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
1020
1021    uint64_t tls_size;
1022    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
1023    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
1024    if (ret)
1025       goto fail;
1026
1027    if (nouveau_mesa_debug)
1028       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
1029             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
1030
1031    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
1032                         &screen->uniforms);
1033    if (ret) {
1034       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
1035       goto fail;
1036    }
1037
1038    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
1039                         &screen->txc);
1040    if (ret) {
1041       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1042       goto fail;
1043    }
1044
1045    screen->tic.entries = CALLOC(4096, sizeof(void *));
1046    screen->tsc.entries = screen->tic.entries + 2048;
1047
1048    if (!nv50_blitter_create(screen))
1049       goto fail;
1050
1051    nv50_screen_init_hwctx(screen);
1052
1053    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1054    if (ret) {
1055       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1056       goto fail;
1057    }
1058
1059    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1060
1061    return &screen->base;
1062
1063 fail:
1064    screen->base.base.context_create = NULL;
1065    return &screen->base;
1066 }
1067
1068 int
1069 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1070 {
1071    int i = screen->tic.next;
1072
1073    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1074       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1075
1076    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1077
1078    if (screen->tic.entries[i])
1079       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1080
1081    screen->tic.entries[i] = entry;
1082    return i;
1083 }
1084
1085 int
1086 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1087 {
1088    int i = screen->tsc.next;
1089
1090    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1091       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1092
1093    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1094
1095    if (screen->tsc.entries[i])
1096       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1097
1098    screen->tsc.entries[i] = entry;
1099    return i;
1100 }