src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 static boolean
  45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  46                                 enum pipe_format format,
  47                                 enum pipe_texture_target target,
  48                                 unsigned sample_count,
  49                                 unsigned bindings)
  50 {
  51    if (sample_count > 8)
  52       return false;
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return false;
  55    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  56       return false;
  57
  58    if (!util_format_is_supported(format, bindings))
  59       return false;
  60
  61    switch (format) {
  62    case PIPE_FORMAT_Z16_UNORM:
  63       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  64          return false;
  65       break;
  66    default:
  67       break;
  68    }
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* transfers & shared are always supported */
  79    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  80                  PIPE_BIND_TRANSFER_WRITE |
  81                  PIPE_BIND_LINEAR |
  82                  PIPE_BIND_SHARED);
  83
  84    return (( nv50_format_table[format].usage |
  85             nv50_vertex_format[format].usage) & bindings) == bindings;
  86 }
  87
  88 static int
  89 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  90 {
  91    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  92    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  93
  94    switch (param) {
  95    /* non-boolean caps */
  96    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  97       return 14;
  98    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  99       return 12;
 100    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 101       return 14;
 102    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 103       return 512;
 104    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 105    case PIPE_CAP_MIN_TEXEL_OFFSET:
 106       return -8;
 107    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 108    case PIPE_CAP_MAX_TEXEL_OFFSET:
 109       return 7;
 110    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 111       return 128 * 1024 * 1024;
 112    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 113       return 330;
 114    case PIPE_CAP_MAX_RENDER_TARGETS:
 115       return 8;
 116    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 117       return 1;
 118    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 119       return 4;
 120    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 121    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 122       return 64;
 123    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 124    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 125       return 1024;
 126    case PIPE_CAP_MAX_VERTEX_STREAMS:
 127       return 1;
 128    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 129       return 2048;
 130    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 131       return 256;
 132    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 133       return 16; /* 256 for binding as RT, but that's not possible in GL */
 134    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 135       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 136    case PIPE_CAP_MAX_VIEWPORTS:
 137       return NV50_MAX_VIEWPORTS;
 138    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 139       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 140    case PIPE_CAP_ENDIANNESS:
 141       return PIPE_ENDIAN_LITTLE;
 142    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 143       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 144
 145    /* supported caps */
 146    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 147    case PIPE_CAP_TEXTURE_SWIZZLE:
 148    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 149    case PIPE_CAP_NPOT_TEXTURES:
 150    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 151    case PIPE_CAP_ANISOTROPIC_FILTER:
 152    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 153    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 154    case PIPE_CAP_TWO_SIDED_STENCIL:
 155    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 156    case PIPE_CAP_POINT_SPRITE:
 157    case PIPE_CAP_SM3:
 158    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 159    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 160    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 161    case PIPE_CAP_QUERY_TIMESTAMP:
 162    case PIPE_CAP_QUERY_TIME_ELAPSED:
 163    case PIPE_CAP_OCCLUSION_QUERY:
 164    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 165    case PIPE_CAP_INDEP_BLEND_ENABLE:
 166    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 167    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 168    case PIPE_CAP_PRIMITIVE_RESTART:
 169    case PIPE_CAP_TGSI_INSTANCEID:
 170    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 171    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 172    case PIPE_CAP_CONDITIONAL_RENDER:
 173    case PIPE_CAP_TEXTURE_BARRIER:
 174    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 175    case PIPE_CAP_START_INSTANCE:
 176    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 177    case PIPE_CAP_USER_INDEX_BUFFERS:
 178    case PIPE_CAP_USER_VERTEX_BUFFERS:
 179    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 180    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 181    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 182    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 183    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 184    case PIPE_CAP_CLIP_HALFZ:
 185    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 186    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 187    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 188    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 189    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 190    case PIPE_CAP_TGSI_TXQS:
 191    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 192    case PIPE_CAP_SHAREABLE_SHADERS:
 193    case PIPE_CAP_CLEAR_TEXTURE:
 194    case PIPE_CAP_COMPUTE:
 195    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 196    case PIPE_CAP_INVALIDATE_BUFFER:
 197    case PIPE_CAP_STRING_MARKER:
 198    case PIPE_CAP_CULL_DISTANCE:
 199       return 1;
 200    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 201       return 1; /* class_3d >= NVA0_3D_CLASS; */
 202    /* supported on nva0+ */
 203    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 204       return class_3d >= NVA0_3D_CLASS;
 205    /* supported on nva3+ */
 206    case PIPE_CAP_CUBE_MAP_ARRAY:
 207    case PIPE_CAP_INDEP_BLEND_FUNC:
 208    case PIPE_CAP_TEXTURE_QUERY_LOD:
 209    case PIPE_CAP_SAMPLE_SHADING:
 210    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 211       return class_3d >= NVA3_3D_CLASS;
 212
 213    /* unsupported caps */
 214    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 215    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 216    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 217    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 218    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 219    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 220    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 221    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 222    case PIPE_CAP_TGSI_TEXCOORD:
 223    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 224    case PIPE_CAP_TEXTURE_GATHER_SM5:
 225    case PIPE_CAP_FAKE_SW_MSAA:
 226    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 227    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 228    case PIPE_CAP_DRAW_INDIRECT:
 229    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 230    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 231    case PIPE_CAP_VERTEXID_NOBASE:
 232    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 233    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 234    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 235    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 236    case PIPE_CAP_DRAW_PARAMETERS:
 237    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 238    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 239    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 240    case PIPE_CAP_GENERATE_MIPMAP:
 241    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 242    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 243    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 244    case PIPE_CAP_QUERY_MEMORY_INFO:
 245    case PIPE_CAP_PCI_GROUP:
 246    case PIPE_CAP_PCI_BUS:
 247    case PIPE_CAP_PCI_DEVICE:
 248    case PIPE_CAP_PCI_FUNCTION:
 249    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 250    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 251    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 252    case PIPE_CAP_TGSI_VOTE:
 253       return 0;
 254
 255    case PIPE_CAP_VENDOR_ID:
 256       return 0x10de;
 257    case PIPE_CAP_DEVICE_ID: {
 258       uint64_t device_id;
 259       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 260          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 261          return -1;
 262       }
 263       return device_id;
 264    }
 265    case PIPE_CAP_ACCELERATED:
 266       return 1;
 267    case PIPE_CAP_VIDEO_MEMORY:
 268       return dev->vram_size >> 20;
 269    case PIPE_CAP_UMA:
 270       return 0;
 271    }
 272
 273    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 274    return 0;
 275 }
 276
 277 static int
 278 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 279                              enum pipe_shader_cap param)
 280 {
 281    switch (shader) {
 282    case PIPE_SHADER_VERTEX:
 283    case PIPE_SHADER_GEOMETRY:
 284    case PIPE_SHADER_FRAGMENT:
 285       break;
 286    case PIPE_SHADER_COMPUTE:
 287    default:
 288       return 0;
 289    }
 290
 291    switch (param) {
 292    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 293    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 294    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 295    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 296       return 16384;
 297    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 298       return 4;
 299    case PIPE_SHADER_CAP_MAX_INPUTS:
 300       if (shader == PIPE_SHADER_VERTEX)
 301          return 32;
 302       return 15;
 303    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 304       return 16;
 305    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 306       return 65536;
 307    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 308       return NV50_MAX_PIPE_CONSTBUFS;
 309    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 310    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 311       return shader != PIPE_SHADER_FRAGMENT;
 312    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 313    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 314       return 1;
 315    case PIPE_SHADER_CAP_MAX_PREDS:
 316       return 0;
 317    case PIPE_SHADER_CAP_MAX_TEMPS:
 318       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 319    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 320       return 1;
 321    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 322       return 1;
 323    case PIPE_SHADER_CAP_SUBROUTINES:
 324       return 0; /* please inline, or provide function declarations */
 325    case PIPE_SHADER_CAP_INTEGERS:
 326       return 1;
 327    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 328       /* The chip could handle more sampler views than samplers */
 329    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 330       return MIN2(16, PIPE_MAX_SAMPLERS);
 331    case PIPE_SHADER_CAP_PREFERRED_IR:
 332       return PIPE_SHADER_IR_TGSI;
 333    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 334       return 32;
 335    case PIPE_SHADER_CAP_DOUBLES:
 336    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 337    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 338    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 339    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 340    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 341    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 342    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 343       return 0;
 344    default:
 345       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 346       return 0;
 347    }
 348 }
 349
 350 static float
 351 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 352 {
 353    switch (param) {
 354    case PIPE_CAPF_MAX_LINE_WIDTH:
 355    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 356       return 10.0f;
 357    case PIPE_CAPF_MAX_POINT_WIDTH:
 358    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 359       return 64.0f;
 360    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 361       return 16.0f;
 362    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 363       return 4.0f;
 364    case PIPE_CAPF_GUARD_BAND_LEFT:
 365    case PIPE_CAPF_GUARD_BAND_TOP:
 366       return 0.0f;
 367    case PIPE_CAPF_GUARD_BAND_RIGHT:
 368    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 369       return 0.0f; /* that or infinity */
 370    }
 371
 372    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 373    return 0.0f;
 374 }
 375
 376 static int
 377 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 378                               enum pipe_shader_ir ir_type,
 379                               enum pipe_compute_cap param, void *data)
 380 {
 381    struct nv50_screen *screen = nv50_screen(pscreen);
 382
 383 #define RET(x) do {                  \
 384    if (data)                         \
 385       memcpy(data, x, sizeof(x));    \
 386    return sizeof(x);                 \
 387 } while (0)
 388
 389    switch (param) {
 390    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 391       RET((uint64_t []) { 2 });
 392    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 393       RET(((uint64_t []) { 65535, 65535 }));
 394    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 395       RET(((uint64_t []) { 512, 512, 64 }));
 396    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 397       RET((uint64_t []) { 512 });
 398    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 399       RET((uint64_t []) { 1ULL << 32 });
 400    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 401       RET((uint64_t []) { 16 << 10 });
 402    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 403       RET((uint64_t []) { 16 << 10 });
 404    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 405       RET((uint64_t []) { 4096 });
 406    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 407       RET((uint32_t []) { 32 });
 408    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 409       RET((uint64_t []) { 1ULL << 40 });
 410    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 411       RET((uint32_t []) { 0 });
 412    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 413       RET((uint32_t []) { screen->mp_count });
 414    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 415       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 416    default:
 417       return 0;
 418    }
 419
 420 #undef RET
 421 }
 422
 423 static void
 424 nv50_screen_destroy(struct pipe_screen *pscreen)
 425 {
 426    struct nv50_screen *screen = nv50_screen(pscreen);
 427
 428    if (!nouveau_drm_screen_unref(&screen->base))
 429       return;
 430
 431    if (screen->base.fence.current) {
 432       struct nouveau_fence *current = NULL;
 433
 434       /* nouveau_fence_wait will create a new current fence, so wait on the
 435        * _current_ one, and remove both.
 436        */
 437       nouveau_fence_ref(screen->base.fence.current, &current);
 438       nouveau_fence_wait(current, NULL);
 439       nouveau_fence_ref(NULL, &current);
 440       nouveau_fence_ref(NULL, &screen->base.fence.current);
 441    }
 442    if (screen->base.pushbuf)
 443       screen->base.pushbuf->user_priv = NULL;
 444
 445    if (screen->blitter)
 446       nv50_blitter_destroy(screen);
 447    if (screen->pm.prog) {
 448       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 449       nv50_program_destroy(NULL, screen->pm.prog);
 450       FREE(screen->pm.prog);
 451    }
 452
 453    nouveau_bo_ref(NULL, &screen->code);
 454    nouveau_bo_ref(NULL, &screen->tls_bo);
 455    nouveau_bo_ref(NULL, &screen->stack_bo);
 456    nouveau_bo_ref(NULL, &screen->txc);
 457    nouveau_bo_ref(NULL, &screen->uniforms);
 458    nouveau_bo_ref(NULL, &screen->fence.bo);
 459
 460    nouveau_heap_destroy(&screen->vp_code_heap);
 461    nouveau_heap_destroy(&screen->gp_code_heap);
 462    nouveau_heap_destroy(&screen->fp_code_heap);
 463
 464    FREE(screen->tic.entries);
 465
 466    nouveau_object_del(&screen->tesla);
 467    nouveau_object_del(&screen->eng2d);
 468    nouveau_object_del(&screen->m2mf);
 469    nouveau_object_del(&screen->compute);
 470    nouveau_object_del(&screen->sync);
 471
 472    nouveau_screen_fini(&screen->base);
 473
 474    FREE(screen);
 475 }
 476
 477 static void
 478 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 479 {
 480    struct nv50_screen *screen = nv50_screen(pscreen);
 481    struct nouveau_pushbuf *push = screen->base.pushbuf;
 482
 483    /* we need to do it after possible flush in MARK_RING */
 484    *sequence = ++screen->base.fence.sequence;
 485
 486    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 487    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 488    PUSH_DATAh(push, screen->fence.bo->offset);
 489    PUSH_DATA (push, screen->fence.bo->offset);
 490    PUSH_DATA (push, *sequence);
 491    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 492                     NV50_3D_QUERY_GET_UNK4 |
 493                     NV50_3D_QUERY_GET_UNIT_CROP |
 494                     NV50_3D_QUERY_GET_TYPE_QUERY |
 495                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 496                     NV50_3D_QUERY_GET_SHORT);
 497 }
 498
 499 static u32
 500 nv50_screen_fence_update(struct pipe_screen *pscreen)
 501 {
 502    return nv50_screen(pscreen)->fence.map[0];
 503 }
 504
 505 static void
 506 nv50_screen_init_hwctx(struct nv50_screen *screen)
 507 {
 508    struct nouveau_pushbuf *push = screen->base.pushbuf;
 509    struct nv04_fifo *fifo;
 510    unsigned i;
 511
 512    fifo = (struct nv04_fifo *)screen->base.channel->data;
 513
 514    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 515    PUSH_DATA (push, screen->m2mf->handle);
 516    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 517    PUSH_DATA (push, screen->sync->handle);
 518    PUSH_DATA (push, fifo->vram);
 519    PUSH_DATA (push, fifo->vram);
 520
 521    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 522    PUSH_DATA (push, screen->eng2d->handle);
 523    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 524    PUSH_DATA (push, screen->sync->handle);
 525    PUSH_DATA (push, fifo->vram);
 526    PUSH_DATA (push, fifo->vram);
 527    PUSH_DATA (push, fifo->vram);
 528    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 529    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 530    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 531    PUSH_DATA (push, 0);
 532    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 533    PUSH_DATA (push, 0);
 534    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 535    PUSH_DATA (push, 1);
 536    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 537    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 538
 539    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 540    PUSH_DATA (push, screen->tesla->handle);
 541
 542    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 543    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 544
 545    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 546    PUSH_DATA (push, screen->sync->handle);
 547    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 548    for (i = 0; i < 11; ++i)
 549       PUSH_DATA(push, fifo->vram);
 550    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 551    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 552       PUSH_DATA(push, fifo->vram);
 553
 554    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 555    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 556    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 557    PUSH_DATA (push, 0xf);
 558
 559    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 560       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 561       PUSH_DATA (push, 0x18);
 562    }
 563
 564    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 565    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 566
 567    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 568    for (i = 0; i < 8; ++i)
 569       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 570
 571    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 572    PUSH_DATA (push, 1);
 573
 574    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 575    PUSH_DATA (push, 0);
 576    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 577    PUSH_DATA (push, 0);
 578    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 579    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 580    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 581    PUSH_DATA (push, 0);
 582    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 583    PUSH_DATA (push, 1);
 584    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 585    PUSH_DATA (push, 1);
 586
 587    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 588       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 589       PUSH_DATA (push, 0);
 590    }
 591
 592    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 593    PUSH_DATA (push, 0);
 594    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 595    PUSH_DATA (push, 0);
 596    PUSH_DATA (push, 0);
 597    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 598    PUSH_DATA (push, 0x3f);
 599
 600    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 601    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 602    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 603
 604    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 605    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 606    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 607
 608    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 609    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 610    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 611
 612    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 613    PUSH_DATAh(push, screen->tls_bo->offset);
 614    PUSH_DATA (push, screen->tls_bo->offset);
 615    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 616
 617    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 618    PUSH_DATAh(push, screen->stack_bo->offset);
 619    PUSH_DATA (push, screen->stack_bo->offset);
 620    PUSH_DATA (push, 4);
 621
 622    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 623    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 624    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 625    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 626
 627    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 628    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 629    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 630    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 631
 632    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 633    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 634    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 635    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 636
 637    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 638    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 639    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 640    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 641
 642    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 643    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 644    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 645    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 646
 647    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 648    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 649    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 650    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 651    PUSH_DATAf(push, 0.0f);
 652    PUSH_DATAf(push, 0.0f);
 653    PUSH_DATAf(push, 0.0f);
 654    PUSH_DATAf(push, 0.0f);
 655    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 656    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 657    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 658
 659    nv50_upload_ms_info(push);
 660
 661    /* max TIC (bits 4:8) & TSC bindings, per program type */
 662    for (i = 0; i < 3; ++i) {
 663       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 664       PUSH_DATA (push, 0x54);
 665    }
 666
 667    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 668    PUSH_DATAh(push, screen->txc->offset);
 669    PUSH_DATA (push, screen->txc->offset);
 670    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 671
 672    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 673    PUSH_DATAh(push, screen->txc->offset + 65536);
 674    PUSH_DATA (push, screen->txc->offset + 65536);
 675    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 676
 677    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 678    PUSH_DATA (push, 0);
 679
 680    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 681    PUSH_DATA (push, 0);
 682    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 683    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 684    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 685    for (i = 0; i < 8 * 2; ++i)
 686       PUSH_DATA(push, 0);
 687    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 688    PUSH_DATA (push, 0);
 689
 690    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 691    PUSH_DATA (push, 1);
 692    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 693       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 694       PUSH_DATAf(push, 0.0f);
 695       PUSH_DATAf(push, 1.0f);
 696       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 697       PUSH_DATA (push, 8192 << 16);
 698       PUSH_DATA (push, 8192 << 16);
 699    }
 700
 701    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 702 #ifdef NV50_SCISSORS_CLIPPING
 703    PUSH_DATA (push, 0x0000);
 704 #else
 705    PUSH_DATA (push, 0x1080);
 706 #endif
 707
 708    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 709    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 710
 711    /* We use scissors instead of exact view volume clipping,
 712     * so they're always enabled.
 713     */
 714    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 715       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 716       PUSH_DATA (push, 1);
 717       PUSH_DATA (push, 8192 << 16);
 718       PUSH_DATA (push, 8192 << 16);
 719    }
 720
 721    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 722    PUSH_DATA (push, 1);
 723    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 724    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 725    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 726    PUSH_DATA (push, 0x11111111);
 727    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 728    PUSH_DATA (push, 1);
 729
 730    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 731    PUSH_DATA (push, 0);
 732    if (screen->base.class_3d >= NV84_3D_CLASS) {
 733       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 734       PUSH_DATA (push, 0);
 735    }
 736
 737    PUSH_KICK (push);
 738 }
 739
 740 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 741       uint64_t *tls_size)
 742 {
 743    struct nouveau_device *dev = screen->base.device;
 744    int ret;
 745
 746    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 747          ONE_TEMP_SIZE;
 748    if (nouveau_mesa_debug)
 749       debug_printf("allocating space for %u temps\n",
 750             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 751    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 752          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 753
 754    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 755                         *tls_size, NULL, &screen->tls_bo);
 756    if (ret) {
 757       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 758       return ret;
 759    }
 760
 761    return 0;
 762 }
 763
 764 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 765 {
 766    struct nouveau_pushbuf *push = screen->base.pushbuf;
 767    int ret;
 768    uint64_t tls_size;
 769
 770    if (tls_space < screen->cur_tls_space)
 771       return 0;
 772    if (tls_space > screen->max_tls_space) {
 773       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 774        * LOCAL_WARPS_NO_CLAMP) */
 775       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 776             (unsigned)(tls_space / ONE_TEMP_SIZE),
 777             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 778       return -ENOMEM;
 779    }
 780
 781    nouveau_bo_ref(NULL, &screen->tls_bo);
 782    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 783    if (ret)
 784       return ret;
 785
 786    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 787    PUSH_DATAh(push, screen->tls_bo->offset);
 788    PUSH_DATA (push, screen->tls_bo->offset);
 789    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 790
 791    return 1;
 792 }
 793
 794 struct nouveau_screen *
 795 nv50_screen_create(struct nouveau_device *dev)
 796 {
 797    struct nv50_screen *screen;
 798    struct pipe_screen *pscreen;
 799    struct nouveau_object *chan;
 800    uint64_t value;
 801    uint32_t tesla_class;
 802    unsigned stack_size;
 803    int ret;
 804
 805    screen = CALLOC_STRUCT(nv50_screen);
 806    if (!screen)
 807       return NULL;
 808    pscreen = &screen->base.base;
 809    pscreen->destroy = nv50_screen_destroy;
 810
 811    ret = nouveau_screen_init(&screen->base, dev);
 812    if (ret) {
 813       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 814       goto fail;
 815    }
 816
 817    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 818     *  admit them to VRAM.
 819     */
 820    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 821       PIPE_BIND_VERTEX_BUFFER;
 822    screen->base.sysmem_bindings |=
 823       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 824
 825    screen->base.pushbuf->user_priv = screen;
 826    screen->base.pushbuf->rsvd_kick = 5;
 827
 828    chan = screen->base.channel;
 829
 830    pscreen->context_create = nv50_create;
 831    pscreen->is_format_supported = nv50_screen_is_format_supported;
 832    pscreen->get_param = nv50_screen_get_param;
 833    pscreen->get_shader_param = nv50_screen_get_shader_param;
 834    pscreen->get_paramf = nv50_screen_get_paramf;
 835    pscreen->get_compute_param = nv50_screen_get_compute_param;
 836    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 837    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 838
 839    nv50_screen_init_resource_functions(pscreen);
 840
 841    if (screen->base.device->chipset < 0x84 ||
 842        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 843       /* PMPEG */
 844       nouveau_screen_init_vdec(&screen->base);
 845    } else if (screen->base.device->chipset < 0x98 ||
 846               screen->base.device->chipset == 0xa0) {
 847       /* VP2 */
 848       screen->base.base.get_video_param = nv84_screen_get_video_param;
 849       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 850    } else {
 851       /* VP3/4 */
 852       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 853       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 854    }
 855
 856    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 857                         NULL, &screen->fence.bo);
 858    if (ret) {
 859       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 860       goto fail;
 861    }
 862
 863    nouveau_bo_map(screen->fence.bo, 0, NULL);
 864    screen->fence.map = screen->fence.bo->map;
 865    screen->base.fence.emit = nv50_screen_fence_emit;
 866    screen->base.fence.update = nv50_screen_fence_update;
 867
 868    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 869                             &(struct nv04_notify){ .length = 32 },
 870                             sizeof(struct nv04_notify), &screen->sync);
 871    if (ret) {
 872       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 873       goto fail;
 874    }
 875
 876    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 877                             NULL, 0, &screen->m2mf);
 878    if (ret) {
 879       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 880       goto fail;
 881    }
 882
 883    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 884                             NULL, 0, &screen->eng2d);
 885    if (ret) {
 886       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 887       goto fail;
 888    }
 889
 890    switch (dev->chipset & 0xf0) {
 891    case 0x50:
 892       tesla_class = NV50_3D_CLASS;
 893       break;
 894    case 0x80:
 895    case 0x90:
 896       tesla_class = NV84_3D_CLASS;
 897       break;
 898    case 0xa0:
 899       switch (dev->chipset) {
 900       case 0xa0:
 901       case 0xaa:
 902       case 0xac:
 903          tesla_class = NVA0_3D_CLASS;
 904          break;
 905       case 0xaf:
 906          tesla_class = NVAF_3D_CLASS;
 907          break;
 908       default:
 909          tesla_class = NVA3_3D_CLASS;
 910          break;
 911       }
 912       break;
 913    default:
 914       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 915       goto fail;
 916    }
 917    screen->base.class_3d = tesla_class;
 918
 919    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 920                             NULL, 0, &screen->tesla);
 921    if (ret) {
 922       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 923       goto fail;
 924    }
 925
 926    /* This over-allocates by a page. The GP, which would execute at the end of
 927     * the last page, would trigger faults. The going theory is that it
 928     * prefetches up to a certain amount.
 929     */
 930    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 931                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 932                         NULL, &screen->code);
 933    if (ret) {
 934       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 935       goto fail;
 936    }
 937
 938    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 939    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 940    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 941
 942    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 943
 944    screen->TPs = util_bitcount(value & 0xffff);
 945    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 946
 947    screen->mp_count = screen->TPs * screen->MPsInTP;
 948
 949    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 950          STACK_WARPS_ALLOC * 64 * 8;
 951
 952    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 953                         &screen->stack_bo);
 954    if (ret) {
 955       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 956       goto fail;
 957    }
 958
 959    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 960          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 961          ONE_TEMP_SIZE;
 962    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 963    screen->max_tls_space /= 2; /* half of vram */
 964
 965    /* hw can address max 64 KiB */
 966    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 967
 968    uint64_t tls_size;
 969    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 970    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 971    if (ret)
 972       goto fail;
 973
 974    if (nouveau_mesa_debug)
 975       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 976             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 977
 978    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 979                         &screen->uniforms);
 980    if (ret) {
 981       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 982       goto fail;
 983    }
 984
 985    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 986                         &screen->txc);
 987    if (ret) {
 988       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 989       goto fail;
 990    }
 991
 992    screen->tic.entries = CALLOC(4096, sizeof(void *));
 993    screen->tsc.entries = screen->tic.entries + 2048;
 994
 995    if (!nv50_blitter_create(screen))
 996       goto fail;
 997
 998    nv50_screen_init_hwctx(screen);
 999
1000    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1001    if (ret) {
1002       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1003       goto fail;
1004    }
1005
1006    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1007
1008    return &screen->base;
1009
1010 fail:
1011    screen->base.base.context_create = NULL;
1012    return &screen->base;
1013 }
1014
1015 int
1016 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1017 {
1018    int i = screen->tic.next;
1019
1020    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1021       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1022
1023    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1024
1025    if (screen->tic.entries[i])
1026       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1027
1028    screen->tic.entries[i] = entry;
1029    return i;
1030 }
1031
1032 int
1033 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1034 {
1035    int i = screen->tsc.next;
1036
1037    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1038       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1039
1040    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1041
1042    if (screen->tsc.entries[i])
1043       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1044
1045    screen->tsc.entries[i] = entry;
1046    return i;
1047 }