src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 static boolean
  45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  46                                 enum pipe_format format,
  47                                 enum pipe_texture_target target,
  48                                 unsigned sample_count,
  49                                 unsigned bindings)
  50 {
  51    if (sample_count > 8)
  52       return false;
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return false;
  55    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  56       return false;
  57
  58    if (!util_format_is_supported(format, bindings))
  59       return false;
  60
  61    switch (format) {
  62    case PIPE_FORMAT_Z16_UNORM:
  63       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  64          return false;
  65       break;
  66    default:
  67       break;
  68    }
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* shared is always supported */
  79    bindings &= ~(PIPE_BIND_LINEAR |
  80                  PIPE_BIND_SHARED);
  81
  82    return (( nv50_format_table[format].usage |
  83             nv50_vertex_format[format].usage) & bindings) == bindings;
  84 }
  85
  86 static int
  87 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  88 {
  89    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  90    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  91
  92    switch (param) {
  93    /* non-boolean caps */
  94    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  95       return 14;
  96    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  97       return 12;
  98    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  99       return 14;
 100    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 101       return 512;
 102    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 103    case PIPE_CAP_MIN_TEXEL_OFFSET:
 104       return -8;
 105    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 106    case PIPE_CAP_MAX_TEXEL_OFFSET:
 107       return 7;
 108    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 109       return 128 * 1024 * 1024;
 110    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 111       return 330;
 112    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 113       return 140;
 114    case PIPE_CAP_MAX_RENDER_TARGETS:
 115       return 8;
 116    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 117       return 1;
 118    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 119       return 4;
 120    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 121    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 122       return 64;
 123    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 124    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 125       return 1024;
 126    case PIPE_CAP_MAX_VERTEX_STREAMS:
 127       return 1;
 128    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 129       return 2048;
 130    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 131       return 256;
 132    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 133       return 16; /* 256 for binding as RT, but that's not possible in GL */
 134    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 135       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 136    case PIPE_CAP_MAX_VIEWPORTS:
 137       return NV50_MAX_VIEWPORTS;
 138    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 139       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 140    case PIPE_CAP_ENDIANNESS:
 141       return PIPE_ENDIAN_LITTLE;
 142    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 143       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 144    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 145       return NV50_MAX_WINDOW_RECTANGLES;
 146
 147    /* supported caps */
 148    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 149    case PIPE_CAP_TEXTURE_SWIZZLE:
 150    case PIPE_CAP_NPOT_TEXTURES:
 151    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 152    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 153    case PIPE_CAP_ANISOTROPIC_FILTER:
 154    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 155    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 156    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 157    case PIPE_CAP_POINT_SPRITE:
 158    case PIPE_CAP_SM3:
 159    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 160    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 161    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 162    case PIPE_CAP_QUERY_TIMESTAMP:
 163    case PIPE_CAP_QUERY_TIME_ELAPSED:
 164    case PIPE_CAP_OCCLUSION_QUERY:
 165    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 166    case PIPE_CAP_INDEP_BLEND_ENABLE:
 167    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 168    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 169    case PIPE_CAP_PRIMITIVE_RESTART:
 170    case PIPE_CAP_TGSI_INSTANCEID:
 171    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 172    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 173    case PIPE_CAP_CONDITIONAL_RENDER:
 174    case PIPE_CAP_TEXTURE_BARRIER:
 175    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 176    case PIPE_CAP_START_INSTANCE:
 177    case PIPE_CAP_USER_VERTEX_BUFFERS:
 178    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 179    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 180    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 181    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 182    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 183    case PIPE_CAP_CLIP_HALFZ:
 184    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 185    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 186    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 187    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 188    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 189    case PIPE_CAP_TGSI_TXQS:
 190    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 191    case PIPE_CAP_SHAREABLE_SHADERS:
 192    case PIPE_CAP_CLEAR_TEXTURE:
 193    case PIPE_CAP_COMPUTE:
 194    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 195    case PIPE_CAP_INVALIDATE_BUFFER:
 196    case PIPE_CAP_STRING_MARKER:
 197    case PIPE_CAP_CULL_DISTANCE:
 198    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 199    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 200    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 201    case PIPE_CAP_TGSI_CLOCK:
 202    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 203    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 204       return 1;
 205    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 206       return 1; /* class_3d >= NVA0_3D_CLASS; */
 207    /* supported on nva0+ */
 208    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 209       return class_3d >= NVA0_3D_CLASS;
 210    /* supported on nva3+ */
 211    case PIPE_CAP_CUBE_MAP_ARRAY:
 212    case PIPE_CAP_INDEP_BLEND_FUNC:
 213    case PIPE_CAP_TEXTURE_QUERY_LOD:
 214    case PIPE_CAP_SAMPLE_SHADING:
 215    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 216       return class_3d >= NVA3_3D_CLASS;
 217
 218    /* unsupported caps */
 219    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 220    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 221    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 222    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 223    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 224    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 225    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 226    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 227    case PIPE_CAP_TGSI_TEXCOORD:
 228    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 229    case PIPE_CAP_TEXTURE_GATHER_SM5:
 230    case PIPE_CAP_FAKE_SW_MSAA:
 231    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 232    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 233    case PIPE_CAP_DRAW_INDIRECT:
 234    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 235    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 236    case PIPE_CAP_VERTEXID_NOBASE:
 237    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 238    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 239    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 240    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 241    case PIPE_CAP_DRAW_PARAMETERS:
 242    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 243    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 244    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 245    case PIPE_CAP_GENERATE_MIPMAP:
 246    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 247    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 248    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 249    case PIPE_CAP_QUERY_MEMORY_INFO:
 250    case PIPE_CAP_PCI_GROUP:
 251    case PIPE_CAP_PCI_BUS:
 252    case PIPE_CAP_PCI_DEVICE:
 253    case PIPE_CAP_PCI_FUNCTION:
 254    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 255    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 256    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 257    case PIPE_CAP_TGSI_VOTE:
 258    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 259    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 260    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 261    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 262    case PIPE_CAP_NATIVE_FENCE_FD:
 263    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 264    case PIPE_CAP_TGSI_FS_FBFETCH:
 265    case PIPE_CAP_DOUBLES:
 266    case PIPE_CAP_INT64:
 267    case PIPE_CAP_INT64_DIVMOD:
 268    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 269    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 270    case PIPE_CAP_TGSI_BALLOT:
 271    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 272    case PIPE_CAP_POST_DEPTH_COVERAGE:
 273    case PIPE_CAP_BINDLESS_TEXTURE:
 274    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 275    case PIPE_CAP_QUERY_SO_OVERFLOW:
 276    case PIPE_CAP_MEMOBJ:
 277    case PIPE_CAP_LOAD_CONSTBUF:
 278    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 279    case PIPE_CAP_TILE_RASTER_ORDER:
 280    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 281    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 282    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 283    case PIPE_CAP_FENCE_SIGNAL:
 284    case PIPE_CAP_CONSTBUF0_FLAGS:
 285    case PIPE_CAP_PACKED_UNIFORMS:
 286    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 287    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 288    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 289    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 290    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 291    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 292    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 293       return 0;
 294
 295    case PIPE_CAP_VENDOR_ID:
 296       return 0x10de;
 297    case PIPE_CAP_DEVICE_ID: {
 298       uint64_t device_id;
 299       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 300          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 301          return -1;
 302       }
 303       return device_id;
 304    }
 305    case PIPE_CAP_ACCELERATED:
 306       return 1;
 307    case PIPE_CAP_VIDEO_MEMORY:
 308       return dev->vram_size >> 20;
 309    case PIPE_CAP_UMA:
 310       return 0;
 311    }
 312
 313    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 314    return 0;
 315 }
 316
 317 static int
 318 nv50_screen_get_shader_param(struct pipe_screen *pscreen,
 319                              enum pipe_shader_type shader,
 320                              enum pipe_shader_cap param)
 321 {
 322    switch (shader) {
 323    case PIPE_SHADER_VERTEX:
 324    case PIPE_SHADER_GEOMETRY:
 325    case PIPE_SHADER_FRAGMENT:
 326       break;
 327    case PIPE_SHADER_COMPUTE:
 328    default:
 329       return 0;
 330    }
 331
 332    switch (param) {
 333    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 334    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 335    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 336    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 337       return 16384;
 338    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 339       return 4;
 340    case PIPE_SHADER_CAP_MAX_INPUTS:
 341       if (shader == PIPE_SHADER_VERTEX)
 342          return 32;
 343       return 15;
 344    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 345       return 16;
 346    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 347       return 65536;
 348    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 349       return NV50_MAX_PIPE_CONSTBUFS;
 350    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 351       return shader != PIPE_SHADER_FRAGMENT;
 352    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 353    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 354    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 355       return 1;
 356    case PIPE_SHADER_CAP_MAX_TEMPS:
 357       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 358    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 359       return 1;
 360    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 361       return 1;
 362    case PIPE_SHADER_CAP_INT64_ATOMICS:
 363    case PIPE_SHADER_CAP_FP16:
 364    case PIPE_SHADER_CAP_SUBROUTINES:
 365       return 0; /* please inline, or provide function declarations */
 366    case PIPE_SHADER_CAP_INTEGERS:
 367       return 1;
 368    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 369       return 1;
 370    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 371       /* The chip could handle more sampler views than samplers */
 372    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 373       return MIN2(16, PIPE_MAX_SAMPLERS);
 374    case PIPE_SHADER_CAP_PREFERRED_IR:
 375       return PIPE_SHADER_IR_TGSI;
 376    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 377       return 32;
 378    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 379    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 380    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 381    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 382    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 383    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 384    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 385    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 386    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 387    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 388    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 389       return 0;
 390    case PIPE_SHADER_CAP_SCALAR_ISA:
 391       return 1;
 392    default:
 393       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 394       return 0;
 395    }
 396 }
 397
 398 static float
 399 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 400 {
 401    switch (param) {
 402    case PIPE_CAPF_MAX_LINE_WIDTH:
 403    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 404       return 10.0f;
 405    case PIPE_CAPF_MAX_POINT_WIDTH:
 406    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 407       return 64.0f;
 408    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 409       return 16.0f;
 410    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 411       return 4.0f;
 412    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 413    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 414    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 415       return 0.0f;
 416    }
 417
 418    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 419    return 0.0f;
 420 }
 421
 422 static int
 423 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 424                               enum pipe_shader_ir ir_type,
 425                               enum pipe_compute_cap param, void *data)
 426 {
 427    struct nv50_screen *screen = nv50_screen(pscreen);
 428
 429 #define RET(x) do {                  \
 430    if (data)                         \
 431       memcpy(data, x, sizeof(x));    \
 432    return sizeof(x);                 \
 433 } while (0)
 434
 435    switch (param) {
 436    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 437       RET((uint64_t []) { 2 });
 438    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 439       RET(((uint64_t []) { 65535, 65535 }));
 440    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 441       RET(((uint64_t []) { 512, 512, 64 }));
 442    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 443       RET((uint64_t []) { 512 });
 444    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 445       RET((uint64_t []) { 1ULL << 32 });
 446    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 447       RET((uint64_t []) { 16 << 10 });
 448    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 449       RET((uint64_t []) { 16 << 10 });
 450    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 451       RET((uint64_t []) { 4096 });
 452    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 453       RET((uint32_t []) { 32 });
 454    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 455       RET((uint64_t []) { 1ULL << 40 });
 456    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 457       RET((uint32_t []) { 0 });
 458    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 459       RET((uint32_t []) { screen->mp_count });
 460    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 461       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 462    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 463       RET((uint32_t []) { 32 });
 464    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 465       RET((uint64_t []) { 0 });
 466    default:
 467       return 0;
 468    }
 469
 470 #undef RET
 471 }
 472
 473 static void
 474 nv50_screen_destroy(struct pipe_screen *pscreen)
 475 {
 476    struct nv50_screen *screen = nv50_screen(pscreen);
 477
 478    if (!nouveau_drm_screen_unref(&screen->base))
 479       return;
 480
 481    if (screen->base.fence.current) {
 482       struct nouveau_fence *current = NULL;
 483
 484       /* nouveau_fence_wait will create a new current fence, so wait on the
 485        * _current_ one, and remove both.
 486        */
 487       nouveau_fence_ref(screen->base.fence.current, &current);
 488       nouveau_fence_wait(current, NULL);
 489       nouveau_fence_ref(NULL, &current);
 490       nouveau_fence_ref(NULL, &screen->base.fence.current);
 491    }
 492    if (screen->base.pushbuf)
 493       screen->base.pushbuf->user_priv = NULL;
 494
 495    if (screen->blitter)
 496       nv50_blitter_destroy(screen);
 497    if (screen->pm.prog) {
 498       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 499       nv50_program_destroy(NULL, screen->pm.prog);
 500       FREE(screen->pm.prog);
 501    }
 502
 503    nouveau_bo_ref(NULL, &screen->code);
 504    nouveau_bo_ref(NULL, &screen->tls_bo);
 505    nouveau_bo_ref(NULL, &screen->stack_bo);
 506    nouveau_bo_ref(NULL, &screen->txc);
 507    nouveau_bo_ref(NULL, &screen->uniforms);
 508    nouveau_bo_ref(NULL, &screen->fence.bo);
 509
 510    nouveau_heap_destroy(&screen->vp_code_heap);
 511    nouveau_heap_destroy(&screen->gp_code_heap);
 512    nouveau_heap_destroy(&screen->fp_code_heap);
 513
 514    FREE(screen->tic.entries);
 515
 516    nouveau_object_del(&screen->tesla);
 517    nouveau_object_del(&screen->eng2d);
 518    nouveau_object_del(&screen->m2mf);
 519    nouveau_object_del(&screen->compute);
 520    nouveau_object_del(&screen->sync);
 521
 522    nouveau_screen_fini(&screen->base);
 523
 524    FREE(screen);
 525 }
 526
 527 static void
 528 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 529 {
 530    struct nv50_screen *screen = nv50_screen(pscreen);
 531    struct nouveau_pushbuf *push = screen->base.pushbuf;
 532
 533    /* we need to do it after possible flush in MARK_RING */
 534    *sequence = ++screen->base.fence.sequence;
 535
 536    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 537    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 538    PUSH_DATAh(push, screen->fence.bo->offset);
 539    PUSH_DATA (push, screen->fence.bo->offset);
 540    PUSH_DATA (push, *sequence);
 541    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 542                     NV50_3D_QUERY_GET_UNK4 |
 543                     NV50_3D_QUERY_GET_UNIT_CROP |
 544                     NV50_3D_QUERY_GET_TYPE_QUERY |
 545                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 546                     NV50_3D_QUERY_GET_SHORT);
 547 }
 548
 549 static u32
 550 nv50_screen_fence_update(struct pipe_screen *pscreen)
 551 {
 552    return nv50_screen(pscreen)->fence.map[0];
 553 }
 554
 555 static void
 556 nv50_screen_init_hwctx(struct nv50_screen *screen)
 557 {
 558    struct nouveau_pushbuf *push = screen->base.pushbuf;
 559    struct nv04_fifo *fifo;
 560    unsigned i;
 561
 562    fifo = (struct nv04_fifo *)screen->base.channel->data;
 563
 564    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 565    PUSH_DATA (push, screen->m2mf->handle);
 566    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 567    PUSH_DATA (push, screen->sync->handle);
 568    PUSH_DATA (push, fifo->vram);
 569    PUSH_DATA (push, fifo->vram);
 570
 571    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 572    PUSH_DATA (push, screen->eng2d->handle);
 573    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 574    PUSH_DATA (push, screen->sync->handle);
 575    PUSH_DATA (push, fifo->vram);
 576    PUSH_DATA (push, fifo->vram);
 577    PUSH_DATA (push, fifo->vram);
 578    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 579    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 580    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 581    PUSH_DATA (push, 0);
 582    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 583    PUSH_DATA (push, 0);
 584    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 585    PUSH_DATA (push, 1);
 586    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 587    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 588
 589    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 590    PUSH_DATA (push, screen->tesla->handle);
 591
 592    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 593    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 594
 595    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 596    PUSH_DATA (push, screen->sync->handle);
 597    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 598    for (i = 0; i < 11; ++i)
 599       PUSH_DATA(push, fifo->vram);
 600    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 601    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 602       PUSH_DATA(push, fifo->vram);
 603
 604    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 605    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 606    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 607    PUSH_DATA (push, 0xf);
 608
 609    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 610       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 611       PUSH_DATA (push, 0x18);
 612    }
 613
 614    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 615    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 616
 617    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 618    for (i = 0; i < 8; ++i)
 619       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 620
 621    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 622    PUSH_DATA (push, 1);
 623
 624    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 625    PUSH_DATA (push, 0);
 626    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 627    PUSH_DATA (push, 0);
 628    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 629    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 630    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 631    PUSH_DATA (push, 0);
 632    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 633    PUSH_DATA (push, 1);
 634    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 635    PUSH_DATA (push, 1);
 636
 637    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 638       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 639       PUSH_DATA (push, 0);
 640    }
 641
 642    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 643    PUSH_DATA (push, 0);
 644    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 645    PUSH_DATA (push, 0);
 646    PUSH_DATA (push, 0);
 647    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 648    PUSH_DATA (push, 0x3f);
 649
 650    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 651    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 652    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 653
 654    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 655    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 656    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 657
 658    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 659    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 660    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 661
 662    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 663    PUSH_DATAh(push, screen->tls_bo->offset);
 664    PUSH_DATA (push, screen->tls_bo->offset);
 665    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 666
 667    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 668    PUSH_DATAh(push, screen->stack_bo->offset);
 669    PUSH_DATA (push, screen->stack_bo->offset);
 670    PUSH_DATA (push, 4);
 671
 672    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 673    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 674    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 675    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 676
 677    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 678    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 679    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 680    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 681
 682    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 683    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 684    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 685    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 686
 687    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 688    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 689    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 690    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 691
 692    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 693    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 694    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 695    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 696
 697    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 698    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 699    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 700    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 701    PUSH_DATAf(push, 0.0f);
 702    PUSH_DATAf(push, 0.0f);
 703    PUSH_DATAf(push, 0.0f);
 704    PUSH_DATAf(push, 0.0f);
 705    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 706    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 707    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 708
 709    nv50_upload_ms_info(push);
 710
 711    /* max TIC (bits 4:8) & TSC bindings, per program type */
 712    for (i = 0; i < 3; ++i) {
 713       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 714       PUSH_DATA (push, 0x54);
 715    }
 716
 717    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 718    PUSH_DATAh(push, screen->txc->offset);
 719    PUSH_DATA (push, screen->txc->offset);
 720    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 721
 722    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 723    PUSH_DATAh(push, screen->txc->offset + 65536);
 724    PUSH_DATA (push, screen->txc->offset + 65536);
 725    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 726
 727    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 728    PUSH_DATA (push, 0);
 729
 730    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 731    PUSH_DATA (push, 0);
 732    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 733    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 734    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 735    for (i = 0; i < 8 * 2; ++i)
 736       PUSH_DATA(push, 0);
 737    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 738    PUSH_DATA (push, 0);
 739
 740    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 741    PUSH_DATA (push, 1);
 742    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 743       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 744       PUSH_DATAf(push, 0.0f);
 745       PUSH_DATAf(push, 1.0f);
 746       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 747       PUSH_DATA (push, 8192 << 16);
 748       PUSH_DATA (push, 8192 << 16);
 749    }
 750
 751    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 752 #ifdef NV50_SCISSORS_CLIPPING
 753    PUSH_DATA (push, 0x0000);
 754 #else
 755    PUSH_DATA (push, 0x1080);
 756 #endif
 757
 758    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 759    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 760
 761    /* We use scissors instead of exact view volume clipping,
 762     * so they're always enabled.
 763     */
 764    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 765       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 766       PUSH_DATA (push, 1);
 767       PUSH_DATA (push, 8192 << 16);
 768       PUSH_DATA (push, 8192 << 16);
 769    }
 770
 771    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 772    PUSH_DATA (push, 1);
 773    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 774    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 775    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 776    PUSH_DATA (push, 0x11111111);
 777    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 778    PUSH_DATA (push, 1);
 779
 780    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 781    PUSH_DATA (push, 0);
 782    if (screen->base.class_3d >= NV84_3D_CLASS) {
 783       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 784       PUSH_DATA (push, 0);
 785    }
 786
 787    BEGIN_NV04(push, NV50_3D(UNK0FDC), 1);
 788    PUSH_DATA (push, 1);
 789    BEGIN_NV04(push, NV50_3D(UNK19C0), 1);
 790    PUSH_DATA (push, 1);
 791
 792    PUSH_KICK (push);
 793 }
 794
 795 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 796       uint64_t *tls_size)
 797 {
 798    struct nouveau_device *dev = screen->base.device;
 799    int ret;
 800
 801    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 802          ONE_TEMP_SIZE;
 803    if (nouveau_mesa_debug)
 804       debug_printf("allocating space for %u temps\n",
 805             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 806    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 807          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 808
 809    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 810                         *tls_size, NULL, &screen->tls_bo);
 811    if (ret) {
 812       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 813       return ret;
 814    }
 815
 816    return 0;
 817 }
 818
 819 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 820 {
 821    struct nouveau_pushbuf *push = screen->base.pushbuf;
 822    int ret;
 823    uint64_t tls_size;
 824
 825    if (tls_space < screen->cur_tls_space)
 826       return 0;
 827    if (tls_space > screen->max_tls_space) {
 828       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 829        * LOCAL_WARPS_NO_CLAMP) */
 830       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 831             (unsigned)(tls_space / ONE_TEMP_SIZE),
 832             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 833       return -ENOMEM;
 834    }
 835
 836    nouveau_bo_ref(NULL, &screen->tls_bo);
 837    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 838    if (ret)
 839       return ret;
 840
 841    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 842    PUSH_DATAh(push, screen->tls_bo->offset);
 843    PUSH_DATA (push, screen->tls_bo->offset);
 844    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 845
 846    return 1;
 847 }
 848
 849 struct nouveau_screen *
 850 nv50_screen_create(struct nouveau_device *dev)
 851 {
 852    struct nv50_screen *screen;
 853    struct pipe_screen *pscreen;
 854    struct nouveau_object *chan;
 855    uint64_t value;
 856    uint32_t tesla_class;
 857    unsigned stack_size;
 858    int ret;
 859
 860    screen = CALLOC_STRUCT(nv50_screen);
 861    if (!screen)
 862       return NULL;
 863    pscreen = &screen->base.base;
 864    pscreen->destroy = nv50_screen_destroy;
 865
 866    ret = nouveau_screen_init(&screen->base, dev);
 867    if (ret) {
 868       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 869       goto fail;
 870    }
 871
 872    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 873     *  admit them to VRAM.
 874     */
 875    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 876       PIPE_BIND_VERTEX_BUFFER;
 877    screen->base.sysmem_bindings |=
 878       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 879
 880    screen->base.pushbuf->user_priv = screen;
 881    screen->base.pushbuf->rsvd_kick = 5;
 882
 883    chan = screen->base.channel;
 884
 885    pscreen->context_create = nv50_create;
 886    pscreen->is_format_supported = nv50_screen_is_format_supported;
 887    pscreen->get_param = nv50_screen_get_param;
 888    pscreen->get_shader_param = nv50_screen_get_shader_param;
 889    pscreen->get_paramf = nv50_screen_get_paramf;
 890    pscreen->get_compute_param = nv50_screen_get_compute_param;
 891    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 892    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 893
 894    nv50_screen_init_resource_functions(pscreen);
 895
 896    if (screen->base.device->chipset < 0x84 ||
 897        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 898       /* PMPEG */
 899       nouveau_screen_init_vdec(&screen->base);
 900    } else if (screen->base.device->chipset < 0x98 ||
 901               screen->base.device->chipset == 0xa0) {
 902       /* VP2 */
 903       screen->base.base.get_video_param = nv84_screen_get_video_param;
 904       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 905    } else {
 906       /* VP3/4 */
 907       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 908       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 909    }
 910
 911    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 912                         NULL, &screen->fence.bo);
 913    if (ret) {
 914       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 915       goto fail;
 916    }
 917
 918    nouveau_bo_map(screen->fence.bo, 0, NULL);
 919    screen->fence.map = screen->fence.bo->map;
 920    screen->base.fence.emit = nv50_screen_fence_emit;
 921    screen->base.fence.update = nv50_screen_fence_update;
 922
 923    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 924                             &(struct nv04_notify){ .length = 32 },
 925                             sizeof(struct nv04_notify), &screen->sync);
 926    if (ret) {
 927       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 928       goto fail;
 929    }
 930
 931    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 932                             NULL, 0, &screen->m2mf);
 933    if (ret) {
 934       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 935       goto fail;
 936    }
 937
 938    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 939                             NULL, 0, &screen->eng2d);
 940    if (ret) {
 941       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 942       goto fail;
 943    }
 944
 945    switch (dev->chipset & 0xf0) {
 946    case 0x50:
 947       tesla_class = NV50_3D_CLASS;
 948       break;
 949    case 0x80:
 950    case 0x90:
 951       tesla_class = NV84_3D_CLASS;
 952       break;
 953    case 0xa0:
 954       switch (dev->chipset) {
 955       case 0xa0:
 956       case 0xaa:
 957       case 0xac:
 958          tesla_class = NVA0_3D_CLASS;
 959          break;
 960       case 0xaf:
 961          tesla_class = NVAF_3D_CLASS;
 962          break;
 963       default:
 964          tesla_class = NVA3_3D_CLASS;
 965          break;
 966       }
 967       break;
 968    default:
 969       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 970       goto fail;
 971    }
 972    screen->base.class_3d = tesla_class;
 973
 974    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 975                             NULL, 0, &screen->tesla);
 976    if (ret) {
 977       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 978       goto fail;
 979    }
 980
 981    /* This over-allocates by a page. The GP, which would execute at the end of
 982     * the last page, would trigger faults. The going theory is that it
 983     * prefetches up to a certain amount.
 984     */
 985    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 986                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 987                         NULL, &screen->code);
 988    if (ret) {
 989       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 990       goto fail;
 991    }
 992
 993    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 994    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 995    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 996
 997    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 998
 999    screen->TPs = util_bitcount(value & 0xffff);
1000    screen->MPsInTP = util_bitcount(value & 0x0f000000);
1001
1002    screen->mp_count = screen->TPs * screen->MPsInTP;
1003
1004    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
1005          STACK_WARPS_ALLOC * 64 * 8;
1006
1007    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
1008                         &screen->stack_bo);
1009    if (ret) {
1010       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
1011       goto fail;
1012    }
1013
1014    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
1015          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
1016          ONE_TEMP_SIZE;
1017    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
1018    screen->max_tls_space /= 2; /* half of vram */
1019
1020    /* hw can address max 64 KiB */
1021    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
1022
1023    uint64_t tls_size;
1024    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
1025    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
1026    if (ret)
1027       goto fail;
1028
1029    if (nouveau_mesa_debug)
1030       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
1031             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
1032
1033    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
1034                         &screen->uniforms);
1035    if (ret) {
1036       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
1037       goto fail;
1038    }
1039
1040    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
1041                         &screen->txc);
1042    if (ret) {
1043       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1044       goto fail;
1045    }
1046
1047    screen->tic.entries = CALLOC(4096, sizeof(void *));
1048    screen->tsc.entries = screen->tic.entries + 2048;
1049
1050    if (!nv50_blitter_create(screen))
1051       goto fail;
1052
1053    nv50_screen_init_hwctx(screen);
1054
1055    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1056    if (ret) {
1057       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1058       goto fail;
1059    }
1060
1061    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1062
1063    return &screen->base;
1064
1065 fail:
1066    screen->base.base.context_create = NULL;
1067    return &screen->base;
1068 }
1069
1070 int
1071 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1072 {
1073    int i = screen->tic.next;
1074
1075    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1076       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1077
1078    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1079
1080    if (screen->tic.entries[i])
1081       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1082
1083    screen->tic.entries[i] = entry;
1084    return i;
1085 }
1086
1087 int
1088 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1089 {
1090    int i = screen->tsc.next;
1091
1092    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1093       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1094
1095    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1096
1097    if (screen->tsc.entries[i])
1098       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1099
1100    screen->tsc.entries[i] = entry;
1101    return i;
1102 }