2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
4 * Copyright (C) 2017 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 #include "pan_context.h"
32 #include "pan_format.h"
34 #include "util/macros.h"
35 #include "util/u_format.h"
36 #include "util/u_inlines.h"
37 #include "util/u_upload_mgr.h"
38 #include "util/u_memory.h"
39 #include "util/u_vbuf.h"
40 #include "util/half_float.h"
41 #include "util/u_helpers.h"
42 #include "util/u_format.h"
43 #include "util/u_prim.h"
44 #include "util/u_prim_restart.h"
45 #include "indices/u_primconvert.h"
46 #include "tgsi/tgsi_parse.h"
47 #include "tgsi/tgsi_from_mesa.h"
48 #include "util/u_math.h"
50 #include "pan_screen.h"
51 #include "pan_blending.h"
52 #include "pan_blend_shaders.h"
55 /* Framebuffer descriptor */
57 static struct midgard_tiler_descriptor
58 panfrost_emit_midg_tiler(struct panfrost_batch
*batch
, unsigned vertex_count
)
60 struct midgard_tiler_descriptor t
= {};
61 unsigned height
= batch
->key
.height
;
62 unsigned width
= batch
->key
.width
;
65 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
);
67 /* Compute the polygon header size and use that to offset the body */
69 unsigned header_size
= panfrost_tiler_header_size(
70 width
, height
, t
.hierarchy_mask
);
72 t
.polygon_list_size
= panfrost_tiler_full_size(
73 width
, height
, t
.hierarchy_mask
);
77 if (t
.hierarchy_mask
) {
78 struct panfrost_bo
*tiler_heap
;
80 tiler_heap
= panfrost_batch_get_tiler_heap(batch
);
81 t
.polygon_list
= panfrost_batch_get_polygon_list(batch
,
86 /* Allow the entire tiler heap */
87 t
.heap_start
= tiler_heap
->gpu
;
88 t
.heap_end
= tiler_heap
->gpu
+ tiler_heap
->size
;
90 struct panfrost_bo
*tiler_dummy
;
92 tiler_dummy
= panfrost_batch_get_tiler_dummy(batch
);
94 /* The tiler is disabled, so don't allow the tiler heap */
95 t
.heap_start
= tiler_dummy
->gpu
;
96 t
.heap_end
= t
.heap_start
;
98 /* Use a dummy polygon list */
99 t
.polygon_list
= tiler_dummy
->gpu
;
101 /* Disable the tiler */
102 t
.hierarchy_mask
|= MALI_TILER_DISABLED
;
105 t
.polygon_list_body
=
106 t
.polygon_list
+ header_size
;
111 struct mali_single_framebuffer
112 panfrost_emit_sfbd(struct panfrost_batch
*batch
, unsigned vertex_count
)
114 unsigned width
= batch
->key
.width
;
115 unsigned height
= batch
->key
.height
;
117 struct mali_single_framebuffer framebuffer
= {
118 .width
= MALI_POSITIVE(width
),
119 .height
= MALI_POSITIVE(height
),
121 .format
= 0x30000000,
122 .clear_flags
= 0x1000,
123 .unknown_address_0
= panfrost_batch_get_scratchpad(batch
)->gpu
,
124 .tiler
= panfrost_emit_midg_tiler(batch
, vertex_count
),
130 struct bifrost_framebuffer
131 panfrost_emit_mfbd(struct panfrost_batch
*batch
, unsigned vertex_count
)
133 unsigned width
= batch
->key
.width
;
134 unsigned height
= batch
->key
.height
;
136 struct bifrost_framebuffer framebuffer
= {
137 .unk0
= 0x1e5, /* 1e4 if no spill */
138 .width1
= MALI_POSITIVE(width
),
139 .height1
= MALI_POSITIVE(height
),
140 .width2
= MALI_POSITIVE(width
),
141 .height2
= MALI_POSITIVE(height
),
145 .rt_count_1
= MALI_POSITIVE(batch
->key
.nr_cbufs
),
150 .scratchpad
= panfrost_batch_get_scratchpad(batch
)->gpu
,
151 .tiler
= panfrost_emit_midg_tiler(batch
, vertex_count
)
159 struct pipe_context
*pipe
,
161 const union pipe_color_union
*color
,
162 double depth
, unsigned stencil
)
164 struct panfrost_context
*ctx
= pan_context(pipe
);
165 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
167 panfrost_batch_add_fbo_bos(batch
);
168 panfrost_batch_clear(batch
, buffers
, color
, depth
, stencil
);
172 panfrost_attach_vt_mfbd(struct panfrost_batch
*batch
)
174 struct bifrost_framebuffer mfbd
= panfrost_emit_mfbd(batch
, ~0);
176 return panfrost_upload_transient(batch
, &mfbd
, sizeof(mfbd
)) | MALI_MFBD
;
180 panfrost_attach_vt_sfbd(struct panfrost_batch
*batch
)
182 struct mali_single_framebuffer sfbd
= panfrost_emit_sfbd(batch
, ~0);
184 return panfrost_upload_transient(batch
, &sfbd
, sizeof(sfbd
)) | MALI_SFBD
;
188 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
190 /* Skip the attach if we can */
192 if (ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.framebuffer
) {
193 assert(ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.framebuffer
);
197 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
198 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
200 if (!batch
->framebuffer
)
201 batch
->framebuffer
= screen
->require_sfbd
?
202 panfrost_attach_vt_sfbd(batch
) :
203 panfrost_attach_vt_mfbd(batch
);
205 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
206 ctx
->payloads
[i
].postfix
.framebuffer
= batch
->framebuffer
;
209 /* Reset per-frame context, called on context initialisation as well as after
210 * flushing a frame */
213 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
215 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
216 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
219 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
222 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
224 /* TODO: When does this need to be handled? */
225 ctx
->active_queries
= true;
228 /* In practice, every field of these payloads should be configurable
229 * arbitrarily, which means these functions are basically catch-all's for
230 * as-of-yet unwavering unknowns */
233 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
235 /* 0x2 bit clear on 32-bit T6XX */
237 struct midgard_payload_vertex_tiler payload
= {
238 .gl_enables
= 0x4 | 0x2,
241 /* Vertex and compute are closely coupled, so share a payload */
243 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
244 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
248 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
250 struct midgard_payload_vertex_tiler payload
= {
252 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
256 memcpy(&ctx
->payloads
[PIPE_SHADER_FRAGMENT
], &payload
, sizeof(payload
));
260 translate_tex_wrap(enum pipe_tex_wrap w
)
263 case PIPE_TEX_WRAP_REPEAT
:
264 return MALI_WRAP_REPEAT
;
266 /* TODO: lower GL_CLAMP? */
267 case PIPE_TEX_WRAP_CLAMP
:
268 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
269 return MALI_WRAP_CLAMP_TO_EDGE
;
271 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
272 return MALI_WRAP_CLAMP_TO_BORDER
;
274 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
275 return MALI_WRAP_MIRRORED_REPEAT
;
278 unreachable("Invalid wrap");
283 panfrost_translate_compare_func(enum pipe_compare_func in
)
286 case PIPE_FUNC_NEVER
:
287 return MALI_FUNC_NEVER
;
290 return MALI_FUNC_LESS
;
292 case PIPE_FUNC_EQUAL
:
293 return MALI_FUNC_EQUAL
;
295 case PIPE_FUNC_LEQUAL
:
296 return MALI_FUNC_LEQUAL
;
298 case PIPE_FUNC_GREATER
:
299 return MALI_FUNC_GREATER
;
301 case PIPE_FUNC_NOTEQUAL
:
302 return MALI_FUNC_NOTEQUAL
;
304 case PIPE_FUNC_GEQUAL
:
305 return MALI_FUNC_GEQUAL
;
307 case PIPE_FUNC_ALWAYS
:
308 return MALI_FUNC_ALWAYS
;
311 unreachable("Invalid func");
316 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
319 case PIPE_FUNC_NEVER
:
320 return MALI_ALT_FUNC_NEVER
;
323 return MALI_ALT_FUNC_LESS
;
325 case PIPE_FUNC_EQUAL
:
326 return MALI_ALT_FUNC_EQUAL
;
328 case PIPE_FUNC_LEQUAL
:
329 return MALI_ALT_FUNC_LEQUAL
;
331 case PIPE_FUNC_GREATER
:
332 return MALI_ALT_FUNC_GREATER
;
334 case PIPE_FUNC_NOTEQUAL
:
335 return MALI_ALT_FUNC_NOTEQUAL
;
337 case PIPE_FUNC_GEQUAL
:
338 return MALI_ALT_FUNC_GEQUAL
;
340 case PIPE_FUNC_ALWAYS
:
341 return MALI_ALT_FUNC_ALWAYS
;
344 unreachable("Invalid alt func");
349 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
352 case PIPE_STENCIL_OP_KEEP
:
353 return MALI_STENCIL_KEEP
;
355 case PIPE_STENCIL_OP_ZERO
:
356 return MALI_STENCIL_ZERO
;
358 case PIPE_STENCIL_OP_REPLACE
:
359 return MALI_STENCIL_REPLACE
;
361 case PIPE_STENCIL_OP_INCR
:
362 return MALI_STENCIL_INCR
;
364 case PIPE_STENCIL_OP_DECR
:
365 return MALI_STENCIL_DECR
;
367 case PIPE_STENCIL_OP_INCR_WRAP
:
368 return MALI_STENCIL_INCR_WRAP
;
370 case PIPE_STENCIL_OP_DECR_WRAP
:
371 return MALI_STENCIL_DECR_WRAP
;
373 case PIPE_STENCIL_OP_INVERT
:
374 return MALI_STENCIL_INVERT
;
377 unreachable("Invalid stencil op");
382 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
384 out
->ref
= 0; /* Gallium gets it from elsewhere */
386 out
->mask
= in
->valuemask
;
387 out
->func
= panfrost_translate_compare_func(in
->func
);
388 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
389 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
390 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
394 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
396 struct mali_shader_meta shader
= {
397 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
399 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
400 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
403 /* unknown2_4 has 0x10 bit set on T6XX. We don't know why this is
404 * required (independent of 32-bit/64-bit descriptors), or why it's not
405 * used on later GPU revisions. Otherwise, all shader jobs fault on
406 * these earlier chips (perhaps this is a chicken bit of some kind).
407 * More investigation is needed. */
410 shader
.unknown2_4
|= 0x10;
413 struct pipe_stencil_state default_stencil
= {
415 .func
= PIPE_FUNC_ALWAYS
,
416 .fail_op
= MALI_STENCIL_KEEP
,
417 .zfail_op
= MALI_STENCIL_KEEP
,
418 .zpass_op
= MALI_STENCIL_KEEP
,
423 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
424 shader
.stencil_mask_front
= default_stencil
.writemask
;
426 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
427 shader
.stencil_mask_back
= default_stencil
.writemask
;
429 if (default_stencil
.enabled
)
430 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
432 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
435 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
436 * graphics command stream. It should be called once per draw, accordding to
437 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
438 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
441 struct panfrost_transfer
442 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
444 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
445 struct mali_job_descriptor_header job
= {
446 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
447 .job_descriptor_size
= 1,
450 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payloads
[PIPE_SHADER_FRAGMENT
] : &ctx
->payloads
[PIPE_SHADER_VERTEX
];
452 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sizeof(job
) + sizeof(*payload
));
453 memcpy(transfer
.cpu
, &job
, sizeof(job
));
454 memcpy(transfer
.cpu
+ sizeof(job
), payload
, sizeof(*payload
));
459 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
461 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
462 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
464 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
468 panfrost_writes_point_size(struct panfrost_context
*ctx
)
470 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
471 struct panfrost_shader_state
*vs
= &ctx
->shader
[PIPE_SHADER_VERTEX
]->variants
[ctx
->shader
[PIPE_SHADER_VERTEX
]->active_variant
];
473 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
476 /* Stage the attribute descriptors so we can adjust src_offset
477 * to let BOs align nicely */
480 panfrost_stage_attributes(struct panfrost_context
*ctx
)
482 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
483 struct panfrost_vertex_state
*so
= ctx
->vertex
;
485 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
486 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, sz
);
487 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
489 /* Copy as-is for the first pass */
490 memcpy(target
, so
->hw
, sz
);
492 /* Fixup offsets for the second pass. Recall that the hardware
493 * calculates attribute addresses as:
495 * addr = base + (stride * vtx) + src_offset;
497 * However, on Mali, base must be aligned to 64-bytes, so we
500 * base' = base & ~63 = base - (base & 63)
502 * To compensate when using base' (see emit_vertex_data), we have
503 * to adjust src_offset by the masked off piece:
505 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
506 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
507 * = base + (stride * vtx) + src_offset
513 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
;
515 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
516 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
517 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
518 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
520 /* Adjust by the masked off bits of the offset */
521 target
[i
].src_offset
+= (addr
& 63);
523 /* Also, somewhat obscurely per-instance data needs to be
524 * offset in response to a delayed start in an indexed draw */
526 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
) {
527 target
[i
].src_offset
-= buf
->stride
* start
;
533 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
537 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
539 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
540 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
542 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
545 if (ctx
->sampler_count
[t
] && ctx
->sampler_view_count
[t
]) {
546 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
548 struct panfrost_transfer transfer
=
549 panfrost_allocate_transient(batch
, transfer_size
);
551 struct mali_sampler_descriptor
*desc
=
552 (struct mali_sampler_descriptor
*) transfer
.cpu
;
554 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
555 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
557 upload
= transfer
.gpu
;
560 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
564 static enum mali_texture_layout
565 panfrost_layout_for_texture(struct panfrost_resource
*rsrc
)
567 /* TODO: other linear depth textures */
568 bool is_depth
= rsrc
->base
.format
== PIPE_FORMAT_Z32_UNORM
;
570 switch (rsrc
->layout
) {
572 return MALI_TEXTURE_AFBC
;
575 return MALI_TEXTURE_TILED
;
577 return is_depth
? MALI_TEXTURE_TILED
: MALI_TEXTURE_LINEAR
;
579 unreachable("Invalid texture layout");
585 struct panfrost_context
*ctx
,
586 struct panfrost_sampler_view
*view
)
591 struct pipe_sampler_view
*pview
= &view
->base
;
592 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
594 /* Do we interleave an explicit stride with every element? */
596 bool has_manual_stride
= view
->manual_stride
;
598 /* For easy access */
600 bool is_buffer
= pview
->target
== PIPE_BUFFER
;
601 unsigned first_level
= is_buffer
? 0 : pview
->u
.tex
.first_level
;
602 unsigned last_level
= is_buffer
? 0 : pview
->u
.tex
.last_level
;
603 unsigned first_layer
= is_buffer
? 0 : pview
->u
.tex
.first_layer
;
604 unsigned last_layer
= is_buffer
? 0 : pview
->u
.tex
.last_layer
;
606 /* Lower-bit is set when sampling from colour AFBC */
607 bool is_afbc
= rsrc
->layout
== PAN_AFBC
;
608 bool is_zs
= rsrc
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
;
609 unsigned afbc_bit
= (is_afbc
&& !is_zs
) ? 1 : 0;
611 /* Add the BO to the job so it's retained until the job is done. */
612 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
613 panfrost_batch_add_bo(batch
, rsrc
->bo
);
615 /* Add the usage flags in, since they can change across the CSO
616 * lifetime due to layout switches */
618 view
->hw
.format
.layout
= panfrost_layout_for_texture(rsrc
);
619 view
->hw
.format
.manual_stride
= has_manual_stride
;
621 /* Inject the addresses in, interleaving mip levels, cube faces, and
622 * strides in that order */
626 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
627 for (unsigned f
= first_layer
; f
<= last_layer
; ++f
) {
629 view
->hw
.payload
[idx
++] =
630 panfrost_get_texture_address(rsrc
, l
, f
) + afbc_bit
;
632 if (has_manual_stride
) {
633 view
->hw
.payload
[idx
++] =
634 rsrc
->slices
[l
].stride
;
639 return panfrost_upload_transient(batch
, &view
->hw
,
640 sizeof(struct mali_texture_descriptor
));
644 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
646 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
648 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
649 mali_ptr trampoline
= 0;
651 if (ctx
->sampler_view_count
[t
]) {
652 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
654 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
656 panfrost_upload_tex(ctx
, ctx
->sampler_views
[t
][i
]);
658 trampoline
= panfrost_upload_transient(batch
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
661 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
665 struct sysval_uniform
{
674 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
675 struct sysval_uniform
*uniform
)
677 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
679 uniform
->f
[0] = vp
->scale
[0];
680 uniform
->f
[1] = vp
->scale
[1];
681 uniform
->f
[2] = vp
->scale
[2];
684 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
685 struct sysval_uniform
*uniform
)
687 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
689 uniform
->f
[0] = vp
->translate
[0];
690 uniform
->f
[1] = vp
->translate
[1];
691 uniform
->f
[2] = vp
->translate
[2];
694 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
695 enum pipe_shader_type st
,
696 unsigned int sysvalid
,
697 struct sysval_uniform
*uniform
)
699 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
700 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
701 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
702 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
705 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
708 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
709 tex
->u
.tex
.first_level
);
712 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
713 tex
->u
.tex
.first_level
);
716 uniform
->i
[dim
] = tex
->texture
->array_size
;
719 static void panfrost_upload_ssbo_sysval(
720 struct panfrost_context
*ctx
,
721 enum pipe_shader_type st
,
723 struct sysval_uniform
*uniform
)
725 assert(ctx
->ssbo_mask
[st
] & (1 << ssbo_id
));
726 struct pipe_shader_buffer sb
= ctx
->ssbo
[st
][ssbo_id
];
728 /* Compute address */
729 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
730 struct panfrost_bo
*bo
= pan_resource(sb
.buffer
)->bo
;
732 panfrost_batch_add_bo(batch
, bo
);
734 /* Upload address and size as sysval */
735 uniform
->du
[0] = bo
->gpu
+ sb
.buffer_offset
;
736 uniform
->u
[2] = sb
.buffer_size
;
739 static void panfrost_upload_num_work_groups_sysval(struct panfrost_context
*ctx
,
740 struct sysval_uniform
*uniform
)
742 uniform
->u
[0] = ctx
->compute_grid
->grid
[0];
743 uniform
->u
[1] = ctx
->compute_grid
->grid
[1];
744 uniform
->u
[2] = ctx
->compute_grid
->grid
[2];
747 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
748 struct panfrost_shader_state
*ss
,
749 enum pipe_shader_type st
)
751 struct sysval_uniform
*uniforms
= (void *)buf
;
753 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
754 int sysval
= ss
->sysval
[i
];
756 switch (PAN_SYSVAL_TYPE(sysval
)) {
757 case PAN_SYSVAL_VIEWPORT_SCALE
:
758 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
760 case PAN_SYSVAL_VIEWPORT_OFFSET
:
761 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
763 case PAN_SYSVAL_TEXTURE_SIZE
:
764 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
767 case PAN_SYSVAL_SSBO
:
768 panfrost_upload_ssbo_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
771 case PAN_SYSVAL_NUM_WORK_GROUPS
:
772 panfrost_upload_num_work_groups_sysval(ctx
, &uniforms
[i
]);
782 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
784 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
785 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
788 return rsrc
->bo
->cpu
;
789 else if (cb
->user_buffer
)
790 return cb
->user_buffer
;
792 unreachable("No constant buffer");
796 panfrost_map_constant_buffer_gpu(
797 struct panfrost_context
*ctx
,
798 struct panfrost_constant_buffer
*buf
,
801 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
802 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
803 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
806 panfrost_batch_add_bo(batch
, rsrc
->bo
);
807 return rsrc
->bo
->gpu
;
808 } else if (cb
->user_buffer
) {
809 return panfrost_upload_transient(batch
, cb
->user_buffer
, cb
->buffer_size
);
811 unreachable("No constant buffer");
815 /* Compute number of UBOs active (more specifically, compute the highest UBO
816 * number addressable -- if there are gaps, include them in the count anyway).
817 * We always include UBO #0 in the count, since we *need* uniforms enabled for
821 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
823 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
824 return 32 - __builtin_clz(mask
);
827 /* Fixes up a shader state with current state, returning a GPU address to the
831 panfrost_patch_shader_state(
832 struct panfrost_context
*ctx
,
833 struct panfrost_shader_state
*ss
,
834 enum pipe_shader_type stage
,
837 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
838 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
840 ss
->tripipe
->midgard1
.flags
= 0x220;
842 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
843 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
845 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
847 /* Add the shader BO to the batch. */
848 panfrost_batch_add_bo(batch
, ss
->bo
);
850 /* We can't reuse over frames; that's not safe. The descriptor must be
851 * transient uploaded */
854 return panfrost_upload_transient(batch
, ss
->tripipe
,
855 sizeof(struct mali_shader_meta
));
858 /* If we don't need an upload, don't bother */
864 panfrost_patch_shader_state_compute(
865 struct panfrost_context
*ctx
,
866 enum pipe_shader_type stage
,
869 struct panfrost_shader_variants
*all
= ctx
->shader
[stage
];
872 ctx
->payloads
[stage
].postfix
._shader_upper
= 0;
876 struct panfrost_shader_state
*s
= &all
->variants
[all
->active_variant
];
878 ctx
->payloads
[stage
].postfix
._shader_upper
=
879 panfrost_patch_shader_state(ctx
, s
, stage
, should_upload
) >> 4;
882 /* Go through dirty flags and actualise them in the cmdstream. */
885 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
887 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
888 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
890 panfrost_batch_add_fbo_bos(batch
);
891 panfrost_attach_vt_framebuffer(ctx
);
893 if (with_vertex_data
) {
894 panfrost_emit_vertex_data(batch
);
896 /* Varyings emitted for -all- geometry */
897 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
898 panfrost_emit_varying_descriptor(ctx
, total_count
);
901 bool msaa
= ctx
->rasterizer
->base
.multisample
;
903 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
904 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
906 /* TODO: Sample size */
907 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
908 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
911 panfrost_batch_set_requirements(batch
);
913 if (ctx
->occlusion_query
) {
914 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
915 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
918 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_VERTEX
, true);
919 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_COMPUTE
, true);
921 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
922 /* Check if we need to link the gl_PointSize varying */
923 if (!panfrost_writes_point_size(ctx
)) {
924 /* If the size is constant, write it out. Otherwise,
925 * don't touch primitive_size (since we would clobber
926 * the pointer there) */
928 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
932 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
933 if (ctx
->shader
[PIPE_SHADER_FRAGMENT
])
934 ctx
->dirty
|= PAN_DIRTY_FS
;
936 if (ctx
->dirty
& PAN_DIRTY_FS
) {
937 assert(ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
938 struct panfrost_shader_state
*variant
= &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
];
940 panfrost_patch_shader_state(ctx
, variant
, PIPE_SHADER_FRAGMENT
, false);
942 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
945 COPY(attribute_count
);
949 COPY(midgard1
.uniform_count
);
950 COPY(midgard1
.uniform_buffer_count
);
951 COPY(midgard1
.work_count
);
952 COPY(midgard1
.flags
);
953 COPY(midgard1
.unknown2
);
957 /* Get blending setup */
958 unsigned rt_count
= MAX2(ctx
->pipe_framebuffer
.nr_cbufs
, 1);
960 struct panfrost_blend_final blend
[PIPE_MAX_COLOR_BUFS
];
962 for (unsigned c
= 0; c
< rt_count
; ++c
)
963 blend
[c
] = panfrost_get_blend_for_context(ctx
, c
);
965 /* If there is a blend shader, work registers are shared. XXX: opt */
967 for (unsigned c
= 0; c
< rt_count
; ++c
) {
968 if (blend
[c
].is_shader
)
969 ctx
->fragment_shader_core
.midgard1
.work_count
= 16;
972 /* Set late due to depending on render state */
973 unsigned flags
= ctx
->fragment_shader_core
.midgard1
.flags
;
975 /* Depending on whether it's legal to in the given shader, we
976 * try to enable early-z testing (or forward-pixel kill?) */
978 if (!variant
->can_discard
)
979 flags
|= MALI_EARLY_Z
;
981 /* Any time texturing is used, derivatives are implicitly
982 * calculated, so we need to enable helper invocations */
984 if (variant
->helper_invocations
)
985 flags
|= MALI_HELPER_INVOCATIONS
;
987 ctx
->fragment_shader_core
.midgard1
.flags
= flags
;
989 /* Assign the stencil refs late */
991 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
992 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
993 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
995 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
996 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
998 /* CAN_DISCARD should be set if the fragment shader possibly
999 * contains a 'discard' instruction. It is likely this is
1000 * related to optimizations related to forward-pixel kill, as
1001 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1002 * thing?" by Peter Harris
1005 if (variant
->can_discard
) {
1006 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1007 ctx
->fragment_shader_core
.midgard1
.flags
|= 0x400;
1010 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1011 * *also* copied to the blend_meta appended (by convention),
1012 * but this is the field actually read by the hardware. (Or
1013 * maybe both are read...?) */
1015 if (blend
[0].is_shader
) {
1016 ctx
->fragment_shader_core
.blend
.shader
=
1017 blend
[0].shader
.bo
->gpu
| blend
[0].shader
.first_tag
;
1019 ctx
->fragment_shader_core
.blend
.shader
= 0;
1022 if (screen
->require_sfbd
) {
1023 /* When only a single render target platform is used, the blend
1024 * information is inside the shader meta itself. We
1025 * additionally need to signal CAN_DISCARD for nontrivial blend
1026 * modes (so we're able to read back the destination buffer) */
1028 if (!blend
[0].is_shader
) {
1029 ctx
->fragment_shader_core
.blend
.equation
=
1030 *blend
[0].equation
.equation
;
1031 ctx
->fragment_shader_core
.blend
.constant
=
1032 blend
[0].equation
.constant
;
1035 if (!blend
[0].no_blending
) {
1036 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1040 size_t size
= sizeof(struct mali_shader_meta
) + (sizeof(struct midgard_blend_rt
) * rt_count
);
1041 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1042 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1044 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1046 if (!screen
->require_sfbd
) {
1047 /* Additional blend descriptor tacked on for jobs using MFBD */
1049 struct midgard_blend_rt rts
[4];
1051 for (unsigned i
= 0; i
< rt_count
; ++i
) {
1052 unsigned blend_count
= 0x200;
1054 if (blend
[i
].is_shader
) {
1055 /* For a blend shader, the bottom nibble corresponds to
1056 * the number of work registers used, which signals the
1057 * -existence- of a blend shader */
1059 assert(blend
[i
].shader
.work_count
>= 2);
1060 blend_count
|= MIN2(blend
[i
].shader
.work_count
, 3);
1062 /* Otherwise, the bottom bit simply specifies if
1063 * blending (anything other than REPLACE) is enabled */
1065 if (!blend
[i
].no_blending
)
1071 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1072 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
1073 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1075 rts
[i
].flags
= blend_count
;
1078 rts
[i
].flags
|= MALI_BLEND_SRGB
;
1080 if (!ctx
->blend
->base
.dither
)
1081 rts
[i
].flags
|= MALI_BLEND_NO_DITHER
;
1083 /* TODO: sRGB in blend shaders is currently
1084 * unimplemented. Contact me (Alyssa) if you're
1085 * interested in working on this. We have
1086 * native Midgard ops for helping here, but
1087 * they're not well-understood yet. */
1089 assert(!(is_srgb
&& blend
[i
].is_shader
));
1091 if (blend
[i
].is_shader
) {
1092 rts
[i
].blend
.shader
= blend
[i
].shader
.bo
->gpu
| blend
[i
].shader
.first_tag
;
1094 rts
[i
].blend
.equation
= *blend
[i
].equation
.equation
;
1095 rts
[i
].blend
.constant
= blend
[i
].equation
.constant
;
1099 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * rt_count
);
1103 /* We stage to transient, so always dirty.. */
1105 panfrost_stage_attributes(ctx
);
1107 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1108 panfrost_upload_sampler_descriptors(ctx
);
1110 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1111 panfrost_upload_texture_descriptors(ctx
);
1113 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1115 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1116 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1121 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1123 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1125 /* Uniforms are implicitly UBO #0 */
1126 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1128 /* Allocate room for the sysval and the uniforms */
1129 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1130 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1131 size_t size
= sys_size
+ uniform_size
;
1132 struct panfrost_transfer transfer
= panfrost_allocate_transient(batch
, size
);
1134 /* Upload sysvals requested by the shader */
1135 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1137 /* Upload uniforms */
1139 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1140 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1144 ctx
->shader
[i
]->variants
[ctx
->shader
[i
]->active_variant
].uniform_count
;
1146 struct mali_vertex_tiler_postfix
*postfix
=
1147 &ctx
->payloads
[i
].postfix
;
1149 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1152 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
1153 assert(ubo_count
>= 1);
1155 size_t sz
= sizeof(struct mali_uniform_buffer_meta
) * ubo_count
;
1156 struct mali_uniform_buffer_meta ubos
[PAN_MAX_CONST_BUFFERS
];
1158 /* Upload uniforms as a UBO */
1159 ubos
[0].size
= MALI_POSITIVE((2 + uniform_count
));
1160 ubos
[0].ptr
= transfer
.gpu
>> 2;
1162 /* The rest are honest-to-goodness UBOs */
1164 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1165 size_t usz
= buf
->cb
[ubo
].buffer_size
;
1167 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1168 bool empty
= usz
== 0;
1170 if (!enabled
|| empty
) {
1171 /* Stub out disabled UBOs to catch accesses */
1174 ubos
[ubo
].ptr
= 0xDEAD0000;
1178 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, buf
, ubo
);
1180 unsigned bytes_per_field
= 16;
1181 unsigned aligned
= ALIGN_POT(usz
, bytes_per_field
);
1182 unsigned fields
= aligned
/ bytes_per_field
;
1184 ubos
[ubo
].size
= MALI_POSITIVE(fields
);
1185 ubos
[ubo
].ptr
= gpu
>> 2;
1188 mali_ptr ubufs
= panfrost_upload_transient(batch
, ubos
, sz
);
1189 postfix
->uniforms
= transfer
.gpu
;
1190 postfix
->uniform_buffers
= ubufs
;
1192 buf
->dirty_mask
= 0;
1195 /* TODO: Upload the viewport somewhere more appropriate */
1197 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1198 * (somewhat) asymmetric ints. */
1199 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1201 struct mali_viewport view
= {
1202 /* By default, do no viewport clipping, i.e. clip to (-inf,
1203 * inf) in each direction. Clipping to the viewport in theory
1204 * should work, but in practice causes issues when we're not
1205 * explicitly trying to scissor */
1207 .clip_minx
= -INFINITY
,
1208 .clip_miny
= -INFINITY
,
1209 .clip_maxx
= INFINITY
,
1210 .clip_maxy
= INFINITY
,
1213 /* Always scissor to the viewport by default. */
1214 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
1215 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
1217 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
1218 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
1220 float minz
= (vp
->translate
[2] - fabsf(vp
->scale
[2]));
1221 float maxz
= (vp
->translate
[2] + fabsf(vp
->scale
[2]));
1223 /* Apply the scissor test */
1225 unsigned minx
, miny
, maxx
, maxy
;
1227 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1228 minx
= MAX2(ss
->minx
, vp_minx
);
1229 miny
= MAX2(ss
->miny
, vp_miny
);
1230 maxx
= MIN2(ss
->maxx
, vp_maxx
);
1231 maxy
= MIN2(ss
->maxy
, vp_maxy
);
1239 /* Hardware needs the min/max to be strictly ordered, so flip if we
1240 * need to. The viewport transformation in the vertex shader will
1241 * handle the negatives if we don't */
1244 unsigned temp
= miny
;
1250 unsigned temp
= minx
;
1261 /* Clamp to the framebuffer size as a last check */
1263 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1264 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1266 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1267 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1269 /* Update the job, unless we're doing wallpapering (whose lack of
1270 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1271 * just... be faster :) */
1273 if (!ctx
->wallpaper_batch
)
1274 panfrost_batch_union_scissor(batch
, minx
, miny
, maxx
, maxy
);
1278 view
.viewport0
[0] = minx
;
1279 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1281 view
.viewport0
[1] = miny
;
1282 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1284 view
.clip_minz
= minz
;
1285 view
.clip_maxz
= maxz
;
1287 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.viewport
=
1288 panfrost_upload_transient(batch
,
1290 sizeof(struct mali_viewport
));
1295 /* Corresponds to exactly one draw, but does not submit anything */
1298 panfrost_queue_draw(struct panfrost_context
*ctx
)
1300 /* Handle dirty flags now */
1301 panfrost_emit_for_draw(ctx
, true);
1303 /* If rasterizer discard is enable, only submit the vertex */
1305 bool rasterizer_discard
= ctx
->rasterizer
1306 && ctx
->rasterizer
->base
.rasterizer_discard
;
1308 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1309 struct panfrost_transfer tiler
;
1311 if (!rasterizer_discard
)
1312 tiler
= panfrost_vertex_tiler_job(ctx
, true);
1314 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1316 if (rasterizer_discard
)
1317 panfrost_scoreboard_queue_vertex_job(batch
, vertex
, FALSE
);
1318 else if (ctx
->wallpaper_batch
)
1319 panfrost_scoreboard_queue_fused_job_prepend(batch
, vertex
, tiler
);
1321 panfrost_scoreboard_queue_fused_job(batch
, vertex
, tiler
);
1324 /* The entire frame is in memory -- send it off to the kernel! */
1328 struct pipe_context
*pipe
,
1329 struct pipe_fence_handle
**fence
,
1332 struct panfrost_context
*ctx
= pan_context(pipe
);
1333 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1335 /* Submit the frame itself */
1336 panfrost_batch_submit(batch
);
1339 struct panfrost_fence
*f
= panfrost_fence_create(ctx
);
1340 pipe
->screen
->fence_reference(pipe
->screen
, fence
, NULL
);
1341 *fence
= (struct pipe_fence_handle
*)f
;
1345 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1348 g2m_draw_mode(enum pipe_prim_type mode
)
1351 DEFINE_CASE(POINTS
);
1353 DEFINE_CASE(LINE_LOOP
);
1354 DEFINE_CASE(LINE_STRIP
);
1355 DEFINE_CASE(TRIANGLES
);
1356 DEFINE_CASE(TRIANGLE_STRIP
);
1357 DEFINE_CASE(TRIANGLE_FAN
);
1359 DEFINE_CASE(QUAD_STRIP
);
1360 DEFINE_CASE(POLYGON
);
1363 unreachable("Invalid draw mode");
1370 panfrost_translate_index_size(unsigned size
)
1374 return MALI_DRAW_INDEXED_UINT8
;
1377 return MALI_DRAW_INDEXED_UINT16
;
1380 return MALI_DRAW_INDEXED_UINT32
;
1383 unreachable("Invalid index size");
1387 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1388 * good for the duration of the draw (transient), could last longer */
1391 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1393 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1395 off_t offset
= info
->start
* info
->index_size
;
1396 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
1398 if (!info
->has_user_indices
) {
1399 /* Only resources can be directly mapped */
1400 panfrost_batch_add_bo(batch
, rsrc
->bo
);
1401 return rsrc
->bo
->gpu
+ offset
;
1403 /* Otherwise, we need to upload to transient memory */
1404 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1405 return panfrost_upload_transient(batch
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1410 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1412 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1414 /* Check if we're scissoring at all */
1416 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1419 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1422 /* Count generated primitives (when there is no geom/tess shaders) for
1423 * transform feedback */
1426 panfrost_statistics_record(
1427 struct panfrost_context
*ctx
,
1428 const struct pipe_draw_info
*info
)
1430 if (!ctx
->active_queries
)
1433 uint32_t prims
= u_prims_for_vertices(info
->mode
, info
->count
);
1434 ctx
->prims_generated
+= prims
;
1436 if (!ctx
->streamout
.num_targets
)
1439 ctx
->tf_prims_generated
+= prims
;
1444 struct pipe_context
*pipe
,
1445 const struct pipe_draw_info
*info
)
1447 struct panfrost_context
*ctx
= pan_context(pipe
);
1449 /* First of all, check the scissor to see if anything is drawn at all.
1450 * If it's not, we drop the draw (mostly a conformance issue;
1451 * well-behaved apps shouldn't hit this) */
1453 if (panfrost_scissor_culls_everything(ctx
))
1456 int mode
= info
->mode
;
1458 /* Fallback unsupported restart index */
1459 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1461 if (info
->primitive_restart
&& info
->index_size
1462 && info
->restart_index
!= primitive_index
) {
1463 util_draw_vbo_without_prim_restart(pipe
, info
);
1467 /* Fallback for unsupported modes */
1469 assert(ctx
->rasterizer
!= NULL
);
1471 if (!(ctx
->draw_modes
& (1 << mode
))) {
1472 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && !ctx
->rasterizer
->base
.flatshade
) {
1473 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1475 if (info
->count
< 4) {
1476 /* Degenerate case? */
1480 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1481 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1486 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= info
->start
;
1487 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= info
->start
;
1489 /* Now that we have a guaranteed terminating path, find the job.
1490 * Assignment commented out to prevent unused warning */
1492 /* struct panfrost_batch *batch = */ panfrost_get_batch_for_fbo(ctx
);
1494 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
1496 /* Take into account a negative bias */
1497 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
1498 ctx
->instance_count
= info
->instance_count
;
1499 ctx
->active_prim
= info
->mode
;
1501 /* For non-indexed draws, they're the same */
1502 unsigned vertex_count
= ctx
->vertex_count
;
1504 unsigned draw_flags
= 0;
1506 /* The draw flags interpret how primitive size is interpreted */
1508 if (panfrost_writes_point_size(ctx
))
1509 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1511 if (info
->primitive_restart
)
1512 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1514 /* For higher amounts of vertices (greater than what fits in a 16-bit
1515 * short), the other value is needed, otherwise there will be bizarre
1516 * rendering artefacts. It's not clear what these values mean yet. This
1517 * change is also needed for instancing and sometimes points (perhaps
1518 * related to dynamically setting gl_PointSize) */
1520 bool is_points
= mode
== PIPE_PRIM_POINTS
;
1521 bool many_verts
= ctx
->vertex_count
> 0xFFFF;
1522 bool instanced
= ctx
->instance_count
> 1;
1524 draw_flags
|= (is_points
|| many_verts
|| instanced
) ? 0x3000 : 0x18000;
1526 /* This doesn't make much sense */
1527 if (mode
== PIPE_PRIM_LINE_STRIP
) {
1528 draw_flags
|= 0x800;
1531 panfrost_statistics_record(ctx
, info
);
1533 if (info
->index_size
) {
1534 /* Calculate the min/max index used so we can figure out how
1535 * many times to invoke the vertex shader */
1537 /* Fetch / calculate index bounds */
1538 unsigned min_index
= 0, max_index
= 0;
1540 if (info
->max_index
== ~0u) {
1541 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1543 min_index
= info
->min_index
;
1544 max_index
= info
->max_index
;
1547 /* Use the corresponding values */
1548 vertex_count
= max_index
- min_index
+ 1;
1549 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= min_index
+ info
->index_bias
;
1550 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= min_index
+ info
->index_bias
;
1552 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= -min_index
;
1553 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
1555 //assert(!info->restart_index); /* TODO: Research */
1557 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1558 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1560 /* Index count == vertex count, if no indexing is applied, as
1561 * if it is internally indexed in the expected order */
1563 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= 0;
1564 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1566 /* Reverse index state */
1567 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (u64
) NULL
;
1570 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1571 * vertex_count, 1) */
1573 panfrost_pack_work_groups_fused(
1574 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
1575 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
1576 1, vertex_count
, info
->instance_count
,
1579 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
1581 /* Encode the padded vertex count */
1583 if (info
->instance_count
> 1) {
1584 /* Triangles have non-even vertex counts so they change how
1585 * padding works internally */
1588 mode
== PIPE_PRIM_TRIANGLES
||
1589 mode
== PIPE_PRIM_TRIANGLE_STRIP
||
1590 mode
== PIPE_PRIM_TRIANGLE_FAN
;
1592 struct pan_shift_odd so
=
1593 panfrost_padded_vertex_count(vertex_count
, !is_triangle
);
1595 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= so
.shift
;
1596 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= so
.shift
;
1598 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= so
.odd
;
1599 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= so
.odd
;
1601 ctx
->padded_count
= pan_expand_shift_odd(so
);
1603 ctx
->padded_count
= vertex_count
;
1605 /* Reset instancing state */
1606 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
1607 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
1608 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
1609 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
1612 /* Fire off the draw itself */
1613 panfrost_queue_draw(ctx
);
1615 /* Increment transform feedback offsets */
1617 for (unsigned i
= 0; i
< ctx
->streamout
.num_targets
; ++i
) {
1618 unsigned output_count
= u_stream_outputs_for_vertices(
1619 ctx
->active_prim
, ctx
->vertex_count
);
1621 ctx
->streamout
.offsets
[i
] += output_count
;
1628 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1634 panfrost_create_rasterizer_state(
1635 struct pipe_context
*pctx
,
1636 const struct pipe_rasterizer_state
*cso
)
1638 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1642 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1643 so
->tiler_gl_enables
= 0x7;
1646 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1648 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1649 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1651 if (cso
->cull_face
& PIPE_FACE_BACK
)
1652 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1658 panfrost_bind_rasterizer_state(
1659 struct pipe_context
*pctx
,
1662 struct panfrost_context
*ctx
= pan_context(pctx
);
1664 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1668 ctx
->rasterizer
= hwcso
;
1669 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1671 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
;
1672 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1674 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1675 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1677 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1679 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1680 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1682 /* Point sprites are emulated */
1684 struct panfrost_shader_state
*variant
=
1685 ctx
->shader
[PIPE_SHADER_FRAGMENT
] ? &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
] : NULL
;
1687 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1688 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1692 panfrost_create_vertex_elements_state(
1693 struct pipe_context
*pctx
,
1694 unsigned num_elements
,
1695 const struct pipe_vertex_element
*elements
)
1697 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1699 so
->num_elements
= num_elements
;
1700 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1702 for (int i
= 0; i
< num_elements
; ++i
) {
1703 so
->hw
[i
].index
= i
;
1705 enum pipe_format fmt
= elements
[i
].src_format
;
1706 const struct util_format_description
*desc
= util_format_description(fmt
);
1707 so
->hw
[i
].unknown1
= 0x2;
1708 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1710 so
->hw
[i
].format
= panfrost_find_format(desc
);
1712 /* The field itself should probably be shifted over */
1713 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1720 panfrost_bind_vertex_elements_state(
1721 struct pipe_context
*pctx
,
1724 struct panfrost_context
*ctx
= pan_context(pctx
);
1726 ctx
->vertex
= hwcso
;
1727 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1731 panfrost_create_shader_state(
1732 struct pipe_context
*pctx
,
1733 const struct pipe_shader_state
*cso
)
1735 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1738 /* Token deep copy to prevent memory corruption */
1740 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1741 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1747 panfrost_delete_shader_state(
1748 struct pipe_context
*pctx
,
1751 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1753 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1754 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1757 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
1758 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
1759 panfrost_bo_unreference(shader_state
->bo
);
1760 shader_state
->bo
= NULL
;
1767 panfrost_create_sampler_state(
1768 struct pipe_context
*pctx
,
1769 const struct pipe_sampler_state
*cso
)
1771 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1774 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1776 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1777 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1778 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
1780 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
1781 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
1782 unsigned mip_filter
= mip_linear
?
1783 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
1784 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
1786 struct mali_sampler_descriptor sampler_descriptor
= {
1787 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
1788 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1789 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1790 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1791 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1793 cso
->border_color
.f
[0],
1794 cso
->border_color
.f
[1],
1795 cso
->border_color
.f
[2],
1796 cso
->border_color
.f
[3]
1798 .min_lod
= FIXED_16(cso
->min_lod
),
1799 .max_lod
= FIXED_16(cso
->max_lod
),
1800 .seamless_cube_map
= cso
->seamless_cube_map
,
1803 /* If necessary, we disable mipmapping in the sampler descriptor by
1804 * clamping the LOD as tight as possible (from 0 to epsilon,
1805 * essentially -- remember these are fixed point numbers, so
1808 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
1809 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1811 /* Enforce that there is something in the middle by adding epsilon*/
1813 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1814 sampler_descriptor
.max_lod
++;
1817 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1819 so
->hw
= sampler_descriptor
;
1825 panfrost_bind_sampler_states(
1826 struct pipe_context
*pctx
,
1827 enum pipe_shader_type shader
,
1828 unsigned start_slot
, unsigned num_sampler
,
1831 assert(start_slot
== 0);
1833 struct panfrost_context
*ctx
= pan_context(pctx
);
1835 /* XXX: Should upload, not just copy? */
1836 ctx
->sampler_count
[shader
] = num_sampler
;
1837 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1839 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1843 panfrost_variant_matches(
1844 struct panfrost_context
*ctx
,
1845 struct panfrost_shader_state
*variant
,
1846 enum pipe_shader_type type
)
1848 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1849 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1851 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1853 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1854 /* Make sure enable state is at least the same */
1855 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1859 /* Check that the contents of the test are the same */
1860 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1861 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1863 if (!(same_func
&& same_ref
)) {
1868 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1869 variant
->point_sprite_mask
)) {
1870 /* Ensure the same varyings are turned to point sprites */
1871 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
1874 /* Ensure the orientation is correct */
1876 rasterizer
->sprite_coord_mode
==
1877 PIPE_SPRITE_COORD_UPPER_LEFT
;
1879 if (variant
->point_sprite_upper_left
!= upper_left
)
1883 /* Otherwise, we're good to go */
1888 * Fix an uncompiled shader's stream output info, and produce a bitmask
1889 * of which VARYING_SLOT_* are captured for stream output.
1891 * Core Gallium stores output->register_index as a "slot" number, where
1892 * slots are assigned consecutively to all outputs in info->outputs_written.
1893 * This naive packing of outputs doesn't work for us - we too have slots,
1894 * but the layout is defined by the VUE map, which we won't have until we
1895 * compile a specific shader variant. So, we remap these and simply store
1896 * VARYING_SLOT_* in our copy's output->register_index fields.
1898 * We then produce a bitmask of outputs which are used for SO.
1900 * Implementation from iris.
1904 update_so_info(struct pipe_stream_output_info
*so_info
,
1905 uint64_t outputs_written
)
1907 uint64_t so_outputs
= 0;
1908 uint8_t reverse_map
[64] = {};
1911 while (outputs_written
)
1912 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
1914 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
1915 struct pipe_stream_output
*output
= &so_info
->output
[i
];
1917 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
1918 output
->register_index
= reverse_map
[output
->register_index
];
1920 so_outputs
|= 1ull << output
->register_index
;
1927 panfrost_bind_shader_state(
1928 struct pipe_context
*pctx
,
1930 enum pipe_shader_type type
)
1932 struct panfrost_context
*ctx
= pan_context(pctx
);
1934 ctx
->shader
[type
] = hwcso
;
1936 if (type
== PIPE_SHADER_FRAGMENT
)
1937 ctx
->dirty
|= PAN_DIRTY_FS
;
1939 ctx
->dirty
|= PAN_DIRTY_VS
;
1943 /* Match the appropriate variant */
1945 signed variant
= -1;
1946 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1948 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1949 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1955 if (variant
== -1) {
1956 /* No variant matched, so create a new one */
1957 variant
= variants
->variant_count
++;
1958 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
1960 struct panfrost_shader_state
*v
=
1961 &variants
->variants
[variant
];
1963 if (type
== PIPE_SHADER_FRAGMENT
) {
1964 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
1966 if (ctx
->rasterizer
) {
1967 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
1968 v
->point_sprite_upper_left
=
1969 ctx
->rasterizer
->base
.sprite_coord_mode
==
1970 PIPE_SPRITE_COORD_UPPER_LEFT
;
1974 variants
->variants
[variant
].tripipe
= calloc(1, sizeof(struct mali_shader_meta
));
1978 /* Select this variant */
1979 variants
->active_variant
= variant
;
1981 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1982 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
1984 /* We finally have a variant, so compile it */
1986 if (!shader_state
->compiled
) {
1987 uint64_t outputs_written
= 0;
1989 panfrost_shader_compile(ctx
, shader_state
->tripipe
,
1990 variants
->base
.type
,
1991 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
1992 variants
->base
.ir
.nir
:
1993 variants
->base
.tokens
,
1994 tgsi_processor_to_shader_stage(type
), shader_state
,
1997 shader_state
->compiled
= true;
1999 /* Fixup the stream out information, since what Gallium returns
2000 * normally is mildly insane */
2002 shader_state
->stream_output
= variants
->base
.stream_output
;
2003 shader_state
->so_mask
=
2004 update_so_info(&shader_state
->stream_output
, outputs_written
);
2009 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
2011 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2015 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2017 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2021 panfrost_set_vertex_buffers(
2022 struct pipe_context
*pctx
,
2023 unsigned start_slot
,
2024 unsigned num_buffers
,
2025 const struct pipe_vertex_buffer
*buffers
)
2027 struct panfrost_context
*ctx
= pan_context(pctx
);
2029 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2033 panfrost_set_constant_buffer(
2034 struct pipe_context
*pctx
,
2035 enum pipe_shader_type shader
, uint index
,
2036 const struct pipe_constant_buffer
*buf
)
2038 struct panfrost_context
*ctx
= pan_context(pctx
);
2039 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2041 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
2043 unsigned mask
= (1 << index
);
2045 if (unlikely(!buf
)) {
2046 pbuf
->enabled_mask
&= ~mask
;
2047 pbuf
->dirty_mask
&= ~mask
;
2051 pbuf
->enabled_mask
|= mask
;
2052 pbuf
->dirty_mask
|= mask
;
2056 panfrost_set_stencil_ref(
2057 struct pipe_context
*pctx
,
2058 const struct pipe_stencil_ref
*ref
)
2060 struct panfrost_context
*ctx
= pan_context(pctx
);
2061 ctx
->stencil_ref
= *ref
;
2063 /* Shader core dirty */
2064 ctx
->dirty
|= PAN_DIRTY_FS
;
2067 static enum mali_texture_type
2068 panfrost_translate_texture_type(enum pipe_texture_target t
) {
2072 case PIPE_TEXTURE_1D
:
2073 case PIPE_TEXTURE_1D_ARRAY
:
2076 case PIPE_TEXTURE_2D
:
2077 case PIPE_TEXTURE_2D_ARRAY
:
2078 case PIPE_TEXTURE_RECT
:
2081 case PIPE_TEXTURE_3D
:
2084 case PIPE_TEXTURE_CUBE
:
2085 case PIPE_TEXTURE_CUBE_ARRAY
:
2086 return MALI_TEX_CUBE
;
2089 unreachable("Unknown target");
2093 static struct pipe_sampler_view
*
2094 panfrost_create_sampler_view(
2095 struct pipe_context
*pctx
,
2096 struct pipe_resource
*texture
,
2097 const struct pipe_sampler_view
*template)
2099 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2100 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2102 pipe_reference(NULL
, &texture
->reference
);
2104 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2107 so
->base
= *template;
2108 so
->base
.texture
= texture
;
2109 so
->base
.reference
.count
= 1;
2110 so
->base
.context
= pctx
;
2112 /* sampler_views correspond to texture descriptors, minus the texture
2113 * (data) itself. So, we serialise the descriptor here and cache it for
2116 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2118 unsigned char user_swizzle
[4] = {
2119 template->swizzle_r
,
2120 template->swizzle_g
,
2121 template->swizzle_b
,
2125 enum mali_format format
= panfrost_find_format(desc
);
2127 /* Check if we need to set a custom stride by computing the "expected"
2128 * stride and comparing it to what the BO actually wants. Only applies
2129 * to linear textures, since tiled/compressed textures have strict
2130 * alignment requirements for their strides as it is */
2132 unsigned first_level
= template->u
.tex
.first_level
;
2133 unsigned last_level
= template->u
.tex
.last_level
;
2135 if (prsrc
->layout
== PAN_LINEAR
) {
2136 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2137 unsigned actual_stride
= prsrc
->slices
[l
].stride
;
2138 unsigned width
= u_minify(texture
->width0
, l
);
2139 unsigned comp_stride
= width
* bytes_per_pixel
;
2141 if (comp_stride
!= actual_stride
) {
2142 so
->manual_stride
= true;
2148 /* In the hardware, array_size refers specifically to array textures,
2149 * whereas in Gallium, it also covers cubemaps */
2151 unsigned array_size
= texture
->array_size
;
2153 if (template->target
== PIPE_TEXTURE_CUBE
) {
2154 /* TODO: Cubemap arrays */
2155 assert(array_size
== 6);
2159 struct mali_texture_descriptor texture_descriptor
= {
2160 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2161 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2162 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2163 .array_size
= MALI_POSITIVE(array_size
),
2166 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2168 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2169 .type
= panfrost_translate_texture_type(template->target
),
2173 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2176 texture_descriptor
.levels
= last_level
- first_level
;
2178 so
->hw
= texture_descriptor
;
2180 return (struct pipe_sampler_view
*) so
;
2184 panfrost_set_sampler_views(
2185 struct pipe_context
*pctx
,
2186 enum pipe_shader_type shader
,
2187 unsigned start_slot
, unsigned num_views
,
2188 struct pipe_sampler_view
**views
)
2190 struct panfrost_context
*ctx
= pan_context(pctx
);
2192 assert(start_slot
== 0);
2194 unsigned new_nr
= 0;
2195 for (unsigned i
= 0; i
< num_views
; ++i
) {
2200 ctx
->sampler_view_count
[shader
] = new_nr
;
2201 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2203 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2207 panfrost_sampler_view_destroy(
2208 struct pipe_context
*pctx
,
2209 struct pipe_sampler_view
*view
)
2211 pipe_resource_reference(&view
->texture
, NULL
);
2216 panfrost_set_shader_buffers(
2217 struct pipe_context
*pctx
,
2218 enum pipe_shader_type shader
,
2219 unsigned start
, unsigned count
,
2220 const struct pipe_shader_buffer
*buffers
,
2221 unsigned writable_bitmask
)
2223 struct panfrost_context
*ctx
= pan_context(pctx
);
2225 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
2226 buffers
, start
, count
);
2229 /* Hints that a framebuffer should use AFBC where possible */
2233 struct panfrost_screen
*screen
,
2234 const struct pipe_framebuffer_state
*fb
)
2236 /* AFBC implemenation incomplete; hide it */
2237 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
2239 /* Hint AFBC to the resources bound to each color buffer */
2241 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
2242 struct pipe_surface
*surf
= fb
->cbufs
[i
];
2243 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
2244 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2247 /* Also hint it to the depth buffer */
2250 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
2251 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2256 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2257 const struct pipe_framebuffer_state
*fb
)
2259 struct panfrost_context
*ctx
= pan_context(pctx
);
2261 /* Flush when switching framebuffers, but not if the framebuffer
2262 * state is being restored by u_blitter
2265 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
2266 bool is_scanout
= panfrost_batch_is_scanout(batch
);
2267 bool has_draws
= batch
->last_job
.gpu
;
2269 /* Bail out early when the current and new states are the same. */
2270 if (util_framebuffer_state_equal(&ctx
->pipe_framebuffer
, fb
))
2273 /* The wallpaper logic sets a new FB state before doing the blit and
2274 * restore the old one when it's done. Those FB states are reported to
2275 * be different because the surface they are pointing to are different,
2276 * but those surfaces actually point to the same cbufs/zbufs. In that
2277 * case we definitely don't want new FB descs to be emitted/attached
2278 * since the job is expected to be flushed just after the blit is done,
2279 * so let's just copy the new state and return here.
2281 if (ctx
->wallpaper_batch
) {
2282 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2286 if (!is_scanout
|| has_draws
)
2287 panfrost_flush(pctx
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2289 assert(!ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.framebuffer
&&
2290 !ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.framebuffer
);
2292 /* Invalidate the FBO job cache since we've just been assigned a new
2297 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2299 /* Given that we're rendering, we'd love to have compression */
2300 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
2302 panfrost_hint_afbc(screen
, &ctx
->pipe_framebuffer
);
2303 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
2304 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
2308 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2309 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2311 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2315 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2318 struct panfrost_context
*ctx
= pan_context(pipe
);
2319 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2320 ctx
->depth_stencil
= depth_stencil
;
2325 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2326 * emulated in the fragment shader */
2328 if (depth_stencil
->alpha
.enabled
) {
2329 /* We need to trigger a new shader (maybe) */
2330 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
2334 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
2336 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2337 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2339 /* If back-stencil is not enabled, use the front values */
2340 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
2341 unsigned back_index
= back_enab
? 1 : 0;
2343 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
2344 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
2346 /* Depth state (TODO: Refactor) */
2347 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2349 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2351 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2352 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2354 /* Bounds test not implemented */
2355 assert(!depth_stencil
->depth
.bounds_test
);
2357 ctx
->dirty
|= PAN_DIRTY_FS
;
2361 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2367 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2368 unsigned sample_mask
)
2373 panfrost_set_clip_state(struct pipe_context
*pipe
,
2374 const struct pipe_clip_state
*clip
)
2376 //struct panfrost_context *panfrost = pan_context(pipe);
2380 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2381 unsigned start_slot
,
2382 unsigned num_viewports
,
2383 const struct pipe_viewport_state
*viewports
)
2385 struct panfrost_context
*ctx
= pan_context(pipe
);
2387 assert(start_slot
== 0);
2388 assert(num_viewports
== 1);
2390 ctx
->pipe_viewport
= *viewports
;
2394 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2395 unsigned start_slot
,
2396 unsigned num_scissors
,
2397 const struct pipe_scissor_state
*scissors
)
2399 struct panfrost_context
*ctx
= pan_context(pipe
);
2401 assert(start_slot
== 0);
2402 assert(num_scissors
== 1);
2404 ctx
->scissor
= *scissors
;
2408 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2409 const struct pipe_poly_stipple
*stipple
)
2411 //struct panfrost_context *panfrost = pan_context(pipe);
2415 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2418 struct panfrost_context
*ctx
= pan_context(pipe
);
2419 ctx
->active_queries
= enable
;
2423 panfrost_destroy(struct pipe_context
*pipe
)
2425 struct panfrost_context
*panfrost
= pan_context(pipe
);
2427 if (panfrost
->blitter
)
2428 util_blitter_destroy(panfrost
->blitter
);
2430 if (panfrost
->blitter_wallpaper
)
2431 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2436 static struct pipe_query
*
2437 panfrost_create_query(struct pipe_context
*pipe
,
2441 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2446 return (struct pipe_query
*) q
;
2450 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2456 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2458 struct panfrost_context
*ctx
= pan_context(pipe
);
2459 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2460 struct panfrost_batch
*batch
= panfrost_get_batch_for_fbo(ctx
);
2462 switch (query
->type
) {
2463 case PIPE_QUERY_OCCLUSION_COUNTER
:
2464 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2465 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2466 /* Allocate a word for the query results to be stored */
2467 query
->transfer
= panfrost_allocate_transient(batch
, sizeof(unsigned));
2468 ctx
->occlusion_query
= query
;
2471 /* Geometry statistics are computed in the driver. XXX: geom/tess
2474 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2475 query
->start
= ctx
->prims_generated
;
2477 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2478 query
->start
= ctx
->tf_prims_generated
;
2482 fprintf(stderr
, "Skipping query %u\n", query
->type
);
2490 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2492 struct panfrost_context
*ctx
= pan_context(pipe
);
2493 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2495 switch (query
->type
) {
2496 case PIPE_QUERY_OCCLUSION_COUNTER
:
2497 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2498 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2499 ctx
->occlusion_query
= NULL
;
2501 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2502 query
->end
= ctx
->prims_generated
;
2504 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2505 query
->end
= ctx
->tf_prims_generated
;
2513 panfrost_get_query_result(struct pipe_context
*pipe
,
2514 struct pipe_query
*q
,
2516 union pipe_query_result
*vresult
)
2518 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2521 switch (query
->type
) {
2522 case PIPE_QUERY_OCCLUSION_COUNTER
:
2523 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2524 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2526 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2528 /* Read back the query results */
2529 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2530 unsigned passed
= *result
;
2532 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2533 vresult
->u64
= passed
;
2535 vresult
->b
= !!passed
;
2540 case PIPE_QUERY_PRIMITIVES_GENERATED
:
2541 case PIPE_QUERY_PRIMITIVES_EMITTED
:
2542 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2543 vresult
->u64
= query
->end
- query
->start
;
2547 DBG("Skipped query get %u\n", query
->type
);
2554 static struct pipe_stream_output_target
*
2555 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2556 struct pipe_resource
*prsc
,
2557 unsigned buffer_offset
,
2558 unsigned buffer_size
)
2560 struct pipe_stream_output_target
*target
;
2562 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2567 pipe_reference_init(&target
->reference
, 1);
2568 pipe_resource_reference(&target
->buffer
, prsc
);
2570 target
->context
= pctx
;
2571 target
->buffer_offset
= buffer_offset
;
2572 target
->buffer_size
= buffer_size
;
2578 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2579 struct pipe_stream_output_target
*target
)
2581 pipe_resource_reference(&target
->buffer
, NULL
);
2582 ralloc_free(target
);
2586 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2587 unsigned num_targets
,
2588 struct pipe_stream_output_target
**targets
,
2589 const unsigned *offsets
)
2591 struct panfrost_context
*ctx
= pan_context(pctx
);
2592 struct panfrost_streamout
*so
= &ctx
->streamout
;
2594 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
2596 for (unsigned i
= 0; i
< num_targets
; i
++) {
2597 if (offsets
[i
] != -1)
2598 so
->offsets
[i
] = offsets
[i
];
2600 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
2603 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
2604 pipe_so_target_reference(&so
->targets
[i
], NULL
);
2606 so
->num_targets
= num_targets
;
2609 struct pipe_context
*
2610 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2612 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2613 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2614 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2616 ctx
->is_t6xx
= pscreen
->gpu_id
< 0x0700; /* Literally, "earlier than T700" */
2618 gallium
->screen
= screen
;
2620 gallium
->destroy
= panfrost_destroy
;
2622 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2624 gallium
->flush
= panfrost_flush
;
2625 gallium
->clear
= panfrost_clear
;
2626 gallium
->draw_vbo
= panfrost_draw_vbo
;
2628 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2629 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2630 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
2632 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2634 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2635 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2636 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2638 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2639 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2640 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2642 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2643 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2644 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2646 gallium
->create_fs_state
= panfrost_create_shader_state
;
2647 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2648 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2650 gallium
->create_vs_state
= panfrost_create_shader_state
;
2651 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2652 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2654 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2655 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2656 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2658 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2659 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2660 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2662 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2664 gallium
->set_clip_state
= panfrost_set_clip_state
;
2665 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2666 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2667 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2668 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2670 gallium
->create_query
= panfrost_create_query
;
2671 gallium
->destroy_query
= panfrost_destroy_query
;
2672 gallium
->begin_query
= panfrost_begin_query
;
2673 gallium
->end_query
= panfrost_end_query
;
2674 gallium
->get_query_result
= panfrost_get_query_result
;
2676 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2677 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2678 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2680 panfrost_resource_context_init(gallium
);
2681 panfrost_blend_context_init(gallium
);
2682 panfrost_compute_context_init(gallium
);
2686 ret
= drmSyncobjCreate(pscreen
->fd
, DRM_SYNCOBJ_CREATE_SIGNALED
,
2691 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2692 gallium
->const_uploader
= gallium
->stream_uploader
;
2693 assert(gallium
->stream_uploader
);
2695 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2696 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2698 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2700 ctx
->blitter
= util_blitter_create(gallium
);
2701 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2703 assert(ctx
->blitter
);
2704 assert(ctx
->blitter_wallpaper
);
2706 /* Prepare for render! */
2708 panfrost_batch_init(ctx
);
2709 panfrost_emit_vertex_payload(ctx
);
2710 panfrost_emit_tiler_payload(ctx
);
2711 panfrost_invalidate_frame(ctx
);
2712 panfrost_default_shader_backend(ctx
);