2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "util/u_blitter.h"
30 #include "util/u_slab.h"
31 #include "util/u_suballoc.h"
32 #include "util/u_double_list.h"
33 #include "util/u_transfer.h"
34 #include "r600_llvm.h"
35 #include "r600_public.h"
36 #include "r600_resource.h"
38 #define R600_NUM_ATOMS 40
40 #define R600_TRACE_CS 0
42 /* the number of CS dwords for flushing and drawing */
43 #define R600_MAX_FLUSH_CS_DWORDS 16
44 #define R600_MAX_DRAW_CS_DWORDS 34
45 #define R600_TRACE_CS_DWORDS 7
47 #define R600_MAX_USER_CONST_BUFFERS 13
48 #define R600_MAX_DRIVER_CONST_BUFFERS 3
49 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
51 /* start driver buffers after user buffers */
52 #define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
53 #define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
54 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
56 #define R600_MAX_CONST_BUFFER_SIZE 4096
58 #ifdef PIPE_ARCH_BIG_ENDIAN
59 #define R600_BIG_ENDIAN 1
61 #define R600_BIG_ENDIAN 0
64 #define R600_MAP_BUFFER_ALIGNMENT 64
66 #define R600_ERR(fmt, args...) \
67 fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
69 #define R600_CONTEXT_INVAL_READ_CACHES (1 << 0)
70 #define R600_CONTEXT_STREAMOUT_FLUSH (1 << 1)
71 #define R600_CONTEXT_WAIT_3D_IDLE (1 << 2)
72 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (1 << 3)
73 #define R600_CONTEXT_FLUSH_AND_INV (1 << 4)
74 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (1 << 5)
75 #define R600_CONTEXT_PS_PARTIAL_FLUSH (1 << 6)
76 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (1 << 7)
78 #define R600_QUERY_DRAW_CALLS (PIPE_QUERY_DRIVER_SPECIFIC + 0)
79 #define R600_QUERY_REQUESTED_VRAM (PIPE_QUERY_DRIVER_SPECIFIC + 1)
80 #define R600_QUERY_REQUESTED_GTT (PIPE_QUERY_DRIVER_SPECIFIC + 2)
81 #define R600_QUERY_BUFFER_WAIT_TIME (PIPE_QUERY_DRIVER_SPECIFIC + 3)
85 struct r600_shader_key
;
87 /* This encapsulates a state or an operation which can emitted into the GPU
88 * command stream. It's not limited to states only, it can be used for anything
89 * that wants to write commands into the CS (e.g. cache flushes). */
91 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
);
97 /* This is an atom containing GPU commands that never change.
98 * This is supposed to be copied directly into the CS. */
99 struct r600_command_buffer
{
106 struct r600_db_state
{
107 struct r600_atom atom
;
108 struct r600_surface
*rsurf
;
111 struct r600_db_misc_state
{
112 struct r600_atom atom
;
113 bool occlusion_query_enabled
;
114 bool flush_depthstencil_through_cb
;
115 bool flush_depthstencil_in_place
;
116 bool copy_depth
, copy_stencil
;
117 unsigned copy_sample
;
118 unsigned log_samples
;
119 unsigned db_shader_control
;
123 struct r600_cb_misc_state
{
124 struct r600_atom atom
;
125 unsigned cb_color_control
; /* this comes from blend state */
126 unsigned blend_colormask
; /* 8*4 bits for 8 RGBA colorbuffers */
128 unsigned nr_ps_color_outputs
;
133 struct r600_clip_misc_state
{
134 struct r600_atom atom
;
135 unsigned pa_cl_clip_cntl
; /* from rasterizer */
136 unsigned pa_cl_vs_out_cntl
; /* from vertex shader */
137 unsigned clip_plane_enable
; /* from rasterizer */
138 unsigned clip_dist_write
; /* from vertex shader */
141 struct r600_alphatest_state
{
142 struct r600_atom atom
;
143 unsigned sx_alpha_test_control
; /* this comes from dsa state */
144 unsigned sx_alpha_ref
; /* this comes from dsa state */
146 bool cb0_export_16bpc
; /* from set_framebuffer_state */
149 struct r600_vgt_state
{
150 struct r600_atom atom
;
151 uint32_t vgt_multi_prim_ib_reset_en
;
152 uint32_t vgt_multi_prim_ib_reset_indx
;
153 uint32_t vgt_indx_offset
;
156 struct r600_blend_color
{
157 struct r600_atom atom
;
158 struct pipe_blend_color state
;
161 struct r600_clip_state
{
162 struct r600_atom atom
;
163 struct pipe_clip_state state
;
166 struct r600_cs_shader_state
{
167 struct r600_atom atom
;
168 unsigned kernel_index
;
169 struct r600_pipe_compute
*shader
;
172 struct r600_framebuffer
{
173 struct r600_atom atom
;
174 struct pipe_framebuffer_state state
;
175 unsigned compressed_cb_mask
;
179 bool is_msaa_resolve
;
182 struct r600_sample_mask
{
183 struct r600_atom atom
;
184 uint16_t sample_mask
; /* there are only 8 bits on EG, 16 bits on Cayman */
187 struct r600_config_state
{
188 struct r600_atom atom
;
189 unsigned sq_gpr_resource_mgmt_1
;
192 struct r600_stencil_ref
199 struct r600_stencil_ref_state
{
200 struct r600_atom atom
;
201 struct r600_stencil_ref state
;
202 struct pipe_stencil_ref pipe_state
;
205 struct r600_viewport_state
{
206 struct r600_atom atom
;
207 struct pipe_viewport_state state
;
210 struct r600_pipe_fences
{
211 struct r600_resource
*bo
;
214 /* linked list of preallocated blocks */
215 struct list_head blocks
;
216 /* linked list of freed fences */
217 struct list_head pool
;
221 enum r600_msaa_texture_mode
{
222 /* If the hw can fetch the first sample only (no decompression available).
223 * This means MSAA texturing is not fully implemented. */
224 MSAA_TEXTURE_SAMPLE_ZERO
,
226 /* If the hw can fetch decompressed MSAA textures.
227 * Supported families: R600, R700, Evergreen.
228 * Cayman cannot use this, because it cannot do the decompression. */
229 MSAA_TEXTURE_DECOMPRESSED
,
231 /* If the hw can fetch compressed MSAA textures, which means shaders can
232 * read resolved FMASK. This yields the best performance.
233 * Supported families: Evergreen, Cayman. */
234 MSAA_TEXTURE_COMPRESSED
237 typedef boolean (*r600g_dma_blit_t
)(struct pipe_context
*ctx
,
238 struct pipe_resource
*dst
,
240 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
241 struct pipe_resource
*src
,
243 const struct pipe_box
*src_box
);
246 #define DBG_TEX_DEPTH (1 << 0)
247 #define DBG_COMPUTE (1 << 1)
248 #define DBG_VM (1 << 2)
250 #define DBG_FS (1 << 8)
251 #define DBG_VS (1 << 9)
252 #define DBG_GS (1 << 10)
253 #define DBG_PS (1 << 11)
254 #define DBG_CS (1 << 12)
256 #define DBG_NO_HYPERZ (1 << 16)
257 #define DBG_NO_LLVM (1 << 17)
258 #define DBG_NO_CP_DMA (1 << 18)
259 #define DBG_NO_ASYNC_DMA (1 << 19)
260 #define DBG_NO_DISCARD_RANGE (1 << 20)
262 struct r600_tiling_info
{
263 unsigned num_channels
;
265 unsigned group_bytes
;
269 struct pipe_screen screen
;
270 struct radeon_winsys
*ws
;
271 unsigned debug_flags
;
273 enum chip_class chip_class
;
274 struct radeon_info info
;
278 enum r600_msaa_texture_mode msaa_texture_support
;
279 struct r600_tiling_info tiling_info
;
280 struct r600_pipe_fences fences
;
282 /*for compute global memory binding, we allocate stuff here, instead of
284 * XXX: Not sure if this is the best place for global_pool. Also,
285 * it's not thread safe, so it won't work with multiple contexts. */
286 struct compute_memory_pool
*global_pool
;
288 struct r600_resource
*trace_bo
;
292 r600g_dma_blit_t dma_blit
;
295 struct r600_pipe_sampler_view
{
296 struct pipe_sampler_view base
;
297 struct r600_resource
*tex_resource
;
298 uint32_t tex_resource_words
[8];
299 bool skip_mip_address_reloc
;
302 struct r600_rasterizer_state
{
303 struct r600_command_buffer buffer
;
306 unsigned sprite_coord_enable
;
307 unsigned clip_plane_enable
;
308 unsigned pa_sc_line_stipple
;
309 unsigned pa_cl_clip_cntl
;
314 bool multisample_enable
;
317 struct r600_poly_offset_state
{
318 struct r600_atom atom
;
319 enum pipe_format zs_format
;
324 struct r600_blend_state
{
325 struct r600_command_buffer buffer
;
326 struct r600_command_buffer buffer_no_blend
;
327 unsigned cb_target_mask
;
328 unsigned cb_color_control
;
329 unsigned cb_color_control_no_blend
;
334 struct r600_dsa_state
{
335 struct r600_command_buffer buffer
;
340 unsigned sx_alpha_test_control
;
343 struct r600_pipe_shader
;
345 struct r600_pipe_shader_selector
{
346 struct r600_pipe_shader
*current
;
348 struct tgsi_token
*tokens
;
349 struct pipe_stream_output_info so
;
351 unsigned num_shaders
;
353 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
356 unsigned nr_ps_max_color_exports
;
359 struct r600_pipe_sampler_state
{
360 uint32_t tex_sampler_words
[3];
361 union pipe_color_union border_color
;
362 bool border_color_use
;
363 bool seamless_cube_map
;
366 /* needed for blitter save */
367 #define NUM_TEX_UNITS 16
369 struct r600_seamless_cube_map
{
370 struct r600_atom atom
;
374 struct r600_samplerview_state
{
375 struct r600_atom atom
;
376 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
377 uint32_t enabled_mask
;
379 uint32_t compressed_depthtex_mask
; /* which textures are depth */
380 uint32_t compressed_colortex_mask
;
381 boolean dirty_txq_constants
;
382 boolean dirty_buffer_constants
;
385 struct r600_sampler_states
{
386 struct r600_atom atom
;
387 struct r600_pipe_sampler_state
*states
[NUM_TEX_UNITS
];
388 uint32_t enabled_mask
;
390 uint32_t has_bordercolor_mask
; /* which states contain the border color */
393 struct r600_textures_info
{
394 struct r600_samplerview_state views
;
395 struct r600_sampler_states states
;
396 bool is_array_sampler
[NUM_TEX_UNITS
];
398 /* cube array txq workaround */
399 uint32_t *txq_constants
;
400 /* buffer related workarounds */
401 uint32_t *buffer_constants
;
405 struct pipe_reference reference
;
406 unsigned index
; /* in the shared bo */
407 struct r600_resource
*sleep_bo
;
408 struct list_head head
;
411 #define FENCE_BLOCK_SIZE 16
413 struct r600_fence_block
{
414 struct r600_fence fences
[FENCE_BLOCK_SIZE
];
415 struct list_head head
;
418 #define R600_CONSTANT_ARRAY_SIZE 256
419 #define R600_RESOURCE_ARRAY_SIZE 160
421 struct r600_constbuf_state
423 struct r600_atom atom
;
424 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
425 uint32_t enabled_mask
;
429 struct r600_vertexbuf_state
431 struct r600_atom atom
;
432 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
433 uint32_t enabled_mask
; /* non-NULL buffers */
437 /* CSO (constant state object, in other words, immutable state). */
438 struct r600_cso_state
440 struct r600_atom atom
;
441 void *cso
; /* e.g. r600_blend_state */
442 struct r600_command_buffer
*cb
;
445 struct r600_scissor_state
447 struct r600_atom atom
;
448 struct pipe_scissor_state scissor
;
449 bool enable
; /* r6xx only */
452 struct r600_fetch_shader
{
453 struct r600_resource
*buffer
;
457 struct r600_shader_state
{
458 struct r600_atom atom
;
459 struct r600_pipe_shader_selector
*shader
;
462 struct r600_query_buffer
{
463 /* The buffer where query results are stored. */
464 struct r600_resource
*buf
;
465 /* Offset of the next free result after current query data */
466 unsigned results_end
;
467 /* If a query buffer is full, a new buffer is created and the old one
468 * is put in here. When we calculate the result, we sum up the samples
469 * from all buffers. */
470 struct r600_query_buffer
*previous
;
474 /* The query buffer and how many results are in it. */
475 struct r600_query_buffer buffer
;
476 /* The type of query */
478 /* Size of the result in memory for both begin_query and end_query,
479 * this can be one or two numbers, or it could even be a size of a structure. */
480 unsigned result_size
;
481 /* The number of dwords for begin_query or end_query. */
483 /* linked list of queries */
484 struct list_head list
;
485 /* for custom non-GPU queries */
486 uint64_t begin_result
;
490 struct r600_so_target
{
491 struct pipe_stream_output_target b
;
493 /* The buffer where BUFFER_FILLED_SIZE is stored. */
494 struct r600_resource
*buf_filled_size
;
495 unsigned buf_filled_size_offset
;
497 unsigned stride_in_dw
;
501 struct r600_streamout
{
502 struct r600_atom begin_atom
;
504 unsigned num_dw_for_end
;
506 unsigned enabled_mask
;
507 unsigned num_targets
;
508 struct r600_so_target
*targets
[PIPE_MAX_SO_BUFFERS
];
510 unsigned append_bitmask
;
515 struct radeon_winsys_cs
*cs
;
517 void (*flush
)(void *ctx
, unsigned flags
);
521 struct r600_ring gfx
;
522 struct r600_ring dma
;
525 struct r600_context
{
526 struct pipe_context context
;
527 struct r600_screen
*screen
;
528 struct radeon_winsys
*ws
;
529 struct r600_rings rings
;
530 struct blitter_context
*blitter
;
531 struct u_upload_mgr
*uploader
;
532 struct u_suballocator
*allocator_so_filled_size
;
533 struct u_suballocator
*allocator_fetch_shader
;
534 struct util_slab_mempool pool_transfers
;
537 enum radeon_family family
;
538 enum chip_class chip_class
;
539 boolean has_vertex_cache
;
540 boolean keep_tiling_flags
;
541 unsigned default_ps_gprs
, default_vs_gprs
;
542 unsigned r6xx_num_clause_temp_gprs
;
543 unsigned backend_mask
;
544 unsigned max_db
; /* for OQ */
546 /* current unaccounted memory usage */
550 /* Miscellaneous state objects. */
551 void *custom_dsa_flush
;
552 void *custom_blend_resolve
;
553 void *custom_blend_decompress
;
554 void *custom_blend_fmask_decompress
;
555 /* With rasterizer discard, there doesn't have to be a pixel shader.
556 * In that case, we bind this one: */
557 void *dummy_pixel_shader
;
558 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
559 * bug where valid CMASK and FMASK are required to be present to avoid
560 * a hardlock in certain operations but aren't actually used
561 * for anything useful. */
562 struct r600_resource
*dummy_fmask
;
563 struct r600_resource
*dummy_cmask
;
565 /* State binding slots are here. */
566 struct r600_atom
*atoms
[R600_NUM_ATOMS
];
567 /* States for CS initialization. */
568 struct r600_command_buffer start_cs_cmd
; /* invariant state mostly */
569 /** Compute specific registers initializations. The start_cs_cmd atom
570 * must be emitted before start_compute_cs_cmd. */
571 struct r600_command_buffer start_compute_cs_cmd
;
572 /* Register states. */
573 struct r600_alphatest_state alphatest_state
;
574 struct r600_cso_state blend_state
;
575 struct r600_blend_color blend_color
;
576 struct r600_cb_misc_state cb_misc_state
;
577 struct r600_clip_misc_state clip_misc_state
;
578 struct r600_clip_state clip_state
;
579 struct r600_db_misc_state db_misc_state
;
580 struct r600_db_state db_state
;
581 struct r600_cso_state dsa_state
;
582 struct r600_framebuffer framebuffer
;
583 struct r600_poly_offset_state poly_offset_state
;
584 struct r600_cso_state rasterizer_state
;
585 struct r600_sample_mask sample_mask
;
586 struct r600_scissor_state scissor
;
587 struct r600_seamless_cube_map seamless_cube_map
;
588 struct r600_config_state config_state
;
589 struct r600_stencil_ref_state stencil_ref
;
590 struct r600_vgt_state vgt_state
;
591 struct r600_viewport_state viewport
;
592 /* Shaders and shader resources. */
593 struct r600_cso_state vertex_fetch_shader
;
594 struct r600_shader_state vertex_shader
;
595 struct r600_shader_state pixel_shader
;
596 struct r600_cs_shader_state cs_shader_state
;
597 struct r600_constbuf_state constbuf_state
[PIPE_SHADER_TYPES
];
598 struct r600_textures_info samplers
[PIPE_SHADER_TYPES
];
599 /** Vertex buffers for fetch shaders */
600 struct r600_vertexbuf_state vertex_buffer_state
;
601 /** Vertex buffers for compute shaders */
602 struct r600_vertexbuf_state cs_vertex_buffer_state
;
603 struct r600_streamout streamout
;
605 /* Additional context states. */
607 unsigned compute_cb_target_mask
;
608 struct r600_pipe_shader_selector
*ps_shader
;
609 struct r600_pipe_shader_selector
*vs_shader
;
610 struct r600_rasterizer_state
*rasterizer
;
612 bool force_blend_disable
;
613 boolean dual_src_blend
;
617 struct pipe_index_buffer index_buffer
;
619 /* Last draw state (-1 = unset). */
620 int last_primitive_type
; /* Last primitive type used in draw_vbo. */
621 int last_start_instance
;
624 /* The list of active queries. Only one query of each type can be active. */
625 int num_occlusion_queries
;
626 /* Keep track of non-timer queries, because they should be suspended
627 * during context flushing.
628 * The timer queries (TIME_ELAPSED) shouldn't be suspended. */
629 struct list_head active_nontimer_queries
;
630 unsigned num_cs_dw_nontimer_queries_suspend
;
631 /* If queries have been suspended. */
632 bool nontimer_queries_suspended
;
633 unsigned num_draw_calls
;
635 /* Render condition. */
636 struct pipe_query
*current_render_cond
;
637 unsigned current_render_cond_mode
;
638 boolean predicate_drawing
;
640 struct r600_isa
*isa
;
643 static INLINE
void r600_emit_command_buffer(struct radeon_winsys_cs
*cs
,
644 struct r600_command_buffer
*cb
)
646 assert(cs
->cdw
+ cb
->num_dw
<= RADEON_MAX_CMDBUF_DWORDS
);
647 memcpy(cs
->buf
+ cs
->cdw
, cb
->buf
, 4 * cb
->num_dw
);
648 cs
->cdw
+= cb
->num_dw
;
652 void r600_trace_emit(struct r600_context
*rctx
);
655 static INLINE
void r600_emit_atom(struct r600_context
*rctx
, struct r600_atom
*atom
)
657 atom
->emit(rctx
, atom
);
660 if (rctx
->screen
->trace_bo
) {
661 r600_trace_emit(rctx
);
666 static INLINE
void r600_set_cso_state(struct r600_cso_state
*state
, void *cso
)
669 state
->atom
.dirty
= cso
!= NULL
;
672 static INLINE
void r600_set_cso_state_with_cb(struct r600_cso_state
*state
, void *cso
,
673 struct r600_command_buffer
*cb
)
676 state
->atom
.num_dw
= cb
->num_dw
;
677 r600_set_cso_state(state
, cso
);
680 /* compute_memory_pool.c */
681 struct compute_memory_pool
;
682 void compute_memory_pool_delete(struct compute_memory_pool
* pool
);
683 struct compute_memory_pool
* compute_memory_pool_new(
684 struct r600_screen
*rscreen
);
686 /* evergreen_state.c */
687 struct pipe_sampler_view
*
688 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
689 struct pipe_resource
*texture
,
690 const struct pipe_sampler_view
*state
,
691 unsigned width0
, unsigned height0
);
692 void evergreen_init_common_regs(struct r600_command_buffer
*cb
,
693 enum chip_class ctx_chip_class
,
694 enum radeon_family ctx_family
,
696 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
697 enum chip_class ctx_chip_class
,
698 enum radeon_family ctx_family
,
701 void evergreen_init_state_functions(struct r600_context
*rctx
);
702 void evergreen_init_atom_start_cs(struct r600_context
*rctx
);
703 void evergreen_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
704 void evergreen_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
705 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
);
706 void *evergreen_create_resolve_blend(struct r600_context
*rctx
);
707 void *evergreen_create_decompress_blend(struct r600_context
*rctx
);
708 void *evergreen_create_fmask_decompress_blend(struct r600_context
*rctx
);
709 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
710 enum pipe_format format
,
711 enum pipe_texture_target target
,
712 unsigned sample_count
,
714 void evergreen_init_color_surface(struct r600_context
*rctx
,
715 struct r600_surface
*surf
);
716 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
717 struct r600_surface
*surf
);
718 void evergreen_update_db_shader_control(struct r600_context
* rctx
);
721 void r600_copy_buffer(struct pipe_context
*ctx
, struct pipe_resource
*dst
, unsigned dstx
,
722 struct pipe_resource
*src
, const struct pipe_box
*src_box
);
723 void r600_init_blit_functions(struct r600_context
*rctx
);
724 void r600_blit_decompress_depth(struct pipe_context
*ctx
,
725 struct r600_texture
*texture
,
726 struct r600_texture
*staging
,
727 unsigned first_level
, unsigned last_level
,
728 unsigned first_layer
, unsigned last_layer
,
729 unsigned first_sample
, unsigned last_sample
);
730 void r600_decompress_depth_textures(struct r600_context
*rctx
,
731 struct r600_samplerview_state
*textures
);
732 void r600_decompress_color_textures(struct r600_context
*rctx
,
733 struct r600_samplerview_state
*textures
);
736 bool r600_init_resource(struct r600_screen
*rscreen
,
737 struct r600_resource
*res
,
738 unsigned size
, unsigned alignment
,
739 bool use_reusable_pool
, unsigned usage
);
740 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
741 const struct pipe_resource
*templ
,
745 boolean
r600_rings_is_buffer_referenced(struct r600_context
*ctx
,
746 struct radeon_winsys_cs_handle
*buf
,
747 enum radeon_bo_usage usage
);
748 void *r600_buffer_mmap_sync_with_rings(struct r600_context
*ctx
,
749 struct r600_resource
*resource
,
751 const char * r600_llvm_gpu_string(enum radeon_family family
);
755 void r600_init_query_functions(struct r600_context
*rctx
);
756 void r600_suspend_nontimer_queries(struct r600_context
*ctx
);
757 void r600_resume_nontimer_queries(struct r600_context
*ctx
);
759 /* r600_resource.c */
760 void r600_init_context_resource_functions(struct r600_context
*r600
);
763 int r600_pipe_shader_create(struct pipe_context
*ctx
,
764 struct r600_pipe_shader
*shader
,
765 struct r600_shader_key key
);
767 int r600_compute_shader_create(struct pipe_context
* ctx
,
768 LLVMModuleRef mod
, struct r600_bytecode
* bytecode
);
770 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
773 struct pipe_sampler_view
*
774 r600_create_sampler_view_custom(struct pipe_context
*ctx
,
775 struct pipe_resource
*texture
,
776 const struct pipe_sampler_view
*state
,
777 unsigned width_first_level
, unsigned height_first_level
);
778 void r600_init_state_functions(struct r600_context
*rctx
);
779 void r600_init_atom_start_cs(struct r600_context
*rctx
);
780 void r600_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
781 void r600_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
782 void *r600_create_db_flush_dsa(struct r600_context
*rctx
);
783 void *r600_create_resolve_blend(struct r600_context
*rctx
);
784 void *r700_create_resolve_blend(struct r600_context
*rctx
);
785 void *r600_create_decompress_blend(struct r600_context
*rctx
);
786 bool r600_adjust_gprs(struct r600_context
*rctx
);
787 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
788 enum pipe_format format
,
789 enum pipe_texture_target target
,
790 unsigned sample_count
,
792 void r600_update_db_shader_control(struct r600_context
* rctx
);
795 void r600_init_screen_texture_functions(struct pipe_screen
*screen
);
796 void r600_init_surface_functions(struct r600_context
*r600
);
797 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
798 const unsigned char *swizzle_view
,
799 uint32_t *word4_p
, uint32_t *yuv_format_p
);
800 unsigned r600_texture_get_offset(struct r600_texture
*rtex
,
801 unsigned level
, unsigned layer
);
802 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
803 struct pipe_resource
*texture
,
804 const struct pipe_surface
*templ
,
805 unsigned width
, unsigned height
);
807 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
808 const unsigned char *swizzle_view
,
811 /* r600_hw_context.c */
812 void r600_get_backend_mask(struct r600_context
*ctx
);
813 void r600_context_flush(struct r600_context
*ctx
, unsigned flags
);
814 void r600_begin_new_cs(struct r600_context
*ctx
);
815 void r600_context_emit_fence(struct r600_context
*ctx
, struct r600_resource
*fence
,
816 unsigned offset
, unsigned value
);
817 void r600_flush_emit(struct r600_context
*ctx
);
818 void r600_need_cs_space(struct r600_context
*ctx
, unsigned num_dw
, boolean count_draw_in
);
819 void r600_need_dma_space(struct r600_context
*ctx
, unsigned num_dw
);
820 void r600_cp_dma_copy_buffer(struct r600_context
*rctx
,
821 struct pipe_resource
*dst
, uint64_t dst_offset
,
822 struct pipe_resource
*src
, uint64_t src_offset
,
824 void r600_dma_copy(struct r600_context
*rctx
,
825 struct pipe_resource
*dst
,
826 struct pipe_resource
*src
,
830 boolean
r600_dma_blit(struct pipe_context
*ctx
,
831 struct pipe_resource
*dst
,
833 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
834 struct pipe_resource
*src
,
836 const struct pipe_box
*src_box
);
837 void r600_emit_streamout_begin(struct r600_context
*ctx
, struct r600_atom
*atom
);
838 void r600_emit_streamout_end(struct r600_context
*ctx
);
841 * evergreen_hw_context.c
843 void evergreen_flush_vgt_streamout(struct r600_context
*ctx
);
844 void evergreen_set_streamout_enable(struct r600_context
*ctx
, unsigned buffer_enable_bit
);
845 void evergreen_dma_copy(struct r600_context
*rctx
,
846 struct pipe_resource
*dst
,
847 struct pipe_resource
*src
,
851 boolean
evergreen_dma_blit(struct pipe_context
*ctx
,
852 struct pipe_resource
*dst
,
854 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
855 struct pipe_resource
*src
,
857 const struct pipe_box
*src_box
);
859 /* r600_state_common.c */
860 void r600_init_common_state_functions(struct r600_context
*rctx
);
861 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
862 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
863 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
);
864 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
865 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
866 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
);
867 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
868 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
);
869 void r600_init_atom(struct r600_context
*rctx
, struct r600_atom
*atom
, unsigned id
,
870 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
872 void r600_vertex_buffers_dirty(struct r600_context
*rctx
);
873 void r600_sampler_views_dirty(struct r600_context
*rctx
,
874 struct r600_samplerview_state
*state
);
875 void r600_sampler_states_dirty(struct r600_context
*rctx
,
876 struct r600_sampler_states
*state
);
877 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
);
878 void r600_streamout_buffers_dirty(struct r600_context
*rctx
);
879 void r600_draw_rectangle(struct blitter_context
*blitter
,
880 int x1
, int y1
, int x2
, int y2
, float depth
,
881 enum blitter_attrib_type type
, const union pipe_color_union
*attrib
);
882 uint32_t r600_translate_stencil_op(int s_op
);
883 uint32_t r600_translate_fill(uint32_t func
);
884 unsigned r600_tex_wrap(unsigned wrap
);
885 unsigned r600_tex_filter(unsigned filter
);
886 unsigned r600_tex_mipfilter(unsigned filter
);
887 unsigned r600_tex_compare(unsigned compare
);
888 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
);
891 struct pipe_video_decoder
*r600_uvd_create_decoder(struct pipe_context
*context
,
892 enum pipe_video_profile profile
,
893 enum pipe_video_entrypoint entrypoint
,
894 enum pipe_video_chroma_format chroma_format
,
895 unsigned width
, unsigned height
,
896 unsigned max_references
, bool expect_chunked_decode
);
898 struct pipe_video_buffer
*r600_video_buffer_create(struct pipe_context
*pipe
,
899 const struct pipe_video_buffer
*tmpl
);
903 * Helpers for building command buffers
906 #define PKT3_SET_CONFIG_REG 0x68
907 #define PKT3_SET_CONTEXT_REG 0x69
908 #define PKT3_SET_CTL_CONST 0x6F
909 #define PKT3_SET_LOOP_CONST 0x6C
911 #define R600_CONFIG_REG_OFFSET 0x08000
912 #define R600_CONTEXT_REG_OFFSET 0x28000
913 #define R600_CTL_CONST_OFFSET 0x3CFF0
914 #define R600_LOOP_CONST_OFFSET 0X0003E200
915 #define EG_LOOP_CONST_OFFSET 0x0003A200
917 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
918 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
919 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
920 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
921 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
923 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
925 /*Evergreen Compute packet3*/
926 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
928 static INLINE
void r600_store_value(struct r600_command_buffer
*cb
, unsigned value
)
930 cb
->buf
[cb
->num_dw
++] = value
;
933 static INLINE
void r600_store_array(struct r600_command_buffer
*cb
, unsigned num
, unsigned *ptr
)
935 assert(cb
->num_dw
+num
<= cb
->max_num_dw
);
936 memcpy(&cb
->buf
[cb
->num_dw
], ptr
, num
* sizeof(ptr
[0]));
940 static INLINE
void r600_store_config_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
942 assert(reg
< R600_CONTEXT_REG_OFFSET
);
943 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
944 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
945 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
949 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
952 static INLINE
void r600_store_context_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
954 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
955 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
956 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0) | cb
->pkt_flags
;
957 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
961 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
964 static INLINE
void r600_store_ctl_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
966 assert(reg
>= R600_CTL_CONST_OFFSET
);
967 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
968 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0) | cb
->pkt_flags
;
969 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
972 static INLINE
void r600_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
974 assert(reg
>= R600_LOOP_CONST_OFFSET
);
975 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
976 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
977 cb
->buf
[cb
->num_dw
++] = (reg
- R600_LOOP_CONST_OFFSET
) >> 2;
981 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
984 static INLINE
void eg_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
986 assert(reg
>= EG_LOOP_CONST_OFFSET
);
987 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
988 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0) | cb
->pkt_flags
;
989 cb
->buf
[cb
->num_dw
++] = (reg
- EG_LOOP_CONST_OFFSET
) >> 2;
992 static INLINE
void r600_store_config_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
994 r600_store_config_reg_seq(cb
, reg
, 1);
995 r600_store_value(cb
, value
);
998 static INLINE
void r600_store_context_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
1000 r600_store_context_reg_seq(cb
, reg
, 1);
1001 r600_store_value(cb
, value
);
1004 static INLINE
void r600_store_ctl_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
1006 r600_store_ctl_const_seq(cb
, reg
, 1);
1007 r600_store_value(cb
, value
);
1010 static INLINE
void r600_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
1012 r600_store_loop_const_seq(cb
, reg
, 1);
1013 r600_store_value(cb
, value
);
1016 static INLINE
void eg_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
1018 eg_store_loop_const_seq(cb
, reg
, 1);
1019 r600_store_value(cb
, value
);
1022 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
);
1023 void r600_release_command_buffer(struct r600_command_buffer
*cb
);
1026 * Helpers for emitting state into a command stream directly.
1028 static INLINE
unsigned r600_context_bo_reloc(struct r600_context
*ctx
,
1029 struct r600_ring
*ring
,
1030 struct r600_resource
*rbo
,
1031 enum radeon_bo_usage usage
)
1034 /* make sure that all previous ring use are flushed so everything
1035 * look serialized from driver pov
1037 if (!ring
->flushing
) {
1038 if (ring
== &ctx
->rings
.gfx
) {
1039 if (ctx
->rings
.dma
.cs
) {
1040 /* flush dma ring */
1041 ctx
->rings
.dma
.flush(ctx
, RADEON_FLUSH_ASYNC
);
1044 /* flush gfx ring */
1045 ctx
->rings
.gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
);
1048 return ctx
->ws
->cs_add_reloc(ring
->cs
, rbo
->cs_buf
, usage
, rbo
->domains
) * 4;
1051 static INLINE
void r600_write_value(struct radeon_winsys_cs
*cs
, unsigned value
)
1053 cs
->buf
[cs
->cdw
++] = value
;
1056 static INLINE
void r600_write_array(struct radeon_winsys_cs
*cs
, unsigned num
, unsigned *ptr
)
1058 assert(cs
->cdw
+num
<= RADEON_MAX_CMDBUF_DWORDS
);
1059 memcpy(&cs
->buf
[cs
->cdw
], ptr
, num
* sizeof(ptr
[0]));
1063 static INLINE
void r600_write_config_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
1065 assert(reg
< R600_CONTEXT_REG_OFFSET
);
1066 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
1067 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
1068 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
1071 static INLINE
void r600_write_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
1073 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
1074 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
1075 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0);
1076 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
1079 static INLINE
void r600_write_compute_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
1081 r600_write_context_reg_seq(cs
, reg
, num
);
1082 /* Set the compute bit on the packet header */
1083 cs
->buf
[cs
->cdw
- 2] |= RADEON_CP_PACKET3_COMPUTE_MODE
;
1086 static INLINE
void r600_write_ctl_const_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
1088 assert(reg
>= R600_CTL_CONST_OFFSET
);
1089 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
1090 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
1091 cs
->buf
[cs
->cdw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
1094 static INLINE
void r600_write_config_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
1096 r600_write_config_reg_seq(cs
, reg
, 1);
1097 r600_write_value(cs
, value
);
1100 static INLINE
void r600_write_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
1102 r600_write_context_reg_seq(cs
, reg
, 1);
1103 r600_write_value(cs
, value
);
1106 static INLINE
void r600_write_compute_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
1108 r600_write_compute_context_reg_seq(cs
, reg
, 1);
1109 r600_write_value(cs
, value
);
1112 static INLINE
void r600_write_ctl_const(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
1114 r600_write_ctl_const_seq(cs
, reg
, 1);
1115 r600_write_value(cs
, value
);
1121 static INLINE
uint32_t S_FIXED(float value
, uint32_t frac_bits
)
1123 return value
* (1 << frac_bits
);
1125 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
1127 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
1129 if (filter
<= 1) return 0;
1130 if (filter
<= 2) return 1;
1131 if (filter
<= 4) return 2;
1132 if (filter
<= 8) return 3;
1133 /* else */ return 4;
1136 /* 12.4 fixed-point */
1137 static INLINE
unsigned r600_pack_float_12p4(float x
)
1140 x
>= 4096 ? 0xffff : x
* 16;
1143 static INLINE
uint64_t r600_resource_va(struct pipe_screen
*screen
, struct pipe_resource
*resource
)
1145 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
1146 struct r600_resource
*rresource
= (struct r600_resource
*)resource
;
1148 return rscreen
->ws
->buffer_get_virtual_address(rresource
->cs_buf
);
1151 static INLINE
void r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
)
1153 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1154 struct r600_resource
*rr
= (struct r600_resource
*)r
;
1161 * The idea is to compute a gross estimate of memory requirement of
1162 * each draw call. After each draw call, memory will be precisely
1163 * accounted. So the uncertainty is only on the current draw call.
1164 * In practice this gave very good estimate (+/- 10% of the target
1167 if (rr
->domains
& RADEON_DOMAIN_GTT
) {
1168 rctx
->gtt
+= rr
->buf
->size
;
1170 if (rr
->domains
& RADEON_DOMAIN_VRAM
) {
1171 rctx
->vram
+= rr
->buf
->size
;