projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: add a debug flag for printing virtual addresses of resources
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_formats.h"
28 #include "evergreen_compute.h"
29 #include "r600d.h"
30
31 #include <errno.h>
32 #include "util/u_format_s3tc.h"
33 #include "util/u_memory.h"
34
35
36 /* Copy from a full GPU texture to a transfer's staging one. */
37 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
38 {
39 struct r600_context *rctx = (struct r600_context*)ctx;
40 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
41 struct pipe_resource *dst = &rtransfer->staging->b.b;
42 struct pipe_resource *src = transfer->resource;
43
44 if (src->nr_samples <= 1) {
45 if (!rctx->screen->dma_blit(ctx, dst, 0, 0, 0, 0,
46 src, transfer->level,
47 &transfer->box)) {
48 /* async dma could not be use */
49 ctx->resource_copy_region(ctx, dst, 0, 0, 0, 0,
50 src, transfer->level, &transfer->box);
51 }
52 } else {
53 /* Resolve the resource. */
54 struct pipe_blit_info blit;
55
56 memset(&blit, 0, sizeof(blit));
57 blit.src.resource = src;
58 blit.src.format = src->format;
59 blit.src.level = transfer->level;
60 blit.src.box = transfer->box;
61 blit.dst.resource = dst;
62 blit.dst.format = dst->format;
63 blit.dst.box.width = transfer->box.width;
64 blit.dst.box.height = transfer->box.height;
65 blit.dst.box.depth = transfer->box.depth;
66 blit.mask = PIPE_MASK_RGBA;
67 blit.filter = PIPE_TEX_FILTER_NEAREST;
68
69 ctx->blit(ctx, &blit);
70 }
71 }
72
73 /* Copy from a transfer's staging texture to a full GPU one. */
74 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
75 {
76 struct r600_context *rctx = (struct r600_context*)ctx;
77 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
78 struct pipe_resource *texture = transfer->resource;
79 struct pipe_box sbox;
80
81 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
82
83 if (!rctx->screen->dma_blit(ctx, texture, transfer->level,
84 transfer->box.x, transfer->box.y, transfer->box.z,
85 &rtransfer->staging->b.b, 0, &sbox)) {
86 /* async dma could not be use */
87 ctx->resource_copy_region(ctx, texture, transfer->level,
88 transfer->box.x, transfer->box.y, transfer->box.z,
89 &rtransfer->staging->b.b,
90 0, &sbox);
91 }
92 }
93
94 unsigned r600_texture_get_offset(struct r600_texture *rtex,
95 unsigned level, unsigned layer)
96 {
97 return rtex->surface.level[level].offset +
98 layer * rtex->surface.level[level].slice_size;
99 }
100
101 static int r600_init_surface(struct r600_screen *rscreen,
102 struct radeon_surface *surface,
103 const struct pipe_resource *ptex,
104 unsigned array_mode,
105 bool is_flushed_depth)
106 {
107 const struct util_format_description *desc =
108 util_format_description(ptex->format);
109 bool is_depth, is_stencil;
110
111 is_depth = util_format_has_depth(desc);
112 is_stencil = util_format_has_stencil(desc);
113
114 surface->npix_x = ptex->width0;
115 surface->npix_y = ptex->height0;
116 surface->npix_z = ptex->depth0;
117 surface->blk_w = util_format_get_blockwidth(ptex->format);
118 surface->blk_h = util_format_get_blockheight(ptex->format);
119 surface->blk_d = 1;
120 surface->array_size = 1;
121 surface->last_level = ptex->last_level;
122
123 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
124 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
125 surface->bpe = 4; /* stencil is allocated separately on evergreen */
126 } else {
127 surface->bpe = util_format_get_blocksize(ptex->format);
128 /* align byte per element on dword */
129 if (surface->bpe == 3) {
130 surface->bpe = 4;
131 }
132 }
133
134 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
135 surface->flags = 0;
136
137 switch (array_mode) {
138 case V_038000_ARRAY_1D_TILED_THIN1:
139 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
140 break;
141 case V_038000_ARRAY_2D_TILED_THIN1:
142 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
143 break;
144 case V_038000_ARRAY_LINEAR_ALIGNED:
145 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
146 break;
147 case V_038000_ARRAY_LINEAR_GENERAL:
148 default:
149 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
150 break;
151 }
152 switch (ptex->target) {
153 case PIPE_TEXTURE_1D:
154 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
155 break;
156 case PIPE_TEXTURE_RECT:
157 case PIPE_TEXTURE_2D:
158 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
159 break;
160 case PIPE_TEXTURE_3D:
161 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
162 break;
163 case PIPE_TEXTURE_1D_ARRAY:
164 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
165 surface->array_size = ptex->array_size;
166 break;
167 case PIPE_TEXTURE_2D_ARRAY:
168 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d layout for now */
169 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
170 surface->array_size = ptex->array_size;
171 break;
172 case PIPE_TEXTURE_CUBE:
173 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
174 break;
175 case PIPE_BUFFER:
176 default:
177 return -EINVAL;
178 }
179 if (ptex->bind & PIPE_BIND_SCANOUT) {
180 surface->flags |= RADEON_SURF_SCANOUT;
181 }
182
183 if (!is_flushed_depth && is_depth) {
184 surface->flags |= RADEON_SURF_ZBUFFER;
185
186 if (is_stencil) {
187 surface->flags |= RADEON_SURF_SBUFFER |
188 RADEON_SURF_HAS_SBUFFER_MIPTREE;
189 }
190 }
191 return 0;
192 }
193
194 static int r600_setup_surface(struct pipe_screen *screen,
195 struct r600_texture *rtex,
196 unsigned pitch_in_bytes_override)
197 {
198 struct pipe_resource *ptex = &rtex->resource.b.b;
199 struct r600_screen *rscreen = (struct r600_screen*)screen;
200 unsigned i;
201 int r;
202
203 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
204 if (r) {
205 return r;
206 }
207 rtex->size = rtex->surface.bo_size;
208 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
209 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
210 * for those
211 */
212 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
213 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
214 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
215 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
216 rtex->surface.stencil_offset =
217 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
218 }
219 }
220 for (i = 0; i <= ptex->last_level; i++) {
221 switch (rtex->surface.level[i].mode) {
222 case RADEON_SURF_MODE_LINEAR_ALIGNED:
223 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
224 break;
225 case RADEON_SURF_MODE_1D:
226 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
227 break;
228 case RADEON_SURF_MODE_2D:
229 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
230 break;
231 default:
232 case RADEON_SURF_MODE_LINEAR:
233 rtex->array_mode[i] = 0;
234 break;
235 }
236 }
237 return 0;
238 }
239
240 static boolean r600_texture_get_handle(struct pipe_screen* screen,
241 struct pipe_resource *ptex,
242 struct winsys_handle *whandle)
243 {
244 struct r600_texture *rtex = (struct r600_texture*)ptex;
245 struct r600_resource *resource = &rtex->resource;
246 struct radeon_surface *surface = &rtex->surface;
247 struct r600_screen *rscreen = (struct r600_screen*)screen;
248
249 rscreen->ws->buffer_set_tiling(resource->buf,
250 NULL,
251 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
252 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
253 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
254 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
255 surface->bankw, surface->bankh,
256 surface->tile_split,
257 surface->stencil_tile_split,
258 surface->mtilea,
259 rtex->surface.level[0].pitch_bytes);
260
261 return rscreen->ws->buffer_get_handle(resource->buf,
262 rtex->surface.level[0].pitch_bytes, whandle);
263 }
264
265 static void r600_texture_destroy(struct pipe_screen *screen,
266 struct pipe_resource *ptex)
267 {
268 struct r600_texture *rtex = (struct r600_texture*)ptex;
269 struct r600_resource *resource = &rtex->resource;
270
271 if (rtex->flushed_depth_texture)
272 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
273
274 pipe_resource_reference((struct pipe_resource**)&rtex->htile, NULL);
275 pb_reference(&resource->buf, NULL);
276 FREE(rtex);
277 }
278
279 static const struct u_resource_vtbl r600_texture_vtbl;
280
281 /* The number of samples can be specified independently of the texture. */
282 void r600_texture_get_fmask_info(struct r600_screen *rscreen,
283 struct r600_texture *rtex,
284 unsigned nr_samples,
285 struct r600_fmask_info *out)
286 {
287 /* FMASK is allocated pretty much like an ordinary texture.
288 * Here we use bpe in the units of bits, not bytes. */
289 struct radeon_surface fmask = rtex->surface;
290
291 switch (nr_samples) {
292 case 2:
293 /* This should be 8,1, but we should set nsamples > 1
294 * for the allocator to treat it as a multisample surface.
295 * Let's set 4,2 then. */
296 case 4:
297 fmask.bpe = 4;
298 fmask.nsamples = 2;
299 break;
300 case 8:
301 fmask.bpe = 8;
302 fmask.nsamples = 4;
303 break;
304 case 16:
305 fmask.bpe = 16;
306 fmask.nsamples = 4;
307 break;
308 default:
309 R600_ERR("Invalid sample count for FMASK allocation.\n");
310 return;
311 }
312
313 /* R600-R700 errata? Anyway, this fixes colorbuffer corruption. */
314 if (rscreen->chip_class <= R700) {
315 fmask.bpe *= 2;
316 }
317
318 if (rscreen->chip_class >= EVERGREEN) {
319 fmask.bankh = nr_samples <= 4 ? 4 : 1;
320 }
321
322 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
323 R600_ERR("Got error in surface_init while allocating FMASK.\n");
324 return;
325 }
326 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
327
328 out->bank_height = fmask.bankh;
329 out->alignment = MAX2(256, fmask.bo_alignment);
330 out->size = (fmask.bo_size + 7) / 8;
331 }
332
333 static void r600_texture_allocate_fmask(struct r600_screen *rscreen,
334 struct r600_texture *rtex)
335 {
336 struct r600_fmask_info fmask;
337
338 r600_texture_get_fmask_info(rscreen, rtex,
339 rtex->resource.b.b.nr_samples, &fmask);
340
341 rtex->fmask_bank_height = fmask.bank_height;
342 rtex->fmask_offset = align(rtex->size, fmask.alignment);
343 rtex->fmask_size = fmask.size;
344 rtex->size = rtex->fmask_offset + rtex->fmask_size;
345 #if 0
346 printf("FMASK width=%u, height=%i, bits=%u, size=%u\n",
347 fmask.npix_x, fmask.npix_y, fmask.bpe * fmask.nsamples, rtex->fmask_size);
348 #endif
349 }
350
351 void r600_texture_get_cmask_info(struct r600_screen *rscreen,
352 struct r600_texture *rtex,
353 struct r600_cmask_info *out)
354 {
355 unsigned cmask_tile_width = 8;
356 unsigned cmask_tile_height = 8;
357 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
358 unsigned element_bits = 4;
359 unsigned cmask_cache_bits = 1024;
360 unsigned num_pipes = rscreen->tiling_info.num_channels;
361 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
362
363 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
364 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
365 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
366 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
367 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
368
369 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
370 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
371
372 unsigned base_align = num_pipes * pipe_interleave_bytes;
373 unsigned slice_bytes =
374 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
375
376 assert(macro_tile_width % 128 == 0);
377 assert(macro_tile_height % 128 == 0);
378
379 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
380 out->alignment = MAX2(256, base_align);
381 out->size = rtex->surface.array_size * align(slice_bytes, base_align);
382 }
383
384 static void r600_texture_allocate_cmask(struct r600_screen *rscreen,
385 struct r600_texture *rtex)
386 {
387 struct r600_cmask_info cmask;
388
389 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
390
391 rtex->cmask_slice_tile_max = cmask.slice_tile_max;
392 rtex->cmask_offset = align(rtex->size, cmask.alignment);
393 rtex->cmask_size = cmask.size;
394 rtex->size = rtex->cmask_offset + rtex->cmask_size;
395 #if 0
396 printf("CMASK: macro tile width = %u, macro tile height = %u, "
397 "pitch elements = %u, height = %u, slice tile max = %u\n",
398 macro_tile_width, macro_tile_height, pitch_elements, height,
399 rtex->cmask_slice_tile_max);
400 #endif
401 }
402
403 static struct r600_texture *
404 r600_texture_create_object(struct pipe_screen *screen,
405 const struct pipe_resource *base,
406 unsigned pitch_in_bytes_override,
407 struct pb_buffer *buf,
408 struct radeon_surface *surface)
409 {
410 struct r600_texture *rtex;
411 struct r600_resource *resource;
412 struct r600_screen *rscreen = (struct r600_screen*)screen;
413 int r;
414
415 rtex = CALLOC_STRUCT(r600_texture);
416 if (rtex == NULL)
417 return NULL;
418
419 resource = &rtex->resource;
420 resource->b.b = *base;
421 resource->b.vtbl = &r600_texture_vtbl;
422 pipe_reference_init(&resource->b.b.reference, 1);
423 resource->b.b.screen = screen;
424 rtex->pitch_override = pitch_in_bytes_override;
425
426 /* don't include stencil-only formats which we don't support for rendering */
427 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
428
429 rtex->surface = *surface;
430 r = r600_setup_surface(screen, rtex,
431 pitch_in_bytes_override);
432 if (r) {
433 FREE(rtex);
434 return NULL;
435 }
436
437 if (base->nr_samples > 1 && !rtex->is_depth && !buf) {
438 r600_texture_allocate_fmask(rscreen, rtex);
439 r600_texture_allocate_cmask(rscreen, rtex);
440 }
441
442 if (!rtex->is_depth && base->nr_samples > 1 &&
443 (!rtex->fmask_size || !rtex->cmask_size)) {
444 FREE(rtex);
445 return NULL;
446 }
447
448 /* Tiled depth textures utilize the non-displayable tile order. */
449 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
450
451 /* only enable hyperz for PIPE_TEXTURE_2D not for PIPE_TEXTURE_2D_ARRAY
452 * Thought it might still be interessting to use hyperz for texture
453 * array without using fast clear features
454 */
455 rtex->htile = NULL;
456 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER | R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
457 util_format_is_depth_or_stencil(base->format) &&
458 rscreen->info.drm_minor >= 26 &&
459 !(rscreen->debug_flags & DBG_NO_HYPERZ) &&
460 base->target == PIPE_TEXTURE_2D &&
461 rtex->surface.level[0].nblk_x >= 32 &&
462 rtex->surface.level[0].nblk_y >= 32) {
463 unsigned sw = rtex->surface.level[0].nblk_x * rtex->surface.blk_w;
464 unsigned sh = rtex->surface.level[0].nblk_y * rtex->surface.blk_h;
465 unsigned htile_size;
466 unsigned npipes = rscreen->info.r600_num_tile_pipes;
467
468 /* this alignment and htile size only apply to linear htile buffer */
469 sw = align(sw, 16 << 3);
470 sh = align(sh, npipes << 3);
471 htile_size = (sw >> 3) * (sh >> 3) * 4;
472 /* must be aligned with 2K * npipes */
473 htile_size = align(htile_size, (2 << 10) * npipes);
474
475 rtex->htile = (struct r600_resource*)pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
476 PIPE_USAGE_STATIC, htile_size);
477 if (rtex->htile == NULL) {
478 /* this is not a fatal error as we can still keep rendering
479 * without htile buffer
480 */
481 R600_ERR("r600: failed to create bo for htile buffers\n");
482 } else {
483 void *ptr;
484 ptr = rscreen->ws->buffer_map(rtex->htile->cs_buf, NULL, PIPE_TRANSFER_WRITE);
485 memset(ptr, 0x0, htile_size);
486 rscreen->ws->buffer_unmap(rtex->htile->cs_buf);
487 }
488 }
489
490 /* Now create the backing buffer. */
491 if (!buf) {
492 unsigned base_align = rtex->surface.bo_alignment;
493 unsigned usage = R600_TEX_IS_TILED(rtex, 0) ? PIPE_USAGE_STATIC : base->usage;
494
495 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, FALSE, usage)) {
496 FREE(rtex);
497 return NULL;
498 }
499 } else {
500 /* This is usually the window framebuffer. We want it in VRAM, always. */
501 resource->buf = buf;
502 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
503 resource->domains = RADEON_DOMAIN_VRAM;
504 }
505
506 if (rtex->cmask_size) {
507 /* Initialize the cmask to 0xCC (= compressed state). */
508 char *ptr = rscreen->ws->buffer_map(resource->cs_buf, NULL, PIPE_TRANSFER_WRITE);
509 memset(ptr + rtex->cmask_offset, 0xCC, rtex->cmask_size);
510 rscreen->ws->buffer_unmap(resource->cs_buf);
511 }
512
513 if (rscreen->debug_flags & DBG_VM) {
514 fprintf(stderr, "VM start=0x%llX end=0x%llX | Texture %ix%ix%i, %i levels, %i samples, %s\n",
515 r600_resource_va(screen, &rtex->resource.b.b),
516 r600_resource_va(screen, &rtex->resource.b.b) + rtex->resource.buf->size,
517 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
518 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
519 }
520
521 if (rscreen->debug_flags & DBG_TEX_DEPTH && rtex->is_depth && rtex->non_disp_tiling) {
522 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
523 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
524 "bpe=%u, nsamples=%u, flags=%u\n",
525 rtex->surface.npix_x, rtex->surface.npix_y,
526 rtex->surface.npix_z, rtex->surface.blk_w,
527 rtex->surface.blk_h, rtex->surface.blk_d,
528 rtex->surface.array_size, rtex->surface.last_level,
529 rtex->surface.bpe, rtex->surface.nsamples,
530 rtex->surface.flags);
531 if (rtex->surface.flags & RADEON_SURF_ZBUFFER) {
532 for (int i = 0; i <= rtex->surface.last_level; i++) {
533 printf(" Z %i: offset=%llu, slice_size=%llu, npix_x=%u, "
534 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
535 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
536 i, (unsigned long long)rtex->surface.level[i].offset,
537 (unsigned long long)rtex->surface.level[i].slice_size,
538 u_minify(rtex->resource.b.b.width0, i),
539 u_minify(rtex->resource.b.b.height0, i),
540 u_minify(rtex->resource.b.b.depth0, i),
541 rtex->surface.level[i].nblk_x,
542 rtex->surface.level[i].nblk_y,
543 rtex->surface.level[i].nblk_z,
544 rtex->surface.level[i].pitch_bytes,
545 rtex->surface.level[i].mode);
546 }
547 }
548 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
549 for (int i = 0; i <= rtex->surface.last_level; i++) {
550 printf(" S %i: offset=%llu, slice_size=%llu, npix_x=%u, "
551 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
552 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
553 i, (unsigned long long)rtex->surface.stencil_level[i].offset,
554 (unsigned long long)rtex->surface.stencil_level[i].slice_size,
555 u_minify(rtex->resource.b.b.width0, i),
556 u_minify(rtex->resource.b.b.height0, i),
557 u_minify(rtex->resource.b.b.depth0, i),
558 rtex->surface.stencil_level[i].nblk_x,
559 rtex->surface.stencil_level[i].nblk_y,
560 rtex->surface.stencil_level[i].nblk_z,
561 rtex->surface.stencil_level[i].pitch_bytes,
562 rtex->surface.stencil_level[i].mode);
563 }
564 }
565 }
566 return rtex;
567 }
568
569 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
570 const struct pipe_resource *templ)
571 {
572 struct r600_screen *rscreen = (struct r600_screen*)screen;
573 struct radeon_surface surface;
574 const struct util_format_description *desc = util_format_description(templ->format);
575 unsigned array_mode;
576 int r;
577
578 /* Default tiling mode for staging textures. */
579 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
580
581 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. That's not an issue,
582 * because 422 formats are used for videos, which prefer linear buffers
583 * for fast uploads anyway. */
584 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
585 desc->layout != UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
586 if (templ->flags & R600_RESOURCE_FLAG_FORCE_TILING) {
587 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
588 } else if (!(templ->bind & PIPE_BIND_SCANOUT) &&
589 templ->usage != PIPE_USAGE_STAGING &&
590 templ->usage != PIPE_USAGE_STREAM &&
591 templ->target != PIPE_TEXTURE_1D &&
592 templ->target != PIPE_TEXTURE_1D_ARRAY &&
593 templ->height0 > 3) {
594 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
595 } else if (util_format_is_compressed(templ->format)) {
596 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
597 }
598 }
599
600 r = r600_init_surface(rscreen, &surface, templ, array_mode,
601 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
602 if (r) {
603 return NULL;
604 }
605 r = rscreen->ws->surface_best(rscreen->ws, &surface);
606 if (r) {
607 return NULL;
608 }
609 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
610 0, NULL, &surface);
611 }
612
613 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
614 struct pipe_resource *texture,
615 const struct pipe_surface *templ,
616 unsigned width, unsigned height)
617 {
618 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
619
620 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
621 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
622 assert(templ->u.tex.first_layer == templ->u.tex.last_layer);
623 if (surface == NULL)
624 return NULL;
625 pipe_reference_init(&surface->base.reference, 1);
626 pipe_resource_reference(&surface->base.texture, texture);
627 surface->base.context = pipe;
628 surface->base.format = templ->format;
629 surface->base.width = width;
630 surface->base.height = height;
631 surface->base.u = templ->u;
632 return &surface->base;
633 }
634
635 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
636 struct pipe_resource *tex,
637 const struct pipe_surface *templ)
638 {
639 unsigned level = templ->u.tex.level;
640
641 return r600_create_surface_custom(pipe, tex, templ,
642 u_minify(tex->width0, level),
643 u_minify(tex->height0, level));
644 }
645
646 static void r600_surface_destroy(struct pipe_context *pipe,
647 struct pipe_surface *surface)
648 {
649 struct r600_surface *surf = (struct r600_surface*)surface;
650 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
651 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
652 pipe_resource_reference(&surface->texture, NULL);
653 FREE(surface);
654 }
655
656 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
657 const struct pipe_resource *templ,
658 struct winsys_handle *whandle)
659 {
660 struct r600_screen *rscreen = (struct r600_screen*)screen;
661 struct pb_buffer *buf = NULL;
662 unsigned stride = 0;
663 unsigned array_mode = 0;
664 enum radeon_bo_layout micro, macro;
665 struct radeon_surface surface;
666 int r;
667
668 /* Support only 2D textures without mipmaps */
669 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
670 templ->depth0 != 1 || templ->last_level != 0)
671 return NULL;
672
673 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
674 if (!buf)
675 return NULL;
676
677 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
678 &surface.bankw, &surface.bankh,
679 &surface.tile_split,
680 &surface.stencil_tile_split,
681 &surface.mtilea);
682
683 if (macro == RADEON_LAYOUT_TILED)
684 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
685 else if (micro == RADEON_LAYOUT_TILED)
686 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
687 else
688 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
689
690 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
691 if (r) {
692 return NULL;
693 }
694 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
695 stride, buf, &surface);
696 }
697
698 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
699 struct pipe_resource *texture,
700 struct r600_texture **staging)
701 {
702 struct r600_texture *rtex = (struct r600_texture*)texture;
703 struct pipe_resource resource;
704 struct r600_texture **flushed_depth_texture = staging ?
705 staging : &rtex->flushed_depth_texture;
706
707 if (!staging && rtex->flushed_depth_texture)
708 return true; /* it's ready */
709
710 resource.target = texture->target;
711 resource.format = texture->format;
712 resource.width0 = texture->width0;
713 resource.height0 = texture->height0;
714 resource.depth0 = texture->depth0;
715 resource.array_size = texture->array_size;
716 resource.last_level = texture->last_level;
717 resource.nr_samples = texture->nr_samples;
718 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC;
719 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
720 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
721
722 if (staging)
723 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
724
725 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
726 if (*flushed_depth_texture == NULL) {
727 R600_ERR("failed to create temporary texture to hold flushed depth\n");
728 return false;
729 }
730
731 (*flushed_depth_texture)->is_flushing_texture = TRUE;
732 (*flushed_depth_texture)->non_disp_tiling = false;
733 return true;
734 }
735
736 static void *r600_texture_transfer_map(struct pipe_context *ctx,
737 struct pipe_resource *texture,
738 unsigned level,
739 unsigned usage,
740 const struct pipe_box *box,
741 struct pipe_transfer **ptransfer)
742 {
743 struct r600_context *rctx = (struct r600_context*)ctx;
744 struct r600_texture *rtex = (struct r600_texture*)texture;
745 struct r600_transfer *trans;
746 boolean use_staging_texture = FALSE;
747 enum pipe_format format = texture->format;
748 struct r600_resource *buf;
749 unsigned offset = 0;
750 char *map;
751
752 if ((texture->bind & PIPE_BIND_GLOBAL) && texture->target == PIPE_BUFFER) {
753 return r600_compute_global_transfer_map(ctx, texture, level, usage, box, ptransfer);
754 }
755
756 /* We cannot map a tiled texture directly because the data is
757 * in a different order, therefore we do detiling using a blit.
758 *
759 * Also, use a temporary in GTT memory for read transfers, as
760 * the CPU is much happier reading out of cached system memory
761 * than uncached VRAM.
762 */
763 if (R600_TEX_IS_TILED(rtex, level)) {
764 use_staging_texture = TRUE;
765 }
766
767 /* Use a staging texture for uploads if the underlying BO is busy. */
768 if (!(usage & PIPE_TRANSFER_READ) &&
769 (r600_rings_is_buffer_referenced(rctx, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
770 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
771 use_staging_texture = TRUE;
772 }
773
774 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
775 use_staging_texture = FALSE;
776 }
777
778 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
779 return NULL;
780 }
781
782 trans = CALLOC_STRUCT(r600_transfer);
783 if (trans == NULL)
784 return NULL;
785 trans->transfer.resource = texture;
786 trans->transfer.level = level;
787 trans->transfer.usage = usage;
788 trans->transfer.box = *box;
789 if (rtex->is_depth) {
790 /* XXX: only readback the rectangle which is being mapped?
791 */
792 /* XXX: when discard is true, no need to read back from depth texture
793 */
794 struct r600_texture *staging_depth;
795
796 assert(rtex->resource.b.b.nr_samples <= 1);
797 if (rtex->resource.b.b.nr_samples > 1) {
798 R600_ERR("mapping MSAA zbuffer unimplemented\n");
799 FREE(trans);
800 return NULL;
801 }
802
803 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
804 R600_ERR("failed to create temporary texture to hold untiled copy\n");
805 FREE(trans);
806 return NULL;
807 }
808
809 r600_blit_decompress_depth(ctx, rtex, staging_depth,
810 level, level,
811 box->z, box->z + box->depth - 1,
812 0, 0);
813
814 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
815 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
816 trans->offset = r600_texture_get_offset(staging_depth, level, box->z);
817 trans->staging = (struct r600_resource*)staging_depth;
818 } else if (use_staging_texture) {
819 struct pipe_resource resource;
820 struct r600_texture *staging;
821
822 memset(&resource, 0, sizeof(resource));
823 resource.format = texture->format;
824 resource.width0 = box->width;
825 resource.height0 = box->height;
826 resource.depth0 = 1;
827 resource.array_size = 1;
828 resource.usage = PIPE_USAGE_STAGING;
829 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
830
831 /* We must set the correct texture target and dimensions if needed for a 3D transfer. */
832 if (box->depth > 1 && util_max_layer(texture, level) > 0)
833 resource.target = texture->target;
834 else
835 resource.target = PIPE_TEXTURE_2D;
836
837 switch (resource.target) {
838 case PIPE_TEXTURE_1D_ARRAY:
839 case PIPE_TEXTURE_2D_ARRAY:
840 case PIPE_TEXTURE_CUBE_ARRAY:
841 resource.array_size = box->depth;
842 break;
843 case PIPE_TEXTURE_3D:
844 resource.depth0 = box->depth;
845 break;
846 default:;
847 }
848
849
850 /* Create the temporary texture. */
851 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
852 if (staging == NULL) {
853 R600_ERR("failed to create temporary texture to hold untiled copy\n");
854 FREE(trans);
855 return NULL;
856 }
857 trans->staging = &staging->resource;
858 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
859 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
860 if (usage & PIPE_TRANSFER_READ) {
861 r600_copy_to_staging_texture(ctx, trans);
862 /* flush gfx & dma ring, order does not matter as only one can be live */
863 if (rctx->rings.dma.cs) {
864 rctx->rings.dma.flush(rctx, 0);
865 }
866 rctx->rings.gfx.flush(rctx, 0);
867 }
868 } else {
869 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
870 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
871 trans->offset = r600_texture_get_offset(rtex, level, box->z);
872 }
873
874 if (trans->staging) {
875 buf = trans->staging;
876 } else {
877 buf = &rtex->resource;
878 }
879
880 if (rtex->is_depth || !trans->staging)
881 offset = trans->offset +
882 box->y / util_format_get_blockheight(format) * trans->transfer.stride +
883 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
884
885 if (!(map = r600_buffer_mmap_sync_with_rings(rctx, buf, usage))) {
886 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
887 FREE(trans);
888 return NULL;
889 }
890
891 *ptransfer = &trans->transfer;
892 return map + offset;
893 }
894
895 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
896 struct pipe_transfer* transfer)
897 {
898 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
899 struct r600_context *rctx = (struct r600_context*)ctx;
900 struct radeon_winsys_cs_handle *buf;
901 struct pipe_resource *texture = transfer->resource;
902 struct r600_texture *rtex = (struct r600_texture*)texture;
903
904 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
905 return r600_compute_global_transfer_unmap(ctx, transfer);
906 }
907
908 if (rtransfer->staging) {
909 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
910 } else {
911 buf = ((struct r600_resource *)transfer->resource)->cs_buf;
912 }
913 rctx->ws->buffer_unmap(buf);
914
915 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
916 if (rtex->is_depth) {
917 ctx->resource_copy_region(ctx, texture, transfer->level,
918 transfer->box.x, transfer->box.y, transfer->box.z,
919 &rtransfer->staging->b.b, transfer->level,
920 &transfer->box);
921 } else {
922 r600_copy_from_staging_texture(ctx, rtransfer);
923 }
924 }
925
926 if (rtransfer->staging)
927 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
928
929 FREE(transfer);
930 }
931
932 void r600_init_surface_functions(struct r600_context *r600)
933 {
934 r600->context.create_surface = r600_create_surface;
935 r600->context.surface_destroy = r600_surface_destroy;
936 }
937
938 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
939 const unsigned char *swizzle_view,
940 boolean vtx)
941 {
942 unsigned i;
943 unsigned char swizzle[4];
944 unsigned result = 0;
945 const uint32_t tex_swizzle_shift[4] = {
946 16, 19, 22, 25,
947 };
948 const uint32_t vtx_swizzle_shift[4] = {
949 3, 6, 9, 12,
950 };
951 const uint32_t swizzle_bit[4] = {
952 0, 1, 2, 3,
953 };
954 const uint32_t *swizzle_shift = tex_swizzle_shift;
955
956 if (vtx)
957 swizzle_shift = vtx_swizzle_shift;
958
959 if (swizzle_view) {
960 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
961 } else {
962 memcpy(swizzle, swizzle_format, 4);
963 }
964
965 /* Get swizzle. */
966 for (i = 0; i < 4; i++) {
967 switch (swizzle[i]) {
968 case UTIL_FORMAT_SWIZZLE_Y:
969 result |= swizzle_bit[1] << swizzle_shift[i];
970 break;
971 case UTIL_FORMAT_SWIZZLE_Z:
972 result |= swizzle_bit[2] << swizzle_shift[i];
973 break;
974 case UTIL_FORMAT_SWIZZLE_W:
975 result |= swizzle_bit[3] << swizzle_shift[i];
976 break;
977 case UTIL_FORMAT_SWIZZLE_0:
978 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
979 break;
980 case UTIL_FORMAT_SWIZZLE_1:
981 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
982 break;
983 default: /* UTIL_FORMAT_SWIZZLE_X */
984 result |= swizzle_bit[0] << swizzle_shift[i];
985 }
986 }
987 return result;
988 }
989
990 /* texture format translate */
991 uint32_t r600_translate_texformat(struct pipe_screen *screen,
992 enum pipe_format format,
993 const unsigned char *swizzle_view,
994 uint32_t *word4_p, uint32_t *yuv_format_p)
995 {
996 struct r600_screen *rscreen = (struct r600_screen *)screen;
997 uint32_t result = 0, word4 = 0, yuv_format = 0;
998 const struct util_format_description *desc;
999 boolean uniform = TRUE;
1000 bool enable_s3tc = rscreen->info.drm_minor >= 9;
1001 bool is_srgb_valid = FALSE;
1002 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
1003 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
1004
1005 int i;
1006 const uint32_t sign_bit[4] = {
1007 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
1008 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
1009 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
1010 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
1011 };
1012 desc = util_format_description(format);
1013
1014 /* Depth and stencil swizzling is handled separately. */
1015 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
1016 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
1017 }
1018
1019 /* Colorspace (return non-RGB formats directly). */
1020 switch (desc->colorspace) {
1021 /* Depth stencil formats */
1022 case UTIL_FORMAT_COLORSPACE_ZS:
1023 switch (format) {
1024 /* Depth sampler formats. */
1025 case PIPE_FORMAT_Z16_UNORM:
1026 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1027 result = FMT_16;
1028 goto out_word4;
1029 case PIPE_FORMAT_Z24X8_UNORM:
1030 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1031 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1032 result = FMT_8_24;
1033 goto out_word4;
1034 case PIPE_FORMAT_X8Z24_UNORM:
1035 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1036 if (rscreen->chip_class < EVERGREEN)
1037 goto out_unknown;
1038 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1039 result = FMT_24_8;
1040 goto out_word4;
1041 case PIPE_FORMAT_Z32_FLOAT:
1042 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1043 result = FMT_32_FLOAT;
1044 goto out_word4;
1045 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1046 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1047 result = FMT_X24_8_32_FLOAT;
1048 goto out_word4;
1049 /* Stencil sampler formats. */
1050 case PIPE_FORMAT_S8_UINT:
1051 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1052 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1053 result = FMT_8;
1054 goto out_word4;
1055 case PIPE_FORMAT_X24S8_UINT:
1056 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1057 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1058 result = FMT_8_24;
1059 goto out_word4;
1060 case PIPE_FORMAT_S8X24_UINT:
1061 if (rscreen->chip_class < EVERGREEN)
1062 goto out_unknown;
1063 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1064 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1065 result = FMT_24_8;
1066 goto out_word4;
1067 case PIPE_FORMAT_X32_S8X24_UINT:
1068 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1069 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1070 result = FMT_X24_8_32_FLOAT;
1071 goto out_word4;
1072 default:
1073 goto out_unknown;
1074 }
1075
1076 case UTIL_FORMAT_COLORSPACE_YUV:
1077 yuv_format |= (1 << 30);
1078 switch (format) {
1079 case PIPE_FORMAT_UYVY:
1080 case PIPE_FORMAT_YUYV:
1081 default:
1082 break;
1083 }
1084 goto out_unknown; /* XXX */
1085
1086 case UTIL_FORMAT_COLORSPACE_SRGB:
1087 word4 |= S_038010_FORCE_DEGAMMA(1);
1088 break;
1089
1090 default:
1091 break;
1092 }
1093
1094 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1095 if (!enable_s3tc)
1096 goto out_unknown;
1097
1098 switch (format) {
1099 case PIPE_FORMAT_RGTC1_SNORM:
1100 case PIPE_FORMAT_LATC1_SNORM:
1101 word4 |= sign_bit[0];
1102 case PIPE_FORMAT_RGTC1_UNORM:
1103 case PIPE_FORMAT_LATC1_UNORM:
1104 result = FMT_BC4;
1105 goto out_word4;
1106 case PIPE_FORMAT_RGTC2_SNORM:
1107 case PIPE_FORMAT_LATC2_SNORM:
1108 word4 |= sign_bit[0] | sign_bit[1];
1109 case PIPE_FORMAT_RGTC2_UNORM:
1110 case PIPE_FORMAT_LATC2_UNORM:
1111 result = FMT_BC5;
1112 goto out_word4;
1113 default:
1114 goto out_unknown;
1115 }
1116 }
1117
1118 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1119
1120 if (!enable_s3tc)
1121 goto out_unknown;
1122
1123 if (!util_format_s3tc_enabled) {
1124 goto out_unknown;
1125 }
1126
1127 switch (format) {
1128 case PIPE_FORMAT_DXT1_RGB:
1129 case PIPE_FORMAT_DXT1_RGBA:
1130 case PIPE_FORMAT_DXT1_SRGB:
1131 case PIPE_FORMAT_DXT1_SRGBA:
1132 result = FMT_BC1;
1133 is_srgb_valid = TRUE;
1134 goto out_word4;
1135 case PIPE_FORMAT_DXT3_RGBA:
1136 case PIPE_FORMAT_DXT3_SRGBA:
1137 result = FMT_BC2;
1138 is_srgb_valid = TRUE;
1139 goto out_word4;
1140 case PIPE_FORMAT_DXT5_RGBA:
1141 case PIPE_FORMAT_DXT5_SRGBA:
1142 result = FMT_BC3;
1143 is_srgb_valid = TRUE;
1144 goto out_word4;
1145 default:
1146 goto out_unknown;
1147 }
1148 }
1149
1150 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1151 switch (format) {
1152 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1153 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1154 result = FMT_GB_GR;
1155 goto out_word4;
1156 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1157 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1158 result = FMT_BG_RG;
1159 goto out_word4;
1160 default:
1161 goto out_unknown;
1162 }
1163 }
1164
1165 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1166 result = FMT_5_9_9_9_SHAREDEXP;
1167 goto out_word4;
1168 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1169 result = FMT_10_11_11_FLOAT;
1170 goto out_word4;
1171 }
1172
1173
1174 for (i = 0; i < desc->nr_channels; i++) {
1175 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1176 word4 |= sign_bit[i];
1177 }
1178 }
1179
1180 /* R8G8Bx_SNORM - XXX CxV8U8 */
1181
1182 /* See whether the components are of the same size. */
1183 for (i = 1; i < desc->nr_channels; i++) {
1184 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1185 }
1186
1187 /* Non-uniform formats. */
1188 if (!uniform) {
1189 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1190 desc->channel[0].pure_integer)
1191 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1192 switch(desc->nr_channels) {
1193 case 3:
1194 if (desc->channel[0].size == 5 &&
1195 desc->channel[1].size == 6 &&
1196 desc->channel[2].size == 5) {
1197 result = FMT_5_6_5;
1198 goto out_word4;
1199 }
1200 goto out_unknown;
1201 case 4:
1202 if (desc->channel[0].size == 5 &&
1203 desc->channel[1].size == 5 &&
1204 desc->channel[2].size == 5 &&
1205 desc->channel[3].size == 1) {
1206 result = FMT_1_5_5_5;
1207 goto out_word4;
1208 }
1209 if (desc->channel[0].size == 10 &&
1210 desc->channel[1].size == 10 &&
1211 desc->channel[2].size == 10 &&
1212 desc->channel[3].size == 2) {
1213 result = FMT_2_10_10_10;
1214 goto out_word4;
1215 }
1216 goto out_unknown;
1217 }
1218 goto out_unknown;
1219 }
1220
1221 /* Find the first non-VOID channel. */
1222 for (i = 0; i < 4; i++) {
1223 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1224 break;
1225 }
1226 }
1227
1228 if (i == 4)
1229 goto out_unknown;
1230
1231 /* uniform formats */
1232 switch (desc->channel[i].type) {
1233 case UTIL_FORMAT_TYPE_UNSIGNED:
1234 case UTIL_FORMAT_TYPE_SIGNED:
1235 #if 0
1236 if (!desc->channel[i].normalized &&
1237 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1238 goto out_unknown;
1239 }
1240 #endif
1241 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1242 desc->channel[i].pure_integer)
1243 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1244
1245 switch (desc->channel[i].size) {
1246 case 4:
1247 switch (desc->nr_channels) {
1248 case 2:
1249 result = FMT_4_4;
1250 goto out_word4;
1251 case 4:
1252 result = FMT_4_4_4_4;
1253 goto out_word4;
1254 }
1255 goto out_unknown;
1256 case 8:
1257 switch (desc->nr_channels) {
1258 case 1:
1259 result = FMT_8;
1260 goto out_word4;
1261 case 2:
1262 result = FMT_8_8;
1263 goto out_word4;
1264 case 4:
1265 result = FMT_8_8_8_8;
1266 is_srgb_valid = TRUE;
1267 goto out_word4;
1268 }
1269 goto out_unknown;
1270 case 16:
1271 switch (desc->nr_channels) {
1272 case 1:
1273 result = FMT_16;
1274 goto out_word4;
1275 case 2:
1276 result = FMT_16_16;
1277 goto out_word4;
1278 case 4:
1279 result = FMT_16_16_16_16;
1280 goto out_word4;
1281 }
1282 goto out_unknown;
1283 case 32:
1284 switch (desc->nr_channels) {
1285 case 1:
1286 result = FMT_32;
1287 goto out_word4;
1288 case 2:
1289 result = FMT_32_32;
1290 goto out_word4;
1291 case 4:
1292 result = FMT_32_32_32_32;
1293 goto out_word4;
1294 }
1295 }
1296 goto out_unknown;
1297
1298 case UTIL_FORMAT_TYPE_FLOAT:
1299 switch (desc->channel[i].size) {
1300 case 16:
1301 switch (desc->nr_channels) {
1302 case 1:
1303 result = FMT_16_FLOAT;
1304 goto out_word4;
1305 case 2:
1306 result = FMT_16_16_FLOAT;
1307 goto out_word4;
1308 case 4:
1309 result = FMT_16_16_16_16_FLOAT;
1310 goto out_word4;
1311 }
1312 goto out_unknown;
1313 case 32:
1314 switch (desc->nr_channels) {
1315 case 1:
1316 result = FMT_32_FLOAT;
1317 goto out_word4;
1318 case 2:
1319 result = FMT_32_32_FLOAT;
1320 goto out_word4;
1321 case 4:
1322 result = FMT_32_32_32_32_FLOAT;
1323 goto out_word4;
1324 }
1325 }
1326 goto out_unknown;
1327 }
1328
1329 out_word4:
1330
1331 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
1332 return ~0;
1333 if (word4_p)
1334 *word4_p = word4;
1335 if (yuv_format_p)
1336 *yuv_format_p = yuv_format;
1337 return result;
1338 out_unknown:
1339 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1340 return ~0;
1341 }
1342
1343 static const struct u_resource_vtbl r600_texture_vtbl =
1344 {
1345 r600_texture_get_handle, /* get_handle */
1346 r600_texture_destroy, /* resource_destroy */
1347 r600_texture_transfer_map, /* transfer_map */
1348 NULL, /* transfer_flush_region */
1349 r600_texture_transfer_unmap, /* transfer_unmap */
1350 NULL /* transfer_inline_write */
1351 };