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ac: pack ac_surface better
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_log.h"
32 #include "util/u_memory.h"
33 #include "util/u_pack_color.h"
34 #include "util/u_surface.h"
35 #include "util/os_time.h"
36 #include <errno.h>
37 #include <inttypes.h>
38
39 static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
40 struct r600_texture *rtex);
41 static enum radeon_surf_mode
42 r600_choose_tiling(struct r600_common_screen *rscreen,
43 const struct pipe_resource *templ);
44
45
46 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
47 struct r600_texture *rdst,
48 unsigned dst_level, unsigned dstx,
49 unsigned dsty, unsigned dstz,
50 struct r600_texture *rsrc,
51 unsigned src_level,
52 const struct pipe_box *src_box)
53 {
54 if (!rctx->dma.cs)
55 return false;
56
57 if (rdst->surface.bpe != rsrc->surface.bpe)
58 return false;
59
60 /* MSAA: Blits don't exist in the real world. */
61 if (rsrc->resource.b.b.nr_samples > 1 ||
62 rdst->resource.b.b.nr_samples > 1)
63 return false;
64
65 /* Depth-stencil surfaces:
66 * When dst is linear, the DB->CB copy preserves HTILE.
67 * When dst is tiled, the 3D path must be used to update HTILE.
68 */
69 if (rsrc->is_depth || rdst->is_depth)
70 return false;
71
72 /* CMASK as:
73 * src: Both texture and SDMA paths need decompression. Use SDMA.
74 * dst: If overwriting the whole texture, discard CMASK and use
75 * SDMA. Otherwise, use the 3D path.
76 */
77 if (rdst->cmask.size && rdst->dirty_level_mask & (1 << dst_level)) {
78 /* The CMASK clear is only enabled for the first level. */
79 assert(dst_level == 0);
80 if (!util_texrange_covers_whole_level(&rdst->resource.b.b, dst_level,
81 dstx, dsty, dstz, src_box->width,
82 src_box->height, src_box->depth))
83 return false;
84
85 r600_texture_discard_cmask(rctx->screen, rdst);
86 }
87
88 /* All requirements are met. Prepare textures for SDMA. */
89 if (rsrc->cmask.size && rsrc->dirty_level_mask & (1 << src_level))
90 rctx->b.flush_resource(&rctx->b, &rsrc->resource.b.b);
91
92 assert(!(rsrc->dirty_level_mask & (1 << src_level)));
93 assert(!(rdst->dirty_level_mask & (1 << dst_level)));
94
95 return true;
96 }
97
98 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
99 static void r600_copy_region_with_blit(struct pipe_context *pipe,
100 struct pipe_resource *dst,
101 unsigned dst_level,
102 unsigned dstx, unsigned dsty, unsigned dstz,
103 struct pipe_resource *src,
104 unsigned src_level,
105 const struct pipe_box *src_box)
106 {
107 struct pipe_blit_info blit;
108
109 memset(&blit, 0, sizeof(blit));
110 blit.src.resource = src;
111 blit.src.format = src->format;
112 blit.src.level = src_level;
113 blit.src.box = *src_box;
114 blit.dst.resource = dst;
115 blit.dst.format = dst->format;
116 blit.dst.level = dst_level;
117 blit.dst.box.x = dstx;
118 blit.dst.box.y = dsty;
119 blit.dst.box.z = dstz;
120 blit.dst.box.width = src_box->width;
121 blit.dst.box.height = src_box->height;
122 blit.dst.box.depth = src_box->depth;
123 blit.mask = util_format_get_mask(src->format) &
124 util_format_get_mask(dst->format);
125 blit.filter = PIPE_TEX_FILTER_NEAREST;
126
127 if (blit.mask) {
128 pipe->blit(pipe, &blit);
129 }
130 }
131
132 /* Copy from a full GPU texture to a transfer's staging one. */
133 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
134 {
135 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
136 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
137 struct pipe_resource *dst = &rtransfer->staging->b.b;
138 struct pipe_resource *src = transfer->resource;
139
140 if (src->nr_samples > 1) {
141 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
142 src, transfer->level, &transfer->box);
143 return;
144 }
145
146 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
147 &transfer->box);
148 }
149
150 /* Copy from a transfer's staging texture to a full GPU one. */
151 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
152 {
153 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
154 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
155 struct pipe_resource *dst = transfer->resource;
156 struct pipe_resource *src = &rtransfer->staging->b.b;
157 struct pipe_box sbox;
158
159 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
160
161 if (dst->nr_samples > 1) {
162 r600_copy_region_with_blit(ctx, dst, transfer->level,
163 transfer->box.x, transfer->box.y, transfer->box.z,
164 src, 0, &sbox);
165 return;
166 }
167
168 rctx->dma_copy(ctx, dst, transfer->level,
169 transfer->box.x, transfer->box.y, transfer->box.z,
170 src, 0, &sbox);
171 }
172
173 static unsigned r600_texture_get_offset(struct r600_common_screen *rscreen,
174 struct r600_texture *rtex, unsigned level,
175 const struct pipe_box *box,
176 unsigned *stride,
177 unsigned *layer_stride)
178 {
179 *stride = rtex->surface.u.legacy.level[level].nblk_x *
180 rtex->surface.bpe;
181 *layer_stride = rtex->surface.u.legacy.level[level].slice_size;
182
183 if (!box)
184 return rtex->surface.u.legacy.level[level].offset;
185
186 /* Each texture is an array of mipmap levels. Each level is
187 * an array of slices. */
188 return rtex->surface.u.legacy.level[level].offset +
189 box->z * rtex->surface.u.legacy.level[level].slice_size +
190 (box->y / rtex->surface.blk_h *
191 rtex->surface.u.legacy.level[level].nblk_x +
192 box->x / rtex->surface.blk_w) * rtex->surface.bpe;
193 }
194
195 static int r600_init_surface(struct r600_common_screen *rscreen,
196 struct radeon_surf *surface,
197 const struct pipe_resource *ptex,
198 enum radeon_surf_mode array_mode,
199 unsigned pitch_in_bytes_override,
200 unsigned offset,
201 bool is_imported,
202 bool is_scanout,
203 bool is_flushed_depth)
204 {
205 const struct util_format_description *desc =
206 util_format_description(ptex->format);
207 bool is_depth, is_stencil;
208 int r;
209 unsigned i, bpe, flags = 0;
210
211 is_depth = util_format_has_depth(desc);
212 is_stencil = util_format_has_stencil(desc);
213
214 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
215 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
216 bpe = 4; /* stencil is allocated separately on evergreen */
217 } else {
218 bpe = util_format_get_blocksize(ptex->format);
219 assert(util_is_power_of_two(bpe));
220 }
221
222 if (!is_flushed_depth && is_depth) {
223 flags |= RADEON_SURF_ZBUFFER;
224
225 if (is_stencil)
226 flags |= RADEON_SURF_SBUFFER;
227 }
228
229 if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
230 /* This should catch bugs in gallium users setting incorrect flags. */
231 assert(ptex->nr_samples <= 1 &&
232 ptex->array_size == 1 &&
233 ptex->depth0 == 1 &&
234 ptex->last_level == 0 &&
235 !(flags & RADEON_SURF_Z_OR_SBUFFER));
236
237 flags |= RADEON_SURF_SCANOUT;
238 }
239
240 if (ptex->bind & PIPE_BIND_SHARED)
241 flags |= RADEON_SURF_SHAREABLE;
242 if (is_imported)
243 flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
244 if (!(ptex->flags & R600_RESOURCE_FLAG_FORCE_TILING))
245 flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
246
247 r = rscreen->ws->surface_init(rscreen->ws, ptex, flags, bpe,
248 array_mode, surface);
249 if (r) {
250 return r;
251 }
252
253 if (pitch_in_bytes_override &&
254 pitch_in_bytes_override != surface->u.legacy.level[0].nblk_x * bpe) {
255 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
256 * for those
257 */
258 surface->u.legacy.level[0].nblk_x = pitch_in_bytes_override / bpe;
259 surface->u.legacy.level[0].slice_size = pitch_in_bytes_override *
260 surface->u.legacy.level[0].nblk_y;
261 }
262
263 if (offset) {
264 for (i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
265 surface->u.legacy.level[i].offset += offset;
266 }
267
268 return 0;
269 }
270
271 static void r600_texture_init_metadata(struct r600_common_screen *rscreen,
272 struct r600_texture *rtex,
273 struct radeon_bo_metadata *metadata)
274 {
275 struct radeon_surf *surface = &rtex->surface;
276
277 memset(metadata, 0, sizeof(*metadata));
278
279 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
280 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
281 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
282 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
283 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
284 metadata->u.legacy.bankw = surface->u.legacy.bankw;
285 metadata->u.legacy.bankh = surface->u.legacy.bankh;
286 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
287 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
288 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
289 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
290 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
291 }
292
293 static void r600_surface_import_metadata(struct r600_common_screen *rscreen,
294 struct radeon_surf *surf,
295 struct radeon_bo_metadata *metadata,
296 enum radeon_surf_mode *array_mode,
297 bool *is_scanout)
298 {
299 surf->u.legacy.pipe_config = metadata->u.legacy.pipe_config;
300 surf->u.legacy.bankw = metadata->u.legacy.bankw;
301 surf->u.legacy.bankh = metadata->u.legacy.bankh;
302 surf->u.legacy.tile_split = metadata->u.legacy.tile_split;
303 surf->u.legacy.mtilea = metadata->u.legacy.mtilea;
304 surf->u.legacy.num_banks = metadata->u.legacy.num_banks;
305
306 if (metadata->u.legacy.macrotile == RADEON_LAYOUT_TILED)
307 *array_mode = RADEON_SURF_MODE_2D;
308 else if (metadata->u.legacy.microtile == RADEON_LAYOUT_TILED)
309 *array_mode = RADEON_SURF_MODE_1D;
310 else
311 *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
312
313 *is_scanout = metadata->u.legacy.scanout;
314 }
315
316 static void r600_eliminate_fast_color_clear(struct r600_common_context *rctx,
317 struct r600_texture *rtex)
318 {
319 struct r600_common_screen *rscreen = rctx->screen;
320 struct pipe_context *ctx = &rctx->b;
321
322 if (ctx == rscreen->aux_context)
323 mtx_lock(&rscreen->aux_context_lock);
324
325 ctx->flush_resource(ctx, &rtex->resource.b.b);
326 ctx->flush(ctx, NULL, 0);
327
328 if (ctx == rscreen->aux_context)
329 mtx_unlock(&rscreen->aux_context_lock);
330 }
331
332 static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
333 struct r600_texture *rtex)
334 {
335 if (!rtex->cmask.size)
336 return;
337
338 assert(rtex->resource.b.b.nr_samples <= 1);
339
340 /* Disable CMASK. */
341 memset(&rtex->cmask, 0, sizeof(rtex->cmask));
342 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
343 rtex->dirty_level_mask = 0;
344
345 rtex->cb_color_info &= ~EG_S_028C70_FAST_CLEAR(1);
346
347 if (rtex->cmask_buffer != &rtex->resource)
348 r600_resource_reference(&rtex->cmask_buffer, NULL);
349
350 /* Notify all contexts about the change. */
351 p_atomic_inc(&rscreen->dirty_tex_counter);
352 p_atomic_inc(&rscreen->compressed_colortex_counter);
353 }
354
355 static void r600_reallocate_texture_inplace(struct r600_common_context *rctx,
356 struct r600_texture *rtex,
357 unsigned new_bind_flag,
358 bool invalidate_storage)
359 {
360 struct pipe_screen *screen = rctx->b.screen;
361 struct r600_texture *new_tex;
362 struct pipe_resource templ = rtex->resource.b.b;
363 unsigned i;
364
365 templ.bind |= new_bind_flag;
366
367 /* r600g doesn't react to dirty_tex_descriptor_counter */
368 if (rctx->chip_class < SI)
369 return;
370
371 if (rtex->resource.b.is_shared)
372 return;
373
374 if (new_bind_flag == PIPE_BIND_LINEAR) {
375 if (rtex->surface.is_linear)
376 return;
377
378 /* This fails with MSAA, depth, and compressed textures. */
379 if (r600_choose_tiling(rctx->screen, &templ) !=
380 RADEON_SURF_MODE_LINEAR_ALIGNED)
381 return;
382 }
383
384 new_tex = (struct r600_texture*)screen->resource_create(screen, &templ);
385 if (!new_tex)
386 return;
387
388 /* Copy the pixels to the new texture. */
389 if (!invalidate_storage) {
390 for (i = 0; i <= templ.last_level; i++) {
391 struct pipe_box box;
392
393 u_box_3d(0, 0, 0,
394 u_minify(templ.width0, i), u_minify(templ.height0, i),
395 util_max_layer(&templ, i) + 1, &box);
396
397 rctx->dma_copy(&rctx->b, &new_tex->resource.b.b, i, 0, 0, 0,
398 &rtex->resource.b.b, i, &box);
399 }
400 }
401
402 if (new_bind_flag == PIPE_BIND_LINEAR) {
403 r600_texture_discard_cmask(rctx->screen, rtex);
404 }
405
406 /* Replace the structure fields of rtex. */
407 rtex->resource.b.b.bind = templ.bind;
408 pb_reference(&rtex->resource.buf, new_tex->resource.buf);
409 rtex->resource.gpu_address = new_tex->resource.gpu_address;
410 rtex->resource.vram_usage = new_tex->resource.vram_usage;
411 rtex->resource.gart_usage = new_tex->resource.gart_usage;
412 rtex->resource.bo_size = new_tex->resource.bo_size;
413 rtex->resource.bo_alignment = new_tex->resource.bo_alignment;
414 rtex->resource.domains = new_tex->resource.domains;
415 rtex->resource.flags = new_tex->resource.flags;
416 rtex->size = new_tex->size;
417 rtex->db_render_format = new_tex->db_render_format;
418 rtex->db_compatible = new_tex->db_compatible;
419 rtex->can_sample_z = new_tex->can_sample_z;
420 rtex->can_sample_s = new_tex->can_sample_s;
421 rtex->surface = new_tex->surface;
422 rtex->fmask = new_tex->fmask;
423 rtex->cmask = new_tex->cmask;
424 rtex->cb_color_info = new_tex->cb_color_info;
425 rtex->last_msaa_resolve_target_micro_mode = new_tex->last_msaa_resolve_target_micro_mode;
426 rtex->htile_offset = new_tex->htile_offset;
427 rtex->depth_cleared = new_tex->depth_cleared;
428 rtex->stencil_cleared = new_tex->stencil_cleared;
429 rtex->non_disp_tiling = new_tex->non_disp_tiling;
430 rtex->framebuffers_bound = new_tex->framebuffers_bound;
431
432 if (new_bind_flag == PIPE_BIND_LINEAR) {
433 assert(!rtex->htile_offset);
434 assert(!rtex->cmask.size);
435 assert(!rtex->fmask.size);
436 assert(!rtex->is_depth);
437 }
438
439 r600_texture_reference(&new_tex, NULL);
440
441 p_atomic_inc(&rctx->screen->dirty_tex_counter);
442 }
443
444 static boolean r600_texture_get_handle(struct pipe_screen* screen,
445 struct pipe_context *ctx,
446 struct pipe_resource *resource,
447 struct winsys_handle *whandle,
448 unsigned usage)
449 {
450 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
451 struct r600_common_context *rctx;
452 struct r600_resource *res = (struct r600_resource*)resource;
453 struct r600_texture *rtex = (struct r600_texture*)resource;
454 struct radeon_bo_metadata metadata;
455 bool update_metadata = false;
456 unsigned stride, offset, slice_size;
457
458 ctx = threaded_context_unwrap_sync(ctx);
459 rctx = (struct r600_common_context*)(ctx ? ctx : rscreen->aux_context);
460
461 if (resource->target != PIPE_BUFFER) {
462 /* This is not supported now, but it might be required for OpenCL
463 * interop in the future.
464 */
465 if (resource->nr_samples > 1 || rtex->is_depth)
466 return false;
467
468 /* Move a suballocated texture into a non-suballocated allocation. */
469 if (rscreen->ws->buffer_is_suballocated(res->buf) ||
470 rtex->surface.tile_swizzle) {
471 assert(!res->b.is_shared);
472 r600_reallocate_texture_inplace(rctx, rtex,
473 PIPE_BIND_SHARED, false);
474 rctx->b.flush(&rctx->b, NULL, 0);
475 assert(res->b.b.bind & PIPE_BIND_SHARED);
476 assert(res->flags & RADEON_FLAG_NO_SUBALLOC);
477 assert(rtex->surface.tile_swizzle == 0);
478 }
479
480 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
481 rtex->cmask.size) {
482 /* Eliminate fast clear (CMASK) */
483 r600_eliminate_fast_color_clear(rctx, rtex);
484
485 /* Disable CMASK if flush_resource isn't going
486 * to be called.
487 */
488 if (rtex->cmask.size)
489 r600_texture_discard_cmask(rscreen, rtex);
490 }
491
492 /* Set metadata. */
493 if (!res->b.is_shared || update_metadata) {
494 r600_texture_init_metadata(rscreen, rtex, &metadata);
495 if (rscreen->query_opaque_metadata)
496 rscreen->query_opaque_metadata(rscreen, rtex,
497 &metadata);
498
499 rscreen->ws->buffer_set_metadata(res->buf, &metadata);
500 }
501
502 offset = rtex->surface.u.legacy.level[0].offset;
503 stride = rtex->surface.u.legacy.level[0].nblk_x *
504 rtex->surface.bpe;
505 slice_size = rtex->surface.u.legacy.level[0].slice_size;
506 } else {
507 /* Move a suballocated buffer into a non-suballocated allocation. */
508 if (rscreen->ws->buffer_is_suballocated(res->buf)) {
509 assert(!res->b.is_shared);
510
511 /* Allocate a new buffer with PIPE_BIND_SHARED. */
512 struct pipe_resource templ = res->b.b;
513 templ.bind |= PIPE_BIND_SHARED;
514
515 struct pipe_resource *newb =
516 screen->resource_create(screen, &templ);
517 if (!newb)
518 return false;
519
520 /* Copy the old buffer contents to the new one. */
521 struct pipe_box box;
522 u_box_1d(0, newb->width0, &box);
523 rctx->b.resource_copy_region(&rctx->b, newb, 0, 0, 0, 0,
524 &res->b.b, 0, &box);
525 /* Move the new buffer storage to the old pipe_resource. */
526 r600_replace_buffer_storage(&rctx->b, &res->b.b, newb);
527 pipe_resource_reference(&newb, NULL);
528
529 assert(res->b.b.bind & PIPE_BIND_SHARED);
530 assert(res->flags & RADEON_FLAG_NO_SUBALLOC);
531 }
532
533 /* Buffers */
534 offset = 0;
535 stride = 0;
536 slice_size = 0;
537 }
538
539 if (res->b.is_shared) {
540 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
541 * doesn't set it.
542 */
543 res->external_usage |= usage & ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
544 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
545 res->external_usage &= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
546 } else {
547 res->b.is_shared = true;
548 res->external_usage = usage;
549 }
550
551 return rscreen->ws->buffer_get_handle(res->buf, stride, offset,
552 slice_size, whandle);
553 }
554
555 static void r600_texture_destroy(struct pipe_screen *screen,
556 struct pipe_resource *ptex)
557 {
558 struct r600_texture *rtex = (struct r600_texture*)ptex;
559 struct r600_resource *resource = &rtex->resource;
560
561 r600_texture_reference(&rtex->flushed_depth_texture, NULL);
562 pipe_resource_reference((struct pipe_resource**)&resource->immed_buffer, NULL);
563
564 if (rtex->cmask_buffer != &rtex->resource) {
565 r600_resource_reference(&rtex->cmask_buffer, NULL);
566 }
567 pb_reference(&resource->buf, NULL);
568 FREE(rtex);
569 }
570
571 static const struct u_resource_vtbl r600_texture_vtbl;
572
573 /* The number of samples can be specified independently of the texture. */
574 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
575 struct r600_texture *rtex,
576 unsigned nr_samples,
577 struct r600_fmask_info *out)
578 {
579 /* FMASK is allocated like an ordinary texture. */
580 struct pipe_resource templ = rtex->resource.b.b;
581 struct radeon_surf fmask = {};
582 unsigned flags, bpe;
583
584 memset(out, 0, sizeof(*out));
585
586 templ.nr_samples = 1;
587 flags = rtex->surface.flags | RADEON_SURF_FMASK;
588
589 /* Use the same parameters and tile mode. */
590 fmask.u.legacy.bankw = rtex->surface.u.legacy.bankw;
591 fmask.u.legacy.bankh = rtex->surface.u.legacy.bankh;
592 fmask.u.legacy.mtilea = rtex->surface.u.legacy.mtilea;
593 fmask.u.legacy.tile_split = rtex->surface.u.legacy.tile_split;
594
595 if (nr_samples <= 4)
596 fmask.u.legacy.bankh = 4;
597
598 switch (nr_samples) {
599 case 2:
600 case 4:
601 bpe = 1;
602 break;
603 case 8:
604 bpe = 4;
605 break;
606 default:
607 R600_ERR("Invalid sample count for FMASK allocation.\n");
608 return;
609 }
610
611 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
612 * This can be fixed by writing a separate FMASK allocator specifically
613 * for R600-R700 asics. */
614 if (rscreen->chip_class <= R700) {
615 bpe *= 2;
616 }
617
618 if (rscreen->ws->surface_init(rscreen->ws, &templ, flags, bpe,
619 RADEON_SURF_MODE_2D, &fmask)) {
620 R600_ERR("Got error in surface_init while allocating FMASK.\n");
621 return;
622 }
623
624 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
625
626 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
627 if (out->slice_tile_max)
628 out->slice_tile_max -= 1;
629
630 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
631 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
632 out->bank_height = fmask.u.legacy.bankh;
633 out->tile_swizzle = fmask.tile_swizzle;
634 out->alignment = MAX2(256, fmask.surf_alignment);
635 out->size = fmask.surf_size;
636 }
637
638 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
639 struct r600_texture *rtex)
640 {
641 r600_texture_get_fmask_info(rscreen, rtex,
642 rtex->resource.b.b.nr_samples, &rtex->fmask);
643
644 rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment);
645 rtex->size = rtex->fmask.offset + rtex->fmask.size;
646 }
647
648 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
649 struct r600_texture *rtex,
650 struct r600_cmask_info *out)
651 {
652 unsigned cmask_tile_width = 8;
653 unsigned cmask_tile_height = 8;
654 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
655 unsigned element_bits = 4;
656 unsigned cmask_cache_bits = 1024;
657 unsigned num_pipes = rscreen->info.num_tile_pipes;
658 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
659
660 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
661 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
662 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
663 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
664 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
665
666 unsigned pitch_elements = align(rtex->resource.b.b.width0, macro_tile_width);
667 unsigned height = align(rtex->resource.b.b.height0, macro_tile_height);
668
669 unsigned base_align = num_pipes * pipe_interleave_bytes;
670 unsigned slice_bytes =
671 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
672
673 assert(macro_tile_width % 128 == 0);
674 assert(macro_tile_height % 128 == 0);
675
676 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
677 out->alignment = MAX2(256, base_align);
678 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
679 align(slice_bytes, base_align);
680 }
681
682 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
683 struct r600_texture *rtex)
684 {
685 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
686
687 rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment);
688 rtex->size = rtex->cmask.offset + rtex->cmask.size;
689
690 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
691 }
692
693 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
694 struct r600_texture *rtex)
695 {
696 if (rtex->cmask_buffer)
697 return;
698
699 assert(rtex->cmask.size == 0);
700
701 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
702
703 rtex->cmask_buffer = (struct r600_resource *)
704 r600_aligned_buffer_create(&rscreen->b,
705 R600_RESOURCE_FLAG_UNMAPPABLE,
706 PIPE_USAGE_DEFAULT,
707 rtex->cmask.size,
708 rtex->cmask.alignment);
709 if (rtex->cmask_buffer == NULL) {
710 rtex->cmask.size = 0;
711 return;
712 }
713
714 /* update colorbuffer state bits */
715 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
716
717 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
718
719 p_atomic_inc(&rscreen->compressed_colortex_counter);
720 }
721
722 void eg_resource_alloc_immed(struct r600_common_screen *rscreen,
723 struct r600_resource *res,
724 unsigned immed_size)
725 {
726 res->immed_buffer = (struct r600_resource *)
727 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
728 PIPE_USAGE_DEFAULT, immed_size);
729 }
730
731 static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
732 struct r600_texture *rtex)
733 {
734 unsigned cl_width, cl_height, width, height;
735 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
736 unsigned num_pipes = rscreen->info.num_tile_pipes;
737
738 rtex->surface.htile_size = 0;
739
740 if (rscreen->chip_class <= EVERGREEN &&
741 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
742 return;
743
744 /* HW bug on R6xx. */
745 if (rscreen->chip_class == R600 &&
746 (rtex->resource.b.b.width0 > 7680 ||
747 rtex->resource.b.b.height0 > 7680))
748 return;
749
750 switch (num_pipes) {
751 case 1:
752 cl_width = 32;
753 cl_height = 16;
754 break;
755 case 2:
756 cl_width = 32;
757 cl_height = 32;
758 break;
759 case 4:
760 cl_width = 64;
761 cl_height = 32;
762 break;
763 case 8:
764 cl_width = 64;
765 cl_height = 64;
766 break;
767 case 16:
768 cl_width = 128;
769 cl_height = 64;
770 break;
771 default:
772 assert(0);
773 return;
774 }
775
776 width = align(rtex->resource.b.b.width0, cl_width * 8);
777 height = align(rtex->resource.b.b.height0, cl_height * 8);
778
779 slice_elements = (width * height) / (8 * 8);
780 slice_bytes = slice_elements * 4;
781
782 pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
783 base_align = num_pipes * pipe_interleave_bytes;
784
785 rtex->surface.htile_alignment = base_align;
786 rtex->surface.htile_size =
787 (util_max_layer(&rtex->resource.b.b, 0) + 1) *
788 align(slice_bytes, base_align);
789 }
790
791 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
792 struct r600_texture *rtex)
793 {
794 r600_texture_get_htile_size(rscreen, rtex);
795
796 if (!rtex->surface.htile_size)
797 return;
798
799 rtex->htile_offset = align(rtex->size, rtex->surface.htile_alignment);
800 rtex->size = rtex->htile_offset + rtex->surface.htile_size;
801 }
802
803 void r600_print_texture_info(struct r600_common_screen *rscreen,
804 struct r600_texture *rtex, struct u_log_context *log)
805 {
806 int i;
807
808 /* Common parameters. */
809 u_log_printf(log, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
810 "blk_h=%u, array_size=%u, last_level=%u, "
811 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
812 rtex->resource.b.b.width0, rtex->resource.b.b.height0,
813 rtex->resource.b.b.depth0, rtex->surface.blk_w,
814 rtex->surface.blk_h,
815 rtex->resource.b.b.array_size, rtex->resource.b.b.last_level,
816 rtex->surface.bpe, rtex->resource.b.b.nr_samples,
817 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
818
819 u_log_printf(log, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, "
820 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
821 rtex->surface.surf_size, rtex->surface.surf_alignment, rtex->surface.u.legacy.bankw,
822 rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea,
823 rtex->surface.u.legacy.tile_split, rtex->surface.u.legacy.pipe_config,
824 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
825
826 if (rtex->fmask.size)
827 u_log_printf(log, " FMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch_in_pixels=%u, "
828 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
829 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
830 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
831 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
832
833 if (rtex->cmask.size)
834 u_log_printf(log, " CMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, "
835 "slice_tile_max=%u\n",
836 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
837 rtex->cmask.slice_tile_max);
838
839 if (rtex->htile_offset)
840 u_log_printf(log, " HTile: offset=%"PRIu64", size=%u "
841 "alignment=%u\n",
842 rtex->htile_offset, rtex->surface.htile_size,
843 rtex->surface.htile_alignment);
844
845 for (i = 0; i <= rtex->resource.b.b.last_level; i++)
846 u_log_printf(log, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
847 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
848 "mode=%u, tiling_index = %u\n",
849 i, rtex->surface.u.legacy.level[i].offset,
850 rtex->surface.u.legacy.level[i].slice_size,
851 u_minify(rtex->resource.b.b.width0, i),
852 u_minify(rtex->resource.b.b.height0, i),
853 u_minify(rtex->resource.b.b.depth0, i),
854 rtex->surface.u.legacy.level[i].nblk_x,
855 rtex->surface.u.legacy.level[i].nblk_y,
856 rtex->surface.u.legacy.level[i].mode,
857 rtex->surface.u.legacy.tiling_index[i]);
858
859 if (rtex->surface.has_stencil) {
860 u_log_printf(log, " StencilLayout: tilesplit=%u\n",
861 rtex->surface.u.legacy.stencil_tile_split);
862 for (i = 0; i <= rtex->resource.b.b.last_level; i++) {
863 u_log_printf(log, " StencilLevel[%i]: offset=%"PRIu64", "
864 "slice_size=%"PRIu64", npix_x=%u, "
865 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
866 "mode=%u, tiling_index = %u\n",
867 i, rtex->surface.u.legacy.stencil_level[i].offset,
868 rtex->surface.u.legacy.stencil_level[i].slice_size,
869 u_minify(rtex->resource.b.b.width0, i),
870 u_minify(rtex->resource.b.b.height0, i),
871 u_minify(rtex->resource.b.b.depth0, i),
872 rtex->surface.u.legacy.stencil_level[i].nblk_x,
873 rtex->surface.u.legacy.stencil_level[i].nblk_y,
874 rtex->surface.u.legacy.stencil_level[i].mode,
875 rtex->surface.u.legacy.stencil_tiling_index[i]);
876 }
877 }
878 }
879
880 /* Common processing for r600_texture_create and r600_texture_from_handle */
881 static struct r600_texture *
882 r600_texture_create_object(struct pipe_screen *screen,
883 const struct pipe_resource *base,
884 struct pb_buffer *buf,
885 struct radeon_surf *surface)
886 {
887 struct r600_texture *rtex;
888 struct r600_resource *resource;
889 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
890
891 rtex = CALLOC_STRUCT(r600_texture);
892 if (!rtex)
893 return NULL;
894
895 resource = &rtex->resource;
896 resource->b.b = *base;
897 resource->b.b.next = NULL;
898 resource->b.vtbl = &r600_texture_vtbl;
899 pipe_reference_init(&resource->b.b.reference, 1);
900 resource->b.b.screen = screen;
901
902 /* don't include stencil-only formats which we don't support for rendering */
903 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
904
905 rtex->surface = *surface;
906 rtex->size = rtex->surface.surf_size;
907 rtex->db_render_format = base->format;
908
909 /* Tiled depth textures utilize the non-displayable tile order.
910 * This must be done after r600_setup_surface.
911 * Applies to R600-Cayman. */
912 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.u.legacy.level[0].mode >= RADEON_SURF_MODE_1D;
913 /* Applies to GCN. */
914 rtex->last_msaa_resolve_target_micro_mode = rtex->surface.micro_tile_mode;
915
916 if (rtex->is_depth) {
917 if (base->flags & (R600_RESOURCE_FLAG_TRANSFER |
918 R600_RESOURCE_FLAG_FLUSHED_DEPTH) ||
919 rscreen->chip_class >= EVERGREEN) {
920 rtex->can_sample_z = !rtex->surface.u.legacy.depth_adjusted;
921 rtex->can_sample_s = !rtex->surface.u.legacy.stencil_adjusted;
922 } else {
923 if (rtex->resource.b.b.nr_samples <= 1 &&
924 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
925 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT))
926 rtex->can_sample_z = true;
927 }
928
929 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
930 R600_RESOURCE_FLAG_FLUSHED_DEPTH))) {
931 rtex->db_compatible = true;
932
933 if (!(rscreen->debug_flags & DBG_NO_HYPERZ))
934 r600_texture_allocate_htile(rscreen, rtex);
935 }
936 } else {
937 if (base->nr_samples > 1) {
938 if (!buf) {
939 r600_texture_allocate_fmask(rscreen, rtex);
940 r600_texture_allocate_cmask(rscreen, rtex);
941 rtex->cmask_buffer = &rtex->resource;
942 }
943 if (!rtex->fmask.size || !rtex->cmask.size) {
944 FREE(rtex);
945 return NULL;
946 }
947 }
948 }
949
950 /* Now create the backing buffer. */
951 if (!buf) {
952 r600_init_resource_fields(rscreen, resource, rtex->size,
953 rtex->surface.surf_alignment);
954
955 /* Displayable surfaces are not suballocated. */
956 if (resource->b.b.bind & PIPE_BIND_SCANOUT)
957 resource->flags |= RADEON_FLAG_NO_SUBALLOC;
958
959 if (!r600_alloc_resource(rscreen, resource)) {
960 FREE(rtex);
961 return NULL;
962 }
963 } else {
964 resource->buf = buf;
965 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
966 resource->bo_size = buf->size;
967 resource->bo_alignment = buf->alignment;
968 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
969 if (resource->domains & RADEON_DOMAIN_VRAM)
970 resource->vram_usage = buf->size;
971 else if (resource->domains & RADEON_DOMAIN_GTT)
972 resource->gart_usage = buf->size;
973 }
974
975 if (rtex->cmask.size) {
976 /* Initialize the cmask to 0xCC (= compressed state). */
977 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
978 rtex->cmask.offset, rtex->cmask.size,
979 0xCCCCCCCC);
980 }
981 if (rtex->htile_offset) {
982 uint32_t clear_value = 0;
983
984 r600_screen_clear_buffer(rscreen, &rtex->resource.b.b,
985 rtex->htile_offset,
986 rtex->surface.htile_size,
987 clear_value);
988 }
989
990 /* Initialize the CMASK base register value. */
991 rtex->cmask.base_address_reg =
992 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
993
994 if (rscreen->debug_flags & DBG_VM) {
995 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
996 rtex->resource.gpu_address,
997 rtex->resource.gpu_address + rtex->resource.buf->size,
998 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
999 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
1000 }
1001
1002 if (rscreen->debug_flags & DBG_TEX) {
1003 puts("Texture:");
1004 struct u_log_context log;
1005 u_log_context_init(&log);
1006 r600_print_texture_info(rscreen, rtex, &log);
1007 u_log_new_page_print(&log, stdout);
1008 fflush(stdout);
1009 u_log_context_destroy(&log);
1010 }
1011
1012 return rtex;
1013 }
1014
1015 static enum radeon_surf_mode
1016 r600_choose_tiling(struct r600_common_screen *rscreen,
1017 const struct pipe_resource *templ)
1018 {
1019 const struct util_format_description *desc = util_format_description(templ->format);
1020 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
1021 bool is_depth_stencil = util_format_is_depth_or_stencil(templ->format) &&
1022 !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
1023
1024 /* MSAA resources must be 2D tiled. */
1025 if (templ->nr_samples > 1)
1026 return RADEON_SURF_MODE_2D;
1027
1028 /* Transfer resources should be linear. */
1029 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
1030 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1031
1032 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1033 if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
1034 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
1035 (templ->target == PIPE_TEXTURE_2D ||
1036 templ->target == PIPE_TEXTURE_3D))
1037 force_tiling = true;
1038
1039 /* Handle common candidates for the linear mode.
1040 * Compressed textures and DB surfaces must always be tiled.
1041 */
1042 if (!force_tiling &&
1043 !is_depth_stencil &&
1044 !util_format_is_compressed(templ->format)) {
1045 if (rscreen->debug_flags & DBG_NO_TILING)
1046 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1047
1048 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1049 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
1050 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1051
1052 if (templ->bind & PIPE_BIND_LINEAR)
1053 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1054
1055 /* Textures with a very small height are recommended to be linear. */
1056 if (templ->target == PIPE_TEXTURE_1D ||
1057 templ->target == PIPE_TEXTURE_1D_ARRAY ||
1058 /* Only very thin and long 2D textures should benefit from
1059 * linear_aligned. */
1060 (templ->width0 > 8 && templ->height0 <= 2))
1061 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1062
1063 /* Textures likely to be mapped often. */
1064 if (templ->usage == PIPE_USAGE_STAGING ||
1065 templ->usage == PIPE_USAGE_STREAM)
1066 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1067 }
1068
1069 /* Make small textures 1D tiled. */
1070 if (templ->width0 <= 16 || templ->height0 <= 16 ||
1071 (rscreen->debug_flags & DBG_NO_2D_TILING))
1072 return RADEON_SURF_MODE_1D;
1073
1074 /* The allocator will switch to 1D if needed. */
1075 return RADEON_SURF_MODE_2D;
1076 }
1077
1078 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
1079 const struct pipe_resource *templ)
1080 {
1081 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1082 struct radeon_surf surface = {0};
1083 bool is_flushed_depth = templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1084 int r;
1085
1086 r = r600_init_surface(rscreen, &surface, templ,
1087 r600_choose_tiling(rscreen, templ), 0, 0,
1088 false, false, is_flushed_depth);
1089 if (r) {
1090 return NULL;
1091 }
1092
1093 return (struct pipe_resource *)
1094 r600_texture_create_object(screen, templ, NULL, &surface);
1095 }
1096
1097 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
1098 const struct pipe_resource *templ,
1099 struct winsys_handle *whandle,
1100 unsigned usage)
1101 {
1102 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1103 struct pb_buffer *buf = NULL;
1104 unsigned stride = 0, offset = 0;
1105 enum radeon_surf_mode array_mode;
1106 struct radeon_surf surface = {};
1107 int r;
1108 struct radeon_bo_metadata metadata = {};
1109 struct r600_texture *rtex;
1110 bool is_scanout;
1111
1112 /* Support only 2D textures without mipmaps */
1113 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
1114 templ->depth0 != 1 || templ->last_level != 0)
1115 return NULL;
1116
1117 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride, &offset);
1118 if (!buf)
1119 return NULL;
1120
1121 rscreen->ws->buffer_get_metadata(buf, &metadata);
1122 r600_surface_import_metadata(rscreen, &surface, &metadata,
1123 &array_mode, &is_scanout);
1124
1125 r = r600_init_surface(rscreen, &surface, templ, array_mode, stride,
1126 offset, true, is_scanout, false);
1127 if (r) {
1128 return NULL;
1129 }
1130
1131 rtex = r600_texture_create_object(screen, templ, buf, &surface);
1132 if (!rtex)
1133 return NULL;
1134
1135 rtex->resource.b.is_shared = true;
1136 rtex->resource.external_usage = usage;
1137
1138 if (rscreen->apply_opaque_metadata)
1139 rscreen->apply_opaque_metadata(rscreen, rtex, &metadata);
1140
1141 assert(rtex->surface.tile_swizzle == 0);
1142 return &rtex->resource.b.b;
1143 }
1144
1145 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
1146 struct pipe_resource *texture,
1147 struct r600_texture **staging)
1148 {
1149 struct r600_texture *rtex = (struct r600_texture*)texture;
1150 struct pipe_resource resource;
1151 struct r600_texture **flushed_depth_texture = staging ?
1152 staging : &rtex->flushed_depth_texture;
1153 enum pipe_format pipe_format = texture->format;
1154
1155 if (!staging) {
1156 if (rtex->flushed_depth_texture)
1157 return true; /* it's ready */
1158
1159 if (!rtex->can_sample_z && rtex->can_sample_s) {
1160 switch (pipe_format) {
1161 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1162 /* Save memory by not allocating the S plane. */
1163 pipe_format = PIPE_FORMAT_Z32_FLOAT;
1164 break;
1165 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1166 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1167 /* Save memory bandwidth by not copying the
1168 * stencil part during flush.
1169 *
1170 * This potentially increases memory bandwidth
1171 * if an application uses both Z and S texturing
1172 * simultaneously (a flushed Z24S8 texture
1173 * would be stored compactly), but how often
1174 * does that really happen?
1175 */
1176 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
1177 break;
1178 default:;
1179 }
1180 } else if (!rtex->can_sample_s && rtex->can_sample_z) {
1181 assert(util_format_has_stencil(util_format_description(pipe_format)));
1182
1183 /* DB->CB copies to an 8bpp surface don't work. */
1184 pipe_format = PIPE_FORMAT_X24S8_UINT;
1185 }
1186 }
1187
1188 memset(&resource, 0, sizeof(resource));
1189 resource.target = texture->target;
1190 resource.format = pipe_format;
1191 resource.width0 = texture->width0;
1192 resource.height0 = texture->height0;
1193 resource.depth0 = texture->depth0;
1194 resource.array_size = texture->array_size;
1195 resource.last_level = texture->last_level;
1196 resource.nr_samples = texture->nr_samples;
1197 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1198 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
1199 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1200
1201 if (staging)
1202 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
1203
1204 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
1205 if (*flushed_depth_texture == NULL) {
1206 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1207 return false;
1208 }
1209
1210 (*flushed_depth_texture)->non_disp_tiling = false;
1211 return true;
1212 }
1213
1214 /**
1215 * Initialize the pipe_resource descriptor to be of the same size as the box,
1216 * which is supposed to hold a subregion of the texture "orig" at the given
1217 * mipmap level.
1218 */
1219 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
1220 struct pipe_resource *orig,
1221 const struct pipe_box *box,
1222 unsigned level, unsigned flags)
1223 {
1224 memset(res, 0, sizeof(*res));
1225 res->format = orig->format;
1226 res->width0 = box->width;
1227 res->height0 = box->height;
1228 res->depth0 = 1;
1229 res->array_size = 1;
1230 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1231 res->flags = flags;
1232
1233 /* We must set the correct texture target and dimensions for a 3D box. */
1234 if (box->depth > 1 && util_max_layer(orig, level) > 0) {
1235 res->target = PIPE_TEXTURE_2D_ARRAY;
1236 res->array_size = box->depth;
1237 } else {
1238 res->target = PIPE_TEXTURE_2D;
1239 }
1240 }
1241
1242 static bool r600_can_invalidate_texture(struct r600_common_screen *rscreen,
1243 struct r600_texture *rtex,
1244 unsigned transfer_usage,
1245 const struct pipe_box *box)
1246 {
1247 /* r600g doesn't react to dirty_tex_descriptor_counter */
1248 return rscreen->chip_class >= SI &&
1249 !rtex->resource.b.is_shared &&
1250 !(transfer_usage & PIPE_TRANSFER_READ) &&
1251 rtex->resource.b.b.last_level == 0 &&
1252 util_texrange_covers_whole_level(&rtex->resource.b.b, 0,
1253 box->x, box->y, box->z,
1254 box->width, box->height,
1255 box->depth);
1256 }
1257
1258 static void r600_texture_invalidate_storage(struct r600_common_context *rctx,
1259 struct r600_texture *rtex)
1260 {
1261 struct r600_common_screen *rscreen = rctx->screen;
1262
1263 /* There is no point in discarding depth and tiled buffers. */
1264 assert(!rtex->is_depth);
1265 assert(rtex->surface.is_linear);
1266
1267 /* Reallocate the buffer in the same pipe_resource. */
1268 r600_alloc_resource(rscreen, &rtex->resource);
1269
1270 /* Initialize the CMASK base address (needed even without CMASK). */
1271 rtex->cmask.base_address_reg =
1272 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
1273
1274 p_atomic_inc(&rscreen->dirty_tex_counter);
1275
1276 rctx->num_alloc_tex_transfer_bytes += rtex->size;
1277 }
1278
1279 static void *r600_texture_transfer_map(struct pipe_context *ctx,
1280 struct pipe_resource *texture,
1281 unsigned level,
1282 unsigned usage,
1283 const struct pipe_box *box,
1284 struct pipe_transfer **ptransfer)
1285 {
1286 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1287 struct r600_texture *rtex = (struct r600_texture*)texture;
1288 struct r600_transfer *trans;
1289 struct r600_resource *buf;
1290 unsigned offset = 0;
1291 char *map;
1292 bool use_staging_texture = false;
1293
1294 assert(!(texture->flags & R600_RESOURCE_FLAG_TRANSFER));
1295 assert(box->width && box->height && box->depth);
1296
1297 /* Depth textures use staging unconditionally. */
1298 if (!rtex->is_depth) {
1299 /* Degrade the tile mode if we get too many transfers on APUs.
1300 * On dGPUs, the staging texture is always faster.
1301 * Only count uploads that are at least 4x4 pixels large.
1302 */
1303 if (!rctx->screen->info.has_dedicated_vram &&
1304 level == 0 &&
1305 box->width >= 4 && box->height >= 4 &&
1306 p_atomic_inc_return(&rtex->num_level0_transfers) == 10) {
1307 bool can_invalidate =
1308 r600_can_invalidate_texture(rctx->screen, rtex,
1309 usage, box);
1310
1311 r600_reallocate_texture_inplace(rctx, rtex,
1312 PIPE_BIND_LINEAR,
1313 can_invalidate);
1314 }
1315
1316 /* Tiled textures need to be converted into a linear texture for CPU
1317 * access. The staging texture is always linear and is placed in GART.
1318 *
1319 * Reading from VRAM or GTT WC is slow, always use the staging
1320 * texture in this case.
1321 *
1322 * Use the staging texture for uploads if the underlying BO
1323 * is busy.
1324 */
1325 if (!rtex->surface.is_linear)
1326 use_staging_texture = true;
1327 else if (usage & PIPE_TRANSFER_READ)
1328 use_staging_texture =
1329 rtex->resource.domains & RADEON_DOMAIN_VRAM ||
1330 rtex->resource.flags & RADEON_FLAG_GTT_WC;
1331 /* Write & linear only: */
1332 else if (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf,
1333 RADEON_USAGE_READWRITE) ||
1334 !rctx->ws->buffer_wait(rtex->resource.buf, 0,
1335 RADEON_USAGE_READWRITE)) {
1336 /* It's busy. */
1337 if (r600_can_invalidate_texture(rctx->screen, rtex,
1338 usage, box))
1339 r600_texture_invalidate_storage(rctx, rtex);
1340 else
1341 use_staging_texture = true;
1342 }
1343 }
1344
1345 trans = CALLOC_STRUCT(r600_transfer);
1346 if (!trans)
1347 return NULL;
1348 pipe_resource_reference(&trans->b.b.resource, texture);
1349 trans->b.b.level = level;
1350 trans->b.b.usage = usage;
1351 trans->b.b.box = *box;
1352
1353 if (rtex->is_depth) {
1354 struct r600_texture *staging_depth;
1355
1356 if (rtex->resource.b.b.nr_samples > 1) {
1357 /* MSAA depth buffers need to be converted to single sample buffers.
1358 *
1359 * Mapping MSAA depth buffers can occur if ReadPixels is called
1360 * with a multisample GLX visual.
1361 *
1362 * First downsample the depth buffer to a temporary texture,
1363 * then decompress the temporary one to staging.
1364 *
1365 * Only the region being mapped is transfered.
1366 */
1367 struct pipe_resource resource;
1368
1369 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1370
1371 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1372 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1373 FREE(trans);
1374 return NULL;
1375 }
1376
1377 if (usage & PIPE_TRANSFER_READ) {
1378 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1379 if (!temp) {
1380 R600_ERR("failed to create a temporary depth texture\n");
1381 FREE(trans);
1382 return NULL;
1383 }
1384
1385 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1386 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1387 0, 0, 0, box->depth, 0, 0);
1388 pipe_resource_reference(&temp, NULL);
1389 }
1390
1391 /* Just get the strides. */
1392 r600_texture_get_offset(rctx->screen, staging_depth, level, NULL,
1393 &trans->b.b.stride,
1394 &trans->b.b.layer_stride);
1395 } else {
1396 /* XXX: only readback the rectangle which is being mapped? */
1397 /* XXX: when discard is true, no need to read back from depth texture */
1398 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1399 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1400 FREE(trans);
1401 return NULL;
1402 }
1403
1404 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1405 level, level,
1406 box->z, box->z + box->depth - 1,
1407 0, 0);
1408
1409 offset = r600_texture_get_offset(rctx->screen, staging_depth,
1410 level, box,
1411 &trans->b.b.stride,
1412 &trans->b.b.layer_stride);
1413 }
1414
1415 trans->staging = (struct r600_resource*)staging_depth;
1416 buf = trans->staging;
1417 } else if (use_staging_texture) {
1418 struct pipe_resource resource;
1419 struct r600_texture *staging;
1420
1421 r600_init_temp_resource_from_box(&resource, texture, box, level,
1422 R600_RESOURCE_FLAG_TRANSFER);
1423 resource.usage = (usage & PIPE_TRANSFER_READ) ?
1424 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1425
1426 /* Create the temporary texture. */
1427 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1428 if (!staging) {
1429 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1430 FREE(trans);
1431 return NULL;
1432 }
1433 trans->staging = &staging->resource;
1434
1435 /* Just get the strides. */
1436 r600_texture_get_offset(rctx->screen, staging, 0, NULL,
1437 &trans->b.b.stride,
1438 &trans->b.b.layer_stride);
1439
1440 if (usage & PIPE_TRANSFER_READ)
1441 r600_copy_to_staging_texture(ctx, trans);
1442 else
1443 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1444
1445 buf = trans->staging;
1446 } else {
1447 /* the resource is mapped directly */
1448 offset = r600_texture_get_offset(rctx->screen, rtex, level, box,
1449 &trans->b.b.stride,
1450 &trans->b.b.layer_stride);
1451 buf = &rtex->resource;
1452 }
1453
1454 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1455 r600_resource_reference(&trans->staging, NULL);
1456 FREE(trans);
1457 return NULL;
1458 }
1459
1460 *ptransfer = &trans->b.b;
1461 return map + offset;
1462 }
1463
1464 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1465 struct pipe_transfer* transfer)
1466 {
1467 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1468 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1469 struct pipe_resource *texture = transfer->resource;
1470 struct r600_texture *rtex = (struct r600_texture*)texture;
1471
1472 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1473 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1474 ctx->resource_copy_region(ctx, texture, transfer->level,
1475 transfer->box.x, transfer->box.y, transfer->box.z,
1476 &rtransfer->staging->b.b, transfer->level,
1477 &transfer->box);
1478 } else {
1479 r600_copy_from_staging_texture(ctx, rtransfer);
1480 }
1481 }
1482
1483 if (rtransfer->staging) {
1484 rctx->num_alloc_tex_transfer_bytes += rtransfer->staging->buf->size;
1485 r600_resource_reference(&rtransfer->staging, NULL);
1486 }
1487
1488 /* Heuristic for {upload, draw, upload, draw, ..}:
1489 *
1490 * Flush the gfx IB if we've allocated too much texture storage.
1491 *
1492 * The idea is that we don't want to build IBs that use too much
1493 * memory and put pressure on the kernel memory manager and we also
1494 * want to make temporary and invalidated buffers go idle ASAP to
1495 * decrease the total memory usage or make them reusable. The memory
1496 * usage will be slightly higher than given here because of the buffer
1497 * cache in the winsys.
1498 *
1499 * The result is that the kernel memory manager is never a bottleneck.
1500 */
1501 if (rctx->num_alloc_tex_transfer_bytes > rctx->screen->info.gart_size / 4) {
1502 rctx->gfx.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
1503 rctx->num_alloc_tex_transfer_bytes = 0;
1504 }
1505
1506 pipe_resource_reference(&transfer->resource, NULL);
1507 FREE(transfer);
1508 }
1509
1510 static const struct u_resource_vtbl r600_texture_vtbl =
1511 {
1512 NULL, /* get_handle */
1513 r600_texture_destroy, /* resource_destroy */
1514 r600_texture_transfer_map, /* transfer_map */
1515 u_default_transfer_flush_region, /* transfer_flush_region */
1516 r600_texture_transfer_unmap, /* transfer_unmap */
1517 };
1518
1519 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1520 struct pipe_resource *texture,
1521 const struct pipe_surface *templ,
1522 unsigned width0, unsigned height0,
1523 unsigned width, unsigned height)
1524 {
1525 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1526
1527 if (!surface)
1528 return NULL;
1529
1530 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1531 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1532
1533 pipe_reference_init(&surface->base.reference, 1);
1534 pipe_resource_reference(&surface->base.texture, texture);
1535 surface->base.context = pipe;
1536 surface->base.format = templ->format;
1537 surface->base.width = width;
1538 surface->base.height = height;
1539 surface->base.u = templ->u;
1540
1541 surface->width0 = width0;
1542 surface->height0 = height0;
1543
1544 return &surface->base;
1545 }
1546
1547 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1548 struct pipe_resource *tex,
1549 const struct pipe_surface *templ)
1550 {
1551 unsigned level = templ->u.tex.level;
1552 unsigned width = u_minify(tex->width0, level);
1553 unsigned height = u_minify(tex->height0, level);
1554 unsigned width0 = tex->width0;
1555 unsigned height0 = tex->height0;
1556
1557 if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
1558 const struct util_format_description *tex_desc
1559 = util_format_description(tex->format);
1560 const struct util_format_description *templ_desc
1561 = util_format_description(templ->format);
1562
1563 assert(tex_desc->block.bits == templ_desc->block.bits);
1564
1565 /* Adjust size of surface if and only if the block width or
1566 * height is changed. */
1567 if (tex_desc->block.width != templ_desc->block.width ||
1568 tex_desc->block.height != templ_desc->block.height) {
1569 unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
1570 unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
1571
1572 width = nblks_x * templ_desc->block.width;
1573 height = nblks_y * templ_desc->block.height;
1574
1575 width0 = util_format_get_nblocksx(tex->format, width0);
1576 height0 = util_format_get_nblocksy(tex->format, height0);
1577 }
1578 }
1579
1580 return r600_create_surface_custom(pipe, tex, templ,
1581 width0, height0,
1582 width, height);
1583 }
1584
1585 static void r600_surface_destroy(struct pipe_context *pipe,
1586 struct pipe_surface *surface)
1587 {
1588 struct r600_surface *surf = (struct r600_surface*)surface;
1589 r600_resource_reference(&surf->cb_buffer_fmask, NULL);
1590 r600_resource_reference(&surf->cb_buffer_cmask, NULL);
1591 pipe_resource_reference(&surface->texture, NULL);
1592 FREE(surface);
1593 }
1594
1595 static void r600_clear_texture(struct pipe_context *pipe,
1596 struct pipe_resource *tex,
1597 unsigned level,
1598 const struct pipe_box *box,
1599 const void *data)
1600 {
1601 struct pipe_screen *screen = pipe->screen;
1602 struct r600_texture *rtex = (struct r600_texture*)tex;
1603 struct pipe_surface tmpl = {{0}};
1604 struct pipe_surface *sf;
1605 const struct util_format_description *desc =
1606 util_format_description(tex->format);
1607
1608 tmpl.format = tex->format;
1609 tmpl.u.tex.first_layer = box->z;
1610 tmpl.u.tex.last_layer = box->z + box->depth - 1;
1611 tmpl.u.tex.level = level;
1612 sf = pipe->create_surface(pipe, tex, &tmpl);
1613 if (!sf)
1614 return;
1615
1616 if (rtex->is_depth) {
1617 unsigned clear;
1618 float depth;
1619 uint8_t stencil = 0;
1620
1621 /* Depth is always present. */
1622 clear = PIPE_CLEAR_DEPTH;
1623 desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
1624
1625 if (rtex->surface.has_stencil) {
1626 clear |= PIPE_CLEAR_STENCIL;
1627 desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
1628 }
1629
1630 pipe->clear_depth_stencil(pipe, sf, clear, depth, stencil,
1631 box->x, box->y,
1632 box->width, box->height, false);
1633 } else {
1634 union pipe_color_union color;
1635
1636 /* pipe_color_union requires the full vec4 representation. */
1637 if (util_format_is_pure_uint(tex->format))
1638 desc->unpack_rgba_uint(color.ui, 0, data, 0, 1, 1);
1639 else if (util_format_is_pure_sint(tex->format))
1640 desc->unpack_rgba_sint(color.i, 0, data, 0, 1, 1);
1641 else
1642 desc->unpack_rgba_float(color.f, 0, data, 0, 1, 1);
1643
1644 if (screen->is_format_supported(screen, tex->format,
1645 tex->target, 0,
1646 PIPE_BIND_RENDER_TARGET)) {
1647 pipe->clear_render_target(pipe, sf, &color,
1648 box->x, box->y,
1649 box->width, box->height, false);
1650 } else {
1651 /* Software fallback - just for R9G9B9E5_FLOAT */
1652 util_clear_render_target(pipe, sf, &color,
1653 box->x, box->y,
1654 box->width, box->height);
1655 }
1656 }
1657 pipe_surface_reference(&sf, NULL);
1658 }
1659
1660 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap)
1661 {
1662 const struct util_format_description *desc = util_format_description(format);
1663
1664 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1665
1666 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1667 return V_0280A0_SWAP_STD;
1668
1669 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1670 return ~0U;
1671
1672 switch (desc->nr_channels) {
1673 case 1:
1674 if (HAS_SWIZZLE(0,X))
1675 return V_0280A0_SWAP_STD; /* X___ */
1676 else if (HAS_SWIZZLE(3,X))
1677 return V_0280A0_SWAP_ALT_REV; /* ___X */
1678 break;
1679 case 2:
1680 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1681 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1682 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1683 return V_0280A0_SWAP_STD; /* XY__ */
1684 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1685 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1686 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1687 /* YX__ */
1688 return (do_endian_swap ? V_0280A0_SWAP_STD : V_0280A0_SWAP_STD_REV);
1689 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1690 return V_0280A0_SWAP_ALT; /* X__Y */
1691 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1692 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1693 break;
1694 case 3:
1695 if (HAS_SWIZZLE(0,X))
1696 return (do_endian_swap ? V_0280A0_SWAP_STD_REV : V_0280A0_SWAP_STD);
1697 else if (HAS_SWIZZLE(0,Z))
1698 return V_0280A0_SWAP_STD_REV; /* ZYX */
1699 break;
1700 case 4:
1701 /* check the middle channels, the 1st and 4th channel can be NONE */
1702 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z)) {
1703 return V_0280A0_SWAP_STD; /* XYZW */
1704 } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y)) {
1705 return V_0280A0_SWAP_STD_REV; /* WZYX */
1706 } else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X)) {
1707 return V_0280A0_SWAP_ALT; /* ZYXW */
1708 } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W)) {
1709 /* YZWX */
1710 if (desc->is_array)
1711 return V_0280A0_SWAP_ALT_REV;
1712 else
1713 return (do_endian_swap ? V_0280A0_SWAP_ALT : V_0280A0_SWAP_ALT_REV);
1714 }
1715 break;
1716 }
1717 return ~0U;
1718 }
1719
1720 /* FAST COLOR CLEAR */
1721
1722 static void evergreen_set_clear_color(struct r600_texture *rtex,
1723 enum pipe_format surface_format,
1724 const union pipe_color_union *color)
1725 {
1726 union util_color uc;
1727
1728 memset(&uc, 0, sizeof(uc));
1729
1730 if (rtex->surface.bpe == 16) {
1731 /* DCC fast clear only:
1732 * CLEAR_WORD0 = R = G = B
1733 * CLEAR_WORD1 = A
1734 */
1735 assert(color->ui[0] == color->ui[1] &&
1736 color->ui[0] == color->ui[2]);
1737 uc.ui[0] = color->ui[0];
1738 uc.ui[1] = color->ui[3];
1739 } else if (util_format_is_pure_uint(surface_format)) {
1740 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1741 } else if (util_format_is_pure_sint(surface_format)) {
1742 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1743 } else {
1744 util_pack_color(color->f, surface_format, &uc);
1745 }
1746
1747 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1748 }
1749
1750 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1751 struct pipe_framebuffer_state *fb,
1752 struct r600_atom *fb_state,
1753 unsigned *buffers, ubyte *dirty_cbufs,
1754 const union pipe_color_union *color)
1755 {
1756 int i;
1757
1758 /* This function is broken in BE, so just disable this path for now */
1759 #ifdef PIPE_ARCH_BIG_ENDIAN
1760 return;
1761 #endif
1762
1763 if (rctx->render_cond)
1764 return;
1765
1766 for (i = 0; i < fb->nr_cbufs; i++) {
1767 struct r600_texture *tex;
1768 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1769
1770 if (!fb->cbufs[i])
1771 continue;
1772
1773 /* if this colorbuffer is not being cleared */
1774 if (!(*buffers & clear_bit))
1775 continue;
1776
1777 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1778
1779 /* the clear is allowed if all layers are bound */
1780 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1781 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1782 continue;
1783 }
1784
1785 /* cannot clear mipmapped textures */
1786 if (fb->cbufs[i]->texture->last_level != 0) {
1787 continue;
1788 }
1789
1790 /* only supported on tiled surfaces */
1791 if (tex->surface.is_linear) {
1792 continue;
1793 }
1794
1795 /* shared textures can't use fast clear without an explicit flush,
1796 * because there is no way to communicate the clear color among
1797 * all clients
1798 */
1799 if (tex->resource.b.is_shared &&
1800 !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
1801 continue;
1802
1803 {
1804 /* 128-bit formats are unusupported */
1805 if (tex->surface.bpe > 8) {
1806 continue;
1807 }
1808
1809 /* ensure CMASK is enabled */
1810 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1811 if (tex->cmask.size == 0) {
1812 continue;
1813 }
1814
1815 /* Do the fast clear. */
1816 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1817 tex->cmask.offset, tex->cmask.size, 0,
1818 R600_COHERENCY_CB_META);
1819
1820 bool need_compressed_update = !tex->dirty_level_mask;
1821
1822 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1823
1824 if (need_compressed_update)
1825 p_atomic_inc(&rctx->screen->compressed_colortex_counter);
1826 }
1827
1828 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1829
1830 if (dirty_cbufs)
1831 *dirty_cbufs |= 1 << i;
1832 rctx->set_atom_dirty(rctx, fb_state, true);
1833 *buffers &= ~clear_bit;
1834 }
1835 }
1836
1837 static struct pipe_memory_object *
1838 r600_memobj_from_handle(struct pipe_screen *screen,
1839 struct winsys_handle *whandle,
1840 bool dedicated)
1841 {
1842 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1843 struct r600_memory_object *memobj = CALLOC_STRUCT(r600_memory_object);
1844 struct pb_buffer *buf = NULL;
1845 uint32_t stride, offset;
1846
1847 if (!memobj)
1848 return NULL;
1849
1850 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle,
1851 &stride, &offset);
1852 if (!buf) {
1853 free(memobj);
1854 return NULL;
1855 }
1856
1857 memobj->b.dedicated = dedicated;
1858 memobj->buf = buf;
1859 memobj->stride = stride;
1860 memobj->offset = offset;
1861
1862 return (struct pipe_memory_object *)memobj;
1863
1864 }
1865
1866 static void
1867 r600_memobj_destroy(struct pipe_screen *screen,
1868 struct pipe_memory_object *_memobj)
1869 {
1870 struct r600_memory_object *memobj = (struct r600_memory_object *)_memobj;
1871
1872 pb_reference(&memobj->buf, NULL);
1873 free(memobj);
1874 }
1875
1876 static struct pipe_resource *
1877 r600_texture_from_memobj(struct pipe_screen *screen,
1878 const struct pipe_resource *templ,
1879 struct pipe_memory_object *_memobj,
1880 uint64_t offset)
1881 {
1882 int r;
1883 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1884 struct r600_memory_object *memobj = (struct r600_memory_object *)_memobj;
1885 struct r600_texture *rtex;
1886 struct radeon_surf surface = {};
1887 struct radeon_bo_metadata metadata = {};
1888 enum radeon_surf_mode array_mode;
1889 bool is_scanout;
1890 struct pb_buffer *buf = NULL;
1891
1892 if (memobj->b.dedicated) {
1893 rscreen->ws->buffer_get_metadata(memobj->buf, &metadata);
1894 r600_surface_import_metadata(rscreen, &surface, &metadata,
1895 &array_mode, &is_scanout);
1896 } else {
1897 /**
1898 * The bo metadata is unset for un-dedicated images. So we fall
1899 * back to linear. See answer to question 5 of the
1900 * VK_KHX_external_memory spec for some details.
1901 *
1902 * It is possible that this case isn't going to work if the
1903 * surface pitch isn't correctly aligned by default.
1904 *
1905 * In order to support it correctly we require multi-image
1906 * metadata to be syncrhonized between radv and radeonsi. The
1907 * semantics of associating multiple image metadata to a memory
1908 * object on the vulkan export side are not concretely defined
1909 * either.
1910 *
1911 * All the use cases we are aware of at the moment for memory
1912 * objects use dedicated allocations. So lets keep the initial
1913 * implementation simple.
1914 *
1915 * A possible alternative is to attempt to reconstruct the
1916 * tiling information when the TexParameter TEXTURE_TILING_EXT
1917 * is set.
1918 */
1919 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
1920 is_scanout = false;
1921
1922 }
1923
1924 r = r600_init_surface(rscreen, &surface, templ,
1925 array_mode, memobj->stride,
1926 offset, true, is_scanout,
1927 false);
1928 if (r)
1929 return NULL;
1930
1931 rtex = r600_texture_create_object(screen, templ, memobj->buf, &surface);
1932 if (!rtex)
1933 return NULL;
1934
1935 /* r600_texture_create_object doesn't increment refcount of
1936 * memobj->buf, so increment it here.
1937 */
1938 pb_reference(&buf, memobj->buf);
1939
1940 rtex->resource.b.is_shared = true;
1941 rtex->resource.external_usage = PIPE_HANDLE_USAGE_READ_WRITE;
1942
1943 if (rscreen->apply_opaque_metadata)
1944 rscreen->apply_opaque_metadata(rscreen, rtex, &metadata);
1945
1946 return &rtex->resource.b.b;
1947 }
1948
1949 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1950 {
1951 rscreen->b.resource_from_handle = r600_texture_from_handle;
1952 rscreen->b.resource_get_handle = r600_texture_get_handle;
1953 rscreen->b.resource_from_memobj = r600_texture_from_memobj;
1954 rscreen->b.memobj_create_from_handle = r600_memobj_from_handle;
1955 rscreen->b.memobj_destroy = r600_memobj_destroy;
1956 }
1957
1958 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1959 {
1960 rctx->b.create_surface = r600_create_surface;
1961 rctx->b.surface_destroy = r600_surface_destroy;
1962 rctx->b.clear_texture = r600_clear_texture;
1963 }