ac: pack ac_surface better

r600_texture: 1736 -> 1488 bytes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 7ac4737e6df33ea8043af48b98eb00525de61f68..1dc95cd0883a7dd1c451bcded1270b1ab0d8fe44 100644 (file)
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -72,8 +72,8 @@ enum radeon_micro_mode {
 struct legacy_surf_level {
     uint64_t                    offset;
     uint64_t                    slice_size;
-    uint64_t                    dcc_offset;
-    uint64_t                    dcc_fast_clear_size;
+    uint32_t                    dcc_offset; /* relative offset within DCC mip tree */
+    uint32_t                    dcc_fast_clear_size;
     uint16_t                    nblk_x;
     uint16_t                    nblk_y;
     enum radeon_surf_mode       mode;
@@ -187,8 +187,9 @@ struct radeon_surf {
     uint8_t                     tile_swizzle;
 
     uint64_t                    surf_size;
-    uint64_t                    dcc_size;
-    uint64_t                    htile_size;
+    /* DCC and HTILE are very small. */
+    uint32_t                    dcc_size;
+    uint32_t                    htile_size;
 
     uint32_t                    htile_slice_size;
 

diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index ee6ed64b9f20784cb281eab7eec47289ff380427..f7c9b63b1126345e245e252f8f92e20c2ad34d48 100644 (file)
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -837,7 +837,7 @@ void r600_print_texture_info(struct r600_common_screen *rscreen,
                        rtex->cmask.slice_tile_max);
 
        if (rtex->htile_offset)
-               u_log_printf(log, "  HTile: offset=%"PRIu64", size=%"PRIu64", "
+               u_log_printf(log, "  HTile: offset=%"PRIu64", size=%u "
                        "alignment=%u\n",
                             rtex->htile_offset, rtex->surface.htile_size,
                             rtex->surface.htile_alignment);

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 9feaee7fbb1e2bfd7e9dd634c23e7726ada37ab7..d77b9e942d90b2da5826595344dbfa052e93ad9f 100644 (file)
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -995,7 +995,7 @@ void si_print_texture_info(struct r600_common_screen *rscreen,
                }
 
                if (rtex->htile_offset) {
-                       u_log_printf(log, "  HTile: offset=%"PRIu64", size=%"PRIu64", alignment=%u, "
+                       u_log_printf(log, "  HTile: offset=%"PRIu64", size=%u, alignment=%u, "
                                "rb_aligned=%u, pipe_aligned=%u\n",
                                rtex->htile_offset,
                                rtex->surface.htile_size,
@@ -1005,7 +1005,7 @@ void si_print_texture_info(struct r600_common_screen *rscreen,
                }
 
                if (rtex->dcc_offset) {
-                       u_log_printf(log, "  DCC: offset=%"PRIu64", size=%"PRIu64", "
+                       u_log_printf(log, "  DCC: offset=%"PRIu64", size=%u, "
                                "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
                                rtex->dcc_offset, rtex->surface.dcc_size,
                                rtex->surface.dcc_alignment,
@@ -1043,19 +1043,19 @@ void si_print_texture_info(struct r600_common_screen *rscreen,
                        rtex->cmask.slice_tile_max);
 
        if (rtex->htile_offset)
-               u_log_printf(log, "  HTile: offset=%"PRIu64", size=%"PRIu64", "
+               u_log_printf(log, "  HTile: offset=%"PRIu64", size=%u, "
                        "alignment=%u, TC_compatible = %u\n",
                        rtex->htile_offset, rtex->surface.htile_size,
                        rtex->surface.htile_alignment,
                        rtex->tc_compatible_htile);
 
        if (rtex->dcc_offset) {
-               u_log_printf(log, "  DCC: offset=%"PRIu64", size=%"PRIu64", alignment=%u\n",
+               u_log_printf(log, "  DCC: offset=%"PRIu64", size=%u, alignment=%u\n",
                        rtex->dcc_offset, rtex->surface.dcc_size,
                        rtex->surface.dcc_alignment);
                for (i = 0; i <= rtex->resource.b.b.last_level; i++)
-                       u_log_printf(log, "  DCCLevel[%i]: enabled=%u, offset=%"PRIu64", "
-                               "fast_clear_size=%"PRIu64"\n",
+                       u_log_printf(log, "  DCCLevel[%i]: enabled=%u, offset=%u, "
+                               "fast_clear_size=%u\n",
                                i, i < rtex->surface.num_dcc_levels,
                                rtex->surface.u.legacy.level[i].dcc_offset,
                                rtex->surface.u.legacy.level[i].dcc_fast_clear_size);