radeonsi: fix the R600_RESOURCE_FLAG_UNMAPPABLE check
[mesa.git] / src / gallium / drivers / radeon / r600_buffer_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "radeonsi/si_pipe.h"
25 #include "r600_cs.h"
26 #include "util/u_memory.h"
27 #include "util/u_upload_mgr.h"
28 #include <inttypes.h>
29 #include <stdio.h>
30
31 bool si_rings_is_buffer_referenced(struct r600_common_context *ctx,
32 struct pb_buffer *buf,
33 enum radeon_bo_usage usage)
34 {
35 if (ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, buf, usage)) {
36 return true;
37 }
38 if (radeon_emitted(ctx->dma.cs, 0) &&
39 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, buf, usage)) {
40 return true;
41 }
42 return false;
43 }
44
45 void *si_buffer_map_sync_with_rings(struct r600_common_context *ctx,
46 struct r600_resource *resource,
47 unsigned usage)
48 {
49 enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
50 bool busy = false;
51
52 assert(!(resource->flags & RADEON_FLAG_SPARSE));
53
54 if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
55 return ctx->ws->buffer_map(resource->buf, NULL, usage);
56 }
57
58 if (!(usage & PIPE_TRANSFER_WRITE)) {
59 /* have to wait for the last write */
60 rusage = RADEON_USAGE_WRITE;
61 }
62
63 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
64 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
65 resource->buf, rusage)) {
66 if (usage & PIPE_TRANSFER_DONTBLOCK) {
67 ctx->gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
68 return NULL;
69 } else {
70 ctx->gfx.flush(ctx, 0, NULL);
71 busy = true;
72 }
73 }
74 if (radeon_emitted(ctx->dma.cs, 0) &&
75 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
76 resource->buf, rusage)) {
77 if (usage & PIPE_TRANSFER_DONTBLOCK) {
78 ctx->dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
79 return NULL;
80 } else {
81 ctx->dma.flush(ctx, 0, NULL);
82 busy = true;
83 }
84 }
85
86 if (busy || !ctx->ws->buffer_wait(resource->buf, 0, rusage)) {
87 if (usage & PIPE_TRANSFER_DONTBLOCK) {
88 return NULL;
89 } else {
90 /* We will be wait for the GPU. Wait for any offloaded
91 * CS flush to complete to avoid busy-waiting in the winsys. */
92 ctx->ws->cs_sync_flush(ctx->gfx.cs);
93 if (ctx->dma.cs)
94 ctx->ws->cs_sync_flush(ctx->dma.cs);
95 }
96 }
97
98 /* Setting the CS to NULL will prevent doing checks we have done already. */
99 return ctx->ws->buffer_map(resource->buf, NULL, usage);
100 }
101
102 void si_init_resource_fields(struct si_screen *sscreen,
103 struct r600_resource *res,
104 uint64_t size, unsigned alignment)
105 {
106 struct r600_texture *rtex = (struct r600_texture*)res;
107
108 res->bo_size = size;
109 res->bo_alignment = alignment;
110 res->flags = 0;
111 res->texture_handle_allocated = false;
112 res->image_handle_allocated = false;
113
114 switch (res->b.b.usage) {
115 case PIPE_USAGE_STREAM:
116 res->flags = RADEON_FLAG_GTT_WC;
117 /* fall through */
118 case PIPE_USAGE_STAGING:
119 /* Transfers are likely to occur more often with these
120 * resources. */
121 res->domains = RADEON_DOMAIN_GTT;
122 break;
123 case PIPE_USAGE_DYNAMIC:
124 /* Older kernels didn't always flush the HDP cache before
125 * CS execution
126 */
127 if (sscreen->info.drm_major == 2 &&
128 sscreen->info.drm_minor < 40) {
129 res->domains = RADEON_DOMAIN_GTT;
130 res->flags |= RADEON_FLAG_GTT_WC;
131 break;
132 }
133 /* fall through */
134 case PIPE_USAGE_DEFAULT:
135 case PIPE_USAGE_IMMUTABLE:
136 default:
137 /* Not listing GTT here improves performance in some
138 * apps. */
139 res->domains = RADEON_DOMAIN_VRAM;
140 res->flags |= RADEON_FLAG_GTT_WC;
141 break;
142 }
143
144 if (res->b.b.target == PIPE_BUFFER &&
145 res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
146 PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
147 /* Use GTT for all persistent mappings with older
148 * kernels, because they didn't always flush the HDP
149 * cache before CS execution.
150 *
151 * Write-combined CPU mappings are fine, the kernel
152 * ensures all CPU writes finish before the GPU
153 * executes a command stream.
154 */
155 if (sscreen->info.drm_major == 2 &&
156 sscreen->info.drm_minor < 40)
157 res->domains = RADEON_DOMAIN_GTT;
158 }
159
160 /* Tiled textures are unmappable. Always put them in VRAM. */
161 if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
162 res->b.b.flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
163 res->domains = RADEON_DOMAIN_VRAM;
164 res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
165 RADEON_FLAG_GTT_WC;
166 }
167
168 /* Displayable and shareable surfaces are not suballocated. */
169 if (res->b.b.bind & (PIPE_BIND_SHARED | PIPE_BIND_SCANOUT))
170 res->flags |= RADEON_FLAG_NO_SUBALLOC; /* shareable */
171 else
172 res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
173
174 if (sscreen->debug_flags & DBG(NO_WC))
175 res->flags &= ~RADEON_FLAG_GTT_WC;
176
177 /* Set expected VRAM and GART usage for the buffer. */
178 res->vram_usage = 0;
179 res->gart_usage = 0;
180 res->max_forced_staging_uploads = 0;
181 res->b.max_forced_staging_uploads = 0;
182
183 if (res->domains & RADEON_DOMAIN_VRAM) {
184 res->vram_usage = size;
185
186 res->max_forced_staging_uploads =
187 res->b.max_forced_staging_uploads =
188 sscreen->info.has_dedicated_vram &&
189 size >= sscreen->info.vram_vis_size / 4 ? 1 : 0;
190 } else if (res->domains & RADEON_DOMAIN_GTT) {
191 res->gart_usage = size;
192 }
193 }
194
195 bool si_alloc_resource(struct si_screen *sscreen,
196 struct r600_resource *res)
197 {
198 struct pb_buffer *old_buf, *new_buf;
199
200 /* Allocate a new resource. */
201 new_buf = sscreen->ws->buffer_create(sscreen->ws, res->bo_size,
202 res->bo_alignment,
203 res->domains, res->flags);
204 if (!new_buf) {
205 return false;
206 }
207
208 /* Replace the pointer such that if res->buf wasn't NULL, it won't be
209 * NULL. This should prevent crashes with multiple contexts using
210 * the same buffer where one of the contexts invalidates it while
211 * the others are using it. */
212 old_buf = res->buf;
213 res->buf = new_buf; /* should be atomic */
214
215 if (sscreen->info.has_virtual_memory)
216 res->gpu_address = sscreen->ws->buffer_get_virtual_address(res->buf);
217 else
218 res->gpu_address = 0;
219
220 pb_reference(&old_buf, NULL);
221
222 util_range_set_empty(&res->valid_buffer_range);
223 res->TC_L2_dirty = false;
224
225 /* Print debug information. */
226 if (sscreen->debug_flags & DBG(VM) && res->b.b.target == PIPE_BUFFER) {
227 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Buffer %"PRIu64" bytes\n",
228 res->gpu_address, res->gpu_address + res->buf->size,
229 res->buf->size);
230 }
231 return true;
232 }
233
234 static void r600_buffer_destroy(struct pipe_screen *screen,
235 struct pipe_resource *buf)
236 {
237 struct r600_resource *rbuffer = r600_resource(buf);
238
239 threaded_resource_deinit(buf);
240 util_range_destroy(&rbuffer->valid_buffer_range);
241 pb_reference(&rbuffer->buf, NULL);
242 FREE(rbuffer);
243 }
244
245 static bool
246 r600_invalidate_buffer(struct r600_common_context *rctx,
247 struct r600_resource *rbuffer)
248 {
249 /* Shared buffers can't be reallocated. */
250 if (rbuffer->b.is_shared)
251 return false;
252
253 /* Sparse buffers can't be reallocated. */
254 if (rbuffer->flags & RADEON_FLAG_SPARSE)
255 return false;
256
257 /* In AMD_pinned_memory, the user pointer association only gets
258 * broken when the buffer is explicitly re-allocated.
259 */
260 if (rbuffer->b.is_user_ptr)
261 return false;
262
263 /* Check if mapping this buffer would cause waiting for the GPU. */
264 if (si_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
265 !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
266 rctx->invalidate_buffer(&rctx->b, &rbuffer->b.b);
267 } else {
268 util_range_set_empty(&rbuffer->valid_buffer_range);
269 }
270
271 return true;
272 }
273
274 /* Replace the storage of dst with src. */
275 void si_replace_buffer_storage(struct pipe_context *ctx,
276 struct pipe_resource *dst,
277 struct pipe_resource *src)
278 {
279 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
280 struct r600_resource *rdst = r600_resource(dst);
281 struct r600_resource *rsrc = r600_resource(src);
282 uint64_t old_gpu_address = rdst->gpu_address;
283
284 pb_reference(&rdst->buf, rsrc->buf);
285 rdst->gpu_address = rsrc->gpu_address;
286 rdst->b.b.bind = rsrc->b.b.bind;
287 rdst->b.max_forced_staging_uploads = rsrc->b.max_forced_staging_uploads;
288 rdst->max_forced_staging_uploads = rsrc->max_forced_staging_uploads;
289 rdst->flags = rsrc->flags;
290
291 assert(rdst->vram_usage == rsrc->vram_usage);
292 assert(rdst->gart_usage == rsrc->gart_usage);
293 assert(rdst->bo_size == rsrc->bo_size);
294 assert(rdst->bo_alignment == rsrc->bo_alignment);
295 assert(rdst->domains == rsrc->domains);
296
297 rctx->rebind_buffer(ctx, dst, old_gpu_address);
298 }
299
300 static void si_invalidate_resource(struct pipe_context *ctx,
301 struct pipe_resource *resource)
302 {
303 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
304 struct r600_resource *rbuffer = r600_resource(resource);
305
306 /* We currently only do anyting here for buffers */
307 if (resource->target == PIPE_BUFFER)
308 (void)r600_invalidate_buffer(rctx, rbuffer);
309 }
310
311 static void *r600_buffer_get_transfer(struct pipe_context *ctx,
312 struct pipe_resource *resource,
313 unsigned usage,
314 const struct pipe_box *box,
315 struct pipe_transfer **ptransfer,
316 void *data, struct r600_resource *staging,
317 unsigned offset)
318 {
319 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
320 struct r600_transfer *transfer;
321
322 if (usage & TC_TRANSFER_MAP_THREADED_UNSYNC)
323 transfer = slab_alloc(&rctx->pool_transfers_unsync);
324 else
325 transfer = slab_alloc(&rctx->pool_transfers);
326
327 transfer->b.b.resource = NULL;
328 pipe_resource_reference(&transfer->b.b.resource, resource);
329 transfer->b.b.level = 0;
330 transfer->b.b.usage = usage;
331 transfer->b.b.box = *box;
332 transfer->b.b.stride = 0;
333 transfer->b.b.layer_stride = 0;
334 transfer->b.staging = NULL;
335 transfer->offset = offset;
336 transfer->staging = staging;
337 *ptransfer = &transfer->b.b;
338 return data;
339 }
340
341 static void *r600_buffer_transfer_map(struct pipe_context *ctx,
342 struct pipe_resource *resource,
343 unsigned level,
344 unsigned usage,
345 const struct pipe_box *box,
346 struct pipe_transfer **ptransfer)
347 {
348 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
349 struct r600_resource *rbuffer = r600_resource(resource);
350 uint8_t *data;
351
352 assert(box->x + box->width <= resource->width0);
353
354 /* From GL_AMD_pinned_memory issues:
355 *
356 * 4) Is glMapBuffer on a shared buffer guaranteed to return the
357 * same system address which was specified at creation time?
358 *
359 * RESOLVED: NO. The GL implementation might return a different
360 * virtual mapping of that memory, although the same physical
361 * page will be used.
362 *
363 * So don't ever use staging buffers.
364 */
365 if (rbuffer->b.is_user_ptr)
366 usage |= PIPE_TRANSFER_PERSISTENT;
367
368 /* See if the buffer range being mapped has never been initialized,
369 * in which case it can be mapped unsynchronized. */
370 if (!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
371 TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED)) &&
372 usage & PIPE_TRANSFER_WRITE &&
373 !rbuffer->b.is_shared &&
374 !util_ranges_intersect(&rbuffer->valid_buffer_range, box->x, box->x + box->width)) {
375 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
376 }
377
378 /* If discarding the entire range, discard the whole resource instead. */
379 if (usage & PIPE_TRANSFER_DISCARD_RANGE &&
380 box->x == 0 && box->width == resource->width0) {
381 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
382 }
383
384 /* If a buffer in VRAM is too large and the range is discarded, don't
385 * map it directly. This makes sure that the buffer stays in VRAM.
386 */
387 bool force_discard_range = false;
388 if (usage & (PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE |
389 PIPE_TRANSFER_DISCARD_RANGE) &&
390 !(usage & PIPE_TRANSFER_PERSISTENT) &&
391 /* Try not to decrement the counter if it's not positive. Still racy,
392 * but it makes it harder to wrap the counter from INT_MIN to INT_MAX. */
393 rbuffer->max_forced_staging_uploads > 0 &&
394 p_atomic_dec_return(&rbuffer->max_forced_staging_uploads) >= 0) {
395 usage &= ~(PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE |
396 PIPE_TRANSFER_UNSYNCHRONIZED);
397 usage |= PIPE_TRANSFER_DISCARD_RANGE;
398 force_discard_range = true;
399 }
400
401 if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE &&
402 !(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
403 TC_TRANSFER_MAP_NO_INVALIDATE))) {
404 assert(usage & PIPE_TRANSFER_WRITE);
405
406 if (r600_invalidate_buffer(rctx, rbuffer)) {
407 /* At this point, the buffer is always idle. */
408 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
409 } else {
410 /* Fall back to a temporary buffer. */
411 usage |= PIPE_TRANSFER_DISCARD_RANGE;
412 }
413 }
414
415 if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
416 ((!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
417 PIPE_TRANSFER_PERSISTENT))) ||
418 (rbuffer->flags & RADEON_FLAG_SPARSE))) {
419 assert(usage & PIPE_TRANSFER_WRITE);
420
421 /* Check if mapping this buffer would cause waiting for the GPU.
422 */
423 if (rbuffer->flags & RADEON_FLAG_SPARSE ||
424 force_discard_range ||
425 si_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
426 !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
427 /* Do a wait-free write-only transfer using a temporary buffer. */
428 unsigned offset;
429 struct r600_resource *staging = NULL;
430
431 u_upload_alloc(ctx->stream_uploader, 0,
432 box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
433 rctx->screen->info.tcc_cache_line_size,
434 &offset, (struct pipe_resource**)&staging,
435 (void**)&data);
436
437 if (staging) {
438 data += box->x % R600_MAP_BUFFER_ALIGNMENT;
439 return r600_buffer_get_transfer(ctx, resource, usage, box,
440 ptransfer, data, staging, offset);
441 } else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
442 return NULL;
443 }
444 } else {
445 /* At this point, the buffer is always idle (we checked it above). */
446 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
447 }
448 }
449 /* Use a staging buffer in cached GTT for reads. */
450 else if (((usage & PIPE_TRANSFER_READ) &&
451 !(usage & PIPE_TRANSFER_PERSISTENT) &&
452 (rbuffer->domains & RADEON_DOMAIN_VRAM ||
453 rbuffer->flags & RADEON_FLAG_GTT_WC)) ||
454 (rbuffer->flags & RADEON_FLAG_SPARSE)) {
455 struct r600_resource *staging;
456
457 assert(!(usage & TC_TRANSFER_MAP_THREADED_UNSYNC));
458 staging = (struct r600_resource*) pipe_buffer_create(
459 ctx->screen, 0, PIPE_USAGE_STAGING,
460 box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT));
461 if (staging) {
462 /* Copy the VRAM buffer to the staging buffer. */
463 rctx->dma_copy(ctx, &staging->b.b, 0,
464 box->x % R600_MAP_BUFFER_ALIGNMENT,
465 0, 0, resource, 0, box);
466
467 data = si_buffer_map_sync_with_rings(rctx, staging,
468 usage & ~PIPE_TRANSFER_UNSYNCHRONIZED);
469 if (!data) {
470 r600_resource_reference(&staging, NULL);
471 return NULL;
472 }
473 data += box->x % R600_MAP_BUFFER_ALIGNMENT;
474
475 return r600_buffer_get_transfer(ctx, resource, usage, box,
476 ptransfer, data, staging, 0);
477 } else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
478 return NULL;
479 }
480 }
481
482 data = si_buffer_map_sync_with_rings(rctx, rbuffer, usage);
483 if (!data) {
484 return NULL;
485 }
486 data += box->x;
487
488 return r600_buffer_get_transfer(ctx, resource, usage, box,
489 ptransfer, data, NULL, 0);
490 }
491
492 static void r600_buffer_do_flush_region(struct pipe_context *ctx,
493 struct pipe_transfer *transfer,
494 const struct pipe_box *box)
495 {
496 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
497 struct r600_resource *rbuffer = r600_resource(transfer->resource);
498
499 if (rtransfer->staging) {
500 struct pipe_resource *dst, *src;
501 unsigned soffset;
502 struct pipe_box dma_box;
503
504 dst = transfer->resource;
505 src = &rtransfer->staging->b.b;
506 soffset = rtransfer->offset + box->x % R600_MAP_BUFFER_ALIGNMENT;
507
508 u_box_1d(soffset, box->width, &dma_box);
509
510 /* Copy the staging buffer into the original one. */
511 ctx->resource_copy_region(ctx, dst, 0, box->x, 0, 0, src, 0, &dma_box);
512 }
513
514 util_range_add(&rbuffer->valid_buffer_range, box->x,
515 box->x + box->width);
516 }
517
518 static void r600_buffer_flush_region(struct pipe_context *ctx,
519 struct pipe_transfer *transfer,
520 const struct pipe_box *rel_box)
521 {
522 unsigned required_usage = PIPE_TRANSFER_WRITE |
523 PIPE_TRANSFER_FLUSH_EXPLICIT;
524
525 if ((transfer->usage & required_usage) == required_usage) {
526 struct pipe_box box;
527
528 u_box_1d(transfer->box.x + rel_box->x, rel_box->width, &box);
529 r600_buffer_do_flush_region(ctx, transfer, &box);
530 }
531 }
532
533 static void r600_buffer_transfer_unmap(struct pipe_context *ctx,
534 struct pipe_transfer *transfer)
535 {
536 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
537 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
538
539 if (transfer->usage & PIPE_TRANSFER_WRITE &&
540 !(transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT))
541 r600_buffer_do_flush_region(ctx, transfer, &transfer->box);
542
543 r600_resource_reference(&rtransfer->staging, NULL);
544 assert(rtransfer->b.staging == NULL); /* for threaded context only */
545 pipe_resource_reference(&transfer->resource, NULL);
546
547 /* Don't use pool_transfers_unsync. We are always in the driver
548 * thread. */
549 slab_free(&rctx->pool_transfers, transfer);
550 }
551
552 static void si_buffer_subdata(struct pipe_context *ctx,
553 struct pipe_resource *buffer,
554 unsigned usage, unsigned offset,
555 unsigned size, const void *data)
556 {
557 struct pipe_transfer *transfer = NULL;
558 struct pipe_box box;
559 uint8_t *map = NULL;
560
561 u_box_1d(offset, size, &box);
562 map = r600_buffer_transfer_map(ctx, buffer, 0,
563 PIPE_TRANSFER_WRITE |
564 PIPE_TRANSFER_DISCARD_RANGE |
565 usage,
566 &box, &transfer);
567 if (!map)
568 return;
569
570 memcpy(map, data, size);
571 r600_buffer_transfer_unmap(ctx, transfer);
572 }
573
574 static const struct u_resource_vtbl r600_buffer_vtbl =
575 {
576 NULL, /* get_handle */
577 r600_buffer_destroy, /* resource_destroy */
578 r600_buffer_transfer_map, /* transfer_map */
579 r600_buffer_flush_region, /* transfer_flush_region */
580 r600_buffer_transfer_unmap, /* transfer_unmap */
581 };
582
583 static struct r600_resource *
584 r600_alloc_buffer_struct(struct pipe_screen *screen,
585 const struct pipe_resource *templ)
586 {
587 struct r600_resource *rbuffer;
588
589 rbuffer = MALLOC_STRUCT(r600_resource);
590
591 rbuffer->b.b = *templ;
592 rbuffer->b.b.next = NULL;
593 pipe_reference_init(&rbuffer->b.b.reference, 1);
594 rbuffer->b.b.screen = screen;
595
596 rbuffer->b.vtbl = &r600_buffer_vtbl;
597 threaded_resource_init(&rbuffer->b.b);
598
599 rbuffer->buf = NULL;
600 rbuffer->bind_history = 0;
601 rbuffer->TC_L2_dirty = false;
602 util_range_init(&rbuffer->valid_buffer_range);
603 return rbuffer;
604 }
605
606 static struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
607 const struct pipe_resource *templ,
608 unsigned alignment)
609 {
610 struct si_screen *sscreen = (struct si_screen*)screen;
611 struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
612
613 si_init_resource_fields(sscreen, rbuffer, templ->width0, alignment);
614
615 if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
616 rbuffer->flags |= RADEON_FLAG_SPARSE;
617
618 if (!si_alloc_resource(sscreen, rbuffer)) {
619 FREE(rbuffer);
620 return NULL;
621 }
622 return &rbuffer->b.b;
623 }
624
625 struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
626 unsigned flags,
627 unsigned usage,
628 unsigned size,
629 unsigned alignment)
630 {
631 struct pipe_resource buffer;
632
633 memset(&buffer, 0, sizeof buffer);
634 buffer.target = PIPE_BUFFER;
635 buffer.format = PIPE_FORMAT_R8_UNORM;
636 buffer.bind = 0;
637 buffer.usage = usage;
638 buffer.flags = flags;
639 buffer.width0 = size;
640 buffer.height0 = 1;
641 buffer.depth0 = 1;
642 buffer.array_size = 1;
643 return si_buffer_create(screen, &buffer, alignment);
644 }
645
646 static struct pipe_resource *
647 si_buffer_from_user_memory(struct pipe_screen *screen,
648 const struct pipe_resource *templ,
649 void *user_memory)
650 {
651 struct si_screen *sscreen = (struct si_screen*)screen;
652 struct radeon_winsys *ws = sscreen->ws;
653 struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
654
655 rbuffer->domains = RADEON_DOMAIN_GTT;
656 rbuffer->flags = 0;
657 rbuffer->b.is_user_ptr = true;
658 util_range_add(&rbuffer->valid_buffer_range, 0, templ->width0);
659 util_range_add(&rbuffer->b.valid_buffer_range, 0, templ->width0);
660
661 /* Convert a user pointer to a buffer. */
662 rbuffer->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0);
663 if (!rbuffer->buf) {
664 FREE(rbuffer);
665 return NULL;
666 }
667
668 if (sscreen->info.has_virtual_memory)
669 rbuffer->gpu_address =
670 ws->buffer_get_virtual_address(rbuffer->buf);
671 else
672 rbuffer->gpu_address = 0;
673
674 rbuffer->vram_usage = 0;
675 rbuffer->gart_usage = templ->width0;
676
677 return &rbuffer->b.b;
678 }
679
680 static struct pipe_resource *si_resource_create(struct pipe_screen *screen,
681 const struct pipe_resource *templ)
682 {
683 if (templ->target == PIPE_BUFFER) {
684 return si_buffer_create(screen, templ, 256);
685 } else {
686 return si_texture_create(screen, templ);
687 }
688 }
689
690 void si_init_screen_buffer_functions(struct si_screen *sscreen)
691 {
692 sscreen->b.resource_create = si_resource_create;
693 sscreen->b.resource_destroy = u_resource_destroy_vtbl;
694 sscreen->b.resource_from_user_memory = si_buffer_from_user_memory;
695 }
696
697 void si_init_buffer_functions(struct si_context *sctx)
698 {
699 sctx->b.b.invalidate_resource = si_invalidate_resource;
700 sctx->b.b.transfer_map = u_transfer_map_vtbl;
701 sctx->b.b.transfer_flush_region = u_transfer_flush_region_vtbl;
702 sctx->b.b.transfer_unmap = u_transfer_unmap_vtbl;
703 sctx->b.b.texture_subdata = u_default_texture_subdata;
704 sctx->b.b.buffer_subdata = si_buffer_subdata;
705 }