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gallium/radeon: emit relocations for query fences
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 struct r600_multi_fence {
47 struct pipe_reference reference;
48 struct pipe_fence_handle *gfx;
49 struct pipe_fence_handle *sdma;
50
51 /* If the context wasn't flushed at fence creation, this is non-NULL. */
52 struct {
53 struct r600_common_context *ctx;
54 unsigned ib_index;
55 } gfx_unflushed;
56 };
57
58 /*
59 * shader binary helpers.
60 */
61 void radeon_shader_binary_init(struct radeon_shader_binary *b)
62 {
63 memset(b, 0, sizeof(*b));
64 }
65
66 void radeon_shader_binary_clean(struct radeon_shader_binary *b)
67 {
68 if (!b)
69 return;
70 FREE(b->code);
71 FREE(b->config);
72 FREE(b->rodata);
73 FREE(b->global_symbol_offsets);
74 FREE(b->relocs);
75 FREE(b->disasm_string);
76 FREE(b->llvm_ir_string);
77 }
78
79 /*
80 * pipe_context
81 */
82
83 void r600_gfx_write_fence(struct r600_common_context *ctx, struct r600_resource *buf,
84 uint64_t va, uint32_t old_value, uint32_t new_value)
85 {
86 struct radeon_winsys_cs *cs = ctx->gfx.cs;
87
88 if (ctx->chip_class == CIK) {
89 /* Two EOP events are required to make all engines go idle
90 * (and optional cache flushes executed) before the timestamp
91 * is written.
92 */
93 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
94 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
95 EVENT_INDEX(5));
96 radeon_emit(cs, va);
97 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
98 radeon_emit(cs, old_value); /* immediate data */
99 radeon_emit(cs, 0); /* unused */
100 }
101
102 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
103 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
104 EVENT_INDEX(5));
105 radeon_emit(cs, va);
106 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
107 radeon_emit(cs, new_value); /* immediate data */
108 radeon_emit(cs, 0); /* unused */
109
110 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
111 }
112
113 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
114 {
115 unsigned dwords = 6;
116
117 if (screen->chip_class == CIK)
118 dwords *= 2;
119
120 if (!screen->info.has_virtual_memory)
121 dwords += 2;
122
123 return dwords;
124 }
125
126 void r600_gfx_wait_fence(struct r600_common_context *ctx,
127 uint64_t va, uint32_t ref, uint32_t mask)
128 {
129 struct radeon_winsys_cs *cs = ctx->gfx.cs;
130
131 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
132 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
133 radeon_emit(cs, va);
134 radeon_emit(cs, va >> 32);
135 radeon_emit(cs, ref); /* reference value */
136 radeon_emit(cs, mask); /* mask */
137 radeon_emit(cs, 4); /* poll interval */
138 }
139
140 void r600_draw_rectangle(struct blitter_context *blitter,
141 int x1, int y1, int x2, int y2, float depth,
142 enum blitter_attrib_type type,
143 const union pipe_color_union *attrib)
144 {
145 struct r600_common_context *rctx =
146 (struct r600_common_context*)util_blitter_get_pipe(blitter);
147 struct pipe_viewport_state viewport;
148 struct pipe_resource *buf = NULL;
149 unsigned offset = 0;
150 float *vb;
151
152 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
153 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
154 return;
155 }
156
157 /* Some operations (like color resolve on r6xx) don't work
158 * with the conventional primitive types.
159 * One that works is PT_RECTLIST, which we use here. */
160
161 /* setup viewport */
162 viewport.scale[0] = 1.0f;
163 viewport.scale[1] = 1.0f;
164 viewport.scale[2] = 1.0f;
165 viewport.translate[0] = 0.0f;
166 viewport.translate[1] = 0.0f;
167 viewport.translate[2] = 0.0f;
168 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
169
170 /* Upload vertices. The hw rectangle has only 3 vertices,
171 * I guess the 4th one is derived from the first 3.
172 * The vertex specification should match u_blitter's vertex element state. */
173 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, 256, &offset, &buf, (void**)&vb);
174 if (!buf)
175 return;
176
177 vb[0] = x1;
178 vb[1] = y1;
179 vb[2] = depth;
180 vb[3] = 1;
181
182 vb[8] = x1;
183 vb[9] = y2;
184 vb[10] = depth;
185 vb[11] = 1;
186
187 vb[16] = x2;
188 vb[17] = y1;
189 vb[18] = depth;
190 vb[19] = 1;
191
192 if (attrib) {
193 memcpy(vb+4, attrib->f, sizeof(float)*4);
194 memcpy(vb+12, attrib->f, sizeof(float)*4);
195 memcpy(vb+20, attrib->f, sizeof(float)*4);
196 }
197
198 /* draw */
199 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
200 R600_PRIM_RECTANGLE_LIST, 3, 2);
201 pipe_resource_reference(&buf, NULL);
202 }
203
204 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
205 struct r600_resource *dst, struct r600_resource *src)
206 {
207 uint64_t vram = 0, gtt = 0;
208
209 if (dst) {
210 vram += dst->vram_usage;
211 gtt += dst->gart_usage;
212 }
213 if (src) {
214 vram += src->vram_usage;
215 gtt += src->gart_usage;
216 }
217
218 /* Flush the GFX IB if DMA depends on it. */
219 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
220 ((dst &&
221 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
222 RADEON_USAGE_READWRITE)) ||
223 (src &&
224 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
225 RADEON_USAGE_WRITE))))
226 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
227
228 /* Flush if there's not enough space, or if the memory usage per IB
229 * is too large.
230 */
231 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
232 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
233 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
234 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
235 }
236
237 /* If GPUVM is not supported, the CS checker needs 2 entries
238 * in the buffer list per packet, which has to be done manually.
239 */
240 if (ctx->screen->info.has_virtual_memory) {
241 if (dst)
242 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
243 RADEON_USAGE_WRITE,
244 RADEON_PRIO_SDMA_BUFFER);
245 if (src)
246 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
247 RADEON_USAGE_READ,
248 RADEON_PRIO_SDMA_BUFFER);
249 }
250 }
251
252 /* This is required to prevent read-after-write hazards. */
253 void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
254 {
255 struct radeon_winsys_cs *cs = rctx->dma.cs;
256
257 /* done at the end of DMA calls, so increment this. */
258 rctx->num_dma_calls++;
259
260 /* IBs using too little memory are limited by the IB submission overhead.
261 * IBs using too much memory are limited by the kernel/TTM overhead.
262 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
263 *
264 * This heuristic makes sure that DMA requests are executed
265 * very soon after the call is made and lowers memory usage.
266 * It improves texture upload performance by keeping the DMA
267 * engine busy while uploads are being submitted.
268 */
269 if (cs->used_vram + cs->used_gart > 64 * 1024 * 1024) {
270 rctx->dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
271 return;
272 }
273
274 r600_need_dma_space(rctx, 1, NULL, NULL);
275
276 if (!radeon_emitted(cs, 0)) /* empty queue */
277 return;
278
279 /* NOP waits for idle on Evergreen and later. */
280 if (rctx->chip_class >= CIK)
281 radeon_emit(cs, 0x00000000); /* NOP */
282 else if (rctx->chip_class >= EVERGREEN)
283 radeon_emit(cs, 0xf0000000); /* NOP */
284 else {
285 /* TODO: R600-R700 should use the FENCE packet.
286 * CS checker support is required. */
287 }
288 }
289
290 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
291 {
292 }
293
294 void r600_preflush_suspend_features(struct r600_common_context *ctx)
295 {
296 /* suspend queries */
297 if (!LIST_IS_EMPTY(&ctx->active_queries))
298 r600_suspend_queries(ctx);
299
300 ctx->streamout.suspended = false;
301 if (ctx->streamout.begin_emitted) {
302 r600_emit_streamout_end(ctx);
303 ctx->streamout.suspended = true;
304 }
305 }
306
307 void r600_postflush_resume_features(struct r600_common_context *ctx)
308 {
309 if (ctx->streamout.suspended) {
310 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
311 r600_streamout_buffers_dirty(ctx);
312 }
313
314 /* resume queries */
315 if (!LIST_IS_EMPTY(&ctx->active_queries))
316 r600_resume_queries(ctx);
317 }
318
319 static void r600_flush_from_st(struct pipe_context *ctx,
320 struct pipe_fence_handle **fence,
321 unsigned flags)
322 {
323 struct pipe_screen *screen = ctx->screen;
324 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
325 struct radeon_winsys *ws = rctx->ws;
326 unsigned rflags = 0;
327 struct pipe_fence_handle *gfx_fence = NULL;
328 struct pipe_fence_handle *sdma_fence = NULL;
329 bool deferred_fence = false;
330
331 if (flags & PIPE_FLUSH_END_OF_FRAME)
332 rflags |= RADEON_FLUSH_END_OF_FRAME;
333 if (flags & PIPE_FLUSH_DEFERRED)
334 rflags |= RADEON_FLUSH_ASYNC;
335
336 if (rctx->dma.cs) {
337 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
338 }
339
340 if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
341 if (fence)
342 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
343 if (!(rflags & RADEON_FLUSH_ASYNC))
344 ws->cs_sync_flush(rctx->gfx.cs);
345 } else {
346 /* Instead of flushing, create a deferred fence. Constraints:
347 * - The state tracker must allow a deferred flush.
348 * - The state tracker must request a fence.
349 * Thread safety in fence_finish must be ensured by the state tracker.
350 */
351 if (flags & PIPE_FLUSH_DEFERRED && fence) {
352 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
353 deferred_fence = true;
354 } else {
355 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
356 }
357 }
358
359 /* Both engines can signal out of order, so we need to keep both fences. */
360 if (fence) {
361 struct r600_multi_fence *multi_fence =
362 CALLOC_STRUCT(r600_multi_fence);
363 if (!multi_fence)
364 return;
365
366 multi_fence->reference.count = 1;
367 /* If both fences are NULL, fence_finish will always return true. */
368 multi_fence->gfx = gfx_fence;
369 multi_fence->sdma = sdma_fence;
370
371 if (deferred_fence) {
372 multi_fence->gfx_unflushed.ctx = rctx;
373 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
374 }
375
376 screen->fence_reference(screen, fence, NULL);
377 *fence = (struct pipe_fence_handle*)multi_fence;
378 }
379 }
380
381 static void r600_flush_dma_ring(void *ctx, unsigned flags,
382 struct pipe_fence_handle **fence)
383 {
384 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
385 struct radeon_winsys_cs *cs = rctx->dma.cs;
386 struct radeon_saved_cs saved;
387 bool check_vm =
388 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
389 rctx->check_vm_faults;
390
391 if (!radeon_emitted(cs, 0)) {
392 if (fence)
393 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
394 return;
395 }
396
397 if (check_vm)
398 radeon_save_cs(rctx->ws, cs, &saved);
399
400 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
401 if (fence)
402 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
403
404 if (check_vm) {
405 /* Use conservative timeout 800ms, after which we won't wait any
406 * longer and assume the GPU is hung.
407 */
408 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
409
410 rctx->check_vm_faults(rctx, &saved, RING_DMA);
411 radeon_clear_saved_cs(&saved);
412 }
413 }
414
415 /**
416 * Store a linearized copy of all chunks of \p cs together with the buffer
417 * list in \p saved.
418 */
419 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
420 struct radeon_saved_cs *saved)
421 {
422 void *buf;
423 unsigned i;
424
425 /* Save the IB chunks. */
426 saved->num_dw = cs->prev_dw + cs->current.cdw;
427 saved->ib = MALLOC(4 * saved->num_dw);
428 if (!saved->ib)
429 goto oom;
430
431 buf = saved->ib;
432 for (i = 0; i < cs->num_prev; ++i) {
433 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
434 buf += cs->prev[i].cdw;
435 }
436 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
437
438 /* Save the buffer list. */
439 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
440 saved->bo_list = CALLOC(saved->bo_count,
441 sizeof(saved->bo_list[0]));
442 if (!saved->bo_list) {
443 FREE(saved->ib);
444 goto oom;
445 }
446 ws->cs_get_buffer_list(cs, saved->bo_list);
447
448 return;
449
450 oom:
451 fprintf(stderr, "%s: out of memory\n", __func__);
452 memset(saved, 0, sizeof(*saved));
453 }
454
455 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
456 {
457 FREE(saved->ib);
458 FREE(saved->bo_list);
459
460 memset(saved, 0, sizeof(*saved));
461 }
462
463 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
464 {
465 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
466 unsigned latest = rctx->ws->query_value(rctx->ws,
467 RADEON_GPU_RESET_COUNTER);
468
469 if (rctx->gpu_reset_counter == latest)
470 return PIPE_NO_RESET;
471
472 rctx->gpu_reset_counter = latest;
473 return PIPE_UNKNOWN_CONTEXT_RESET;
474 }
475
476 static void r600_set_debug_callback(struct pipe_context *ctx,
477 const struct pipe_debug_callback *cb)
478 {
479 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
480
481 if (cb)
482 rctx->debug = *cb;
483 else
484 memset(&rctx->debug, 0, sizeof(rctx->debug));
485 }
486
487 bool r600_common_context_init(struct r600_common_context *rctx,
488 struct r600_common_screen *rscreen,
489 unsigned context_flags)
490 {
491 slab_create(&rctx->pool_transfers,
492 sizeof(struct r600_transfer), 64);
493
494 rctx->screen = rscreen;
495 rctx->ws = rscreen->ws;
496 rctx->family = rscreen->family;
497 rctx->chip_class = rscreen->chip_class;
498
499 if (rscreen->chip_class >= CIK)
500 rctx->max_db = MAX2(8, rscreen->info.num_render_backends);
501 else if (rscreen->chip_class >= EVERGREEN)
502 rctx->max_db = 8;
503 else
504 rctx->max_db = 4;
505
506 rctx->b.invalidate_resource = r600_invalidate_resource;
507 rctx->b.transfer_map = u_transfer_map_vtbl;
508 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
509 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
510 rctx->b.texture_subdata = u_default_texture_subdata;
511 rctx->b.memory_barrier = r600_memory_barrier;
512 rctx->b.flush = r600_flush_from_st;
513 rctx->b.set_debug_callback = r600_set_debug_callback;
514
515 /* evergreen_compute.c has a special codepath for global buffers.
516 * Everything else can use the direct path.
517 */
518 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
519 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
520 rctx->b.buffer_subdata = u_default_buffer_subdata;
521 else
522 rctx->b.buffer_subdata = r600_buffer_subdata;
523
524 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
525 rctx->b.get_device_reset_status = r600_get_reset_status;
526 rctx->gpu_reset_counter =
527 rctx->ws->query_value(rctx->ws,
528 RADEON_GPU_RESET_COUNTER);
529 }
530
531 LIST_INITHEAD(&rctx->texture_buffers);
532
533 r600_init_context_texture_functions(rctx);
534 r600_init_viewport_functions(rctx);
535 r600_streamout_init(rctx);
536 r600_query_init(rctx);
537 cayman_init_msaa(&rctx->b);
538
539 rctx->allocator_zeroed_memory =
540 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
541 0, PIPE_USAGE_DEFAULT, true);
542 if (!rctx->allocator_zeroed_memory)
543 return false;
544
545 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024,
546 PIPE_BIND_INDEX_BUFFER |
547 PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM);
548 if (!rctx->uploader)
549 return false;
550
551 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
552 if (!rctx->ctx)
553 return false;
554
555 if (rscreen->info.has_sdma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
556 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
557 r600_flush_dma_ring,
558 rctx);
559 rctx->dma.flush = r600_flush_dma_ring;
560 }
561
562 return true;
563 }
564
565 void r600_common_context_cleanup(struct r600_common_context *rctx)
566 {
567 unsigned i,j;
568
569 /* Release DCC stats. */
570 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
571 assert(!rctx->dcc_stats[i].query_active);
572
573 for (j = 0; j < ARRAY_SIZE(rctx->dcc_stats[i].ps_stats); j++)
574 if (rctx->dcc_stats[i].ps_stats[j])
575 rctx->b.destroy_query(&rctx->b,
576 rctx->dcc_stats[i].ps_stats[j]);
577
578 r600_texture_reference(&rctx->dcc_stats[i].tex, NULL);
579 }
580
581 if (rctx->query_result_shader)
582 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
583
584 if (rctx->gfx.cs)
585 rctx->ws->cs_destroy(rctx->gfx.cs);
586 if (rctx->dma.cs)
587 rctx->ws->cs_destroy(rctx->dma.cs);
588 if (rctx->ctx)
589 rctx->ws->ctx_destroy(rctx->ctx);
590
591 if (rctx->uploader) {
592 u_upload_destroy(rctx->uploader);
593 }
594
595 slab_destroy(&rctx->pool_transfers);
596
597 if (rctx->allocator_zeroed_memory) {
598 u_suballocator_destroy(rctx->allocator_zeroed_memory);
599 }
600 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
601 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
602 }
603
604 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
605 {
606 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
607 struct r600_resource *rr = (struct r600_resource *)r;
608
609 if (!r) {
610 return;
611 }
612
613 /*
614 * The idea is to compute a gross estimate of memory requirement of
615 * each draw call. After each draw call, memory will be precisely
616 * accounted. So the uncertainty is only on the current draw call.
617 * In practice this gave very good estimate (+/- 10% of the target
618 * memory limit).
619 */
620 rctx->vram += rr->vram_usage;
621 rctx->gtt += rr->gart_usage;
622 }
623
624 /*
625 * pipe_screen
626 */
627
628 static const struct debug_named_value common_debug_options[] = {
629 /* logging */
630 { "tex", DBG_TEX, "Print texture info" },
631 { "compute", DBG_COMPUTE, "Print compute info" },
632 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
633 { "info", DBG_INFO, "Print driver information" },
634
635 /* shaders */
636 { "fs", DBG_FS, "Print fetch shaders" },
637 { "vs", DBG_VS, "Print vertex shaders" },
638 { "gs", DBG_GS, "Print geometry shaders" },
639 { "ps", DBG_PS, "Print pixel shaders" },
640 { "cs", DBG_CS, "Print compute shaders" },
641 { "tcs", DBG_TCS, "Print tessellation control shaders" },
642 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
643 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
644 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
645 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
646 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
647
648 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
649
650 /* features */
651 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
652 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
653 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
654 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
655 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
656 { "notiling", DBG_NO_TILING, "Disable tiling" },
657 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
658 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
659 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
660 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
661 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
662 { "nodcc", DBG_NO_DCC, "Disable DCC." },
663 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
664 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
665 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
666 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
667 { "noce", DBG_NO_CE, "Disable the constant engine"},
668 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
669 { "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
670
671 DEBUG_NAMED_VALUE_END /* must be last */
672 };
673
674 static const char* r600_get_vendor(struct pipe_screen* pscreen)
675 {
676 return "X.Org";
677 }
678
679 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
680 {
681 return "AMD";
682 }
683
684 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
685 {
686 switch (rscreen->info.family) {
687 case CHIP_R600: return "AMD R600";
688 case CHIP_RV610: return "AMD RV610";
689 case CHIP_RV630: return "AMD RV630";
690 case CHIP_RV670: return "AMD RV670";
691 case CHIP_RV620: return "AMD RV620";
692 case CHIP_RV635: return "AMD RV635";
693 case CHIP_RS780: return "AMD RS780";
694 case CHIP_RS880: return "AMD RS880";
695 case CHIP_RV770: return "AMD RV770";
696 case CHIP_RV730: return "AMD RV730";
697 case CHIP_RV710: return "AMD RV710";
698 case CHIP_RV740: return "AMD RV740";
699 case CHIP_CEDAR: return "AMD CEDAR";
700 case CHIP_REDWOOD: return "AMD REDWOOD";
701 case CHIP_JUNIPER: return "AMD JUNIPER";
702 case CHIP_CYPRESS: return "AMD CYPRESS";
703 case CHIP_HEMLOCK: return "AMD HEMLOCK";
704 case CHIP_PALM: return "AMD PALM";
705 case CHIP_SUMO: return "AMD SUMO";
706 case CHIP_SUMO2: return "AMD SUMO2";
707 case CHIP_BARTS: return "AMD BARTS";
708 case CHIP_TURKS: return "AMD TURKS";
709 case CHIP_CAICOS: return "AMD CAICOS";
710 case CHIP_CAYMAN: return "AMD CAYMAN";
711 case CHIP_ARUBA: return "AMD ARUBA";
712 case CHIP_TAHITI: return "AMD TAHITI";
713 case CHIP_PITCAIRN: return "AMD PITCAIRN";
714 case CHIP_VERDE: return "AMD CAPE VERDE";
715 case CHIP_OLAND: return "AMD OLAND";
716 case CHIP_HAINAN: return "AMD HAINAN";
717 case CHIP_BONAIRE: return "AMD BONAIRE";
718 case CHIP_KAVERI: return "AMD KAVERI";
719 case CHIP_KABINI: return "AMD KABINI";
720 case CHIP_HAWAII: return "AMD HAWAII";
721 case CHIP_MULLINS: return "AMD MULLINS";
722 case CHIP_TONGA: return "AMD TONGA";
723 case CHIP_ICELAND: return "AMD ICELAND";
724 case CHIP_CARRIZO: return "AMD CARRIZO";
725 case CHIP_FIJI: return "AMD FIJI";
726 case CHIP_POLARIS10: return "AMD POLARIS10";
727 case CHIP_POLARIS11: return "AMD POLARIS11";
728 case CHIP_STONEY: return "AMD STONEY";
729 default: return "AMD unknown";
730 }
731 }
732
733 static const char* r600_get_name(struct pipe_screen* pscreen)
734 {
735 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
736
737 return rscreen->renderer_string;
738 }
739
740 static float r600_get_paramf(struct pipe_screen* pscreen,
741 enum pipe_capf param)
742 {
743 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
744
745 switch (param) {
746 case PIPE_CAPF_MAX_LINE_WIDTH:
747 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
748 case PIPE_CAPF_MAX_POINT_WIDTH:
749 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
750 if (rscreen->family >= CHIP_CEDAR)
751 return 16384.0f;
752 else
753 return 8192.0f;
754 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
755 return 16.0f;
756 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
757 return 16.0f;
758 case PIPE_CAPF_GUARD_BAND_LEFT:
759 case PIPE_CAPF_GUARD_BAND_TOP:
760 case PIPE_CAPF_GUARD_BAND_RIGHT:
761 case PIPE_CAPF_GUARD_BAND_BOTTOM:
762 return 0.0f;
763 }
764 return 0.0f;
765 }
766
767 static int r600_get_video_param(struct pipe_screen *screen,
768 enum pipe_video_profile profile,
769 enum pipe_video_entrypoint entrypoint,
770 enum pipe_video_cap param)
771 {
772 switch (param) {
773 case PIPE_VIDEO_CAP_SUPPORTED:
774 return vl_profile_supported(screen, profile, entrypoint);
775 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
776 return 1;
777 case PIPE_VIDEO_CAP_MAX_WIDTH:
778 case PIPE_VIDEO_CAP_MAX_HEIGHT:
779 return vl_video_buffer_max_size(screen);
780 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
781 return PIPE_FORMAT_NV12;
782 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
783 return false;
784 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
785 return false;
786 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
787 return true;
788 case PIPE_VIDEO_CAP_MAX_LEVEL:
789 return vl_level_supported(screen, profile);
790 default:
791 return 0;
792 }
793 }
794
795 const char *r600_get_llvm_processor_name(enum radeon_family family)
796 {
797 switch (family) {
798 case CHIP_R600:
799 case CHIP_RV630:
800 case CHIP_RV635:
801 case CHIP_RV670:
802 return "r600";
803 case CHIP_RV610:
804 case CHIP_RV620:
805 case CHIP_RS780:
806 case CHIP_RS880:
807 return "rs880";
808 case CHIP_RV710:
809 return "rv710";
810 case CHIP_RV730:
811 return "rv730";
812 case CHIP_RV740:
813 case CHIP_RV770:
814 return "rv770";
815 case CHIP_PALM:
816 case CHIP_CEDAR:
817 return "cedar";
818 case CHIP_SUMO:
819 case CHIP_SUMO2:
820 return "sumo";
821 case CHIP_REDWOOD:
822 return "redwood";
823 case CHIP_JUNIPER:
824 return "juniper";
825 case CHIP_HEMLOCK:
826 case CHIP_CYPRESS:
827 return "cypress";
828 case CHIP_BARTS:
829 return "barts";
830 case CHIP_TURKS:
831 return "turks";
832 case CHIP_CAICOS:
833 return "caicos";
834 case CHIP_CAYMAN:
835 case CHIP_ARUBA:
836 return "cayman";
837
838 case CHIP_TAHITI: return "tahiti";
839 case CHIP_PITCAIRN: return "pitcairn";
840 case CHIP_VERDE: return "verde";
841 case CHIP_OLAND: return "oland";
842 case CHIP_HAINAN: return "hainan";
843 case CHIP_BONAIRE: return "bonaire";
844 case CHIP_KABINI: return "kabini";
845 case CHIP_KAVERI: return "kaveri";
846 case CHIP_HAWAII: return "hawaii";
847 case CHIP_MULLINS:
848 return "mullins";
849 case CHIP_TONGA: return "tonga";
850 case CHIP_ICELAND: return "iceland";
851 case CHIP_CARRIZO: return "carrizo";
852 #if HAVE_LLVM <= 0x0307
853 case CHIP_FIJI: return "tonga";
854 case CHIP_STONEY: return "carrizo";
855 #else
856 case CHIP_FIJI: return "fiji";
857 case CHIP_STONEY: return "stoney";
858 #endif
859 #if HAVE_LLVM <= 0x0308
860 case CHIP_POLARIS10: return "tonga";
861 case CHIP_POLARIS11: return "tonga";
862 #else
863 case CHIP_POLARIS10: return "polaris10";
864 case CHIP_POLARIS11: return "polaris11";
865 #endif
866 default: return "";
867 }
868 }
869
870 static int r600_get_compute_param(struct pipe_screen *screen,
871 enum pipe_shader_ir ir_type,
872 enum pipe_compute_cap param,
873 void *ret)
874 {
875 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
876
877 //TODO: select these params by asic
878 switch (param) {
879 case PIPE_COMPUTE_CAP_IR_TARGET: {
880 const char *gpu;
881 const char *triple;
882 if (rscreen->family <= CHIP_ARUBA) {
883 triple = "r600--";
884 } else {
885 if (HAVE_LLVM < 0x0400) {
886 triple = "amdgcn--";
887 } else {
888 triple = "amdgcn-mesa-mesa3d";
889 }
890 }
891 switch(rscreen->family) {
892 /* Clang < 3.6 is missing Hainan in its list of
893 * GPUs, so we need to use the name of a similar GPU.
894 */
895 default:
896 gpu = r600_get_llvm_processor_name(rscreen->family);
897 break;
898 }
899 if (ret) {
900 sprintf(ret, "%s-%s", gpu, triple);
901 }
902 /* +2 for dash and terminating NIL byte */
903 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
904 }
905 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
906 if (ret) {
907 uint64_t *grid_dimension = ret;
908 grid_dimension[0] = 3;
909 }
910 return 1 * sizeof(uint64_t);
911
912 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
913 if (ret) {
914 uint64_t *grid_size = ret;
915 grid_size[0] = 65535;
916 grid_size[1] = 65535;
917 grid_size[2] = 65535;
918 }
919 return 3 * sizeof(uint64_t) ;
920
921 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
922 if (ret) {
923 uint64_t *block_size = ret;
924 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
925 ir_type == PIPE_SHADER_IR_TGSI) {
926 block_size[0] = 2048;
927 block_size[1] = 2048;
928 block_size[2] = 2048;
929 } else {
930 block_size[0] = 256;
931 block_size[1] = 256;
932 block_size[2] = 256;
933 }
934 }
935 return 3 * sizeof(uint64_t);
936
937 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
938 if (ret) {
939 uint64_t *max_threads_per_block = ret;
940 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
941 ir_type == PIPE_SHADER_IR_TGSI)
942 *max_threads_per_block = 2048;
943 else
944 *max_threads_per_block = 256;
945 }
946 return sizeof(uint64_t);
947 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
948 if (ret) {
949 uint32_t *address_bits = ret;
950 address_bits[0] = 32;
951 if (rscreen->chip_class >= SI)
952 address_bits[0] = 64;
953 }
954 return 1 * sizeof(uint32_t);
955
956 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
957 if (ret) {
958 uint64_t *max_global_size = ret;
959 uint64_t max_mem_alloc_size;
960
961 r600_get_compute_param(screen, ir_type,
962 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
963 &max_mem_alloc_size);
964
965 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
966 * 1/4 of the MAX_GLOBAL_SIZE. Since the
967 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
968 * make sure we never report more than
969 * 4 * MAX_MEM_ALLOC_SIZE.
970 */
971 *max_global_size = MIN2(4 * max_mem_alloc_size,
972 MAX2(rscreen->info.gart_size,
973 rscreen->info.vram_size));
974 }
975 return sizeof(uint64_t);
976
977 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
978 if (ret) {
979 uint64_t *max_local_size = ret;
980 /* Value reported by the closed source driver. */
981 *max_local_size = 32768;
982 }
983 return sizeof(uint64_t);
984
985 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
986 if (ret) {
987 uint64_t *max_input_size = ret;
988 /* Value reported by the closed source driver. */
989 *max_input_size = 1024;
990 }
991 return sizeof(uint64_t);
992
993 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
994 if (ret) {
995 uint64_t *max_mem_alloc_size = ret;
996
997 *max_mem_alloc_size = rscreen->info.max_alloc_size;
998 }
999 return sizeof(uint64_t);
1000
1001 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1002 if (ret) {
1003 uint32_t *max_clock_frequency = ret;
1004 *max_clock_frequency = rscreen->info.max_shader_clock;
1005 }
1006 return sizeof(uint32_t);
1007
1008 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1009 if (ret) {
1010 uint32_t *max_compute_units = ret;
1011 *max_compute_units = rscreen->info.num_good_compute_units;
1012 }
1013 return sizeof(uint32_t);
1014
1015 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1016 if (ret) {
1017 uint32_t *images_supported = ret;
1018 *images_supported = 0;
1019 }
1020 return sizeof(uint32_t);
1021 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1022 break; /* unused */
1023 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1024 if (ret) {
1025 uint32_t *subgroup_size = ret;
1026 *subgroup_size = r600_wavefront_size(rscreen->family);
1027 }
1028 return sizeof(uint32_t);
1029 }
1030
1031 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1032 return 0;
1033 }
1034
1035 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1036 {
1037 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1038
1039 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1040 rscreen->info.clock_crystal_freq;
1041 }
1042
1043 static void r600_fence_reference(struct pipe_screen *screen,
1044 struct pipe_fence_handle **dst,
1045 struct pipe_fence_handle *src)
1046 {
1047 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1048 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1049 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1050
1051 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1052 ws->fence_reference(&(*rdst)->gfx, NULL);
1053 ws->fence_reference(&(*rdst)->sdma, NULL);
1054 FREE(*rdst);
1055 }
1056 *rdst = rsrc;
1057 }
1058
1059 static boolean r600_fence_finish(struct pipe_screen *screen,
1060 struct pipe_context *ctx,
1061 struct pipe_fence_handle *fence,
1062 uint64_t timeout)
1063 {
1064 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1065 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1066 struct r600_common_context *rctx =
1067 ctx ? (struct r600_common_context*)ctx : NULL;
1068 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1069
1070 if (rfence->sdma) {
1071 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1072 return false;
1073
1074 /* Recompute the timeout after waiting. */
1075 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1076 int64_t time = os_time_get_nano();
1077 timeout = abs_timeout > time ? abs_timeout - time : 0;
1078 }
1079 }
1080
1081 if (!rfence->gfx)
1082 return true;
1083
1084 /* Flush the gfx IB if it hasn't been flushed yet. */
1085 if (rctx &&
1086 rfence->gfx_unflushed.ctx == rctx &&
1087 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1088 rctx->gfx.flush(rctx, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
1089 rfence->gfx_unflushed.ctx = NULL;
1090
1091 if (!timeout)
1092 return false;
1093
1094 /* Recompute the timeout after all that. */
1095 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1096 int64_t time = os_time_get_nano();
1097 timeout = abs_timeout > time ? abs_timeout - time : 0;
1098 }
1099 }
1100
1101 return rws->fence_wait(rws, rfence->gfx, timeout);
1102 }
1103
1104 static void r600_query_memory_info(struct pipe_screen *screen,
1105 struct pipe_memory_info *info)
1106 {
1107 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1108 struct radeon_winsys *ws = rscreen->ws;
1109 unsigned vram_usage, gtt_usage;
1110
1111 info->total_device_memory = rscreen->info.vram_size / 1024;
1112 info->total_staging_memory = rscreen->info.gart_size / 1024;
1113
1114 /* The real TTM memory usage is somewhat random, because:
1115 *
1116 * 1) TTM delays freeing memory, because it can only free it after
1117 * fences expire.
1118 *
1119 * 2) The memory usage can be really low if big VRAM evictions are
1120 * taking place, but the real usage is well above the size of VRAM.
1121 *
1122 * Instead, return statistics of this process.
1123 */
1124 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1125 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1126
1127 info->avail_device_memory =
1128 vram_usage <= info->total_device_memory ?
1129 info->total_device_memory - vram_usage : 0;
1130 info->avail_staging_memory =
1131 gtt_usage <= info->total_staging_memory ?
1132 info->total_staging_memory - gtt_usage : 0;
1133
1134 info->device_memory_evicted =
1135 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1136
1137 if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
1138 info->nr_device_memory_evictions =
1139 ws->query_value(ws, RADEON_NUM_EVICTIONS);
1140 else
1141 /* Just return the number of evicted 64KB pages. */
1142 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1143 }
1144
1145 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1146 const struct pipe_resource *templ)
1147 {
1148 if (templ->target == PIPE_BUFFER) {
1149 return r600_buffer_create(screen, templ, 256);
1150 } else {
1151 return r600_texture_create(screen, templ);
1152 }
1153 }
1154
1155 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1156 struct radeon_winsys *ws)
1157 {
1158 char llvm_string[32] = {}, kernel_version[128] = {};
1159 struct utsname uname_data;
1160
1161 ws->query_info(ws, &rscreen->info);
1162
1163 if (uname(&uname_data) == 0)
1164 snprintf(kernel_version, sizeof(kernel_version),
1165 " / %s", uname_data.release);
1166
1167 #if HAVE_LLVM
1168 snprintf(llvm_string, sizeof(llvm_string),
1169 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1170 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1171 #endif
1172
1173 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1174 "%s (DRM %i.%i.%i%s%s)",
1175 r600_get_chip_name(rscreen), rscreen->info.drm_major,
1176 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1177 kernel_version, llvm_string);
1178
1179 rscreen->b.get_name = r600_get_name;
1180 rscreen->b.get_vendor = r600_get_vendor;
1181 rscreen->b.get_device_vendor = r600_get_device_vendor;
1182 rscreen->b.get_compute_param = r600_get_compute_param;
1183 rscreen->b.get_paramf = r600_get_paramf;
1184 rscreen->b.get_timestamp = r600_get_timestamp;
1185 rscreen->b.fence_finish = r600_fence_finish;
1186 rscreen->b.fence_reference = r600_fence_reference;
1187 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1188 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1189 rscreen->b.query_memory_info = r600_query_memory_info;
1190
1191 if (rscreen->info.has_uvd) {
1192 rscreen->b.get_video_param = rvid_get_video_param;
1193 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1194 } else {
1195 rscreen->b.get_video_param = r600_get_video_param;
1196 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1197 }
1198
1199 r600_init_screen_texture_functions(rscreen);
1200 r600_init_screen_query_functions(rscreen);
1201
1202 rscreen->ws = ws;
1203 rscreen->family = rscreen->info.family;
1204 rscreen->chip_class = rscreen->info.chip_class;
1205 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1206
1207 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1208 if (rscreen->force_aniso >= 0) {
1209 printf("radeon: Forcing anisotropy filter to %ix\n",
1210 /* round down to a power of two */
1211 1 << util_logbase2(rscreen->force_aniso));
1212 }
1213
1214 util_format_s3tc_init();
1215 pipe_mutex_init(rscreen->aux_context_lock);
1216 pipe_mutex_init(rscreen->gpu_load_mutex);
1217
1218 if (rscreen->debug_flags & DBG_INFO) {
1219 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1220 printf("family = %i (%s)\n", rscreen->info.family,
1221 r600_get_chip_name(rscreen));
1222 printf("chip_class = %i\n", rscreen->info.chip_class);
1223 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1224 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1225 printf("max_alloc_size = %i MB\n",
1226 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1227 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1228 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1229 printf("has_sdma = %i\n", rscreen->info.has_sdma);
1230 printf("has_uvd = %i\n", rscreen->info.has_uvd);
1231 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1232 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1233 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1234 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
1235 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1236 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1237 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1238 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1239 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1240
1241 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1242 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1243 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1244 printf("max_se = %i\n", rscreen->info.max_se);
1245 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1246
1247 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1248 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1249 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1250 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1251 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1252 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1253 }
1254 return true;
1255 }
1256
1257 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1258 {
1259 r600_perfcounters_destroy(rscreen);
1260 r600_gpu_load_kill_thread(rscreen);
1261
1262 pipe_mutex_destroy(rscreen->gpu_load_mutex);
1263 pipe_mutex_destroy(rscreen->aux_context_lock);
1264 rscreen->aux_context->destroy(rscreen->aux_context);
1265
1266 rscreen->ws->destroy(rscreen->ws);
1267 FREE(rscreen);
1268 }
1269
1270 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1271 unsigned processor)
1272 {
1273 switch (processor) {
1274 case PIPE_SHADER_VERTEX:
1275 return (rscreen->debug_flags & DBG_VS) != 0;
1276 case PIPE_SHADER_TESS_CTRL:
1277 return (rscreen->debug_flags & DBG_TCS) != 0;
1278 case PIPE_SHADER_TESS_EVAL:
1279 return (rscreen->debug_flags & DBG_TES) != 0;
1280 case PIPE_SHADER_GEOMETRY:
1281 return (rscreen->debug_flags & DBG_GS) != 0;
1282 case PIPE_SHADER_FRAGMENT:
1283 return (rscreen->debug_flags & DBG_PS) != 0;
1284 case PIPE_SHADER_COMPUTE:
1285 return (rscreen->debug_flags & DBG_CS) != 0;
1286 default:
1287 return false;
1288 }
1289 }
1290
1291 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1292 uint64_t offset, uint64_t size, unsigned value,
1293 enum r600_coherency coher)
1294 {
1295 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1296
1297 pipe_mutex_lock(rscreen->aux_context_lock);
1298 rctx->clear_buffer(&rctx->b, dst, offset, size, value, coher);
1299 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1300 pipe_mutex_unlock(rscreen->aux_context_lock);
1301 }