2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * This file contains common screen and context structures and functions
26 * for r600g and radeonsi.
29 #ifndef R600_PIPE_COMMON_H
30 #define R600_PIPE_COMMON_H
34 #include "amd/common/ac_binary.h"
36 #include "radeon/radeon_winsys.h"
38 #include "util/disk_cache.h"
39 #include "util/u_blitter.h"
40 #include "util/list.h"
41 #include "util/u_range.h"
42 #include "util/slab.h"
43 #include "util/u_suballoc.h"
44 #include "util/u_transfer.h"
45 #include "util/u_threaded_context.h"
49 #define ATI_VENDOR_ID 0x1002
51 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
52 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
53 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
54 #define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
55 #define R600_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
57 #define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
58 /* Pipeline & streamout query controls. */
59 #define R600_CONTEXT_START_PIPELINE_STATS (1u << 1)
60 #define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2)
61 #define R600_CONTEXT_FLUSH_FOR_RENDER_COND (1u << 3)
62 #define R600_CONTEXT_PRIVATE_FLAG (1u << 4)
64 /* special primitive types */
65 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
67 #define R600_NOT_QUERY 0xffffffff
71 /* Shader logging options: */
72 DBG_VS
= PIPE_SHADER_VERTEX
,
73 DBG_PS
= PIPE_SHADER_FRAGMENT
,
74 DBG_GS
= PIPE_SHADER_GEOMETRY
,
75 DBG_TCS
= PIPE_SHADER_TESS_CTRL
,
76 DBG_TES
= PIPE_SHADER_TESS_EVAL
,
77 DBG_CS
= PIPE_SHADER_COMPUTE
,
83 /* Shader compiler options the shader cache should be aware of: */
84 DBG_FS_CORRECT_DERIVS_AFTER_KILL
,
88 /* Shader compiler options (with no effect on the shader cache): */
92 DBG_MONOLITHIC_SHADERS
,
95 /* Information logging options: */
101 /* Driver options: */
108 /* 3D engine options: */
128 DBG_TEST_VMFAULT_SDMA
,
129 DBG_TEST_VMFAULT_SHADER
,
132 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
133 #define DBG(name) (1ull << DBG_##name)
135 #define R600_MAP_BUFFER_ALIGNMENT 64
137 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
139 enum r600_coherency
{
140 R600_COHERENCY_NONE
, /* no cache flushes needed */
141 R600_COHERENCY_SHADER
,
142 R600_COHERENCY_CB_META
,
145 #ifdef PIPE_ARCH_BIG_ENDIAN
146 #define R600_BIG_ENDIAN 1
148 #define R600_BIG_ENDIAN 0
151 struct r600_common_context
;
152 struct r600_perfcounters
;
153 struct tgsi_shader_info
;
154 struct r600_qbo_state
;
156 void si_radeon_shader_binary_init(struct ac_shader_binary
*b
);
157 void si_radeon_shader_binary_clean(struct ac_shader_binary
*b
);
159 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
162 struct r600_resource
{
163 struct threaded_resource b
;
165 /* Winsys objects. */
166 struct pb_buffer
*buf
;
167 uint64_t gpu_address
;
168 /* Memory usage if the buffer placement is optimal. */
172 /* Resource properties. */
174 unsigned bo_alignment
;
175 enum radeon_bo_domain domains
;
176 enum radeon_bo_flag flags
;
177 unsigned bind_history
;
178 int max_forced_staging_uploads
;
180 /* The buffer range which is initialized (with a write transfer,
181 * streamout, DMA, or as a random access target). The rest of
182 * the buffer is considered invalid and can be mapped unsynchronized.
184 * This allows unsychronized mapping of a buffer range which hasn't
185 * been used yet. It's for applications which forget to use
186 * the unsynchronized map flag and expect the driver to figure it out.
188 struct util_range valid_buffer_range
;
190 /* For buffers only. This indicates that a write operation has been
191 * performed by TC L2, but the cache hasn't been flushed.
192 * Any hw block which doesn't use or bypasses TC L2 should check this
193 * flag and flush the cache before using the buffer.
195 * For example, TC L2 must be flushed if a buffer which has been
196 * modified by a shader store instruction is about to be used as
197 * an index buffer. The reason is that VGT DMA index fetching doesn't
202 /* Whether the resource has been exported via resource_get_handle. */
203 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
205 /* Whether this resource is referenced by bindless handles. */
206 bool texture_handle_allocated
;
207 bool image_handle_allocated
;
210 struct r600_transfer
{
211 struct threaded_transfer b
;
212 struct r600_resource
*staging
;
216 struct r600_fmask_info
{
220 unsigned pitch_in_pixels
;
221 unsigned bank_height
;
222 unsigned slice_tile_max
;
223 unsigned tile_mode_index
;
224 unsigned tile_swizzle
;
227 struct r600_cmask_info
{
231 unsigned slice_tile_max
;
232 uint64_t base_address_reg
;
235 struct r600_texture
{
236 struct r600_resource resource
;
238 struct radeon_surf surface
;
240 struct r600_texture
*flushed_depth_texture
;
242 /* Colorbuffer compression and fast clear. */
243 struct r600_fmask_info fmask
;
244 struct r600_cmask_info cmask
;
245 struct r600_resource
*cmask_buffer
;
246 uint64_t dcc_offset
; /* 0 = disabled */
247 unsigned cb_color_info
; /* fast clear enable bit */
248 unsigned color_clear_value
[2];
249 unsigned last_msaa_resolve_target_micro_mode
;
250 unsigned num_level0_transfers
;
252 /* Depth buffer compression and fast clear. */
253 uint64_t htile_offset
;
254 float depth_clear_value
;
255 uint16_t dirty_level_mask
; /* each bit says if that mipmap is compressed */
256 uint16_t stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
257 enum pipe_format db_render_format
:16;
258 uint8_t stencil_clear_value
;
259 bool tc_compatible_htile
:1;
260 bool depth_cleared
:1; /* if it was cleared at least once */
261 bool stencil_cleared
:1; /* if it was cleared at least once */
262 bool upgraded_depth
:1; /* upgraded from unorm to Z32_FLOAT */
264 bool db_compatible
:1;
268 /* We need to track DCC dirtiness, because st/dri usually calls
269 * flush_resource twice per frame (not a bug) and we don't wanna
270 * decompress DCC twice. Also, the dirty tracking must be done even
271 * if DCC isn't used, because it's required by the DCC usage analysis
272 * for a possible future enablement.
274 bool separate_dcc_dirty
:1;
275 /* Statistics gathering for the DCC enablement heuristic. */
276 bool dcc_gather_statistics
:1;
277 /* Counter that should be non-zero if the texture is bound to a
280 unsigned framebuffers_bound
;
281 /* Whether the texture is a displayable back buffer and needs DCC
282 * decompression, which is expensive. Therefore, it's enabled only
283 * if statistics suggest that it will pay off and it's allocated
284 * separately. It can't be bound as a sampler by apps. Limited to
285 * target == 2D and last_level == 0. If enabled, dcc_offset contains
286 * the absolute GPUVM address, not the relative one.
288 struct r600_resource
*dcc_separate_buffer
;
289 /* When DCC is temporarily disabled, the separate buffer is here. */
290 struct r600_resource
*last_dcc_separate_buffer
;
291 /* Estimate of how much this color buffer is written to in units of
292 * full-screen draws: ps_invocations / (width * height)
293 * Shader kills, late Z, and blending with trivial discards make it
294 * inaccurate (we need to count CB updates, not PS invocations).
296 unsigned ps_draw_ratio
;
297 /* The number of clears since the last DCC usage analysis. */
298 unsigned num_slow_clears
;
301 struct r600_surface
{
302 struct pipe_surface base
;
304 /* These can vary with block-compressed textures. */
308 bool color_initialized
:1;
309 bool depth_initialized
:1;
311 /* Misc. color flags. */
312 bool color_is_int8
:1;
313 bool color_is_int10
:1;
314 bool dcc_incompatible
:1;
316 /* Color registers. */
317 unsigned cb_color_info
;
318 unsigned cb_color_view
;
319 unsigned cb_color_attrib
;
320 unsigned cb_color_attrib2
; /* GFX9 and later */
321 unsigned cb_dcc_control
; /* VI and later */
322 unsigned spi_shader_col_format
:8; /* no blending, no alpha-to-coverage. */
323 unsigned spi_shader_col_format_alpha
:8; /* alpha-to-coverage */
324 unsigned spi_shader_col_format_blend
:8; /* blending without alpha. */
325 unsigned spi_shader_col_format_blend_alpha
:8; /* blending with alpha. */
328 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE */
329 uint64_t db_stencil_base
;
330 uint64_t db_htile_data_base
;
331 unsigned db_depth_info
;
333 unsigned db_z_info2
; /* GFX9+ */
334 unsigned db_depth_view
;
335 unsigned db_depth_size
;
336 unsigned db_depth_slice
;
337 unsigned db_stencil_info
;
338 unsigned db_stencil_info2
; /* GFX9+ */
339 unsigned db_htile_surface
;
342 struct r600_mmio_counter
{
347 union r600_mmio_counters
{
349 /* For global GPU load including SDMA. */
350 struct r600_mmio_counter gpu
;
353 struct r600_mmio_counter spi
;
354 struct r600_mmio_counter gui
;
355 struct r600_mmio_counter ta
;
356 struct r600_mmio_counter gds
;
357 struct r600_mmio_counter vgt
;
358 struct r600_mmio_counter ia
;
359 struct r600_mmio_counter sx
;
360 struct r600_mmio_counter wd
;
361 struct r600_mmio_counter bci
;
362 struct r600_mmio_counter sc
;
363 struct r600_mmio_counter pa
;
364 struct r600_mmio_counter db
;
365 struct r600_mmio_counter cp
;
366 struct r600_mmio_counter cb
;
369 struct r600_mmio_counter sdma
;
372 struct r600_mmio_counter pfp
;
373 struct r600_mmio_counter meq
;
374 struct r600_mmio_counter me
;
375 struct r600_mmio_counter surf_sync
;
376 struct r600_mmio_counter cp_dma
;
377 struct r600_mmio_counter scratch_ram
;
382 struct r600_memory_object
{
383 struct pipe_memory_object b
;
384 struct pb_buffer
*buf
;
389 struct r600_common_screen
{
390 struct pipe_screen b
;
391 struct radeon_winsys
*ws
;
392 enum radeon_family family
;
393 enum chip_class chip_class
;
394 struct radeon_info info
;
395 uint64_t debug_flags
;
396 bool has_rbplus
; /* if RB+ registers exist */
397 bool rbplus_allowed
; /* if RB+ is allowed */
398 bool dcc_msaa_allowed
;
400 struct disk_cache
*disk_shader_cache
;
402 struct slab_parent_pool pool_transfers
;
404 /* Texture filter settings. */
405 int force_aniso
; /* -1 = disabled */
407 /* Auxiliary context. Mainly used to initialize resources.
408 * It must be locked prior to using and flushed before unlocking. */
409 struct pipe_context
*aux_context
;
410 mtx_t aux_context_lock
;
412 /* This must be in the screen, because UE4 uses one context for
413 * compilation and another one for rendering.
415 unsigned num_compilations
;
416 /* Along with ST_DEBUG=precompile, this should show if applications
417 * are loading shaders on demand. This is a monotonic counter.
419 unsigned num_shaders_created
;
420 unsigned num_shader_cache_hits
;
422 /* GPU load thread. */
423 mtx_t gpu_load_mutex
;
424 thrd_t gpu_load_thread
;
425 union r600_mmio_counters mmio_counters
;
426 volatile unsigned gpu_load_stop_thread
; /* bool */
428 char renderer_string
[100];
430 /* Performance counters. */
431 struct r600_perfcounters
*perfcounters
;
433 /* If pipe_screen wants to recompute and re-emit the framebuffer,
434 * sampler, and image states of all contexts, it should atomically
437 * Each context will compare this with its own last known value of
438 * the counter before drawing and re-emit the states accordingly.
440 unsigned dirty_tex_counter
;
442 /* Atomically increment this counter when an existing texture's
443 * metadata is enabled or disabled in a way that requires changing
444 * contexts' compressed texture binding masks.
446 unsigned compressed_colortex_counter
;
449 /* Context flags to set so that all writes from earlier jobs
450 * in the CP are seen by L2 clients.
454 /* Context flags to set so that all writes from earlier jobs
455 * that end in L2 are seen by CP.
459 /* Context flags to set so that all writes from earlier
460 * compute jobs are seen by L2 clients.
462 unsigned compute_to_L2
;
465 void (*query_opaque_metadata
)(struct r600_common_screen
*rscreen
,
466 struct r600_texture
*rtex
,
467 struct radeon_bo_metadata
*md
);
469 void (*apply_opaque_metadata
)(struct r600_common_screen
*rscreen
,
470 struct r600_texture
*rtex
,
471 struct radeon_bo_metadata
*md
);
474 /* This encapsulates a state or an operation which can emitted into the GPU
477 void (*emit
)(struct r600_common_context
*ctx
, struct r600_atom
*state
);
482 struct radeon_winsys_cs
*cs
;
483 void (*flush
)(void *ctx
, unsigned flags
,
484 struct pipe_fence_handle
**fence
);
487 /* Saved CS data for debugging features. */
488 struct radeon_saved_cs
{
492 struct radeon_bo_list_item
*bo_list
;
496 struct r600_common_context
{
497 struct pipe_context b
; /* base class */
499 struct r600_common_screen
*screen
;
500 struct radeon_winsys
*ws
;
501 struct radeon_winsys_ctx
*ctx
;
502 enum radeon_family family
;
503 enum chip_class chip_class
;
504 struct r600_ring gfx
;
505 struct r600_ring dma
;
506 struct pipe_fence_handle
*last_gfx_fence
;
507 struct pipe_fence_handle
*last_sdma_fence
;
508 struct r600_resource
*eop_bug_scratch
;
509 unsigned num_gfx_cs_flushes
;
510 unsigned initial_gfx_cs_size
;
511 unsigned gpu_reset_counter
;
512 unsigned last_dirty_tex_counter
;
513 unsigned last_compressed_colortex_counter
;
514 unsigned last_num_draw_calls
;
516 struct threaded_context
*tc
;
517 struct u_suballocator
*allocator_zeroed_memory
;
518 struct slab_child_pool pool_transfers
;
519 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
521 /* Current unaccounted memory usage. */
525 /* Additional context states. */
526 unsigned flags
; /* flush flags */
529 /* Maintain the list of active queries for pausing between IBs. */
530 int num_occlusion_queries
;
531 int num_perfect_occlusion_queries
;
532 struct list_head active_queries
;
533 unsigned num_cs_dw_queries_suspend
;
535 unsigned num_draw_calls
;
536 unsigned num_decompress_calls
;
537 unsigned num_mrt_draw_calls
;
538 unsigned num_prim_restart_calls
;
539 unsigned num_spill_draw_calls
;
540 unsigned num_compute_calls
;
541 unsigned num_spill_compute_calls
;
542 unsigned num_dma_calls
;
543 unsigned num_cp_dma_calls
;
544 unsigned num_vs_flushes
;
545 unsigned num_ps_flushes
;
546 unsigned num_cs_flushes
;
547 unsigned num_cb_cache_flushes
;
548 unsigned num_db_cache_flushes
;
549 unsigned num_L2_invalidates
;
550 unsigned num_L2_writebacks
;
551 unsigned num_resident_handles
;
552 uint64_t num_alloc_tex_transfer_bytes
;
553 unsigned last_tex_ps_draw_ratio
; /* for query */
555 /* Render condition. */
556 struct r600_atom render_cond_atom
;
557 struct pipe_query
*render_cond
;
558 unsigned render_cond_mode
;
559 bool render_cond_invert
;
560 bool render_cond_force_off
; /* for u_blitter */
562 /* Statistics gathering for the DCC enablement heuristic. It can't be
563 * in r600_texture because r600_texture can be shared by multiple
564 * contexts. This is for back buffers only. We shouldn't get too many
567 * X11 DRI3 rotates among a finite set of back buffers. They should
568 * all fit in this array. If they don't, separate DCC might never be
569 * enabled by DCC stat gathering.
572 struct r600_texture
*tex
;
573 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
574 struct pipe_query
*ps_stats
[3];
575 /* If all slots are used and another slot is needed,
576 * the least recently used slot is evicted based on this. */
577 int64_t last_use_timestamp
;
581 struct pipe_device_reset_callback device_reset_callback
;
582 struct u_log_context
*log
;
584 void *query_result_shader
;
586 /* Copy one resource to another using async DMA. */
587 void (*dma_copy
)(struct pipe_context
*ctx
,
588 struct pipe_resource
*dst
,
590 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
591 struct pipe_resource
*src
,
593 const struct pipe_box
*src_box
);
595 void (*dma_clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
596 uint64_t offset
, uint64_t size
, unsigned value
);
598 void (*clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
599 uint64_t offset
, uint64_t size
, unsigned value
,
600 enum r600_coherency coher
);
602 void (*blit_decompress_depth
)(struct pipe_context
*ctx
,
603 struct r600_texture
*texture
,
604 struct r600_texture
*staging
,
605 unsigned first_level
, unsigned last_level
,
606 unsigned first_layer
, unsigned last_layer
,
607 unsigned first_sample
, unsigned last_sample
);
609 void (*decompress_dcc
)(struct pipe_context
*ctx
,
610 struct r600_texture
*rtex
);
612 /* Reallocate the buffer and update all resource bindings where
613 * the buffer is bound, including all resource descriptors. */
614 void (*invalidate_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
);
616 /* Update all resource bindings where the buffer is bound, including
617 * all resource descriptors. This is invalidate_buffer without
618 * the invalidation. */
619 void (*rebind_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
,
620 uint64_t old_gpu_address
);
622 /* Enable or disable occlusion queries. */
623 void (*set_occlusion_query_state
)(struct pipe_context
*ctx
,
625 bool old_perfect_enable
);
627 void (*save_qbo_state
)(struct pipe_context
*ctx
, struct r600_qbo_state
*st
);
629 /* This ensures there is enough space in the command stream. */
630 void (*need_gfx_cs_space
)(struct pipe_context
*ctx
, unsigned num_dw
,
631 bool include_draw_vbo
);
633 void (*set_atom_dirty
)(struct r600_common_context
*ctx
,
634 struct r600_atom
*atom
, bool dirty
);
636 void (*check_vm_faults
)(struct r600_common_context
*ctx
,
637 struct radeon_saved_cs
*saved
,
638 enum ring_type ring
);
641 /* r600_buffer_common.c */
642 bool si_rings_is_buffer_referenced(struct r600_common_context
*ctx
,
643 struct pb_buffer
*buf
,
644 enum radeon_bo_usage usage
);
645 void *si_buffer_map_sync_with_rings(struct r600_common_context
*ctx
,
646 struct r600_resource
*resource
,
648 void si_buffer_subdata(struct pipe_context
*ctx
,
649 struct pipe_resource
*buffer
,
650 unsigned usage
, unsigned offset
,
651 unsigned size
, const void *data
);
652 void si_init_resource_fields(struct r600_common_screen
*rscreen
,
653 struct r600_resource
*res
,
654 uint64_t size
, unsigned alignment
);
655 bool si_alloc_resource(struct r600_common_screen
*rscreen
,
656 struct r600_resource
*res
);
657 struct pipe_resource
*si_buffer_create(struct pipe_screen
*screen
,
658 const struct pipe_resource
*templ
,
660 struct pipe_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
,
665 struct pipe_resource
*
666 si_buffer_from_user_memory(struct pipe_screen
*screen
,
667 const struct pipe_resource
*templ
,
669 void si_invalidate_resource(struct pipe_context
*ctx
,
670 struct pipe_resource
*resource
);
671 void si_replace_buffer_storage(struct pipe_context
*ctx
,
672 struct pipe_resource
*dst
,
673 struct pipe_resource
*src
);
675 /* r600_common_pipe.c */
676 void si_gfx_write_event_eop(struct r600_common_context
*ctx
,
677 unsigned event
, unsigned event_flags
,
679 struct r600_resource
*buf
, uint64_t va
,
680 uint32_t new_fence
, unsigned query_type
);
681 unsigned si_gfx_write_fence_dwords(struct r600_common_screen
*screen
);
682 void si_gfx_wait_fence(struct r600_common_context
*ctx
,
683 uint64_t va
, uint32_t ref
, uint32_t mask
);
684 bool si_common_screen_init(struct r600_common_screen
*rscreen
,
685 struct radeon_winsys
*ws
);
686 void si_destroy_common_screen(struct r600_common_screen
*rscreen
);
687 void si_preflush_suspend_features(struct r600_common_context
*ctx
);
688 void si_postflush_resume_features(struct r600_common_context
*ctx
);
689 bool si_common_context_init(struct r600_common_context
*rctx
,
690 struct r600_common_screen
*rscreen
,
691 unsigned context_flags
);
692 void si_common_context_cleanup(struct r600_common_context
*rctx
);
693 bool si_can_dump_shader(struct r600_common_screen
*rscreen
,
695 bool si_extra_shader_checks(struct r600_common_screen
*rscreen
,
697 void si_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
698 uint64_t offset
, uint64_t size
, unsigned value
);
699 struct pipe_resource
*si_resource_create_common(struct pipe_screen
*screen
,
700 const struct pipe_resource
*templ
);
701 void si_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
,
702 struct r600_resource
*dst
, struct r600_resource
*src
);
703 void si_save_cs(struct radeon_winsys
*ws
, struct radeon_winsys_cs
*cs
,
704 struct radeon_saved_cs
*saved
, bool get_buffer_list
);
705 void si_clear_saved_cs(struct radeon_saved_cs
*saved
);
706 bool si_check_device_reset(struct r600_common_context
*rctx
);
708 /* r600_gpu_load.c */
709 void si_gpu_load_kill_thread(struct r600_common_screen
*rscreen
);
710 uint64_t si_begin_counter(struct r600_common_screen
*rscreen
, unsigned type
);
711 unsigned si_end_counter(struct r600_common_screen
*rscreen
, unsigned type
,
714 /* r600_perfcounters.c */
715 void si_perfcounters_destroy(struct r600_common_screen
*rscreen
);
718 void si_init_screen_query_functions(struct r600_common_screen
*rscreen
);
719 void si_init_query_functions(struct r600_common_context
*rctx
);
720 void si_suspend_queries(struct r600_common_context
*ctx
);
721 void si_resume_queries(struct r600_common_context
*ctx
);
723 /* r600_test_dma.c */
724 void si_test_dma(struct r600_common_screen
*rscreen
);
727 bool si_prepare_for_dma_blit(struct r600_common_context
*rctx
,
728 struct r600_texture
*rdst
,
729 unsigned dst_level
, unsigned dstx
,
730 unsigned dsty
, unsigned dstz
,
731 struct r600_texture
*rsrc
,
733 const struct pipe_box
*src_box
);
734 void si_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
735 struct r600_texture
*rtex
,
737 struct r600_fmask_info
*out
);
738 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
739 struct pipe_resource
*texture
,
740 struct r600_texture
**staging
);
741 void si_print_texture_info(struct r600_common_screen
*rscreen
,
742 struct r600_texture
*rtex
, struct u_log_context
*log
);
743 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
744 const struct pipe_resource
*templ
);
745 bool vi_dcc_formats_compatible(enum pipe_format format1
,
746 enum pipe_format format2
);
747 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
749 enum pipe_format view_format
);
750 void vi_disable_dcc_if_incompatible_format(struct r600_common_context
*rctx
,
751 struct pipe_resource
*tex
,
753 enum pipe_format view_format
);
754 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
755 struct pipe_resource
*texture
,
756 const struct pipe_surface
*templ
,
757 unsigned width0
, unsigned height0
,
758 unsigned width
, unsigned height
);
759 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
760 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
761 struct r600_texture
*tex
);
762 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
763 struct r600_texture
*tex
);
764 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
765 struct r600_texture
*tex
);
766 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
767 struct r600_texture
*rtex
,
768 unsigned level
, unsigned clear_value
);
769 void si_do_fast_color_clear(struct r600_common_context
*rctx
,
770 struct pipe_framebuffer_state
*fb
,
771 struct r600_atom
*fb_state
,
772 unsigned *buffers
, ubyte
*dirty_cbufs
,
773 const union pipe_color_union
*color
);
774 bool si_texture_disable_dcc(struct r600_common_context
*rctx
,
775 struct r600_texture
*rtex
);
776 void si_init_screen_texture_functions(struct r600_common_screen
*rscreen
);
777 void si_init_context_texture_functions(struct r600_common_context
*rctx
);
780 /* Inline helpers. */
782 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
784 return (struct r600_resource
*)r
;
788 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
790 pipe_resource_reference((struct pipe_resource
**)ptr
,
791 (struct pipe_resource
*)res
);
795 r600_texture_reference(struct r600_texture
**ptr
, struct r600_texture
*res
)
797 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->resource
.b
.b
);
801 r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
)
803 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
804 struct r600_resource
*res
= (struct r600_resource
*)r
;
807 /* Add memory usage for need_gfx_cs_space */
808 rctx
->vram
+= res
->vram_usage
;
809 rctx
->gtt
+= res
->gart_usage
;
813 #define SQ_TEX_XY_FILTER_POINT 0x00
814 #define SQ_TEX_XY_FILTER_BILINEAR 0x01
815 #define SQ_TEX_XY_FILTER_ANISO_POINT 0x02
816 #define SQ_TEX_XY_FILTER_ANISO_BILINEAR 0x03
818 static inline unsigned eg_tex_filter(unsigned filter
, unsigned max_aniso
)
820 if (filter
== PIPE_TEX_FILTER_LINEAR
)
821 return max_aniso
> 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
822 : SQ_TEX_XY_FILTER_BILINEAR
;
824 return max_aniso
> 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
825 : SQ_TEX_XY_FILTER_POINT
;
828 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
841 static inline enum radeon_bo_priority
842 r600_get_sampler_view_priority(struct r600_resource
*res
)
844 if (res
->b
.b
.target
== PIPE_BUFFER
)
845 return RADEON_PRIO_SAMPLER_BUFFER
;
847 if (res
->b
.b
.nr_samples
> 1)
848 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
850 return RADEON_PRIO_SAMPLER_TEXTURE
;
854 r600_can_sample_zs(struct r600_texture
*tex
, bool stencil_sampler
)
856 return (stencil_sampler
&& tex
->can_sample_s
) ||
857 (!stencil_sampler
&& tex
->can_sample_z
);
861 vi_dcc_enabled(struct r600_texture
*tex
, unsigned level
)
863 return tex
->dcc_offset
&& level
< tex
->surface
.num_dcc_levels
;
867 r600_htile_enabled(struct r600_texture
*tex
, unsigned level
)
869 return tex
->htile_offset
&& level
== 0;
873 vi_tc_compat_htile_enabled(struct r600_texture
*tex
, unsigned level
)
875 assert(!tex
->tc_compatible_htile
|| tex
->htile_offset
);
876 return tex
->tc_compatible_htile
&& level
== 0;
879 #define COMPUTE_DBG(rscreen, fmt, args...) \
881 if ((rscreen->b.debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
884 #define R600_ERR(fmt, args...) \
885 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
887 static inline int S_FIXED(float value
, unsigned frac_bits
)
889 return value
* (1 << frac_bits
);