src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2017 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "pipe/p_video_codec.h"
  29 #include "radeon_vcn_enc.h"
  30 #include "radeon_video.h"
  31 #include "si_pipe.h"
  32 #include "util/u_video.h"
  33
  34 #include <stdio.h>
  35
  36 #define RENCODE_FW_INTERFACE_MAJOR_VERSION         1
  37 #define RENCODE_FW_INTERFACE_MINOR_VERSION         1
  38
  39 #define RENCODE_IB_PARAM_SESSION_INFO              0x00000001
  40 #define RENCODE_IB_PARAM_TASK_INFO                 0x00000002
  41 #define RENCODE_IB_PARAM_SESSION_INIT              0x00000003
  42 #define RENCODE_IB_PARAM_LAYER_CONTROL             0x00000004
  43 #define RENCODE_IB_PARAM_LAYER_SELECT              0x00000005
  44 #define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
  45 #define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT   0x00000007
  46 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE  0x00000008
  47 #define RENCODE_IB_PARAM_QUALITY_PARAMS            0x00000009
  48 #define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU        0x0000000a
  49 #define RENCODE_IB_PARAM_SLICE_HEADER              0x0000000b
  50 #define RENCODE_IB_PARAM_INPUT_FORMAT              0x0000000c
  51 #define RENCODE_IB_PARAM_OUTPUT_FORMAT             0x0000000d
  52 #define RENCODE_IB_PARAM_ENCODE_PARAMS             0x0000000f
  53 #define RENCODE_IB_PARAM_INTRA_REFRESH             0x00000010
  54 #define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER     0x00000011
  55 #define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER    0x00000012
  56 #define RENCODE_IB_PARAM_FEEDBACK_BUFFER           0x00000015
  57
  58 #define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL        0x00100001
  59 #define RENCODE_HEVC_IB_PARAM_SPEC_MISC            0x00100002
  60 #define RENCODE_HEVC_IB_PARAM_LOOP_FILTER          0x00100003
  61
  62 #define RENCODE_H264_IB_PARAM_SLICE_CONTROL        0x00200001
  63 #define RENCODE_H264_IB_PARAM_SPEC_MISC            0x00200002
  64 #define RENCODE_H264_IB_PARAM_ENCODE_PARAMS        0x00200003
  65 #define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER    0x00200004
  66
  67 #define RENCODE_COLOR_VOLUME_G22_BT709             0
  68 #define RENCODE_COLOR_VOLUME_G10_BT2020            3
  69
  70 #define RENCODE_COLOR_BIT_DEPTH_8_BIT              0
  71 #define RENCODE_COLOR_BIT_DEPTH_10_BIT             1
  72
  73 #define RENCODE_COLOR_PACKING_FORMAT_NV12          0
  74 #define RENCODE_COLOR_PACKING_FORMAT_P010          1
  75
  76 static void radeon_enc_quality_params(struct radeon_encoder *enc)
  77 {
  78    enc->enc_pic.quality_params.vbaq_mode = 0;
  79    enc->enc_pic.quality_params.scene_change_sensitivity = 0;
  80    enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
  81    enc->enc_pic.quality_params.two_pass_search_center_map_mode = 0;
  82
  83    RADEON_ENC_BEGIN(enc->cmd.quality_params);
  84    RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
  85    RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
  86    RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
  87    RADEON_ENC_CS(enc->enc_pic.quality_params.two_pass_search_center_map_mode);
  88    RADEON_ENC_END();
  89 }
  90
  91 static void radeon_enc_loop_filter_hevc(struct radeon_encoder *enc)
  92 {
  93    RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc);
  94    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
  95    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
  96    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
  97    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
  98    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
  99    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
 100    RADEON_ENC_CS(1);
 101    RADEON_ENC_END();
 102 }
 103
 104 static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
 105 {
 106    RADEON_ENC_BEGIN(enc->cmd.nalu);
 107    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
 108    uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 109    int i;
 110
 111    radeon_enc_reset(enc);
 112    radeon_enc_set_emulation_prevention(enc, false);
 113    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 114    radeon_enc_code_fixed_bits(enc, 0x4201, 16);
 115    radeon_enc_byte_align(enc);
 116    radeon_enc_set_emulation_prevention(enc, true);
 117    radeon_enc_code_fixed_bits(enc, 0x0, 4);
 118    radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
 119    radeon_enc_code_fixed_bits(enc, 0x1, 1);
 120    radeon_enc_code_fixed_bits(enc, 0x0, 2);
 121    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
 122    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
 123    radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
 124    radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
 125    radeon_enc_code_fixed_bits(enc, 0x0, 16);
 126    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
 127
 128    for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
 129       radeon_enc_code_fixed_bits(enc, 0x0, 2);
 130
 131    if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
 132       for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
 133          radeon_enc_code_fixed_bits(enc, 0x0, 2);
 134    }
 135
 136    radeon_enc_code_ue(enc, 0x0);
 137    radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
 138    radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width);
 139    radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height);
 140    radeon_enc_code_fixed_bits(enc, 0x0, 1);
 141    radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
 142    radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
 143    radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);
 144    radeon_enc_code_fixed_bits(enc, 0x0, 1);
 145    radeon_enc_code_ue(enc, 1);
 146    radeon_enc_code_ue(enc, 0x0);
 147    radeon_enc_code_ue(enc, 0x0);
 148    radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
 149    // Only support CTBSize 64
 150    radeon_enc_code_ue(enc,
 151                       6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
 152    radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2);
 153    radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size);
 154    radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter);
 155    radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra);
 156
 157    radeon_enc_code_fixed_bits(enc, 0x0, 1);
 158    radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
 159    radeon_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1);
 160    radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
 161
 162    radeon_enc_code_ue(enc, 1);
 163    radeon_enc_code_ue(enc, 1);
 164    radeon_enc_code_ue(enc, 0);
 165    radeon_enc_code_ue(enc, 0);
 166    radeon_enc_code_fixed_bits(enc, 0x1, 1);
 167
 168    radeon_enc_code_fixed_bits(enc, 0x0, 1);
 169
 170    radeon_enc_code_fixed_bits(enc, 0, 1);
 171    radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1);
 172
 173    radeon_enc_code_fixed_bits(enc, 0x0, 1);
 174
 175    radeon_enc_code_fixed_bits(enc, 0x0, 1);
 176
 177    radeon_enc_code_fixed_bits(enc, 0x1, 1);
 178
 179    radeon_enc_byte_align(enc);
 180    radeon_enc_flush_headers(enc);
 181    *size_in_bytes = (enc->bits_output + 7) / 8;
 182    RADEON_ENC_END();
 183 }
 184
 185 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
 186 {
 187    RADEON_ENC_BEGIN(enc->cmd.nalu);
 188    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
 189    uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 190    radeon_enc_reset(enc);
 191    radeon_enc_set_emulation_prevention(enc, false);
 192    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 193    radeon_enc_code_fixed_bits(enc, 0x4401, 16);
 194    radeon_enc_byte_align(enc);
 195    radeon_enc_set_emulation_prevention(enc, true);
 196    radeon_enc_code_ue(enc, 0x0);
 197    radeon_enc_code_ue(enc, 0x0);
 198    radeon_enc_code_fixed_bits(enc, 0x1, 1);
 199    radeon_enc_code_fixed_bits(enc, 0x0, 4);
 200    radeon_enc_code_fixed_bits(enc, 0x0, 1);
 201    radeon_enc_code_fixed_bits(enc, 0x1, 1);
 202    radeon_enc_code_ue(enc, 0x0);
 203    radeon_enc_code_ue(enc, 0x0);
 204    radeon_enc_code_se(enc, 0x0);
 205    radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
 206    radeon_enc_code_fixed_bits(enc, 0x0, 1);
 207    if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE)
 208       radeon_enc_code_fixed_bits(enc, 0x0, 1);
 209    else {
 210       radeon_enc_code_fixed_bits(enc, 0x1, 1);
 211       radeon_enc_code_ue(enc, 0x0);
 212    }
 213    radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
 214    radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
 215    radeon_enc_code_fixed_bits(enc, 0x0, 1);
 216    radeon_enc_code_fixed_bits(enc, 0x0, 2);
 217    radeon_enc_code_fixed_bits(enc, 0x0, 1);
 218    radeon_enc_code_fixed_bits(enc, 0x0, 1);
 219    radeon_enc_code_fixed_bits(enc, 0x0, 1);
 220    radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
 221    radeon_enc_code_fixed_bits(enc, 0x1, 1);
 222    radeon_enc_code_fixed_bits(enc, 0x0, 1);
 223    radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
 224
 225    if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
 226       radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
 227       radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
 228    }
 229
 230    radeon_enc_code_fixed_bits(enc, 0x0, 1);
 231    radeon_enc_code_fixed_bits(enc, 0x0, 1);
 232    radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
 233    radeon_enc_code_fixed_bits(enc, 0x0, 2);
 234
 235    radeon_enc_code_fixed_bits(enc, 0x1, 1);
 236
 237    radeon_enc_byte_align(enc);
 238    radeon_enc_flush_headers(enc);
 239    *size_in_bytes = (enc->bits_output + 7) / 8;
 240    RADEON_ENC_END();
 241 }
 242
 243 static void radeon_enc_input_format(struct radeon_encoder *enc)
 244 {
 245    RADEON_ENC_BEGIN(enc->cmd.input_format);
 246    if (enc->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
 247       RADEON_ENC_CS(RENCODE_COLOR_VOLUME_G10_BT2020);
 248       RADEON_ENC_CS(0);
 249       RADEON_ENC_CS(0);
 250       RADEON_ENC_CS(0);
 251       RADEON_ENC_CS(0);
 252       RADEON_ENC_CS(RENCODE_COLOR_BIT_DEPTH_10_BIT);
 253       RADEON_ENC_CS(RENCODE_COLOR_PACKING_FORMAT_P010);
 254    } else {
 255       RADEON_ENC_CS(RENCODE_COLOR_VOLUME_G22_BT709);
 256       RADEON_ENC_CS(0);
 257       RADEON_ENC_CS(0);
 258       RADEON_ENC_CS(0);
 259       RADEON_ENC_CS(0);
 260       RADEON_ENC_CS(RENCODE_COLOR_BIT_DEPTH_8_BIT);
 261       RADEON_ENC_CS(RENCODE_COLOR_PACKING_FORMAT_NV12);
 262    }
 263    RADEON_ENC_END();
 264 }
 265
 266 static void radeon_enc_output_format(struct radeon_encoder *enc)
 267 {
 268    RADEON_ENC_BEGIN(enc->cmd.output_format);
 269    if (enc->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
 270       RADEON_ENC_CS(RENCODE_COLOR_VOLUME_G10_BT2020);
 271       RADEON_ENC_CS(0);
 272       RADEON_ENC_CS(0);
 273       RADEON_ENC_CS(RENCODE_COLOR_BIT_DEPTH_10_BIT);
 274    } else {
 275       RADEON_ENC_CS(RENCODE_COLOR_VOLUME_G22_BT709);
 276       RADEON_ENC_CS(0);
 277       RADEON_ENC_CS(0);
 278       RADEON_ENC_CS(RENCODE_COLOR_BIT_DEPTH_8_BIT);
 279    }
 280    RADEON_ENC_END();
 281 }
 282
 283 static void radeon_enc_ctx(struct radeon_encoder *enc)
 284 {
 285    enc->enc_pic.ctx_buf.swizzle_mode = 0;
 286
 287    uint32_t aligned_width = enc->enc_pic.session_init.aligned_picture_width;
 288    uint32_t aligned_height = enc->enc_pic.session_init.aligned_picture_height;
 289
 290    enc->enc_pic.ctx_buf.rec_luma_pitch = align(aligned_width, enc->alignment);
 291    enc->enc_pic.ctx_buf.rec_chroma_pitch = align(aligned_width, enc->alignment);
 292
 293    int luma_size = enc->enc_pic.ctx_buf.rec_luma_pitch * align(aligned_height, enc->alignment);
 294    if (enc->enc_pic.bit_depth_luma_minus8 == 2)
 295       luma_size *= 2;
 296    int chroma_size = align(luma_size / 2, enc->alignment);
 297    int offset = 0;
 298
 299    enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2;
 300    for (int i = 0; i < enc->enc_pic.ctx_buf.num_reconstructed_pictures; i++) {
 301       enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset = offset;
 302       offset += luma_size;
 303       enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset = offset;
 304       offset += chroma_size;
 305    }
 306
 307    RADEON_ENC_BEGIN(enc->cmd.ctx);
 308    RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0);
 309    RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
 310    RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
 311    RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
 312    RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
 313
 314    for (int i = 0; i < enc->enc_pic.ctx_buf.num_reconstructed_pictures; i++) {
 315       RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset);
 316       RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset);
 317    }
 318
 319    for (int i = 0; i < 136; i++)
 320       RADEON_ENC_CS(0x00000000);
 321
 322    RADEON_ENC_END();
 323 }
 324
 325 static void encode(struct radeon_encoder *enc)
 326 {
 327    enc->session_info(enc);
 328    enc->total_task_size = 0;
 329    enc->task_info(enc, enc->need_feedback);
 330
 331    enc->encode_headers(enc);
 332    enc->ctx(enc);
 333    enc->bitstream(enc);
 334    enc->feedback(enc);
 335    enc->intra_refresh(enc);
 336    enc->input_format(enc);
 337    enc->output_format(enc);
 338
 339    enc->op_speed(enc);
 340    enc->op_enc(enc);
 341    *enc->p_task_size = (enc->total_task_size);
 342 }
 343
 344 void radeon_enc_2_0_init(struct radeon_encoder *enc)
 345 {
 346    radeon_enc_1_2_init(enc);
 347    enc->encode = encode;
 348    enc->ctx = radeon_enc_ctx;
 349    enc->quality_params = radeon_enc_quality_params;
 350    enc->input_format = radeon_enc_input_format;
 351    enc->output_format = radeon_enc_output_format;
 352
 353    if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
 354       enc->deblocking_filter = radeon_enc_loop_filter_hevc;
 355       enc->nalu_sps = radeon_enc_nalu_sps_hevc;
 356       enc->nalu_pps = radeon_enc_nalu_pps_hevc;
 357    }
 358
 359    enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO;
 360    enc->cmd.task_info = RENCODE_IB_PARAM_TASK_INFO;
 361    enc->cmd.session_init = RENCODE_IB_PARAM_SESSION_INIT;
 362    enc->cmd.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL;
 363    enc->cmd.layer_select = RENCODE_IB_PARAM_LAYER_SELECT;
 364    enc->cmd.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT;
 365    enc->cmd.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT;
 366    enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE;
 367    enc->cmd.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS;
 368    enc->cmd.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU;
 369    enc->cmd.slice_header = RENCODE_IB_PARAM_SLICE_HEADER;
 370    enc->cmd.input_format = RENCODE_IB_PARAM_INPUT_FORMAT;
 371    enc->cmd.output_format = RENCODE_IB_PARAM_OUTPUT_FORMAT;
 372    enc->cmd.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS;
 373    enc->cmd.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH;
 374    enc->cmd.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER;
 375    enc->cmd.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
 376    enc->cmd.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER;
 377    enc->cmd.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL;
 378    enc->cmd.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC;
 379    enc->cmd.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_LOOP_FILTER;
 380    enc->cmd.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL;
 381    enc->cmd.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC;
 382    enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
 383    enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
 384
 385    enc->enc_pic.session_info.interface_version =
 386       ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
 387        (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
 388 }