projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: Fix handling of TGSI_SEMANTIC_PSIZE
[mesa.git] / src / gallium / drivers / radeonsi / radeonsi_shader.c
1
2 /*
3 * Copyright 2012 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Tom Stellard <thomas.stellard@amd.com>
26 * Michel Dänzer <michel.daenzer@amd.com>
27 * Christian König <christian.koenig@amd.com>
28 */
29
30 #include "gallivm/lp_bld_tgsi_action.h"
31 #include "gallivm/lp_bld_const.h"
32 #include "gallivm/lp_bld_gather.h"
33 #include "gallivm/lp_bld_intr.h"
34 #include "gallivm/lp_bld_logic.h"
35 #include "gallivm/lp_bld_tgsi.h"
36 #include "gallivm/lp_bld_arit.h"
37 #include "radeon_llvm.h"
38 #include "radeon_llvm_emit.h"
39 #include "util/u_memory.h"
40 #include "tgsi/tgsi_info.h"
41 #include "tgsi/tgsi_parse.h"
42 #include "tgsi/tgsi_scan.h"
43 #include "tgsi/tgsi_dump.h"
44
45 #include "radeonsi_pipe.h"
46 #include "radeonsi_shader.h"
47 #include "si_state.h"
48 #include "sid.h"
49
50 #include <assert.h>
51 #include <errno.h>
52 #include <stdio.h>
53
54 struct si_shader_context
55 {
56 struct radeon_llvm_context radeon_bld;
57 struct tgsi_parse_context parse;
58 struct tgsi_token * tokens;
59 struct si_pipe_shader *shader;
60 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
61 LLVMValueRef const_md;
62 LLVMValueRef const_resource;
63 LLVMValueRef *constants;
64 LLVMValueRef *resources;
65 LLVMValueRef *samplers;
66 };
67
68 static struct si_shader_context * si_shader_context(
69 struct lp_build_tgsi_context * bld_base)
70 {
71 return (struct si_shader_context *)bld_base;
72 }
73
74
75 #define PERSPECTIVE_BASE 0
76 #define LINEAR_BASE 9
77
78 #define SAMPLE_OFFSET 0
79 #define CENTER_OFFSET 2
80 #define CENTROID_OFSET 4
81
82 #define USE_SGPR_MAX_SUFFIX_LEN 5
83 #define CONST_ADDR_SPACE 2
84 #define USER_SGPR_ADDR_SPACE 8
85
86 /**
87 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
88 *
89 * @param offset The offset parameter specifies the number of
90 * elements to offset, not the number of bytes or dwords. An element is the
91 * the type pointed to by the base_ptr parameter (e.g. int is the element of
92 * an int* pointer)
93 *
94 * When LLVM lowers the load instruction, it will convert the element offset
95 * into a dword offset automatically.
96 *
97 */
98 static LLVMValueRef build_indexed_load(
99 struct si_shader_context * si_shader_ctx,
100 LLVMValueRef base_ptr,
101 LLVMValueRef offset)
102 {
103 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
104
105 LLVMValueRef computed_ptr = LLVMBuildGEP(
106 base->gallivm->builder, base_ptr, &offset, 1, "");
107
108 LLVMValueRef result = LLVMBuildLoad(base->gallivm->builder, computed_ptr, "");
109 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
110 return result;
111 }
112
113 static LLVMValueRef get_instance_index(
114 struct radeon_llvm_context * radeon_bld,
115 unsigned divisor)
116 {
117 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
118
119 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_INSTANCE_ID);
120 result = LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
121 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
122
123 if (divisor > 1)
124 result = LLVMBuildUDiv(gallivm->builder, result,
125 lp_build_const_int32(gallivm, divisor), "");
126
127 return result;
128 }
129
130 static void declare_input_vs(
131 struct si_shader_context * si_shader_ctx,
132 unsigned input_index,
133 const struct tgsi_full_declaration *decl)
134 {
135 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
136 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
137
138 unsigned chan;
139
140 LLVMValueRef t_list_ptr;
141 LLVMValueRef t_offset;
142 LLVMValueRef t_list;
143 LLVMValueRef attribute_offset;
144 LLVMValueRef buffer_index;
145 LLVMValueRef args[3];
146 LLVMTypeRef vec4_type;
147 LLVMValueRef input;
148
149 /* Load the T list */
150 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
151
152 t_offset = lp_build_const_int32(base->gallivm, input_index);
153
154 t_list = build_indexed_load(si_shader_ctx, t_list_ptr, t_offset);
155
156 /* Build the attribute offset */
157 attribute_offset = lp_build_const_int32(base->gallivm, 0);
158
159 if (divisor) {
160 /* Build index from instance ID, start instance and divisor */
161 si_shader_ctx->shader->shader.uses_instanceid = true;
162 buffer_index = get_instance_index(&si_shader_ctx->radeon_bld, divisor);
163 } else {
164 /* Load the buffer index, which is always stored in VGPR0
165 * for Vertex Shaders */
166 buffer_index = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_ID);
167 }
168
169 vec4_type = LLVMVectorType(base->elem_type, 4);
170 args[0] = t_list;
171 args[1] = attribute_offset;
172 args[2] = buffer_index;
173 input = build_intrinsic(base->gallivm->builder,
174 "llvm.SI.vs.load.input", vec4_type, args, 3,
175 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
176
177 /* Break up the vec4 into individual components */
178 for (chan = 0; chan < 4; chan++) {
179 LLVMValueRef llvm_chan = lp_build_const_int32(base->gallivm, chan);
180 /* XXX: Use a helper function for this. There is one in
181 * tgsi_llvm.c. */
182 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
183 LLVMBuildExtractElement(base->gallivm->builder,
184 input, llvm_chan, "");
185 }
186 }
187
188 static void declare_input_fs(
189 struct si_shader_context * si_shader_ctx,
190 unsigned input_index,
191 const struct tgsi_full_declaration *decl)
192 {
193 struct si_shader *shader = &si_shader_ctx->shader->shader;
194 struct lp_build_context * base =
195 &si_shader_ctx->radeon_bld.soa.bld_base.base;
196 struct gallivm_state * gallivm = base->gallivm;
197 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
198 LLVMValueRef main_fn = si_shader_ctx->radeon_bld.main_fn;
199
200 LLVMValueRef interp_param;
201 const char * intr_name;
202
203 /* This value is:
204 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
205 * quad begins a new primitive. Bit 0 always needs
206 * to be unset)
207 * [32:16] ParamOffset
208 *
209 */
210 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
211 LLVMValueRef attr_number;
212
213 unsigned chan;
214
215 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
216 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
217 unsigned soa_index =
218 radeon_llvm_reg_index_soa(input_index, chan);
219 si_shader_ctx->radeon_bld.inputs[soa_index] =
220 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
221
222 if (chan == 3)
223 /* RCP for fragcoord.w */
224 si_shader_ctx->radeon_bld.inputs[soa_index] =
225 LLVMBuildFDiv(gallivm->builder,
226 lp_build_const_float(gallivm, 1.0f),
227 si_shader_ctx->radeon_bld.inputs[soa_index],
228 "");
229 }
230 return;
231 }
232
233 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
234 LLVMValueRef face, is_face_positive;
235
236 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
237
238 is_face_positive = LLVMBuildFCmp(gallivm->builder,
239 LLVMRealUGT, face,
240 lp_build_const_float(gallivm, 0.0f),
241 "");
242
243 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
244 LLVMBuildSelect(gallivm->builder,
245 is_face_positive,
246 lp_build_const_float(gallivm, 1.0f),
247 lp_build_const_float(gallivm, 0.0f),
248 "");
249 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
250 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
251 lp_build_const_float(gallivm, 0.0f);
252 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
253 lp_build_const_float(gallivm, 1.0f);
254
255 return;
256 }
257
258 shader->input[input_index].param_offset = shader->ninterp++;
259 attr_number = lp_build_const_int32(gallivm,
260 shader->input[input_index].param_offset);
261
262 /* XXX: Handle all possible interpolation modes */
263 switch (decl->Interp.Interpolate) {
264 case TGSI_INTERPOLATE_COLOR:
265 if (si_shader_ctx->shader->key.ps.flatshade) {
266 interp_param = 0;
267 } else {
268 if (decl->Interp.Centroid)
269 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
270 else
271 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
272 }
273 break;
274 case TGSI_INTERPOLATE_CONSTANT:
275 interp_param = 0;
276 break;
277 case TGSI_INTERPOLATE_LINEAR:
278 if (decl->Interp.Centroid)
279 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
280 else
281 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
282 break;
283 case TGSI_INTERPOLATE_PERSPECTIVE:
284 if (decl->Interp.Centroid)
285 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
286 else
287 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
288 break;
289 default:
290 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
291 return;
292 }
293
294 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
295
296 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
297 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
298 si_shader_ctx->shader->key.ps.color_two_side) {
299 LLVMValueRef args[4];
300 LLVMValueRef face, is_face_positive;
301 LLVMValueRef back_attr_number =
302 lp_build_const_int32(gallivm,
303 shader->input[input_index].param_offset + 1);
304
305 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
306
307 is_face_positive = LLVMBuildFCmp(gallivm->builder,
308 LLVMRealUGT, face,
309 lp_build_const_float(gallivm, 0.0f),
310 "");
311
312 args[2] = params;
313 args[3] = interp_param;
314 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
315 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
316 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
317 LLVMValueRef front, back;
318
319 args[0] = llvm_chan;
320 args[1] = attr_number;
321 front = build_intrinsic(base->gallivm->builder, intr_name,
322 input_type, args, args[3] ? 4 : 3,
323 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
324
325 args[1] = back_attr_number;
326 back = build_intrinsic(base->gallivm->builder, intr_name,
327 input_type, args, args[3] ? 4 : 3,
328 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
329
330 si_shader_ctx->radeon_bld.inputs[soa_index] =
331 LLVMBuildSelect(gallivm->builder,
332 is_face_positive,
333 front,
334 back,
335 "");
336 }
337
338 shader->ninterp++;
339 } else {
340 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
341 LLVMValueRef args[4];
342 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
343 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
344 args[0] = llvm_chan;
345 args[1] = attr_number;
346 args[2] = params;
347 args[3] = interp_param;
348 si_shader_ctx->radeon_bld.inputs[soa_index] =
349 build_intrinsic(base->gallivm->builder, intr_name,
350 input_type, args, args[3] ? 4 : 3,
351 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
352 }
353 }
354 }
355
356 static void declare_input(
357 struct radeon_llvm_context * radeon_bld,
358 unsigned input_index,
359 const struct tgsi_full_declaration *decl)
360 {
361 struct si_shader_context * si_shader_ctx =
362 si_shader_context(&radeon_bld->soa.bld_base);
363 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
364 declare_input_vs(si_shader_ctx, input_index, decl);
365 } else if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
366 declare_input_fs(si_shader_ctx, input_index, decl);
367 } else {
368 fprintf(stderr, "Warning: Unsupported shader type,\n");
369 }
370 }
371
372 static void declare_system_value(
373 struct radeon_llvm_context * radeon_bld,
374 unsigned index,
375 const struct tgsi_full_declaration *decl)
376 {
377
378 LLVMValueRef value = 0;
379
380 switch (decl->Semantic.Name) {
381 case TGSI_SEMANTIC_INSTANCEID:
382 value = get_instance_index(radeon_bld, 1);
383 break;
384
385 case TGSI_SEMANTIC_VERTEXID:
386 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_VERTEX_ID);
387 break;
388
389 default:
390 assert(!"unknown system value");
391 return;
392 }
393
394 radeon_bld->system_values[index] = value;
395 }
396
397 static LLVMValueRef fetch_constant(
398 struct lp_build_tgsi_context * bld_base,
399 const struct tgsi_full_src_register *reg,
400 enum tgsi_opcode_type type,
401 unsigned swizzle)
402 {
403 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
404 struct lp_build_context * base = &bld_base->base;
405 const struct tgsi_ind_register *ireg = &reg->Indirect;
406 unsigned idx;
407
408 LLVMValueRef args[2];
409 LLVMValueRef addr;
410 LLVMValueRef result;
411
412 if (swizzle == LP_CHAN_ALL) {
413 unsigned chan;
414 LLVMValueRef values[4];
415 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
416 values[chan] = fetch_constant(bld_base, reg, type, chan);
417
418 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
419 }
420
421 idx = reg->Register.Index * 4 + swizzle;
422 if (!reg->Register.Indirect)
423 return bitcast(bld_base, type, si_shader_ctx->constants[idx]);
424
425 args[0] = si_shader_ctx->const_resource;
426 args[1] = lp_build_const_int32(base->gallivm, idx * 4);
427 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
428 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
429 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
430 args[1] = lp_build_add(&bld_base->uint_bld, addr, args[1]);
431
432 result = build_intrinsic(base->gallivm->builder, "llvm.SI.load.const", base->elem_type,
433 args, 2, LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
434
435 return bitcast(bld_base, type, result);
436 }
437
438 /* Initialize arguments for the shader export intrinsic */
439 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
440 struct tgsi_full_declaration *d,
441 unsigned index,
442 unsigned target,
443 LLVMValueRef *args)
444 {
445 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
446 struct lp_build_context *uint =
447 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
448 struct lp_build_context *base = &bld_base->base;
449 unsigned compressed = 0;
450 unsigned chan;
451
452 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
453 int cbuf = target - V_008DFC_SQ_EXP_MRT;
454
455 if (cbuf >= 0 && cbuf < 8) {
456 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
457
458 if (compressed)
459 si_shader_ctx->shader->spi_shader_col_format |=
460 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
461 else
462 si_shader_ctx->shader->spi_shader_col_format |=
463 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
464 }
465 }
466
467 if (compressed) {
468 /* Pixel shader needs to pack output values before export */
469 for (chan = 0; chan < 2; chan++ ) {
470 LLVMValueRef *out_ptr =
471 si_shader_ctx->radeon_bld.soa.outputs[index];
472 args[0] = LLVMBuildLoad(base->gallivm->builder,
473 out_ptr[2 * chan], "");
474 args[1] = LLVMBuildLoad(base->gallivm->builder,
475 out_ptr[2 * chan + 1], "");
476 args[chan + 5] =
477 build_intrinsic(base->gallivm->builder,
478 "llvm.SI.packf16",
479 LLVMInt32TypeInContext(base->gallivm->context),
480 args, 2,
481 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
482 args[chan + 7] = args[chan + 5] =
483 LLVMBuildBitCast(base->gallivm->builder,
484 args[chan + 5],
485 LLVMFloatTypeInContext(base->gallivm->context),
486 "");
487 }
488
489 /* Set COMPR flag */
490 args[4] = uint->one;
491 } else {
492 for (chan = 0; chan < 4; chan++ ) {
493 LLVMValueRef out_ptr =
494 si_shader_ctx->radeon_bld.soa.outputs[index][chan];
495 /* +5 because the first output value will be
496 * the 6th argument to the intrinsic. */
497 args[chan + 5] = LLVMBuildLoad(base->gallivm->builder,
498 out_ptr, "");
499 }
500
501 /* Clear COMPR flag */
502 args[4] = uint->zero;
503 }
504
505 /* XXX: This controls which components of the output
506 * registers actually get exported. (e.g bit 0 means export
507 * X component, bit 1 means export Y component, etc.) I'm
508 * hard coding this to 0xf for now. In the future, we might
509 * want to do something else. */
510 args[0] = lp_build_const_int32(base->gallivm, 0xf);
511
512 /* Specify whether the EXEC mask represents the valid mask */
513 args[1] = uint->zero;
514
515 /* Specify whether this is the last export */
516 args[2] = uint->zero;
517
518 /* Specify the target we are exporting */
519 args[3] = lp_build_const_int32(base->gallivm, target);
520
521 /* XXX: We probably need to keep track of the output
522 * values, so we know what we are passing to the next
523 * stage. */
524 }
525
526 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
527 unsigned index)
528 {
529 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
530 struct gallivm_state *gallivm = bld_base->base.gallivm;
531
532 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
533 LLVMValueRef out_ptr = si_shader_ctx->radeon_bld.soa.outputs[index][3];
534 LLVMValueRef alpha_pass =
535 lp_build_cmp(&bld_base->base,
536 si_shader_ctx->shader->key.ps.alpha_func,
537 LLVMBuildLoad(gallivm->builder, out_ptr, ""),
538 lp_build_const_float(gallivm, si_shader_ctx->shader->key.ps.alpha_ref));
539 LLVMValueRef arg =
540 lp_build_select(&bld_base->base,
541 alpha_pass,
542 lp_build_const_float(gallivm, 1.0f),
543 lp_build_const_float(gallivm, -1.0f));
544
545 build_intrinsic(gallivm->builder,
546 "llvm.AMDGPU.kill",
547 LLVMVoidTypeInContext(gallivm->context),
548 &arg, 1, 0);
549 } else {
550 build_intrinsic(gallivm->builder,
551 "llvm.AMDGPU.kilp",
552 LLVMVoidTypeInContext(gallivm->context),
553 NULL, 0, 0);
554 }
555 }
556
557 /* XXX: This is partially implemented for VS only at this point. It is not complete */
558 static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
559 {
560 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
561 struct si_shader * shader = &si_shader_ctx->shader->shader;
562 struct lp_build_context * base = &bld_base->base;
563 struct lp_build_context * uint =
564 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
565 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
566 LLVMValueRef args[9];
567 LLVMValueRef last_args[9] = { 0 };
568 unsigned color_count = 0;
569 unsigned param_count = 0;
570 int depth_index = -1, stencil_index = -1;
571
572 while (!tgsi_parse_end_of_tokens(parse)) {
573 struct tgsi_full_declaration *d =
574 &parse->FullToken.FullDeclaration;
575 unsigned target;
576 unsigned index;
577 int i;
578
579 tgsi_parse_token(parse);
580
581 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_PROPERTY &&
582 parse->FullToken.FullProperty.Property.PropertyName ==
583 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS)
584 shader->fs_write_all = TRUE;
585
586 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
587 continue;
588
589 switch (d->Declaration.File) {
590 case TGSI_FILE_INPUT:
591 i = shader->ninput++;
592 assert(i < Elements(shader->input));
593 shader->input[i].name = d->Semantic.Name;
594 shader->input[i].sid = d->Semantic.Index;
595 shader->input[i].interpolate = d->Interp.Interpolate;
596 shader->input[i].centroid = d->Interp.Centroid;
597 continue;
598
599 case TGSI_FILE_OUTPUT:
600 i = shader->noutput++;
601 assert(i < Elements(shader->output));
602 shader->output[i].name = d->Semantic.Name;
603 shader->output[i].sid = d->Semantic.Index;
604 shader->output[i].interpolate = d->Interp.Interpolate;
605 break;
606
607 default:
608 continue;
609 }
610
611 for (index = d->Range.First; index <= d->Range.Last; index++) {
612 /* Select the correct target */
613 switch(d->Semantic.Name) {
614 case TGSI_SEMANTIC_PSIZE:
615 shader->vs_out_misc_write = 1;
616 shader->vs_out_point_size = 1;
617 target = V_008DFC_SQ_EXP_POS + 1;
618 break;
619 case TGSI_SEMANTIC_POSITION:
620 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
621 target = V_008DFC_SQ_EXP_POS;
622 break;
623 } else {
624 depth_index = index;
625 continue;
626 }
627 case TGSI_SEMANTIC_STENCIL:
628 stencil_index = index;
629 continue;
630 case TGSI_SEMANTIC_COLOR:
631 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
632 case TGSI_SEMANTIC_BCOLOR:
633 target = V_008DFC_SQ_EXP_PARAM + param_count;
634 shader->output[i].param_offset = param_count;
635 param_count++;
636 } else {
637 target = V_008DFC_SQ_EXP_MRT + color_count;
638 if (color_count == 0 &&
639 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
640 si_alpha_test(bld_base, index);
641
642 color_count++;
643 }
644 break;
645 case TGSI_SEMANTIC_FOG:
646 case TGSI_SEMANTIC_GENERIC:
647 target = V_008DFC_SQ_EXP_PARAM + param_count;
648 shader->output[i].param_offset = param_count;
649 param_count++;
650 break;
651 default:
652 target = 0;
653 fprintf(stderr,
654 "Warning: SI unhandled output type:%d\n",
655 d->Semantic.Name);
656 }
657
658 si_llvm_init_export_args(bld_base, d, index, target, args);
659
660 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX ?
661 (d->Semantic.Name == TGSI_SEMANTIC_POSITION) :
662 (d->Semantic.Name == TGSI_SEMANTIC_COLOR)) {
663 if (last_args[0]) {
664 lp_build_intrinsic(base->gallivm->builder,
665 "llvm.SI.export",
666 LLVMVoidTypeInContext(base->gallivm->context),
667 last_args, 9);
668 }
669
670 memcpy(last_args, args, sizeof(args));
671 } else {
672 lp_build_intrinsic(base->gallivm->builder,
673 "llvm.SI.export",
674 LLVMVoidTypeInContext(base->gallivm->context),
675 args, 9);
676 }
677
678 }
679 }
680
681 if (depth_index >= 0 || stencil_index >= 0) {
682 LLVMValueRef out_ptr;
683 unsigned mask = 0;
684
685 /* Specify the target we are exporting */
686 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
687
688 if (depth_index >= 0) {
689 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
690 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
691 mask |= 0x1;
692
693 if (stencil_index < 0) {
694 args[6] =
695 args[7] =
696 args[8] = args[5];
697 }
698 }
699
700 if (stencil_index >= 0) {
701 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
702 args[7] =
703 args[8] =
704 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
705 mask |= 0x2;
706
707 if (depth_index < 0)
708 args[5] = args[6];
709 }
710
711 /* Specify which components to enable */
712 args[0] = lp_build_const_int32(base->gallivm, mask);
713
714 args[1] =
715 args[2] =
716 args[4] = uint->zero;
717
718 if (last_args[0])
719 lp_build_intrinsic(base->gallivm->builder,
720 "llvm.SI.export",
721 LLVMVoidTypeInContext(base->gallivm->context),
722 args, 9);
723 else
724 memcpy(last_args, args, sizeof(args));
725 }
726
727 if (!last_args[0]) {
728 assert(si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT);
729
730 /* Specify which components to enable */
731 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
732
733 /* Specify the target we are exporting */
734 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
735
736 /* Set COMPR flag to zero to export data as 32-bit */
737 last_args[4] = uint->zero;
738
739 /* dummy bits */
740 last_args[5]= uint->zero;
741 last_args[6]= uint->zero;
742 last_args[7]= uint->zero;
743 last_args[8]= uint->zero;
744
745 si_shader_ctx->shader->spi_shader_col_format |=
746 V_028714_SPI_SHADER_32_ABGR;
747 }
748
749 /* Specify whether the EXEC mask represents the valid mask */
750 last_args[1] = lp_build_const_int32(base->gallivm,
751 si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT);
752
753 if (shader->fs_write_all && shader->nr_cbufs > 1) {
754 int i;
755
756 /* Specify that this is not yet the last export */
757 last_args[2] = lp_build_const_int32(base->gallivm, 0);
758
759 for (i = 1; i < shader->nr_cbufs; i++) {
760 /* Specify the target we are exporting */
761 last_args[3] = lp_build_const_int32(base->gallivm,
762 V_008DFC_SQ_EXP_MRT + i);
763
764 lp_build_intrinsic(base->gallivm->builder,
765 "llvm.SI.export",
766 LLVMVoidTypeInContext(base->gallivm->context),
767 last_args, 9);
768
769 si_shader_ctx->shader->spi_shader_col_format |=
770 si_shader_ctx->shader->spi_shader_col_format << 4;
771 }
772
773 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
774 }
775
776 /* Specify that this is the last export */
777 last_args[2] = lp_build_const_int32(base->gallivm, 1);
778
779 lp_build_intrinsic(base->gallivm->builder,
780 "llvm.SI.export",
781 LLVMVoidTypeInContext(base->gallivm->context),
782 last_args, 9);
783
784 /* XXX: Look up what this function does */
785 /* ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);*/
786 }
787
788 static void tex_fetch_args(
789 struct lp_build_tgsi_context * bld_base,
790 struct lp_build_emit_data * emit_data)
791 {
792 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
793 struct gallivm_state *gallivm = bld_base->base.gallivm;
794 const struct tgsi_full_instruction * inst = emit_data->inst;
795 unsigned opcode = inst->Instruction.Opcode;
796 unsigned target = inst->Texture.Texture;
797 LLVMValueRef coords[4];
798 LLVMValueRef address[16];
799 unsigned count = 0;
800 unsigned chan;
801
802 /* Fetch and project texture coordinates */
803 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
804 for (chan = 0; chan < 3; chan++ ) {
805 coords[chan] = lp_build_emit_fetch(bld_base,
806 emit_data->inst, 0,
807 chan);
808 if (opcode == TGSI_OPCODE_TXP)
809 coords[chan] = lp_build_emit_llvm_binary(bld_base,
810 TGSI_OPCODE_DIV,
811 coords[chan],
812 coords[3]);
813 }
814
815 if (opcode == TGSI_OPCODE_TXP)
816 coords[3] = bld_base->base.one;
817
818 /* Pack LOD bias value */
819 if (opcode == TGSI_OPCODE_TXB)
820 address[count++] = coords[3];
821
822 if ((target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE) &&
823 opcode != TGSI_OPCODE_TXQ)
824 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
825
826 /* Pack depth comparison value */
827 switch (target) {
828 case TGSI_TEXTURE_SHADOW1D:
829 case TGSI_TEXTURE_SHADOW1D_ARRAY:
830 case TGSI_TEXTURE_SHADOW2D:
831 case TGSI_TEXTURE_SHADOWRECT:
832 address[count++] = coords[2];
833 break;
834 case TGSI_TEXTURE_SHADOWCUBE:
835 case TGSI_TEXTURE_SHADOW2D_ARRAY:
836 address[count++] = coords[3];
837 break;
838 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
839 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
840 }
841
842 /* Pack texture coordinates */
843 address[count++] = coords[0];
844 switch (target) {
845 case TGSI_TEXTURE_2D:
846 case TGSI_TEXTURE_2D_ARRAY:
847 case TGSI_TEXTURE_3D:
848 case TGSI_TEXTURE_CUBE:
849 case TGSI_TEXTURE_RECT:
850 case TGSI_TEXTURE_SHADOW2D:
851 case TGSI_TEXTURE_SHADOWRECT:
852 case TGSI_TEXTURE_SHADOW2D_ARRAY:
853 case TGSI_TEXTURE_SHADOWCUBE:
854 case TGSI_TEXTURE_2D_MSAA:
855 case TGSI_TEXTURE_2D_ARRAY_MSAA:
856 case TGSI_TEXTURE_CUBE_ARRAY:
857 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
858 address[count++] = coords[1];
859 }
860 switch (target) {
861 case TGSI_TEXTURE_3D:
862 case TGSI_TEXTURE_CUBE:
863 case TGSI_TEXTURE_SHADOWCUBE:
864 case TGSI_TEXTURE_CUBE_ARRAY:
865 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
866 address[count++] = coords[2];
867 }
868
869 /* Pack array slice */
870 switch (target) {
871 case TGSI_TEXTURE_1D_ARRAY:
872 address[count++] = coords[1];
873 }
874 switch (target) {
875 case TGSI_TEXTURE_2D_ARRAY:
876 case TGSI_TEXTURE_2D_ARRAY_MSAA:
877 case TGSI_TEXTURE_SHADOW2D_ARRAY:
878 address[count++] = coords[2];
879 }
880 switch (target) {
881 case TGSI_TEXTURE_CUBE_ARRAY:
882 case TGSI_TEXTURE_SHADOW1D_ARRAY:
883 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
884 address[count++] = coords[3];
885 }
886
887 /* Pack LOD */
888 if (opcode == TGSI_OPCODE_TXL)
889 address[count++] = coords[3];
890
891 if (count > 16) {
892 assert(!"Cannot handle more than 16 texture address parameters");
893 count = 16;
894 }
895
896 for (chan = 0; chan < count; chan++ ) {
897 address[chan] = LLVMBuildBitCast(gallivm->builder,
898 address[chan],
899 LLVMInt32TypeInContext(gallivm->context),
900 "");
901 }
902
903 /* Pad to power of two vector */
904 while (count < util_next_power_of_two(count))
905 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
906
907 emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
908
909 /* Resource */
910 emit_data->args[1] = si_shader_ctx->resources[emit_data->inst->Src[1].Register.Index];
911
912 /* Sampler */
913 emit_data->args[2] = si_shader_ctx->samplers[emit_data->inst->Src[1].Register.Index];
914
915 /* Dimensions */
916 emit_data->args[3] = lp_build_const_int32(bld_base->base.gallivm, target);
917
918 emit_data->arg_count = 4;
919
920 emit_data->dst_type = LLVMVectorType(
921 LLVMFloatTypeInContext(bld_base->base.gallivm->context),
922 4);
923 }
924
925 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
926 struct lp_build_tgsi_context * bld_base,
927 struct lp_build_emit_data * emit_data)
928 {
929 struct lp_build_context * base = &bld_base->base;
930 char intr_name[23];
931
932 sprintf(intr_name, "%sv%ui32", action->intr_name,
933 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
934
935 emit_data->output[emit_data->chan] = build_intrinsic(
936 base->gallivm->builder, intr_name, emit_data->dst_type,
937 emit_data->args, emit_data->arg_count,
938 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
939 }
940
941 static const struct lp_build_tgsi_action tex_action = {
942 .fetch_args = tex_fetch_args,
943 .emit = build_tex_intrinsic,
944 .intr_name = "llvm.SI.sample."
945 };
946
947 static const struct lp_build_tgsi_action txb_action = {
948 .fetch_args = tex_fetch_args,
949 .emit = build_tex_intrinsic,
950 .intr_name = "llvm.SI.sampleb."
951 };
952
953 static const struct lp_build_tgsi_action txl_action = {
954 .fetch_args = tex_fetch_args,
955 .emit = build_tex_intrinsic,
956 .intr_name = "llvm.SI.samplel."
957 };
958
959 static void create_meta_data(struct si_shader_context *si_shader_ctx)
960 {
961 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
962 LLVMValueRef args[3];
963
964 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
965 args[1] = 0;
966 args[2] = lp_build_const_int32(gallivm, 1);
967
968 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
969 }
970
971 static void create_function(struct si_shader_context *si_shader_ctx)
972 {
973 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
974 LLVMTypeRef params[20], f32, i8, i32, v2i32, v3i32;
975 unsigned i;
976
977 i8 = LLVMInt8TypeInContext(gallivm->context);
978 i32 = LLVMInt32TypeInContext(gallivm->context);
979 f32 = LLVMFloatTypeInContext(gallivm->context);
980 v2i32 = LLVMVectorType(i32, 2);
981 v3i32 = LLVMVectorType(i32, 3);
982
983 params[SI_PARAM_CONST] = LLVMPointerType(LLVMVectorType(i8, 16), CONST_ADDR_SPACE);
984 params[SI_PARAM_SAMPLER] = params[SI_PARAM_CONST];
985 params[SI_PARAM_RESOURCE] = LLVMPointerType(LLVMVectorType(i8, 32), CONST_ADDR_SPACE);
986
987 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
988 params[SI_PARAM_VERTEX_BUFFER] = params[SI_PARAM_SAMPLER];
989 params[SI_PARAM_START_INSTANCE] = i32;
990 params[SI_PARAM_VERTEX_ID] = i32;
991 params[SI_PARAM_DUMMY_0] = i32;
992 params[SI_PARAM_DUMMY_1] = i32;
993 params[SI_PARAM_INSTANCE_ID] = i32;
994 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, 9);
995
996 } else {
997 params[SI_PARAM_PRIM_MASK] = i32;
998 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
999 params[SI_PARAM_PERSP_CENTER] = v2i32;
1000 params[SI_PARAM_PERSP_CENTROID] = v2i32;
1001 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
1002 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
1003 params[SI_PARAM_LINEAR_CENTER] = v2i32;
1004 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
1005 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
1006 params[SI_PARAM_POS_X_FLOAT] = f32;
1007 params[SI_PARAM_POS_Y_FLOAT] = f32;
1008 params[SI_PARAM_POS_Z_FLOAT] = f32;
1009 params[SI_PARAM_POS_W_FLOAT] = f32;
1010 params[SI_PARAM_FRONT_FACE] = f32;
1011 params[SI_PARAM_ANCILLARY] = f32;
1012 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
1013 params[SI_PARAM_POS_FIXED_PT] = f32;
1014 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, 20);
1015 }
1016
1017 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
1018 for (i = SI_PARAM_CONST; i <= SI_PARAM_VERTEX_BUFFER; ++i) {
1019 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
1020 LLVMAddAttribute(P, LLVMInRegAttribute);
1021 }
1022
1023 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
1024 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1025 SI_PARAM_START_INSTANCE);
1026 LLVMAddAttribute(P, LLVMInRegAttribute);
1027 }
1028 }
1029
1030 static void preload_constants(struct si_shader_context *si_shader_ctx)
1031 {
1032 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
1033 struct gallivm_state * gallivm = bld_base->base.gallivm;
1034 const struct tgsi_shader_info * info = bld_base->info;
1035
1036 unsigned i, num_const = info->file_max[TGSI_FILE_CONSTANT] + 1;
1037
1038 LLVMValueRef ptr;
1039
1040 if (num_const == 0)
1041 return;
1042
1043 /* Allocate space for the constant values */
1044 si_shader_ctx->constants = CALLOC(num_const * 4, sizeof(LLVMValueRef));
1045
1046 /* Load the resource descriptor */
1047 ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1048 si_shader_ctx->const_resource = build_indexed_load(si_shader_ctx, ptr, bld_base->uint_bld.zero);
1049
1050 /* Load the constants, we rely on the code sinking to do the rest */
1051 for (i = 0; i < num_const * 4; ++i) {
1052 LLVMValueRef args[2] = {
1053 si_shader_ctx->const_resource,
1054 lp_build_const_int32(gallivm, i * 4)
1055 };
1056 si_shader_ctx->constants[i] = build_intrinsic(gallivm->builder, "llvm.SI.load.const",
1057 bld_base->base.elem_type, args, 2, LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1058 }
1059 }
1060
1061 static void preload_samplers(struct si_shader_context *si_shader_ctx)
1062 {
1063 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
1064 struct gallivm_state * gallivm = bld_base->base.gallivm;
1065 const struct tgsi_shader_info * info = bld_base->info;
1066
1067 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
1068
1069 LLVMValueRef res_ptr, samp_ptr;
1070 LLVMValueRef offset;
1071
1072 if (num_samplers == 0)
1073 return;
1074
1075 /* Allocate space for the values */
1076 si_shader_ctx->resources = CALLOC(num_samplers, sizeof(LLVMValueRef));
1077 si_shader_ctx->samplers = CALLOC(num_samplers, sizeof(LLVMValueRef));
1078
1079 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
1080 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
1081
1082 /* Load the resources and samplers, we rely on the code sinking to do the rest */
1083 for (i = 0; i < num_samplers; ++i) {
1084
1085 /* Resource */
1086 offset = lp_build_const_int32(gallivm, i);
1087 si_shader_ctx->resources[i] = build_indexed_load(si_shader_ctx, res_ptr, offset);
1088
1089 /* Sampler */
1090 offset = lp_build_const_int32(gallivm, i);
1091 si_shader_ctx->samplers[i] = build_indexed_load(si_shader_ctx, samp_ptr, offset);
1092 }
1093 }
1094
1095 int si_compile_llvm(struct r600_context *rctx, struct si_pipe_shader *shader,
1096 LLVMModuleRef mod)
1097 {
1098 unsigned i;
1099 uint32_t *ptr;
1100 bool dump;
1101 struct radeon_llvm_binary binary;
1102
1103 dump = debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE);
1104
1105 memset(&binary, 0, sizeof(binary));
1106 radeon_llvm_compile(mod, &binary,
1107 r600_get_llvm_processor_name(rctx->screen->family), dump);
1108 if (dump) {
1109 fprintf(stderr, "SI CODE:\n");
1110 for (i = 0; i < binary.code_size; i+=4 ) {
1111 fprintf(stderr, "%02x%02x%02x%02x\n", binary.code[i + 3],
1112 binary.code[i + 2], binary.code[i + 1],
1113 binary.code[i]);
1114 }
1115 }
1116
1117 /* XXX: We may be able to emit some of these values directly rather than
1118 * extracting fields to be emitted later.
1119 */
1120 for (i = 0; i < binary.config_size; i+= 8) {
1121 unsigned reg = util_le32_to_cpu(*(uint32_t*)(binary.config + i));
1122 unsigned value = util_le32_to_cpu(*(uint32_t*)(binary.config + i + 4));
1123 switch (reg) {
1124 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
1125 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
1126 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
1127 case R_00B848_COMPUTE_PGM_RSRC1:
1128 shader->num_sgprs = (G_00B028_SGPRS(value) + 1) * 8;
1129 shader->num_vgprs = (G_00B028_VGPRS(value) + 1) * 4;
1130 break;
1131 case R_0286CC_SPI_PS_INPUT_ENA:
1132 shader->spi_ps_input_ena = value;
1133 break;
1134 default:
1135 fprintf(stderr, "Warning: Compiler emitted unknown "
1136 "config register: 0x%x\n", reg);
1137 break;
1138 }
1139 }
1140
1141 /* copy new shader */
1142 si_resource_reference(&shader->bo, NULL);
1143 shader->bo = si_resource_create_custom(rctx->context.screen, PIPE_USAGE_IMMUTABLE,
1144 binary.code_size);
1145 if (shader->bo == NULL) {
1146 return -ENOMEM;
1147 }
1148
1149 ptr = (uint32_t*)rctx->ws->buffer_map(shader->bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
1150 if (0 /*R600_BIG_ENDIAN*/) {
1151 for (i = 0; i < binary.code_size / 4; ++i) {
1152 ptr[i] = util_bswap32(*(uint32_t*)(binary.code + i*4));
1153 }
1154 } else {
1155 memcpy(ptr, binary.code, binary.code_size);
1156 }
1157 rctx->ws->buffer_unmap(shader->bo->cs_buf);
1158
1159 free(binary.code);
1160 free(binary.config);
1161
1162 return 0;
1163 }
1164
1165 int si_pipe_shader_create(
1166 struct pipe_context *ctx,
1167 struct si_pipe_shader *shader)
1168 {
1169 struct r600_context *rctx = (struct r600_context*)ctx;
1170 struct si_pipe_shader_selector *sel = shader->selector;
1171 struct si_shader_context si_shader_ctx;
1172 struct tgsi_shader_info shader_info;
1173 struct lp_build_tgsi_context * bld_base;
1174 LLVMModuleRef mod;
1175 bool dump;
1176 int r = 0;
1177
1178 dump = debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE);
1179
1180 assert(shader->shader.noutput == 0);
1181 assert(shader->shader.ninterp == 0);
1182 assert(shader->shader.ninput == 0);
1183
1184 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
1185 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
1186 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
1187
1188 tgsi_scan_shader(sel->tokens, &shader_info);
1189 shader->shader.uses_kill = shader_info.uses_kill;
1190 shader->shader.uses_instanceid = shader_info.uses_instanceid;
1191 bld_base->info = &shader_info;
1192 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
1193 bld_base->emit_epilogue = si_llvm_emit_epilogue;
1194
1195 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
1196 bld_base->op_actions[TGSI_OPCODE_TXB] = txb_action;
1197 bld_base->op_actions[TGSI_OPCODE_TXL] = txl_action;
1198 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
1199
1200 si_shader_ctx.radeon_bld.load_input = declare_input;
1201 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
1202 si_shader_ctx.tokens = sel->tokens;
1203 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
1204 si_shader_ctx.shader = shader;
1205 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
1206
1207 create_meta_data(&si_shader_ctx);
1208 create_function(&si_shader_ctx);
1209 preload_constants(&si_shader_ctx);
1210 preload_samplers(&si_shader_ctx);
1211
1212 shader->shader.nr_cbufs = rctx->framebuffer.nr_cbufs;
1213
1214 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
1215 * conversion fails. */
1216 if (dump) {
1217 tgsi_dump(sel->tokens, 0);
1218 }
1219
1220 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
1221 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
1222 FREE(si_shader_ctx.constants);
1223 FREE(si_shader_ctx.resources);
1224 FREE(si_shader_ctx.samplers);
1225 return -EINVAL;
1226 }
1227
1228 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
1229
1230 mod = bld_base->base.gallivm->module;
1231 r = si_compile_llvm(rctx, shader, mod);
1232
1233 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
1234 tgsi_parse_free(&si_shader_ctx.parse);
1235
1236 FREE(si_shader_ctx.constants);
1237 FREE(si_shader_ctx.resources);
1238 FREE(si_shader_ctx.samplers);
1239
1240 return r;
1241 }
1242
1243 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader)
1244 {
1245 si_resource_reference(&shader->bo, NULL);
1246 }