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gallium/radeon: add radeon_surf::is_linear
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "sid.h"
26 #include "util/u_format.h"
27 #include "util/u_surface.h"
28
29 enum si_blitter_op /* bitmask */
30 {
31 SI_SAVE_TEXTURES = 1,
32 SI_SAVE_FRAMEBUFFER = 2,
33 SI_SAVE_FRAGMENT_STATE = 4,
34 SI_DISABLE_RENDER_COND = 8,
35
36 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
37
38 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
39
40 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
41 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
42
43 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
44 SI_SAVE_FRAGMENT_STATE,
45
46 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
47 SI_DISABLE_RENDER_COND,
48
49 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
50 };
51
52 static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
53 {
54 struct si_context *sctx = (struct si_context *)ctx;
55
56 util_blitter_save_vertex_buffer_slot(sctx->blitter, sctx->vertex_buffer);
57 util_blitter_save_vertex_elements(sctx->blitter, sctx->vertex_elements);
58 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
59 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
60 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
61 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
62 util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
63 (struct pipe_stream_output_target**)sctx->b.streamout.targets);
64 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
65
66 if (op & SI_SAVE_FRAGMENT_STATE) {
67 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
68 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
69 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
70 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
71 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask.sample_mask);
72 util_blitter_save_viewport(sctx->blitter, &sctx->b.viewports.states[0]);
73 util_blitter_save_scissor(sctx->blitter, &sctx->b.scissors.states[0]);
74 }
75
76 if (op & SI_SAVE_FRAMEBUFFER)
77 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
78
79 if (op & SI_SAVE_TEXTURES) {
80 util_blitter_save_fragment_sampler_states(
81 sctx->blitter, 2,
82 sctx->samplers[PIPE_SHADER_FRAGMENT].views.sampler_states);
83
84 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
85 sctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
86 }
87
88 if (op & SI_DISABLE_RENDER_COND)
89 sctx->b.render_cond_force_off = true;
90 }
91
92 static void si_blitter_end(struct pipe_context *ctx)
93 {
94 struct si_context *sctx = (struct si_context *)ctx;
95
96 sctx->b.render_cond_force_off = false;
97 }
98
99 static unsigned u_max_sample(struct pipe_resource *r)
100 {
101 return r->nr_samples ? r->nr_samples - 1 : 0;
102 }
103
104 static unsigned
105 si_blit_dbcb_copy(struct si_context *sctx,
106 struct r600_texture *src,
107 struct r600_texture *dst,
108 unsigned planes, unsigned level_mask,
109 unsigned first_layer, unsigned last_layer,
110 unsigned first_sample, unsigned last_sample)
111 {
112 struct pipe_surface surf_tmpl = {{0}};
113 unsigned layer, sample, checked_last_layer, max_layer;
114 unsigned fully_copied_levels = 0;
115
116 if (planes & PIPE_MASK_Z)
117 sctx->dbcb_depth_copy_enabled = true;
118 if (planes & PIPE_MASK_S)
119 sctx->dbcb_stencil_copy_enabled = true;
120 si_mark_atom_dirty(sctx, &sctx->db_render_state);
121
122 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
123
124 while (level_mask) {
125 unsigned level = u_bit_scan(&level_mask);
126
127 /* The smaller the mipmap level, the less layers there are
128 * as far as 3D textures are concerned. */
129 max_layer = util_max_layer(&src->resource.b.b, level);
130 checked_last_layer = MIN2(last_layer, max_layer);
131
132 surf_tmpl.u.tex.level = level;
133
134 for (layer = first_layer; layer <= checked_last_layer; layer++) {
135 struct pipe_surface *zsurf, *cbsurf;
136
137 surf_tmpl.format = src->resource.b.b.format;
138 surf_tmpl.u.tex.first_layer = layer;
139 surf_tmpl.u.tex.last_layer = layer;
140
141 zsurf = sctx->b.b.create_surface(&sctx->b.b, &src->resource.b.b, &surf_tmpl);
142
143 surf_tmpl.format = dst->resource.b.b.format;
144 cbsurf = sctx->b.b.create_surface(&sctx->b.b, &dst->resource.b.b, &surf_tmpl);
145
146 for (sample = first_sample; sample <= last_sample; sample++) {
147 if (sample != sctx->dbcb_copy_sample) {
148 sctx->dbcb_copy_sample = sample;
149 si_mark_atom_dirty(sctx, &sctx->db_render_state);
150 }
151
152 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
153 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
154 sctx->custom_dsa_flush, 1.0f);
155 si_blitter_end(&sctx->b.b);
156 }
157
158 pipe_surface_reference(&zsurf, NULL);
159 pipe_surface_reference(&cbsurf, NULL);
160 }
161
162 if (first_layer == 0 && last_layer >= max_layer &&
163 first_sample == 0 && last_sample >= u_max_sample(&src->resource.b.b))
164 fully_copied_levels |= 1u << level;
165 }
166
167 sctx->dbcb_depth_copy_enabled = false;
168 sctx->dbcb_stencil_copy_enabled = false;
169 si_mark_atom_dirty(sctx, &sctx->db_render_state);
170
171 return fully_copied_levels;
172 }
173
174 static void si_blit_decompress_depth(struct pipe_context *ctx,
175 struct r600_texture *texture,
176 struct r600_texture *staging,
177 unsigned first_level, unsigned last_level,
178 unsigned first_layer, unsigned last_layer,
179 unsigned first_sample, unsigned last_sample)
180 {
181 const struct util_format_description *desc;
182 unsigned planes = 0;
183
184 assert(staging != NULL && "use si_blit_decompress_zs_in_place instead");
185
186 desc = util_format_description(staging->resource.b.b.format);
187
188 if (util_format_has_depth(desc))
189 planes |= PIPE_MASK_Z;
190 if (util_format_has_stencil(desc))
191 planes |= PIPE_MASK_S;
192
193 si_blit_dbcb_copy(
194 (struct si_context *)ctx, texture, staging, planes,
195 u_bit_consecutive(first_level, last_level - first_level + 1),
196 first_layer, last_layer, first_sample, last_sample);
197 }
198
199 /* Helper function for si_blit_decompress_zs_in_place.
200 */
201 static void
202 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
203 struct r600_texture *texture,
204 unsigned planes, unsigned level_mask,
205 unsigned first_layer, unsigned last_layer)
206 {
207 struct pipe_surface *zsurf, surf_tmpl = {{0}};
208 unsigned layer, max_layer, checked_last_layer;
209 unsigned fully_decompressed_mask = 0;
210
211 if (!level_mask)
212 return;
213
214 if (planes & PIPE_MASK_S)
215 sctx->db_flush_stencil_inplace = true;
216 if (planes & PIPE_MASK_Z)
217 sctx->db_flush_depth_inplace = true;
218 si_mark_atom_dirty(sctx, &sctx->db_render_state);
219
220 surf_tmpl.format = texture->resource.b.b.format;
221
222 while (level_mask) {
223 unsigned level = u_bit_scan(&level_mask);
224
225 surf_tmpl.u.tex.level = level;
226
227 /* The smaller the mipmap level, the less layers there are
228 * as far as 3D textures are concerned. */
229 max_layer = util_max_layer(&texture->resource.b.b, level);
230 checked_last_layer = MIN2(last_layer, max_layer);
231
232 for (layer = first_layer; layer <= checked_last_layer; layer++) {
233 surf_tmpl.u.tex.first_layer = layer;
234 surf_tmpl.u.tex.last_layer = layer;
235
236 zsurf = sctx->b.b.create_surface(&sctx->b.b, &texture->resource.b.b, &surf_tmpl);
237
238 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
239 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
240 sctx->custom_dsa_flush,
241 1.0f);
242 si_blitter_end(&sctx->b.b);
243
244 pipe_surface_reference(&zsurf, NULL);
245 }
246
247 /* The texture will always be dirty if some layers aren't flushed.
248 * I don't think this case occurs often though. */
249 if (first_layer == 0 && last_layer >= max_layer) {
250 fully_decompressed_mask |= 1u << level;
251 }
252 }
253
254 if (planes & PIPE_MASK_Z)
255 texture->dirty_level_mask &= ~fully_decompressed_mask;
256 if (planes & PIPE_MASK_S)
257 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
258
259 sctx->db_flush_depth_inplace = false;
260 sctx->db_flush_stencil_inplace = false;
261 si_mark_atom_dirty(sctx, &sctx->db_render_state);
262 }
263
264 /* Helper function of si_flush_depth_texture: decompress the given levels
265 * of Z and/or S planes in place.
266 */
267 static void
268 si_blit_decompress_zs_in_place(struct si_context *sctx,
269 struct r600_texture *texture,
270 unsigned levels_z, unsigned levels_s,
271 unsigned first_layer, unsigned last_layer)
272 {
273 unsigned both = levels_z & levels_s;
274
275 /* First, do combined Z & S decompresses for levels that need it. */
276 if (both) {
277 si_blit_decompress_zs_planes_in_place(
278 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
279 both,
280 first_layer, last_layer);
281 levels_z &= ~both;
282 levels_s &= ~both;
283 }
284
285 /* Now do separate Z and S decompresses. */
286 if (levels_z) {
287 si_blit_decompress_zs_planes_in_place(
288 sctx, texture, PIPE_MASK_Z,
289 levels_z,
290 first_layer, last_layer);
291 }
292
293 if (levels_s) {
294 si_blit_decompress_zs_planes_in_place(
295 sctx, texture, PIPE_MASK_S,
296 levels_s,
297 first_layer, last_layer);
298 }
299 }
300
301 static void
302 si_flush_depth_texture(struct si_context *sctx,
303 struct r600_texture *tex,
304 unsigned required_planes,
305 unsigned first_level, unsigned last_level,
306 unsigned first_layer, unsigned last_layer)
307 {
308 unsigned inplace_planes = 0;
309 unsigned copy_planes = 0;
310 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
311 unsigned levels_z = 0;
312 unsigned levels_s = 0;
313
314 if (required_planes & PIPE_MASK_Z) {
315 levels_z = level_mask & tex->dirty_level_mask;
316
317 if (levels_z) {
318 if (r600_can_sample_zs(tex, false))
319 inplace_planes |= PIPE_MASK_Z;
320 else
321 copy_planes |= PIPE_MASK_Z;
322 }
323 }
324 if (required_planes & PIPE_MASK_S) {
325 levels_s = level_mask & tex->stencil_dirty_level_mask;
326
327 if (levels_s) {
328 if (r600_can_sample_zs(tex, true))
329 inplace_planes |= PIPE_MASK_S;
330 else
331 copy_planes |= PIPE_MASK_S;
332 }
333 }
334
335 assert(!tex->tc_compatible_htile || levels_z == 0);
336
337 /* We may have to allocate the flushed texture here when called from
338 * si_decompress_subresource.
339 */
340 if (copy_planes &&
341 (tex->flushed_depth_texture ||
342 r600_init_flushed_depth_texture(&sctx->b.b, &tex->resource.b.b, NULL))) {
343 struct r600_texture *dst = tex->flushed_depth_texture;
344 unsigned fully_copied_levels;
345 unsigned levels = 0;
346
347 assert(tex->flushed_depth_texture);
348
349 if (util_format_is_depth_and_stencil(dst->resource.b.b.format))
350 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
351
352 if (copy_planes & PIPE_MASK_Z) {
353 levels |= levels_z;
354 levels_z = 0;
355 }
356 if (copy_planes & PIPE_MASK_S) {
357 levels |= levels_s;
358 levels_s = 0;
359 }
360
361 fully_copied_levels = si_blit_dbcb_copy(
362 sctx, tex, dst, copy_planes, levels,
363 first_layer, last_layer,
364 0, u_max_sample(&tex->resource.b.b));
365
366 if (copy_planes & PIPE_MASK_Z)
367 tex->dirty_level_mask &= ~fully_copied_levels;
368 if (copy_planes & PIPE_MASK_S)
369 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
370 }
371
372 if (inplace_planes) {
373 si_blit_decompress_zs_in_place(
374 sctx, tex,
375 levels_z, levels_s,
376 first_layer, last_layer);
377 }
378 }
379
380 static void
381 si_flush_depth_textures(struct si_context *sctx,
382 struct si_textures_info *textures)
383 {
384 unsigned i;
385 unsigned mask = textures->depth_texture_mask;
386
387 while (mask) {
388 struct pipe_sampler_view *view;
389 struct si_sampler_view *sview;
390 struct r600_texture *tex;
391
392 i = u_bit_scan(&mask);
393
394 view = textures->views.views[i];
395 assert(view);
396 sview = (struct si_sampler_view*)view;
397
398 tex = (struct r600_texture *)view->texture;
399 assert(tex->db_compatible);
400
401 si_flush_depth_texture(
402 sctx, tex,
403 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
404 view->u.tex.first_level, view->u.tex.last_level,
405 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
406 }
407 }
408
409 static void si_blit_decompress_color(struct pipe_context *ctx,
410 struct r600_texture *rtex,
411 unsigned first_level, unsigned last_level,
412 unsigned first_layer, unsigned last_layer,
413 bool need_dcc_decompress)
414 {
415 struct si_context *sctx = (struct si_context *)ctx;
416 void* custom_blend;
417 unsigned layer, checked_last_layer, max_layer;
418 unsigned level_mask =
419 u_bit_consecutive(first_level, last_level - first_level + 1);
420
421 if (!need_dcc_decompress)
422 level_mask &= rtex->dirty_level_mask;
423 if (!level_mask)
424 return;
425
426 if (rtex->dcc_offset && need_dcc_decompress) {
427 custom_blend = sctx->custom_blend_dcc_decompress;
428
429 /* disable levels without DCC */
430 for (int i = first_level; i <= last_level; i++) {
431 if (!rtex->dcc_offset ||
432 i >= rtex->surface.num_dcc_levels)
433 level_mask &= ~(1 << i);
434 }
435 } else if (rtex->fmask.size) {
436 custom_blend = sctx->custom_blend_decompress;
437 } else {
438 custom_blend = sctx->custom_blend_fastclear;
439 }
440
441 while (level_mask) {
442 unsigned level = u_bit_scan(&level_mask);
443
444 /* The smaller the mipmap level, the less layers there are
445 * as far as 3D textures are concerned. */
446 max_layer = util_max_layer(&rtex->resource.b.b, level);
447 checked_last_layer = MIN2(last_layer, max_layer);
448
449 for (layer = first_layer; layer <= checked_last_layer; layer++) {
450 struct pipe_surface *cbsurf, surf_tmpl;
451
452 surf_tmpl.format = rtex->resource.b.b.format;
453 surf_tmpl.u.tex.level = level;
454 surf_tmpl.u.tex.first_layer = layer;
455 surf_tmpl.u.tex.last_layer = layer;
456 cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
457
458 si_blitter_begin(ctx, SI_DECOMPRESS);
459 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
460 si_blitter_end(ctx);
461
462 pipe_surface_reference(&cbsurf, NULL);
463 }
464
465 /* The texture will always be dirty if some layers aren't flushed.
466 * I don't think this case occurs often though. */
467 if (first_layer == 0 && last_layer >= max_layer) {
468 rtex->dirty_level_mask &= ~(1 << level);
469 }
470 }
471 }
472
473 static void
474 si_decompress_sampler_color_textures(struct si_context *sctx,
475 struct si_textures_info *textures)
476 {
477 unsigned i;
478 unsigned mask = textures->compressed_colortex_mask;
479
480 while (mask) {
481 struct pipe_sampler_view *view;
482 struct r600_texture *tex;
483
484 i = u_bit_scan(&mask);
485
486 view = textures->views.views[i];
487 assert(view);
488
489 tex = (struct r600_texture *)view->texture;
490 assert(tex->cmask.size || tex->fmask.size || tex->dcc_offset);
491
492 si_blit_decompress_color(&sctx->b.b, tex,
493 view->u.tex.first_level, view->u.tex.last_level,
494 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level),
495 false);
496 }
497 }
498
499 static void
500 si_decompress_image_color_textures(struct si_context *sctx,
501 struct si_images_info *images)
502 {
503 unsigned i;
504 unsigned mask = images->compressed_colortex_mask;
505
506 while (mask) {
507 const struct pipe_image_view *view;
508 struct r600_texture *tex;
509
510 i = u_bit_scan(&mask);
511
512 view = &images->views[i];
513 assert(view->resource->target != PIPE_BUFFER);
514
515 tex = (struct r600_texture *)view->resource;
516 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
517 continue;
518
519 si_blit_decompress_color(&sctx->b.b, tex,
520 view->u.tex.level, view->u.tex.level,
521 0, util_max_layer(&tex->resource.b.b, view->u.tex.level),
522 false);
523 }
524 }
525
526 static void si_check_render_feedback_textures(struct si_context *sctx,
527 struct si_textures_info *textures)
528 {
529 uint32_t mask = textures->views.enabled_mask;
530
531 while (mask) {
532 const struct pipe_sampler_view *view;
533 struct r600_texture *tex;
534 bool render_feedback = false;
535
536 unsigned i = u_bit_scan(&mask);
537
538 view = textures->views.views[i];
539 if(view->texture->target == PIPE_BUFFER)
540 continue;
541
542 tex = (struct r600_texture *)view->texture;
543 if (!tex->dcc_offset)
544 continue;
545
546 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
547 struct r600_surface * surf;
548
549 if (!sctx->framebuffer.state.cbufs[j])
550 continue;
551
552 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
553
554 if (tex == (struct r600_texture*)surf->base.texture &&
555 surf->base.u.tex.level >= view->u.tex.first_level &&
556 surf->base.u.tex.level <= view->u.tex.last_level &&
557 surf->base.u.tex.first_layer <= view->u.tex.last_layer &&
558 surf->base.u.tex.last_layer >= view->u.tex.first_layer)
559 render_feedback = true;
560 }
561
562 if (render_feedback)
563 r600_texture_disable_dcc(&sctx->b, tex);
564 }
565 }
566
567 static void si_check_render_feedback_images(struct si_context *sctx,
568 struct si_images_info *images)
569 {
570 uint32_t mask = images->enabled_mask;
571
572 while (mask) {
573 const struct pipe_image_view *view;
574 struct r600_texture *tex;
575 bool render_feedback = false;
576
577 unsigned i = u_bit_scan(&mask);
578
579 view = &images->views[i];
580 if (view->resource->target == PIPE_BUFFER)
581 continue;
582
583 tex = (struct r600_texture *)view->resource;
584 if (!tex->dcc_offset)
585 continue;
586
587 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
588 struct r600_surface * surf;
589
590 if (!sctx->framebuffer.state.cbufs[j])
591 continue;
592
593 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
594
595 if (tex == (struct r600_texture*)surf->base.texture &&
596 surf->base.u.tex.level == view->u.tex.level &&
597 surf->base.u.tex.first_layer <= view->u.tex.last_layer &&
598 surf->base.u.tex.last_layer >= view->u.tex.first_layer)
599 render_feedback = true;
600 }
601
602 if (render_feedback)
603 r600_texture_disable_dcc(&sctx->b, tex);
604 }
605 }
606
607 static void si_check_render_feedback(struct si_context *sctx)
608 {
609
610 if (!sctx->need_check_render_feedback)
611 return;
612
613 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
614 si_check_render_feedback_images(sctx, &sctx->images[i]);
615 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
616 }
617 sctx->need_check_render_feedback = false;
618 }
619
620 static void si_decompress_textures(struct si_context *sctx, int shader_start,
621 int shader_end)
622 {
623 unsigned compressed_colortex_counter;
624
625 if (sctx->blitter->running)
626 return;
627
628 /* Update the compressed_colortex_mask if necessary. */
629 compressed_colortex_counter = p_atomic_read(&sctx->screen->b.compressed_colortex_counter);
630 if (compressed_colortex_counter != sctx->b.last_compressed_colortex_counter) {
631 sctx->b.last_compressed_colortex_counter = compressed_colortex_counter;
632 si_update_compressed_colortex_masks(sctx);
633 }
634
635 /* Flush depth textures which need to be flushed. */
636 for (int i = shader_start; i < shader_end; i++) {
637 if (sctx->samplers[i].depth_texture_mask) {
638 si_flush_depth_textures(sctx, &sctx->samplers[i]);
639 }
640 if (sctx->samplers[i].compressed_colortex_mask) {
641 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
642 }
643 if (sctx->images[i].compressed_colortex_mask) {
644 si_decompress_image_color_textures(sctx, &sctx->images[i]);
645 }
646 }
647
648 si_check_render_feedback(sctx);
649 }
650
651 void si_decompress_graphics_textures(struct si_context *sctx)
652 {
653 si_decompress_textures(sctx, 0, SI_NUM_GRAPHICS_SHADERS);
654 }
655
656 void si_decompress_compute_textures(struct si_context *sctx)
657 {
658 si_decompress_textures(sctx, SI_NUM_GRAPHICS_SHADERS, SI_NUM_SHADERS);
659 }
660
661 static void si_clear(struct pipe_context *ctx, unsigned buffers,
662 const union pipe_color_union *color,
663 double depth, unsigned stencil)
664 {
665 struct si_context *sctx = (struct si_context *)ctx;
666 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
667 struct pipe_surface *zsbuf = fb->zsbuf;
668 struct r600_texture *zstex =
669 zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
670
671 if (buffers & PIPE_CLEAR_COLOR) {
672 evergreen_do_fast_color_clear(&sctx->b, fb,
673 &sctx->framebuffer.atom, &buffers,
674 &sctx->framebuffer.dirty_cbufs,
675 color);
676 if (!buffers)
677 return; /* all buffers have been fast cleared */
678 }
679
680 if (buffers & PIPE_CLEAR_COLOR) {
681 int i;
682
683 /* These buffers cannot use fast clear, make sure to disable expansion. */
684 for (i = 0; i < fb->nr_cbufs; i++) {
685 struct r600_texture *tex;
686
687 /* If not clearing this buffer, skip. */
688 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
689 continue;
690
691 if (!fb->cbufs[i])
692 continue;
693
694 tex = (struct r600_texture *)fb->cbufs[i]->texture;
695 if (tex->fmask.size == 0)
696 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
697 }
698 }
699
700 if (zstex && zstex->htile_buffer &&
701 zsbuf->u.tex.level == 0 &&
702 zsbuf->u.tex.first_layer == 0 &&
703 zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
704 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
705 if (buffers & PIPE_CLEAR_DEPTH &&
706 (!zstex->tc_compatible_htile ||
707 depth == 0 || depth == 1)) {
708 /* Need to disable EXPCLEAR temporarily if clearing
709 * to a new value. */
710 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
711 sctx->db_depth_disable_expclear = true;
712 }
713
714 zstex->depth_clear_value = depth;
715 sctx->framebuffer.dirty_zsbuf = true;
716 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_DEPTH_CLEAR */
717 sctx->db_depth_clear = true;
718 si_mark_atom_dirty(sctx, &sctx->db_render_state);
719 }
720
721 /* TC-compatible HTILE only supports stencil clears to 0. */
722 if (buffers & PIPE_CLEAR_STENCIL &&
723 (!zstex->tc_compatible_htile || stencil == 0)) {
724 stencil &= 0xff;
725
726 /* Need to disable EXPCLEAR temporarily if clearing
727 * to a new value. */
728 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
729 sctx->db_stencil_disable_expclear = true;
730 }
731
732 zstex->stencil_clear_value = stencil;
733 sctx->framebuffer.dirty_zsbuf = true;
734 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_STENCIL_CLEAR */
735 sctx->db_stencil_clear = true;
736 si_mark_atom_dirty(sctx, &sctx->db_render_state);
737 }
738 }
739
740 si_blitter_begin(ctx, SI_CLEAR);
741 util_blitter_clear(sctx->blitter, fb->width, fb->height,
742 util_framebuffer_get_num_layers(fb),
743 buffers, color, depth, stencil);
744 si_blitter_end(ctx);
745
746 if (sctx->db_depth_clear) {
747 sctx->db_depth_clear = false;
748 sctx->db_depth_disable_expclear = false;
749 zstex->depth_cleared = true;
750 si_mark_atom_dirty(sctx, &sctx->db_render_state);
751 }
752
753 if (sctx->db_stencil_clear) {
754 sctx->db_stencil_clear = false;
755 sctx->db_stencil_disable_expclear = false;
756 zstex->stencil_cleared = true;
757 si_mark_atom_dirty(sctx, &sctx->db_render_state);
758 }
759 }
760
761 static void si_clear_render_target(struct pipe_context *ctx,
762 struct pipe_surface *dst,
763 const union pipe_color_union *color,
764 unsigned dstx, unsigned dsty,
765 unsigned width, unsigned height,
766 bool render_condition_enabled)
767 {
768 struct si_context *sctx = (struct si_context *)ctx;
769
770 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
771 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
772 util_blitter_clear_render_target(sctx->blitter, dst, color,
773 dstx, dsty, width, height);
774 si_blitter_end(ctx);
775 }
776
777 static void si_clear_depth_stencil(struct pipe_context *ctx,
778 struct pipe_surface *dst,
779 unsigned clear_flags,
780 double depth,
781 unsigned stencil,
782 unsigned dstx, unsigned dsty,
783 unsigned width, unsigned height,
784 bool render_condition_enabled)
785 {
786 struct si_context *sctx = (struct si_context *)ctx;
787
788 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
789 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
790 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
791 dstx, dsty, width, height);
792 si_blitter_end(ctx);
793 }
794
795 /* Helper for decompressing a portion of a color or depth resource before
796 * blitting if any decompression is needed.
797 * The driver doesn't decompress resources automatically while u_blitter is
798 * rendering. */
799 static void si_decompress_subresource(struct pipe_context *ctx,
800 struct pipe_resource *tex,
801 unsigned planes, unsigned level,
802 unsigned first_layer, unsigned last_layer)
803 {
804 struct si_context *sctx = (struct si_context *)ctx;
805 struct r600_texture *rtex = (struct r600_texture*)tex;
806
807 if (rtex->db_compatible) {
808 planes &= PIPE_MASK_Z | PIPE_MASK_S;
809
810 if (!(rtex->surface.flags & RADEON_SURF_SBUFFER))
811 planes &= ~PIPE_MASK_S;
812
813 si_flush_depth_texture(sctx, rtex, planes,
814 level, level,
815 first_layer, last_layer);
816 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) {
817 si_blit_decompress_color(ctx, rtex, level, level,
818 first_layer, last_layer, false);
819 }
820 }
821
822 struct texture_orig_info {
823 unsigned format;
824 unsigned width0;
825 unsigned height0;
826 unsigned npix_x;
827 unsigned npix_y;
828 unsigned npix0_x;
829 unsigned npix0_y;
830 };
831
832 void si_resource_copy_region(struct pipe_context *ctx,
833 struct pipe_resource *dst,
834 unsigned dst_level,
835 unsigned dstx, unsigned dsty, unsigned dstz,
836 struct pipe_resource *src,
837 unsigned src_level,
838 const struct pipe_box *src_box)
839 {
840 struct si_context *sctx = (struct si_context *)ctx;
841 struct r600_texture *rsrc = (struct r600_texture*)src;
842 struct pipe_surface *dst_view, dst_templ;
843 struct pipe_sampler_view src_templ, *src_view;
844 unsigned dst_width, dst_height, src_width0, src_height0;
845 unsigned src_force_level = 0;
846 struct pipe_box sbox, dstbox;
847
848 /* Handle buffers first. */
849 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
850 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width);
851 return;
852 }
853
854 assert(u_max_sample(dst) == u_max_sample(src));
855
856 /* The driver doesn't decompress resources automatically while
857 * u_blitter is rendering. */
858 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
859 src_box->z, src_box->z + src_box->depth - 1);
860
861 dst_width = u_minify(dst->width0, dst_level);
862 dst_height = u_minify(dst->height0, dst_level);
863 src_width0 = src->width0;
864 src_height0 = src->height0;
865
866 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
867 util_blitter_default_src_texture(&src_templ, src, src_level);
868
869 if (util_format_is_compressed(src->format) ||
870 util_format_is_compressed(dst->format)) {
871 unsigned blocksize = rsrc->surface.bpe;
872
873 if (blocksize == 8)
874 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
875 else
876 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
877 dst_templ.format = src_templ.format;
878
879 dst_width = util_format_get_nblocksx(dst->format, dst_width);
880 dst_height = util_format_get_nblocksy(dst->format, dst_height);
881 src_width0 = util_format_get_nblocksx(src->format, src_width0);
882 src_height0 = util_format_get_nblocksy(src->format, src_height0);
883
884 dstx = util_format_get_nblocksx(dst->format, dstx);
885 dsty = util_format_get_nblocksy(dst->format, dsty);
886
887 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
888 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
889 sbox.z = src_box->z;
890 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
891 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
892 sbox.depth = src_box->depth;
893 src_box = &sbox;
894
895 src_force_level = src_level;
896 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src) ||
897 /* also *8_SNORM has precision issues, use UNORM instead */
898 util_format_is_snorm8(src->format)) {
899 if (util_format_is_subsampled_422(src->format)) {
900 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
901 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
902
903 dst_width = util_format_get_nblocksx(dst->format, dst_width);
904 src_width0 = util_format_get_nblocksx(src->format, src_width0);
905
906 dstx = util_format_get_nblocksx(dst->format, dstx);
907
908 sbox = *src_box;
909 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
910 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
911 src_box = &sbox;
912 } else {
913 unsigned blocksize = rsrc->surface.bpe;
914
915 switch (blocksize) {
916 case 1:
917 dst_templ.format = PIPE_FORMAT_R8_UNORM;
918 src_templ.format = PIPE_FORMAT_R8_UNORM;
919 break;
920 case 2:
921 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
922 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
923 break;
924 case 4:
925 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
926 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
927 break;
928 case 8:
929 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
930 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
931 break;
932 case 16:
933 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
934 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
935 break;
936 default:
937 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
938 util_format_short_name(src->format), blocksize);
939 assert(0);
940 }
941 }
942 }
943
944 /* Initialize the surface. */
945 dst_view = r600_create_surface_custom(ctx, dst, &dst_templ,
946 dst_width, dst_height);
947
948 /* Initialize the sampler view. */
949 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
950 src_width0, src_height0,
951 src_force_level);
952
953 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
954 abs(src_box->depth), &dstbox);
955
956 /* Copy. */
957 si_blitter_begin(ctx, SI_COPY);
958 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
959 src_view, src_box, src_width0, src_height0,
960 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
961 false);
962 si_blitter_end(ctx);
963
964 pipe_surface_reference(&dst_view, NULL);
965 pipe_sampler_view_reference(&src_view, NULL);
966 }
967
968 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
969 const struct pipe_blit_info *info)
970 {
971 struct si_context *sctx = (struct si_context*)ctx;
972 struct r600_texture *src = (struct r600_texture*)info->src.resource;
973 struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
974 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
975 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
976 enum pipe_format format = info->src.format;
977 unsigned sample_mask = ~0;
978 struct pipe_resource *tmp, templ;
979 struct pipe_blit_info blit;
980
981 /* Check basic requirements for hw resolve. */
982 if (!(info->src.resource->nr_samples > 1 &&
983 info->dst.resource->nr_samples <= 1 &&
984 !util_format_is_pure_integer(format) &&
985 !util_format_is_depth_or_stencil(format) &&
986 util_max_layer(info->src.resource, 0) == 0))
987 return false;
988
989 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
990 * the format is R16G16. Use R16A16, which does work.
991 */
992 if (format == PIPE_FORMAT_R16G16_UNORM)
993 format = PIPE_FORMAT_R16A16_UNORM;
994 if (format == PIPE_FORMAT_R16G16_SNORM)
995 format = PIPE_FORMAT_R16A16_SNORM;
996
997 /* Check the remaining requirements for hw resolve. */
998 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
999 !info->scissor_enable &&
1000 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
1001 util_is_format_compatible(util_format_description(info->src.format),
1002 util_format_description(info->dst.format)) &&
1003 dst_width == info->src.resource->width0 &&
1004 dst_height == info->src.resource->height0 &&
1005 info->dst.box.x == 0 &&
1006 info->dst.box.y == 0 &&
1007 info->dst.box.width == dst_width &&
1008 info->dst.box.height == dst_height &&
1009 info->dst.box.depth == 1 &&
1010 info->src.box.x == 0 &&
1011 info->src.box.y == 0 &&
1012 info->src.box.width == dst_width &&
1013 info->src.box.height == dst_height &&
1014 info->src.box.depth == 1 &&
1015 !dst->surface.is_linear &&
1016 (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1017 /* Check the last constraint. */
1018 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1019 /* The next fast clear will switch to this mode to
1020 * get direct hw resolve next time if the mode is
1021 * different now.
1022 */
1023 src->last_msaa_resolve_target_micro_mode =
1024 dst->surface.micro_tile_mode;
1025 goto resolve_to_temp;
1026 }
1027
1028 /* Resolving into a surface with DCC is unsupported. Since
1029 * it's being overwritten anyway, clear it to uncompressed.
1030 * This is still the fastest codepath even with this clear.
1031 */
1032 if (dst->dcc_offset &&
1033 info->dst.level < dst->surface.num_dcc_levels) {
1034 vi_dcc_clear_level(&sctx->b, dst, info->dst.level,
1035 0xFFFFFFFF);
1036 dst->dirty_level_mask &= ~(1 << info->dst.level);
1037 }
1038
1039 /* Resolve directly from src to dst. */
1040 si_blitter_begin(ctx, SI_COLOR_RESOLVE |
1041 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1042 util_blitter_custom_resolve_color(sctx->blitter,
1043 info->dst.resource, info->dst.level,
1044 info->dst.box.z,
1045 info->src.resource, info->src.box.z,
1046 sample_mask, sctx->custom_blend_resolve,
1047 format);
1048 si_blitter_end(ctx);
1049 return true;
1050 }
1051
1052 resolve_to_temp:
1053 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1054 * a temporary texture and blit.
1055 */
1056 memset(&templ, 0, sizeof(templ));
1057 templ.target = PIPE_TEXTURE_2D;
1058 templ.format = info->src.resource->format;
1059 templ.width0 = info->src.resource->width0;
1060 templ.height0 = info->src.resource->height0;
1061 templ.depth0 = 1;
1062 templ.array_size = 1;
1063 templ.usage = PIPE_USAGE_DEFAULT;
1064 templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
1065 R600_RESOURCE_FLAG_DISABLE_DCC;
1066
1067 /* The src and dst microtile modes must be the same. */
1068 if (src->surface.micro_tile_mode == V_009910_ADDR_SURF_DISPLAY_MICRO_TILING)
1069 templ.bind = PIPE_BIND_SCANOUT;
1070 else
1071 templ.bind = 0;
1072
1073 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1074 if (!tmp)
1075 return false;
1076
1077 assert(src->surface.micro_tile_mode ==
1078 ((struct r600_texture*)tmp)->surface.micro_tile_mode);
1079
1080 /* resolve */
1081 si_blitter_begin(ctx, SI_COLOR_RESOLVE |
1082 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1083 util_blitter_custom_resolve_color(sctx->blitter, tmp, 0, 0,
1084 info->src.resource, info->src.box.z,
1085 sample_mask, sctx->custom_blend_resolve,
1086 format);
1087 si_blitter_end(ctx);
1088
1089 /* blit */
1090 blit = *info;
1091 blit.src.resource = tmp;
1092 blit.src.box.z = 0;
1093
1094 si_blitter_begin(ctx, SI_BLIT |
1095 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1096 util_blitter_blit(sctx->blitter, &blit);
1097 si_blitter_end(ctx);
1098
1099 pipe_resource_reference(&tmp, NULL);
1100 return true;
1101 }
1102
1103 static void si_blit(struct pipe_context *ctx,
1104 const struct pipe_blit_info *info)
1105 {
1106 struct si_context *sctx = (struct si_context*)ctx;
1107 struct r600_texture *rdst = (struct r600_texture *)info->dst.resource;
1108
1109 if (do_hardware_msaa_resolve(ctx, info)) {
1110 return;
1111 }
1112
1113 /* Using SDMA for copying to a linear texture in GTT is much faster.
1114 * This improves DRI PRIME performance.
1115 *
1116 * resource_copy_region can't do this yet, because dma_copy calls it
1117 * on failure (recursion).
1118 */
1119 if (rdst->surface.is_linear &&
1120 sctx->b.dma_copy &&
1121 util_can_blit_via_copy_region(info, false)) {
1122 sctx->b.dma_copy(ctx, info->dst.resource, info->dst.level,
1123 info->dst.box.x, info->dst.box.y,
1124 info->dst.box.z,
1125 info->src.resource, info->src.level,
1126 &info->src.box);
1127 return;
1128 }
1129
1130 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1131
1132 /* The driver doesn't decompress resources automatically while
1133 * u_blitter is rendering. */
1134 vi_dcc_disable_if_incompatible_format(&sctx->b, info->src.resource,
1135 info->src.level,
1136 info->src.format);
1137 vi_dcc_disable_if_incompatible_format(&sctx->b, info->dst.resource,
1138 info->dst.level,
1139 info->dst.format);
1140 si_decompress_subresource(ctx, info->src.resource, info->mask,
1141 info->src.level,
1142 info->src.box.z,
1143 info->src.box.z + info->src.box.depth - 1);
1144
1145 if (sctx->screen->b.debug_flags & DBG_FORCE_DMA &&
1146 util_try_blit_via_copy_region(ctx, info))
1147 return;
1148
1149 si_blitter_begin(ctx, SI_BLIT |
1150 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1151 util_blitter_blit(sctx->blitter, info);
1152 si_blitter_end(ctx);
1153 }
1154
1155 static boolean si_generate_mipmap(struct pipe_context *ctx,
1156 struct pipe_resource *tex,
1157 enum pipe_format format,
1158 unsigned base_level, unsigned last_level,
1159 unsigned first_layer, unsigned last_layer)
1160 {
1161 struct si_context *sctx = (struct si_context*)ctx;
1162 struct r600_texture *rtex = (struct r600_texture *)tex;
1163
1164 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1165 return false;
1166
1167 /* The driver doesn't decompress resources automatically while
1168 * u_blitter is rendering. */
1169 vi_dcc_disable_if_incompatible_format(&sctx->b, tex, base_level,
1170 format);
1171 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1172 base_level, first_layer, last_layer);
1173
1174 /* Clear dirty_level_mask for the levels that will be overwritten. */
1175 assert(base_level < last_level);
1176 rtex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1177 last_level - base_level);
1178
1179 si_blitter_begin(ctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1180 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1181 base_level, last_level,
1182 first_layer, last_layer);
1183 si_blitter_end(ctx);
1184 return true;
1185 }
1186
1187 static void si_flush_resource(struct pipe_context *ctx,
1188 struct pipe_resource *res)
1189 {
1190 struct r600_texture *rtex = (struct r600_texture*)res;
1191
1192 assert(res->target != PIPE_BUFFER);
1193 assert(!rtex->dcc_separate_buffer || rtex->dcc_gather_statistics);
1194
1195 /* st/dri calls flush twice per frame (not a bug), this prevents double
1196 * decompression. */
1197 if (rtex->dcc_separate_buffer && !rtex->separate_dcc_dirty)
1198 return;
1199
1200 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) {
1201 si_blit_decompress_color(ctx, rtex, 0, res->last_level,
1202 0, util_max_layer(res, 0),
1203 rtex->dcc_separate_buffer != NULL);
1204 }
1205
1206 /* Always do the analysis even if DCC is disabled at the moment. */
1207 if (rtex->dcc_gather_statistics && rtex->separate_dcc_dirty) {
1208 rtex->separate_dcc_dirty = false;
1209 vi_separate_dcc_process_and_reset_stats(ctx, rtex);
1210 }
1211 }
1212
1213 static void si_decompress_dcc(struct pipe_context *ctx,
1214 struct r600_texture *rtex)
1215 {
1216 if (!rtex->dcc_offset)
1217 return;
1218
1219 si_blit_decompress_color(ctx, rtex, 0, rtex->resource.b.b.last_level,
1220 0, util_max_layer(&rtex->resource.b.b, 0),
1221 true);
1222 }
1223
1224 static void si_pipe_clear_buffer(struct pipe_context *ctx,
1225 struct pipe_resource *dst,
1226 unsigned offset, unsigned size,
1227 const void *clear_value_ptr,
1228 int clear_value_size)
1229 {
1230 struct si_context *sctx = (struct si_context*)ctx;
1231 uint32_t dword_value;
1232 unsigned i;
1233
1234 assert(offset % clear_value_size == 0);
1235 assert(size % clear_value_size == 0);
1236
1237 if (clear_value_size > 4) {
1238 const uint32_t *u32 = clear_value_ptr;
1239 bool clear_dword_duplicated = true;
1240
1241 /* See if we can lower large fills to dword fills. */
1242 for (i = 1; i < clear_value_size / 4; i++)
1243 if (u32[0] != u32[i]) {
1244 clear_dword_duplicated = false;
1245 break;
1246 }
1247
1248 if (!clear_dword_duplicated) {
1249 /* Use transform feedback for 64-bit, 96-bit, and
1250 * 128-bit fills.
1251 */
1252 union pipe_color_union clear_value;
1253
1254 memcpy(&clear_value, clear_value_ptr, clear_value_size);
1255 si_blitter_begin(ctx, SI_DISABLE_RENDER_COND);
1256 util_blitter_clear_buffer(sctx->blitter, dst, offset,
1257 size, clear_value_size / 4,
1258 &clear_value);
1259 si_blitter_end(ctx);
1260 return;
1261 }
1262 }
1263
1264 /* Expand the clear value to a dword. */
1265 switch (clear_value_size) {
1266 case 1:
1267 dword_value = *(uint8_t*)clear_value_ptr;
1268 dword_value |= (dword_value << 8) |
1269 (dword_value << 16) |
1270 (dword_value << 24);
1271 break;
1272 case 2:
1273 dword_value = *(uint16_t*)clear_value_ptr;
1274 dword_value |= dword_value << 16;
1275 break;
1276 default:
1277 dword_value = *(uint32_t*)clear_value_ptr;
1278 }
1279
1280 sctx->b.clear_buffer(ctx, dst, offset, size, dword_value,
1281 R600_COHERENCY_SHADER);
1282 }
1283
1284 void si_init_blit_functions(struct si_context *sctx)
1285 {
1286 sctx->b.b.clear = si_clear;
1287 sctx->b.b.clear_buffer = si_pipe_clear_buffer;
1288 sctx->b.b.clear_render_target = si_clear_render_target;
1289 sctx->b.b.clear_depth_stencil = si_clear_depth_stencil;
1290 sctx->b.b.resource_copy_region = si_resource_copy_region;
1291 sctx->b.b.blit = si_blit;
1292 sctx->b.b.flush_resource = si_flush_resource;
1293 sctx->b.b.generate_mipmap = si_generate_mipmap;
1294 sctx->b.blit_decompress_depth = si_blit_decompress_depth;
1295 sctx->b.decompress_dcc = si_decompress_dcc;
1296 }