2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_compute.h"
26 #include "util/u_format.h"
27 #include "util/u_log.h"
28 #include "util/u_surface.h"
30 enum si_blitter_op
/* bitmask */
33 SI_SAVE_FRAMEBUFFER
= 2,
34 SI_SAVE_FRAGMENT_STATE
= 4,
35 SI_DISABLE_RENDER_COND
= 8,
37 SI_CLEAR
= SI_SAVE_FRAGMENT_STATE
,
39 SI_CLEAR_SURFACE
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
,
41 SI_COPY
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_TEXTURES
|
42 SI_SAVE_FRAGMENT_STATE
| SI_DISABLE_RENDER_COND
,
44 SI_BLIT
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_TEXTURES
|
45 SI_SAVE_FRAGMENT_STATE
,
47 SI_DECOMPRESS
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
|
48 SI_DISABLE_RENDER_COND
,
50 SI_COLOR_RESOLVE
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
53 static void si_blitter_begin(struct pipe_context
*ctx
, enum si_blitter_op op
)
55 struct si_context
*sctx
= (struct si_context
*)ctx
;
57 util_blitter_save_vertex_buffer_slot(sctx
->blitter
, sctx
->vertex_buffer
);
58 util_blitter_save_vertex_elements(sctx
->blitter
, sctx
->vertex_elements
);
59 util_blitter_save_vertex_shader(sctx
->blitter
, sctx
->vs_shader
.cso
);
60 util_blitter_save_tessctrl_shader(sctx
->blitter
, sctx
->tcs_shader
.cso
);
61 util_blitter_save_tesseval_shader(sctx
->blitter
, sctx
->tes_shader
.cso
);
62 util_blitter_save_geometry_shader(sctx
->blitter
, sctx
->gs_shader
.cso
);
63 util_blitter_save_so_targets(sctx
->blitter
, sctx
->b
.streamout
.num_targets
,
64 (struct pipe_stream_output_target
**)sctx
->b
.streamout
.targets
);
65 util_blitter_save_rasterizer(sctx
->blitter
, sctx
->queued
.named
.rasterizer
);
67 if (op
& SI_SAVE_FRAGMENT_STATE
) {
68 util_blitter_save_blend(sctx
->blitter
, sctx
->queued
.named
.blend
);
69 util_blitter_save_depth_stencil_alpha(sctx
->blitter
, sctx
->queued
.named
.dsa
);
70 util_blitter_save_stencil_ref(sctx
->blitter
, &sctx
->stencil_ref
.state
);
71 util_blitter_save_fragment_shader(sctx
->blitter
, sctx
->ps_shader
.cso
);
72 util_blitter_save_sample_mask(sctx
->blitter
, sctx
->sample_mask
.sample_mask
);
73 util_blitter_save_viewport(sctx
->blitter
, &sctx
->viewports
.states
[0]);
74 util_blitter_save_scissor(sctx
->blitter
, &sctx
->scissors
.states
[0]);
77 if (op
& SI_SAVE_FRAMEBUFFER
)
78 util_blitter_save_framebuffer(sctx
->blitter
, &sctx
->framebuffer
.state
);
80 if (op
& SI_SAVE_TEXTURES
) {
81 util_blitter_save_fragment_sampler_states(
83 (void**)sctx
->samplers
[PIPE_SHADER_FRAGMENT
].sampler_states
);
85 util_blitter_save_fragment_sampler_views(sctx
->blitter
, 2,
86 sctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
);
89 if (op
& SI_DISABLE_RENDER_COND
)
90 sctx
->b
.render_cond_force_off
= true;
93 static void si_blitter_end(struct pipe_context
*ctx
)
95 struct si_context
*sctx
= (struct si_context
*)ctx
;
97 sctx
->b
.render_cond_force_off
= false;
100 static unsigned u_max_sample(struct pipe_resource
*r
)
102 return r
->nr_samples
? r
->nr_samples
- 1 : 0;
106 si_blit_dbcb_copy(struct si_context
*sctx
,
107 struct r600_texture
*src
,
108 struct r600_texture
*dst
,
109 unsigned planes
, unsigned level_mask
,
110 unsigned first_layer
, unsigned last_layer
,
111 unsigned first_sample
, unsigned last_sample
)
113 struct pipe_surface surf_tmpl
= {{0}};
114 unsigned layer
, sample
, checked_last_layer
, max_layer
;
115 unsigned fully_copied_levels
= 0;
117 if (planes
& PIPE_MASK_Z
)
118 sctx
->dbcb_depth_copy_enabled
= true;
119 if (planes
& PIPE_MASK_S
)
120 sctx
->dbcb_stencil_copy_enabled
= true;
121 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
123 assert(sctx
->dbcb_depth_copy_enabled
|| sctx
->dbcb_stencil_copy_enabled
);
125 sctx
->decompression_enabled
= true;
128 unsigned level
= u_bit_scan(&level_mask
);
130 /* The smaller the mipmap level, the less layers there are
131 * as far as 3D textures are concerned. */
132 max_layer
= util_max_layer(&src
->resource
.b
.b
, level
);
133 checked_last_layer
= MIN2(last_layer
, max_layer
);
135 surf_tmpl
.u
.tex
.level
= level
;
137 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
138 struct pipe_surface
*zsurf
, *cbsurf
;
140 surf_tmpl
.format
= src
->resource
.b
.b
.format
;
141 surf_tmpl
.u
.tex
.first_layer
= layer
;
142 surf_tmpl
.u
.tex
.last_layer
= layer
;
144 zsurf
= sctx
->b
.b
.create_surface(&sctx
->b
.b
, &src
->resource
.b
.b
, &surf_tmpl
);
146 surf_tmpl
.format
= dst
->resource
.b
.b
.format
;
147 cbsurf
= sctx
->b
.b
.create_surface(&sctx
->b
.b
, &dst
->resource
.b
.b
, &surf_tmpl
);
149 for (sample
= first_sample
; sample
<= last_sample
; sample
++) {
150 if (sample
!= sctx
->dbcb_copy_sample
) {
151 sctx
->dbcb_copy_sample
= sample
;
152 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
155 si_blitter_begin(&sctx
->b
.b
, SI_DECOMPRESS
);
156 util_blitter_custom_depth_stencil(sctx
->blitter
, zsurf
, cbsurf
, 1 << sample
,
157 sctx
->custom_dsa_flush
, 1.0f
);
158 si_blitter_end(&sctx
->b
.b
);
161 pipe_surface_reference(&zsurf
, NULL
);
162 pipe_surface_reference(&cbsurf
, NULL
);
165 if (first_layer
== 0 && last_layer
>= max_layer
&&
166 first_sample
== 0 && last_sample
>= u_max_sample(&src
->resource
.b
.b
))
167 fully_copied_levels
|= 1u << level
;
170 sctx
->decompression_enabled
= false;
171 sctx
->dbcb_depth_copy_enabled
= false;
172 sctx
->dbcb_stencil_copy_enabled
= false;
173 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
175 return fully_copied_levels
;
178 static void si_blit_decompress_depth(struct pipe_context
*ctx
,
179 struct r600_texture
*texture
,
180 struct r600_texture
*staging
,
181 unsigned first_level
, unsigned last_level
,
182 unsigned first_layer
, unsigned last_layer
,
183 unsigned first_sample
, unsigned last_sample
)
185 const struct util_format_description
*desc
;
188 assert(staging
!= NULL
&& "use si_blit_decompress_zs_in_place instead");
190 desc
= util_format_description(staging
->resource
.b
.b
.format
);
192 if (util_format_has_depth(desc
))
193 planes
|= PIPE_MASK_Z
;
194 if (util_format_has_stencil(desc
))
195 planes
|= PIPE_MASK_S
;
198 (struct si_context
*)ctx
, texture
, staging
, planes
,
199 u_bit_consecutive(first_level
, last_level
- first_level
+ 1),
200 first_layer
, last_layer
, first_sample
, last_sample
);
203 /* Helper function for si_blit_decompress_zs_in_place.
206 si_blit_decompress_zs_planes_in_place(struct si_context
*sctx
,
207 struct r600_texture
*texture
,
208 unsigned planes
, unsigned level_mask
,
209 unsigned first_layer
, unsigned last_layer
)
211 struct pipe_surface
*zsurf
, surf_tmpl
= {{0}};
212 unsigned layer
, max_layer
, checked_last_layer
;
213 unsigned fully_decompressed_mask
= 0;
218 if (planes
& PIPE_MASK_S
)
219 sctx
->db_flush_stencil_inplace
= true;
220 if (planes
& PIPE_MASK_Z
)
221 sctx
->db_flush_depth_inplace
= true;
222 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
224 surf_tmpl
.format
= texture
->resource
.b
.b
.format
;
226 sctx
->decompression_enabled
= true;
229 unsigned level
= u_bit_scan(&level_mask
);
231 surf_tmpl
.u
.tex
.level
= level
;
233 /* The smaller the mipmap level, the less layers there are
234 * as far as 3D textures are concerned. */
235 max_layer
= util_max_layer(&texture
->resource
.b
.b
, level
);
236 checked_last_layer
= MIN2(last_layer
, max_layer
);
238 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
239 surf_tmpl
.u
.tex
.first_layer
= layer
;
240 surf_tmpl
.u
.tex
.last_layer
= layer
;
242 zsurf
= sctx
->b
.b
.create_surface(&sctx
->b
.b
, &texture
->resource
.b
.b
, &surf_tmpl
);
244 si_blitter_begin(&sctx
->b
.b
, SI_DECOMPRESS
);
245 util_blitter_custom_depth_stencil(sctx
->blitter
, zsurf
, NULL
, ~0,
246 sctx
->custom_dsa_flush
,
248 si_blitter_end(&sctx
->b
.b
);
250 pipe_surface_reference(&zsurf
, NULL
);
253 /* The texture will always be dirty if some layers aren't flushed.
254 * I don't think this case occurs often though. */
255 if (first_layer
== 0 && last_layer
>= max_layer
) {
256 fully_decompressed_mask
|= 1u << level
;
260 if (planes
& PIPE_MASK_Z
)
261 texture
->dirty_level_mask
&= ~fully_decompressed_mask
;
262 if (planes
& PIPE_MASK_S
)
263 texture
->stencil_dirty_level_mask
&= ~fully_decompressed_mask
;
265 sctx
->decompression_enabled
= false;
266 sctx
->db_flush_depth_inplace
= false;
267 sctx
->db_flush_stencil_inplace
= false;
268 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
271 /* Helper function of si_flush_depth_texture: decompress the given levels
272 * of Z and/or S planes in place.
275 si_blit_decompress_zs_in_place(struct si_context
*sctx
,
276 struct r600_texture
*texture
,
277 unsigned levels_z
, unsigned levels_s
,
278 unsigned first_layer
, unsigned last_layer
)
280 unsigned both
= levels_z
& levels_s
;
282 /* First, do combined Z & S decompresses for levels that need it. */
284 si_blit_decompress_zs_planes_in_place(
285 sctx
, texture
, PIPE_MASK_Z
| PIPE_MASK_S
,
287 first_layer
, last_layer
);
292 /* Now do separate Z and S decompresses. */
294 si_blit_decompress_zs_planes_in_place(
295 sctx
, texture
, PIPE_MASK_Z
,
297 first_layer
, last_layer
);
301 si_blit_decompress_zs_planes_in_place(
302 sctx
, texture
, PIPE_MASK_S
,
304 first_layer
, last_layer
);
309 si_decompress_depth(struct si_context
*sctx
,
310 struct r600_texture
*tex
,
311 unsigned required_planes
,
312 unsigned first_level
, unsigned last_level
,
313 unsigned first_layer
, unsigned last_layer
)
315 unsigned inplace_planes
= 0;
316 unsigned copy_planes
= 0;
317 unsigned level_mask
= u_bit_consecutive(first_level
, last_level
- first_level
+ 1);
318 unsigned levels_z
= 0;
319 unsigned levels_s
= 0;
321 if (required_planes
& PIPE_MASK_Z
) {
322 levels_z
= level_mask
& tex
->dirty_level_mask
;
325 if (r600_can_sample_zs(tex
, false))
326 inplace_planes
|= PIPE_MASK_Z
;
328 copy_planes
|= PIPE_MASK_Z
;
331 if (required_planes
& PIPE_MASK_S
) {
332 levels_s
= level_mask
& tex
->stencil_dirty_level_mask
;
335 if (r600_can_sample_zs(tex
, true))
336 inplace_planes
|= PIPE_MASK_S
;
338 copy_planes
|= PIPE_MASK_S
;
342 if (unlikely(sctx
->b
.log
))
343 u_log_printf(sctx
->b
.log
,
344 "\n------------------------------------------------\n"
345 "Decompress Depth (levels %u - %u, levels Z: 0x%x S: 0x%x)\n\n",
346 first_level
, last_level
, levels_z
, levels_s
);
348 /* We may have to allocate the flushed texture here when called from
349 * si_decompress_subresource.
352 (tex
->flushed_depth_texture
||
353 si_init_flushed_depth_texture(&sctx
->b
.b
, &tex
->resource
.b
.b
, NULL
))) {
354 struct r600_texture
*dst
= tex
->flushed_depth_texture
;
355 unsigned fully_copied_levels
;
358 assert(tex
->flushed_depth_texture
);
360 if (util_format_is_depth_and_stencil(dst
->resource
.b
.b
.format
))
361 copy_planes
= PIPE_MASK_Z
| PIPE_MASK_S
;
363 if (copy_planes
& PIPE_MASK_Z
) {
367 if (copy_planes
& PIPE_MASK_S
) {
372 fully_copied_levels
= si_blit_dbcb_copy(
373 sctx
, tex
, dst
, copy_planes
, levels
,
374 first_layer
, last_layer
,
375 0, u_max_sample(&tex
->resource
.b
.b
));
377 if (copy_planes
& PIPE_MASK_Z
)
378 tex
->dirty_level_mask
&= ~fully_copied_levels
;
379 if (copy_planes
& PIPE_MASK_S
)
380 tex
->stencil_dirty_level_mask
&= ~fully_copied_levels
;
383 if (inplace_planes
) {
384 bool has_htile
= r600_htile_enabled(tex
, first_level
);
385 bool tc_compat_htile
= vi_tc_compat_htile_enabled(tex
, first_level
);
387 /* Don't decompress if there is no HTILE or when HTILE is
389 if (has_htile
&& !tc_compat_htile
) {
390 si_blit_decompress_zs_in_place(
393 first_layer
, last_layer
);
395 /* This is only a cache flush.
397 * Only clear the mask that we are flushing, because
398 * si_make_DB_shader_coherent() treats different levels
399 * and depth and stencil differently.
401 if (inplace_planes
& PIPE_MASK_Z
)
402 tex
->dirty_level_mask
&= ~levels_z
;
403 if (inplace_planes
& PIPE_MASK_S
)
404 tex
->stencil_dirty_level_mask
&= ~levels_s
;
407 /* Only in-place decompression needs to flush DB caches, or
408 * when we don't decompress but TC-compatible planes are dirty.
410 si_make_DB_shader_coherent(sctx
, tex
->resource
.b
.b
.nr_samples
,
411 inplace_planes
& PIPE_MASK_S
,
414 /* set_framebuffer_state takes care of coherency for single-sample.
415 * The DB->CB copy uses CB for the final writes.
417 if (copy_planes
&& tex
->resource
.b
.b
.nr_samples
> 1)
418 si_make_CB_shader_coherent(sctx
, tex
->resource
.b
.b
.nr_samples
,
423 si_decompress_sampler_depth_textures(struct si_context
*sctx
,
424 struct si_samplers
*textures
)
427 unsigned mask
= textures
->needs_depth_decompress_mask
;
430 struct pipe_sampler_view
*view
;
431 struct si_sampler_view
*sview
;
432 struct r600_texture
*tex
;
434 i
= u_bit_scan(&mask
);
436 view
= textures
->views
[i
];
438 sview
= (struct si_sampler_view
*)view
;
440 tex
= (struct r600_texture
*)view
->texture
;
441 assert(tex
->db_compatible
);
443 si_decompress_depth(sctx
, tex
,
444 sview
->is_stencil_sampler
? PIPE_MASK_S
: PIPE_MASK_Z
,
445 view
->u
.tex
.first_level
, view
->u
.tex
.last_level
,
446 0, util_max_layer(&tex
->resource
.b
.b
, view
->u
.tex
.first_level
));
450 static void si_blit_decompress_color(struct pipe_context
*ctx
,
451 struct r600_texture
*rtex
,
452 unsigned first_level
, unsigned last_level
,
453 unsigned first_layer
, unsigned last_layer
,
454 bool need_dcc_decompress
)
456 struct si_context
*sctx
= (struct si_context
*)ctx
;
458 unsigned layer
, checked_last_layer
, max_layer
;
459 unsigned level_mask
=
460 u_bit_consecutive(first_level
, last_level
- first_level
+ 1);
462 if (!need_dcc_decompress
)
463 level_mask
&= rtex
->dirty_level_mask
;
467 if (unlikely(sctx
->b
.log
))
468 u_log_printf(sctx
->b
.log
,
469 "\n------------------------------------------------\n"
470 "Decompress Color (levels %u - %u, mask 0x%x)\n\n",
471 first_level
, last_level
, level_mask
);
473 if (need_dcc_decompress
) {
474 custom_blend
= sctx
->custom_blend_dcc_decompress
;
476 assert(rtex
->dcc_offset
);
478 /* disable levels without DCC */
479 for (int i
= first_level
; i
<= last_level
; i
++) {
480 if (!vi_dcc_enabled(rtex
, i
))
481 level_mask
&= ~(1 << i
);
483 } else if (rtex
->fmask
.size
) {
484 custom_blend
= sctx
->custom_blend_fmask_decompress
;
486 custom_blend
= sctx
->custom_blend_eliminate_fastclear
;
489 sctx
->decompression_enabled
= true;
492 unsigned level
= u_bit_scan(&level_mask
);
494 /* The smaller the mipmap level, the less layers there are
495 * as far as 3D textures are concerned. */
496 max_layer
= util_max_layer(&rtex
->resource
.b
.b
, level
);
497 checked_last_layer
= MIN2(last_layer
, max_layer
);
499 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
500 struct pipe_surface
*cbsurf
, surf_tmpl
;
502 surf_tmpl
.format
= rtex
->resource
.b
.b
.format
;
503 surf_tmpl
.u
.tex
.level
= level
;
504 surf_tmpl
.u
.tex
.first_layer
= layer
;
505 surf_tmpl
.u
.tex
.last_layer
= layer
;
506 cbsurf
= ctx
->create_surface(ctx
, &rtex
->resource
.b
.b
, &surf_tmpl
);
508 /* Required before and after FMASK and DCC_DECOMPRESS. */
509 if (custom_blend
== sctx
->custom_blend_fmask_decompress
||
510 custom_blend
== sctx
->custom_blend_dcc_decompress
)
511 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
513 si_blitter_begin(ctx
, SI_DECOMPRESS
);
514 util_blitter_custom_color(sctx
->blitter
, cbsurf
, custom_blend
);
517 if (custom_blend
== sctx
->custom_blend_fmask_decompress
||
518 custom_blend
== sctx
->custom_blend_dcc_decompress
)
519 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
521 pipe_surface_reference(&cbsurf
, NULL
);
524 /* The texture will always be dirty if some layers aren't flushed.
525 * I don't think this case occurs often though. */
526 if (first_layer
== 0 && last_layer
>= max_layer
) {
527 rtex
->dirty_level_mask
&= ~(1 << level
);
531 sctx
->decompression_enabled
= false;
532 si_make_CB_shader_coherent(sctx
, rtex
->resource
.b
.b
.nr_samples
,
533 vi_dcc_enabled(rtex
, first_level
));
537 si_decompress_color_texture(struct si_context
*sctx
, struct r600_texture
*tex
,
538 unsigned first_level
, unsigned last_level
)
540 /* CMASK or DCC can be discarded and we can still end up here. */
541 if (!tex
->cmask
.size
&& !tex
->fmask
.size
&& !tex
->dcc_offset
)
544 si_blit_decompress_color(&sctx
->b
.b
, tex
, first_level
, last_level
, 0,
545 util_max_layer(&tex
->resource
.b
.b
, first_level
),
550 si_decompress_sampler_color_textures(struct si_context
*sctx
,
551 struct si_samplers
*textures
)
554 unsigned mask
= textures
->needs_color_decompress_mask
;
557 struct pipe_sampler_view
*view
;
558 struct r600_texture
*tex
;
560 i
= u_bit_scan(&mask
);
562 view
= textures
->views
[i
];
565 tex
= (struct r600_texture
*)view
->texture
;
567 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.first_level
,
568 view
->u
.tex
.last_level
);
573 si_decompress_image_color_textures(struct si_context
*sctx
,
574 struct si_images
*images
)
577 unsigned mask
= images
->needs_color_decompress_mask
;
580 const struct pipe_image_view
*view
;
581 struct r600_texture
*tex
;
583 i
= u_bit_scan(&mask
);
585 view
= &images
->views
[i
];
586 assert(view
->resource
->target
!= PIPE_BUFFER
);
588 tex
= (struct r600_texture
*)view
->resource
;
590 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.level
,
595 static void si_check_render_feedback_texture(struct si_context
*sctx
,
596 struct r600_texture
*tex
,
597 unsigned first_level
,
599 unsigned first_layer
,
602 bool render_feedback
= false;
604 if (!tex
->dcc_offset
)
607 for (unsigned j
= 0; j
< sctx
->framebuffer
.state
.nr_cbufs
; ++j
) {
608 struct r600_surface
* surf
;
610 if (!sctx
->framebuffer
.state
.cbufs
[j
])
613 surf
= (struct r600_surface
*)sctx
->framebuffer
.state
.cbufs
[j
];
615 if (tex
== (struct r600_texture
*)surf
->base
.texture
&&
616 surf
->base
.u
.tex
.level
>= first_level
&&
617 surf
->base
.u
.tex
.level
<= last_level
&&
618 surf
->base
.u
.tex
.first_layer
<= last_layer
&&
619 surf
->base
.u
.tex
.last_layer
>= first_layer
) {
620 render_feedback
= true;
626 si_texture_disable_dcc(&sctx
->b
, tex
);
629 static void si_check_render_feedback_textures(struct si_context
*sctx
,
630 struct si_samplers
*textures
)
632 uint32_t mask
= textures
->enabled_mask
;
635 const struct pipe_sampler_view
*view
;
636 struct r600_texture
*tex
;
638 unsigned i
= u_bit_scan(&mask
);
640 view
= textures
->views
[i
];
641 if(view
->texture
->target
== PIPE_BUFFER
)
644 tex
= (struct r600_texture
*)view
->texture
;
646 si_check_render_feedback_texture(sctx
, tex
,
647 view
->u
.tex
.first_level
,
648 view
->u
.tex
.last_level
,
649 view
->u
.tex
.first_layer
,
650 view
->u
.tex
.last_layer
);
654 static void si_check_render_feedback_images(struct si_context
*sctx
,
655 struct si_images
*images
)
657 uint32_t mask
= images
->enabled_mask
;
660 const struct pipe_image_view
*view
;
661 struct r600_texture
*tex
;
663 unsigned i
= u_bit_scan(&mask
);
665 view
= &images
->views
[i
];
666 if (view
->resource
->target
== PIPE_BUFFER
)
669 tex
= (struct r600_texture
*)view
->resource
;
671 si_check_render_feedback_texture(sctx
, tex
,
674 view
->u
.tex
.first_layer
,
675 view
->u
.tex
.last_layer
);
679 static void si_check_render_feedback_resident_textures(struct si_context
*sctx
)
681 util_dynarray_foreach(&sctx
->resident_tex_handles
,
682 struct si_texture_handle
*, tex_handle
) {
683 struct pipe_sampler_view
*view
;
684 struct r600_texture
*tex
;
686 view
= (*tex_handle
)->view
;
687 if (view
->texture
->target
== PIPE_BUFFER
)
690 tex
= (struct r600_texture
*)view
->texture
;
692 si_check_render_feedback_texture(sctx
, tex
,
693 view
->u
.tex
.first_level
,
694 view
->u
.tex
.last_level
,
695 view
->u
.tex
.first_layer
,
696 view
->u
.tex
.last_layer
);
700 static void si_check_render_feedback_resident_images(struct si_context
*sctx
)
702 util_dynarray_foreach(&sctx
->resident_img_handles
,
703 struct si_image_handle
*, img_handle
) {
704 struct pipe_image_view
*view
;
705 struct r600_texture
*tex
;
707 view
= &(*img_handle
)->view
;
708 if (view
->resource
->target
== PIPE_BUFFER
)
711 tex
= (struct r600_texture
*)view
->resource
;
713 si_check_render_feedback_texture(sctx
, tex
,
716 view
->u
.tex
.first_layer
,
717 view
->u
.tex
.last_layer
);
721 static void si_check_render_feedback(struct si_context
*sctx
)
724 if (!sctx
->need_check_render_feedback
)
727 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
728 si_check_render_feedback_images(sctx
, &sctx
->images
[i
]);
729 si_check_render_feedback_textures(sctx
, &sctx
->samplers
[i
]);
732 si_check_render_feedback_resident_images(sctx
);
733 si_check_render_feedback_resident_textures(sctx
);
735 sctx
->need_check_render_feedback
= false;
738 static void si_decompress_resident_textures(struct si_context
*sctx
)
740 util_dynarray_foreach(&sctx
->resident_tex_needs_color_decompress
,
741 struct si_texture_handle
*, tex_handle
) {
742 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
743 struct r600_texture
*tex
= (struct r600_texture
*)view
->texture
;
745 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.first_level
,
746 view
->u
.tex
.last_level
);
749 util_dynarray_foreach(&sctx
->resident_tex_needs_depth_decompress
,
750 struct si_texture_handle
*, tex_handle
) {
751 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
752 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
753 struct r600_texture
*tex
= (struct r600_texture
*)view
->texture
;
755 si_decompress_depth(sctx
, tex
,
756 sview
->is_stencil_sampler
? PIPE_MASK_S
: PIPE_MASK_Z
,
757 view
->u
.tex
.first_level
, view
->u
.tex
.last_level
,
758 0, util_max_layer(&tex
->resource
.b
.b
, view
->u
.tex
.first_level
));
762 static void si_decompress_resident_images(struct si_context
*sctx
)
764 util_dynarray_foreach(&sctx
->resident_img_needs_color_decompress
,
765 struct si_image_handle
*, img_handle
) {
766 struct pipe_image_view
*view
= &(*img_handle
)->view
;
767 struct r600_texture
*tex
= (struct r600_texture
*)view
->resource
;
769 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.level
,
774 void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
)
776 unsigned compressed_colortex_counter
, mask
;
778 if (sctx
->blitter
->running
)
781 /* Update the compressed_colortex_mask if necessary. */
782 compressed_colortex_counter
= p_atomic_read(&sctx
->screen
->b
.compressed_colortex_counter
);
783 if (compressed_colortex_counter
!= sctx
->b
.last_compressed_colortex_counter
) {
784 sctx
->b
.last_compressed_colortex_counter
= compressed_colortex_counter
;
785 si_update_needs_color_decompress_masks(sctx
);
788 /* Decompress color & depth textures if needed. */
789 mask
= sctx
->shader_needs_decompress_mask
& shader_mask
;
791 unsigned i
= u_bit_scan(&mask
);
793 if (sctx
->samplers
[i
].needs_depth_decompress_mask
) {
794 si_decompress_sampler_depth_textures(sctx
, &sctx
->samplers
[i
]);
796 if (sctx
->samplers
[i
].needs_color_decompress_mask
) {
797 si_decompress_sampler_color_textures(sctx
, &sctx
->samplers
[i
]);
799 if (sctx
->images
[i
].needs_color_decompress_mask
) {
800 si_decompress_image_color_textures(sctx
, &sctx
->images
[i
]);
804 if (shader_mask
& u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS
)) {
805 if (sctx
->uses_bindless_samplers
)
806 si_decompress_resident_textures(sctx
);
807 if (sctx
->uses_bindless_images
)
808 si_decompress_resident_images(sctx
);
809 } else if (shader_mask
& (1 << PIPE_SHADER_COMPUTE
)) {
810 if (sctx
->cs_shader_state
.program
->uses_bindless_samplers
)
811 si_decompress_resident_textures(sctx
);
812 if (sctx
->cs_shader_state
.program
->uses_bindless_images
)
813 si_decompress_resident_images(sctx
);
816 si_check_render_feedback(sctx
);
819 static void si_clear(struct pipe_context
*ctx
, unsigned buffers
,
820 const union pipe_color_union
*color
,
821 double depth
, unsigned stencil
)
823 struct si_context
*sctx
= (struct si_context
*)ctx
;
824 struct pipe_framebuffer_state
*fb
= &sctx
->framebuffer
.state
;
825 struct pipe_surface
*zsbuf
= fb
->zsbuf
;
826 struct r600_texture
*zstex
=
827 zsbuf
? (struct r600_texture
*)zsbuf
->texture
: NULL
;
829 if (buffers
& PIPE_CLEAR_COLOR
) {
830 si_do_fast_color_clear(&sctx
->b
, fb
,
831 &sctx
->framebuffer
.atom
, &buffers
,
832 &sctx
->framebuffer
.dirty_cbufs
,
835 return; /* all buffers have been fast cleared */
838 if (buffers
& PIPE_CLEAR_COLOR
) {
841 /* These buffers cannot use fast clear, make sure to disable expansion. */
842 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
843 struct r600_texture
*tex
;
845 /* If not clearing this buffer, skip. */
846 if (!(buffers
& (PIPE_CLEAR_COLOR0
<< i
)))
852 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
853 if (tex
->fmask
.size
== 0)
854 tex
->dirty_level_mask
&= ~(1 << fb
->cbufs
[i
]->u
.tex
.level
);
859 r600_htile_enabled(zstex
, zsbuf
->u
.tex
.level
) &&
860 zsbuf
->u
.tex
.first_layer
== 0 &&
861 zsbuf
->u
.tex
.last_layer
== util_max_layer(&zstex
->resource
.b
.b
, 0)) {
862 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
863 if (buffers
& PIPE_CLEAR_DEPTH
&&
864 (!zstex
->tc_compatible_htile
||
865 depth
== 0 || depth
== 1)) {
866 /* Need to disable EXPCLEAR temporarily if clearing
868 if (!zstex
->depth_cleared
|| zstex
->depth_clear_value
!= depth
) {
869 sctx
->db_depth_disable_expclear
= true;
872 zstex
->depth_clear_value
= depth
;
873 sctx
->framebuffer
.dirty_zsbuf
= true;
874 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
); /* updates DB_DEPTH_CLEAR */
875 sctx
->db_depth_clear
= true;
876 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
879 /* TC-compatible HTILE only supports stencil clears to 0. */
880 if (buffers
& PIPE_CLEAR_STENCIL
&&
881 (!zstex
->tc_compatible_htile
|| stencil
== 0)) {
884 /* Need to disable EXPCLEAR temporarily if clearing
886 if (!zstex
->stencil_cleared
|| zstex
->stencil_clear_value
!= stencil
) {
887 sctx
->db_stencil_disable_expclear
= true;
890 zstex
->stencil_clear_value
= stencil
;
891 sctx
->framebuffer
.dirty_zsbuf
= true;
892 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
); /* updates DB_STENCIL_CLEAR */
893 sctx
->db_stencil_clear
= true;
894 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
897 /* TODO: Find out what's wrong here. Fast depth clear leads to
898 * corruption in ARK: Survival Evolved, but that may just be
899 * a coincidence and the root cause is elsewhere.
901 * The corruption can be fixed by putting the DB metadata flush
902 * before or after the depth clear. (suprisingly)
904 * https://bugs.freedesktop.org/show_bug.cgi?id=102955 (apitrace)
906 * This hack decreases back-to-back ClearDepth performance.
908 if (sctx
->screen
->clear_db_meta_before_clear
)
909 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
|
910 SI_CONTEXT_PS_PARTIAL_FLUSH
;
913 si_blitter_begin(ctx
, SI_CLEAR
);
914 util_blitter_clear(sctx
->blitter
, fb
->width
, fb
->height
,
915 util_framebuffer_get_num_layers(fb
),
916 buffers
, color
, depth
, stencil
);
919 if (sctx
->db_depth_clear
) {
920 sctx
->db_depth_clear
= false;
921 sctx
->db_depth_disable_expclear
= false;
922 zstex
->depth_cleared
= true;
923 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
926 if (sctx
->db_stencil_clear
) {
927 sctx
->db_stencil_clear
= false;
928 sctx
->db_stencil_disable_expclear
= false;
929 zstex
->stencil_cleared
= true;
930 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
934 static void si_clear_render_target(struct pipe_context
*ctx
,
935 struct pipe_surface
*dst
,
936 const union pipe_color_union
*color
,
937 unsigned dstx
, unsigned dsty
,
938 unsigned width
, unsigned height
,
939 bool render_condition_enabled
)
941 struct si_context
*sctx
= (struct si_context
*)ctx
;
943 si_blitter_begin(ctx
, SI_CLEAR_SURFACE
|
944 (render_condition_enabled
? 0 : SI_DISABLE_RENDER_COND
));
945 util_blitter_clear_render_target(sctx
->blitter
, dst
, color
,
946 dstx
, dsty
, width
, height
);
950 static void si_clear_depth_stencil(struct pipe_context
*ctx
,
951 struct pipe_surface
*dst
,
952 unsigned clear_flags
,
955 unsigned dstx
, unsigned dsty
,
956 unsigned width
, unsigned height
,
957 bool render_condition_enabled
)
959 struct si_context
*sctx
= (struct si_context
*)ctx
;
961 si_blitter_begin(ctx
, SI_CLEAR_SURFACE
|
962 (render_condition_enabled
? 0 : SI_DISABLE_RENDER_COND
));
963 util_blitter_clear_depth_stencil(sctx
->blitter
, dst
, clear_flags
, depth
, stencil
,
964 dstx
, dsty
, width
, height
);
968 /* Helper for decompressing a portion of a color or depth resource before
969 * blitting if any decompression is needed.
970 * The driver doesn't decompress resources automatically while u_blitter is
972 static void si_decompress_subresource(struct pipe_context
*ctx
,
973 struct pipe_resource
*tex
,
974 unsigned planes
, unsigned level
,
975 unsigned first_layer
, unsigned last_layer
)
977 struct si_context
*sctx
= (struct si_context
*)ctx
;
978 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
980 if (rtex
->db_compatible
) {
981 planes
&= PIPE_MASK_Z
| PIPE_MASK_S
;
983 if (!rtex
->surface
.has_stencil
)
984 planes
&= ~PIPE_MASK_S
;
986 /* If we've rendered into the framebuffer and it's a blitting
987 * source, make sure the decompression pass is invoked
988 * by dirtying the framebuffer.
990 if (sctx
->framebuffer
.state
.zsbuf
&&
991 sctx
->framebuffer
.state
.zsbuf
->u
.tex
.level
== level
&&
992 sctx
->framebuffer
.state
.zsbuf
->texture
== tex
)
993 si_update_fb_dirtiness_after_rendering(sctx
);
995 si_decompress_depth(sctx
, rtex
, planes
,
997 first_layer
, last_layer
);
998 } else if (rtex
->fmask
.size
|| rtex
->cmask
.size
|| rtex
->dcc_offset
) {
999 /* If we've rendered into the framebuffer and it's a blitting
1000 * source, make sure the decompression pass is invoked
1001 * by dirtying the framebuffer.
1003 for (unsigned i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
1004 if (sctx
->framebuffer
.state
.cbufs
[i
] &&
1005 sctx
->framebuffer
.state
.cbufs
[i
]->u
.tex
.level
== level
&&
1006 sctx
->framebuffer
.state
.cbufs
[i
]->texture
== tex
) {
1007 si_update_fb_dirtiness_after_rendering(sctx
);
1012 si_blit_decompress_color(ctx
, rtex
, level
, level
,
1013 first_layer
, last_layer
, false);
1017 struct texture_orig_info
{
1027 void si_resource_copy_region(struct pipe_context
*ctx
,
1028 struct pipe_resource
*dst
,
1030 unsigned dstx
, unsigned dsty
, unsigned dstz
,
1031 struct pipe_resource
*src
,
1033 const struct pipe_box
*src_box
)
1035 struct si_context
*sctx
= (struct si_context
*)ctx
;
1036 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
1037 struct pipe_surface
*dst_view
, dst_templ
;
1038 struct pipe_sampler_view src_templ
, *src_view
;
1039 unsigned dst_width
, dst_height
, src_width0
, src_height0
;
1040 unsigned dst_width0
, dst_height0
, src_force_level
= 0;
1041 struct pipe_box sbox
, dstbox
;
1043 /* Handle buffers first. */
1044 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
1045 si_copy_buffer(sctx
, dst
, src
, dstx
, src_box
->x
, src_box
->width
, 0);
1049 assert(u_max_sample(dst
) == u_max_sample(src
));
1051 /* The driver doesn't decompress resources automatically while
1052 * u_blitter is rendering. */
1053 si_decompress_subresource(ctx
, src
, PIPE_MASK_RGBAZS
, src_level
,
1054 src_box
->z
, src_box
->z
+ src_box
->depth
- 1);
1056 dst_width
= u_minify(dst
->width0
, dst_level
);
1057 dst_height
= u_minify(dst
->height0
, dst_level
);
1058 dst_width0
= dst
->width0
;
1059 dst_height0
= dst
->height0
;
1060 src_width0
= src
->width0
;
1061 src_height0
= src
->height0
;
1063 util_blitter_default_dst_texture(&dst_templ
, dst
, dst_level
, dstz
);
1064 util_blitter_default_src_texture(sctx
->blitter
, &src_templ
, src
, src_level
);
1066 if (util_format_is_compressed(src
->format
) ||
1067 util_format_is_compressed(dst
->format
)) {
1068 unsigned blocksize
= rsrc
->surface
.bpe
;
1071 src_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
; /* 64-bit block */
1073 src_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
; /* 128-bit block */
1074 dst_templ
.format
= src_templ
.format
;
1076 dst_width
= util_format_get_nblocksx(dst
->format
, dst_width
);
1077 dst_height
= util_format_get_nblocksy(dst
->format
, dst_height
);
1078 dst_width0
= util_format_get_nblocksx(dst
->format
, dst_width0
);
1079 dst_height0
= util_format_get_nblocksy(dst
->format
, dst_height0
);
1080 src_width0
= util_format_get_nblocksx(src
->format
, src_width0
);
1081 src_height0
= util_format_get_nblocksy(src
->format
, src_height0
);
1083 dstx
= util_format_get_nblocksx(dst
->format
, dstx
);
1084 dsty
= util_format_get_nblocksy(dst
->format
, dsty
);
1086 sbox
.x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
1087 sbox
.y
= util_format_get_nblocksy(src
->format
, src_box
->y
);
1088 sbox
.z
= src_box
->z
;
1089 sbox
.width
= util_format_get_nblocksx(src
->format
, src_box
->width
);
1090 sbox
.height
= util_format_get_nblocksy(src
->format
, src_box
->height
);
1091 sbox
.depth
= src_box
->depth
;
1094 src_force_level
= src_level
;
1095 } else if (!util_blitter_is_copy_supported(sctx
->blitter
, dst
, src
)) {
1096 if (util_format_is_subsampled_422(src
->format
)) {
1097 src_templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
;
1098 dst_templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
;
1100 dst_width
= util_format_get_nblocksx(dst
->format
, dst_width
);
1101 dst_width0
= util_format_get_nblocksx(dst
->format
, dst_width0
);
1102 src_width0
= util_format_get_nblocksx(src
->format
, src_width0
);
1104 dstx
= util_format_get_nblocksx(dst
->format
, dstx
);
1107 sbox
.x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
1108 sbox
.width
= util_format_get_nblocksx(src
->format
, src_box
->width
);
1111 unsigned blocksize
= rsrc
->surface
.bpe
;
1113 switch (blocksize
) {
1115 dst_templ
.format
= PIPE_FORMAT_R8_UNORM
;
1116 src_templ
.format
= PIPE_FORMAT_R8_UNORM
;
1119 dst_templ
.format
= PIPE_FORMAT_R8G8_UNORM
;
1120 src_templ
.format
= PIPE_FORMAT_R8G8_UNORM
;
1123 dst_templ
.format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
1124 src_templ
.format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
1127 dst_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
;
1128 src_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
;
1131 dst_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
;
1132 src_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
;
1135 fprintf(stderr
, "Unhandled format %s with blocksize %u\n",
1136 util_format_short_name(src
->format
), blocksize
);
1142 /* SNORM8 blitting has precision issues on some chips. Use the SINT
1143 * equivalent instead, which doesn't force DCC decompression.
1144 * Note that some chips avoid this issue by using SDMA.
1146 if (util_format_is_snorm8(dst_templ
.format
)) {
1147 switch (dst_templ
.format
) {
1148 case PIPE_FORMAT_R8_SNORM
:
1149 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_R8_SINT
;
1151 case PIPE_FORMAT_R8G8_SNORM
:
1152 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_R8G8_SINT
;
1154 case PIPE_FORMAT_R8G8B8X8_SNORM
:
1155 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_R8G8B8X8_SINT
;
1157 case PIPE_FORMAT_R8G8B8A8_SNORM
:
1158 /* There are no SINT variants for ABGR and XBGR, so we have to use RGBA. */
1159 case PIPE_FORMAT_A8B8G8R8_SNORM
:
1160 case PIPE_FORMAT_X8B8G8R8_SNORM
:
1161 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_R8G8B8A8_SINT
;
1163 case PIPE_FORMAT_A8_SNORM
:
1164 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_A8_SINT
;
1166 case PIPE_FORMAT_L8_SNORM
:
1167 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_L8_SINT
;
1169 case PIPE_FORMAT_L8A8_SNORM
:
1170 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_L8A8_SINT
;
1172 case PIPE_FORMAT_I8_SNORM
:
1173 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_I8_SINT
;
1175 default:; /* fall through */
1179 vi_disable_dcc_if_incompatible_format(&sctx
->b
, dst
, dst_level
,
1181 vi_disable_dcc_if_incompatible_format(&sctx
->b
, src
, src_level
,
1184 /* Initialize the surface. */
1185 dst_view
= si_create_surface_custom(ctx
, dst
, &dst_templ
,
1186 dst_width0
, dst_height0
,
1187 dst_width
, dst_height
);
1189 /* Initialize the sampler view. */
1190 src_view
= si_create_sampler_view_custom(ctx
, src
, &src_templ
,
1191 src_width0
, src_height0
,
1194 u_box_3d(dstx
, dsty
, dstz
, abs(src_box
->width
), abs(src_box
->height
),
1195 abs(src_box
->depth
), &dstbox
);
1198 si_blitter_begin(ctx
, SI_COPY
);
1199 util_blitter_blit_generic(sctx
->blitter
, dst_view
, &dstbox
,
1200 src_view
, src_box
, src_width0
, src_height0
,
1201 PIPE_MASK_RGBAZS
, PIPE_TEX_FILTER_NEAREST
, NULL
,
1203 si_blitter_end(ctx
);
1205 pipe_surface_reference(&dst_view
, NULL
);
1206 pipe_sampler_view_reference(&src_view
, NULL
);
1209 static void si_do_CB_resolve(struct si_context
*sctx
,
1210 const struct pipe_blit_info
*info
,
1211 struct pipe_resource
*dst
,
1212 unsigned dst_level
, unsigned dst_z
,
1213 enum pipe_format format
)
1215 /* Required before and after CB_RESOLVE. */
1216 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
1218 si_blitter_begin(&sctx
->b
.b
, SI_COLOR_RESOLVE
|
1219 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1220 util_blitter_custom_resolve_color(sctx
->blitter
, dst
, dst_level
, dst_z
,
1221 info
->src
.resource
, info
->src
.box
.z
,
1222 ~0, sctx
->custom_blend_resolve
,
1224 si_blitter_end(&sctx
->b
.b
);
1226 /* Flush caches for possible texturing. */
1227 si_make_CB_shader_coherent(sctx
, 1, false);
1230 static bool do_hardware_msaa_resolve(struct pipe_context
*ctx
,
1231 const struct pipe_blit_info
*info
)
1233 struct si_context
*sctx
= (struct si_context
*)ctx
;
1234 struct r600_texture
*src
= (struct r600_texture
*)info
->src
.resource
;
1235 struct r600_texture
*dst
= (struct r600_texture
*)info
->dst
.resource
;
1236 MAYBE_UNUSED
struct r600_texture
*rtmp
;
1237 unsigned dst_width
= u_minify(info
->dst
.resource
->width0
, info
->dst
.level
);
1238 unsigned dst_height
= u_minify(info
->dst
.resource
->height0
, info
->dst
.level
);
1239 enum pipe_format format
= info
->src
.format
;
1240 struct pipe_resource
*tmp
, templ
;
1241 struct pipe_blit_info blit
;
1243 /* Check basic requirements for hw resolve. */
1244 if (!(info
->src
.resource
->nr_samples
> 1 &&
1245 info
->dst
.resource
->nr_samples
<= 1 &&
1246 !util_format_is_pure_integer(format
) &&
1247 !util_format_is_depth_or_stencil(format
) &&
1248 util_max_layer(info
->src
.resource
, 0) == 0))
1251 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1252 * the format is R16G16. Use R16A16, which does work.
1254 if (format
== PIPE_FORMAT_R16G16_UNORM
)
1255 format
= PIPE_FORMAT_R16A16_UNORM
;
1256 if (format
== PIPE_FORMAT_R16G16_SNORM
)
1257 format
= PIPE_FORMAT_R16A16_SNORM
;
1259 /* Check the remaining requirements for hw resolve. */
1260 if (util_max_layer(info
->dst
.resource
, info
->dst
.level
) == 0 &&
1261 !info
->scissor_enable
&&
1262 (info
->mask
& PIPE_MASK_RGBA
) == PIPE_MASK_RGBA
&&
1263 util_is_format_compatible(util_format_description(info
->src
.format
),
1264 util_format_description(info
->dst
.format
)) &&
1265 dst_width
== info
->src
.resource
->width0
&&
1266 dst_height
== info
->src
.resource
->height0
&&
1267 info
->dst
.box
.x
== 0 &&
1268 info
->dst
.box
.y
== 0 &&
1269 info
->dst
.box
.width
== dst_width
&&
1270 info
->dst
.box
.height
== dst_height
&&
1271 info
->dst
.box
.depth
== 1 &&
1272 info
->src
.box
.x
== 0 &&
1273 info
->src
.box
.y
== 0 &&
1274 info
->src
.box
.width
== dst_width
&&
1275 info
->src
.box
.height
== dst_height
&&
1276 info
->src
.box
.depth
== 1 &&
1277 !dst
->surface
.is_linear
&&
1278 (!dst
->cmask
.size
|| !dst
->dirty_level_mask
)) { /* dst cannot be fast-cleared */
1279 /* Check the last constraint. */
1280 if (src
->surface
.micro_tile_mode
!= dst
->surface
.micro_tile_mode
) {
1281 /* The next fast clear will switch to this mode to
1282 * get direct hw resolve next time if the mode is
1285 src
->last_msaa_resolve_target_micro_mode
=
1286 dst
->surface
.micro_tile_mode
;
1287 goto resolve_to_temp
;
1290 /* Resolving into a surface with DCC is unsupported. Since
1291 * it's being overwritten anyway, clear it to uncompressed.
1292 * This is still the fastest codepath even with this clear.
1294 if (vi_dcc_enabled(dst
, info
->dst
.level
)) {
1295 /* TODO: Implement per-level DCC clears for GFX9. */
1296 if (sctx
->b
.chip_class
>= GFX9
&&
1297 info
->dst
.resource
->last_level
!= 0)
1298 goto resolve_to_temp
;
1300 vi_dcc_clear_level(&sctx
->b
, dst
, info
->dst
.level
,
1302 dst
->dirty_level_mask
&= ~(1 << info
->dst
.level
);
1305 /* Resolve directly from src to dst. */
1306 si_do_CB_resolve(sctx
, info
, info
->dst
.resource
,
1307 info
->dst
.level
, info
->dst
.box
.z
, format
);
1312 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1313 * a temporary texture and blit.
1315 memset(&templ
, 0, sizeof(templ
));
1316 templ
.target
= PIPE_TEXTURE_2D
;
1317 templ
.format
= info
->src
.resource
->format
;
1318 templ
.width0
= info
->src
.resource
->width0
;
1319 templ
.height0
= info
->src
.resource
->height0
;
1321 templ
.array_size
= 1;
1322 templ
.usage
= PIPE_USAGE_DEFAULT
;
1323 templ
.flags
= R600_RESOURCE_FLAG_FORCE_TILING
|
1324 R600_RESOURCE_FLAG_DISABLE_DCC
;
1326 /* The src and dst microtile modes must be the same. */
1327 if (src
->surface
.micro_tile_mode
== RADEON_MICRO_MODE_DISPLAY
)
1328 templ
.bind
= PIPE_BIND_SCANOUT
;
1332 tmp
= ctx
->screen
->resource_create(ctx
->screen
, &templ
);
1335 rtmp
= (struct r600_texture
*)tmp
;
1337 assert(!rtmp
->surface
.is_linear
);
1338 assert(src
->surface
.micro_tile_mode
== rtmp
->surface
.micro_tile_mode
);
1341 si_do_CB_resolve(sctx
, info
, tmp
, 0, 0, format
);
1345 blit
.src
.resource
= tmp
;
1348 si_blitter_begin(ctx
, SI_BLIT
|
1349 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1350 util_blitter_blit(sctx
->blitter
, &blit
);
1351 si_blitter_end(ctx
);
1353 pipe_resource_reference(&tmp
, NULL
);
1357 static void si_blit(struct pipe_context
*ctx
,
1358 const struct pipe_blit_info
*info
)
1360 struct si_context
*sctx
= (struct si_context
*)ctx
;
1361 struct r600_texture
*rdst
= (struct r600_texture
*)info
->dst
.resource
;
1363 if (do_hardware_msaa_resolve(ctx
, info
)) {
1367 /* Using SDMA for copying to a linear texture in GTT is much faster.
1368 * This improves DRI PRIME performance.
1370 * resource_copy_region can't do this yet, because dma_copy calls it
1371 * on failure (recursion).
1373 if (rdst
->surface
.is_linear
&&
1375 util_can_blit_via_copy_region(info
, false)) {
1376 sctx
->b
.dma_copy(ctx
, info
->dst
.resource
, info
->dst
.level
,
1377 info
->dst
.box
.x
, info
->dst
.box
.y
,
1379 info
->src
.resource
, info
->src
.level
,
1384 assert(util_blitter_is_blit_supported(sctx
->blitter
, info
));
1386 /* The driver doesn't decompress resources automatically while
1387 * u_blitter is rendering. */
1388 vi_disable_dcc_if_incompatible_format(&sctx
->b
, info
->src
.resource
,
1391 vi_disable_dcc_if_incompatible_format(&sctx
->b
, info
->dst
.resource
,
1394 si_decompress_subresource(ctx
, info
->src
.resource
, info
->mask
,
1397 info
->src
.box
.z
+ info
->src
.box
.depth
- 1);
1399 if (sctx
->screen
->b
.debug_flags
& DBG_FORCE_DMA
&&
1400 util_try_blit_via_copy_region(ctx
, info
))
1403 si_blitter_begin(ctx
, SI_BLIT
|
1404 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1405 util_blitter_blit(sctx
->blitter
, info
);
1406 si_blitter_end(ctx
);
1409 static boolean
si_generate_mipmap(struct pipe_context
*ctx
,
1410 struct pipe_resource
*tex
,
1411 enum pipe_format format
,
1412 unsigned base_level
, unsigned last_level
,
1413 unsigned first_layer
, unsigned last_layer
)
1415 struct si_context
*sctx
= (struct si_context
*)ctx
;
1416 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1418 if (!util_blitter_is_copy_supported(sctx
->blitter
, tex
, tex
))
1421 /* The driver doesn't decompress resources automatically while
1422 * u_blitter is rendering. */
1423 vi_disable_dcc_if_incompatible_format(&sctx
->b
, tex
, base_level
,
1425 si_decompress_subresource(ctx
, tex
, PIPE_MASK_RGBAZS
,
1426 base_level
, first_layer
, last_layer
);
1428 /* Clear dirty_level_mask for the levels that will be overwritten. */
1429 assert(base_level
< last_level
);
1430 rtex
->dirty_level_mask
&= ~u_bit_consecutive(base_level
+ 1,
1431 last_level
- base_level
);
1433 sctx
->generate_mipmap_for_depth
= rtex
->is_depth
;
1435 si_blitter_begin(ctx
, SI_BLIT
| SI_DISABLE_RENDER_COND
);
1436 util_blitter_generate_mipmap(sctx
->blitter
, tex
, format
,
1437 base_level
, last_level
,
1438 first_layer
, last_layer
);
1439 si_blitter_end(ctx
);
1441 sctx
->generate_mipmap_for_depth
= false;
1445 static void si_flush_resource(struct pipe_context
*ctx
,
1446 struct pipe_resource
*res
)
1448 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
1450 assert(res
->target
!= PIPE_BUFFER
);
1451 assert(!rtex
->dcc_separate_buffer
|| rtex
->dcc_gather_statistics
);
1453 /* st/dri calls flush twice per frame (not a bug), this prevents double
1455 if (rtex
->dcc_separate_buffer
&& !rtex
->separate_dcc_dirty
)
1458 if (!rtex
->is_depth
&& (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
1459 si_blit_decompress_color(ctx
, rtex
, 0, res
->last_level
,
1460 0, util_max_layer(res
, 0),
1461 rtex
->dcc_separate_buffer
!= NULL
);
1464 /* Always do the analysis even if DCC is disabled at the moment. */
1465 if (rtex
->dcc_gather_statistics
&& rtex
->separate_dcc_dirty
) {
1466 rtex
->separate_dcc_dirty
= false;
1467 vi_separate_dcc_process_and_reset_stats(ctx
, rtex
);
1471 static void si_decompress_dcc(struct pipe_context
*ctx
,
1472 struct r600_texture
*rtex
)
1474 if (!rtex
->dcc_offset
)
1477 si_blit_decompress_color(ctx
, rtex
, 0, rtex
->resource
.b
.b
.last_level
,
1478 0, util_max_layer(&rtex
->resource
.b
.b
, 0),
1482 static void si_pipe_clear_buffer(struct pipe_context
*ctx
,
1483 struct pipe_resource
*dst
,
1484 unsigned offset
, unsigned size
,
1485 const void *clear_value_ptr
,
1486 int clear_value_size
)
1488 struct si_context
*sctx
= (struct si_context
*)ctx
;
1489 uint32_t dword_value
;
1492 assert(offset
% clear_value_size
== 0);
1493 assert(size
% clear_value_size
== 0);
1495 if (clear_value_size
> 4) {
1496 const uint32_t *u32
= clear_value_ptr
;
1497 bool clear_dword_duplicated
= true;
1499 /* See if we can lower large fills to dword fills. */
1500 for (i
= 1; i
< clear_value_size
/ 4; i
++)
1501 if (u32
[0] != u32
[i
]) {
1502 clear_dword_duplicated
= false;
1506 if (!clear_dword_duplicated
) {
1507 /* Use transform feedback for 64-bit, 96-bit, and
1510 union pipe_color_union clear_value
;
1512 memcpy(&clear_value
, clear_value_ptr
, clear_value_size
);
1513 si_blitter_begin(ctx
, SI_DISABLE_RENDER_COND
);
1514 util_blitter_clear_buffer(sctx
->blitter
, dst
, offset
,
1515 size
, clear_value_size
/ 4,
1517 si_blitter_end(ctx
);
1522 /* Expand the clear value to a dword. */
1523 switch (clear_value_size
) {
1525 dword_value
= *(uint8_t*)clear_value_ptr
;
1526 dword_value
|= (dword_value
<< 8) |
1527 (dword_value
<< 16) |
1528 (dword_value
<< 24);
1531 dword_value
= *(uint16_t*)clear_value_ptr
;
1532 dword_value
|= dword_value
<< 16;
1535 dword_value
= *(uint32_t*)clear_value_ptr
;
1538 sctx
->b
.clear_buffer(ctx
, dst
, offset
, size
, dword_value
,
1539 R600_COHERENCY_SHADER
);
1542 void si_init_blit_functions(struct si_context
*sctx
)
1544 sctx
->b
.b
.clear
= si_clear
;
1545 sctx
->b
.b
.clear_buffer
= si_pipe_clear_buffer
;
1546 sctx
->b
.b
.clear_render_target
= si_clear_render_target
;
1547 sctx
->b
.b
.clear_depth_stencil
= si_clear_depth_stencil
;
1548 sctx
->b
.b
.resource_copy_region
= si_resource_copy_region
;
1549 sctx
->b
.b
.blit
= si_blit
;
1550 sctx
->b
.b
.flush_resource
= si_flush_resource
;
1551 sctx
->b
.b
.generate_mipmap
= si_generate_mipmap
;
1552 sctx
->b
.blit_decompress_depth
= si_blit_decompress_depth
;
1553 sctx
->b
.decompress_dcc
= si_decompress_dcc
;