2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "util/u_format.h"
29 #include "util/u_pack_color.h"
30 #include "util/u_surface.h"
33 SI_CLEAR
= SI_SAVE_FRAGMENT_STATE
,
34 SI_CLEAR_SURFACE
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
,
37 static void si_alloc_separate_cmask(struct si_screen
*sscreen
,
38 struct si_texture
*tex
)
40 if (tex
->cmask_buffer
|| !tex
->surface
.cmask_size
)
44 si_aligned_buffer_create(&sscreen
->b
,
45 SI_RESOURCE_FLAG_UNMAPPABLE
,
47 tex
->surface
.cmask_size
,
48 tex
->surface
.cmask_alignment
);
49 if (tex
->cmask_buffer
== NULL
)
52 tex
->cmask_base_address_reg
= tex
->cmask_buffer
->gpu_address
>> 8;
53 tex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
55 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
58 static bool si_set_clear_color(struct si_texture
*tex
,
59 enum pipe_format surface_format
,
60 const union pipe_color_union
*color
)
64 memset(&uc
, 0, sizeof(uc
));
66 if (tex
->surface
.bpe
== 16) {
67 /* DCC fast clear only:
68 * CLEAR_WORD0 = R = G = B
71 assert(color
->ui
[0] == color
->ui
[1] &&
72 color
->ui
[0] == color
->ui
[2]);
73 uc
.ui
[0] = color
->ui
[0];
74 uc
.ui
[1] = color
->ui
[3];
75 } else if (util_format_is_pure_uint(surface_format
)) {
76 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
77 } else if (util_format_is_pure_sint(surface_format
)) {
78 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
80 util_pack_color(color
->f
, surface_format
, &uc
);
83 if (memcmp(tex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t)) == 0)
86 memcpy(tex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
90 /** Linearize and convert luminace/intensity to red. */
91 enum pipe_format
si_simplify_cb_format(enum pipe_format format
)
93 format
= util_format_linear(format
);
94 format
= util_format_luminance_to_red(format
);
95 return util_format_intensity_to_red(format
);
98 bool vi_alpha_is_on_msb(enum pipe_format format
)
100 format
= si_simplify_cb_format(format
);
102 /* Formats with 3 channels can't have alpha. */
103 if (util_format_description(format
)->nr_channels
== 3)
104 return true; /* same as xxxA; is any value OK here? */
106 return si_translate_colorswap(format
, false) <= 1;
109 static bool vi_get_fast_clear_parameters(enum pipe_format base_format
,
110 enum pipe_format surface_format
,
111 const union pipe_color_union
*color
,
112 uint32_t* clear_value
,
113 bool *eliminate_needed
)
115 /* If we want to clear without needing a fast clear eliminate step, we
116 * can set color and alpha independently to 0 or 1 (or 0/max for integer
119 bool values
[4] = {}; /* whether to clear to 0 or 1 */
120 bool color_value
= false; /* clear color to 0 or 1 */
121 bool alpha_value
= false; /* clear alpha to 0 or 1 */
122 int alpha_channel
; /* index of the alpha component */
123 bool has_color
= false;
124 bool has_alpha
= false;
126 const struct util_format_description
*desc
=
127 util_format_description(si_simplify_cb_format(surface_format
));
129 /* 128-bit fast clear with different R,G,B values is unsupported. */
130 if (desc
->block
.bits
== 128 &&
131 (color
->ui
[0] != color
->ui
[1] ||
132 color
->ui
[0] != color
->ui
[2]))
135 *eliminate_needed
= true;
136 *clear_value
= DCC_CLEAR_COLOR_REG
;
138 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
139 return true; /* need ELIMINATE_FAST_CLEAR */
141 bool base_alpha_is_on_msb
= vi_alpha_is_on_msb(base_format
);
142 bool surf_alpha_is_on_msb
= vi_alpha_is_on_msb(surface_format
);
144 /* Formats with 3 channels can't have alpha. */
145 if (desc
->nr_channels
== 3)
147 else if (surf_alpha_is_on_msb
)
148 alpha_channel
= desc
->nr_channels
- 1;
152 for (int i
= 0; i
< 4; ++i
) {
153 if (desc
->swizzle
[i
] >= PIPE_SWIZZLE_0
)
156 if (desc
->channel
[i
].pure_integer
&&
157 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
158 /* Use the maximum value for clamping the clear color. */
159 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
161 values
[i
] = color
->i
[i
] != 0;
162 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
163 return true; /* need ELIMINATE_FAST_CLEAR */
164 } else if (desc
->channel
[i
].pure_integer
&&
165 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
166 /* Use the maximum value for clamping the clear color. */
167 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
169 values
[i
] = color
->ui
[i
] != 0U;
170 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
171 return true; /* need ELIMINATE_FAST_CLEAR */
173 values
[i
] = color
->f
[i
] != 0.0F
;
174 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
175 return true; /* need ELIMINATE_FAST_CLEAR */
178 if (desc
->swizzle
[i
] == alpha_channel
) {
179 alpha_value
= values
[i
];
182 color_value
= values
[i
];
187 /* If alpha isn't present, make it the same as color, and vice versa. */
189 alpha_value
= color_value
;
191 color_value
= alpha_value
;
193 if (color_value
!= alpha_value
&&
194 base_alpha_is_on_msb
!= surf_alpha_is_on_msb
)
195 return true; /* require ELIMINATE_FAST_CLEAR */
197 /* Check if all color values are equal if they are present. */
198 for (int i
= 0; i
< 4; ++i
) {
199 if (desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
200 desc
->swizzle
[i
] != alpha_channel
&&
201 values
[i
] != color_value
)
202 return true; /* require ELIMINATE_FAST_CLEAR */
205 /* This doesn't need ELIMINATE_FAST_CLEAR.
206 * On chips predating Raven2, the DCC clear codes and the CB clear
207 * color registers must match.
209 *eliminate_needed
= false;
213 *clear_value
= DCC_CLEAR_COLOR_1111
;
215 *clear_value
= DCC_CLEAR_COLOR_1110
;
218 *clear_value
= DCC_CLEAR_COLOR_0001
;
220 *clear_value
= DCC_CLEAR_COLOR_0000
;
225 void vi_dcc_clear_level(struct si_context
*sctx
,
226 struct si_texture
*tex
,
227 unsigned level
, unsigned clear_value
)
229 struct pipe_resource
*dcc_buffer
;
230 uint64_t dcc_offset
, clear_size
;
232 assert(vi_dcc_enabled(tex
, level
));
234 if (tex
->dcc_separate_buffer
) {
235 dcc_buffer
= &tex
->dcc_separate_buffer
->b
.b
;
238 dcc_buffer
= &tex
->buffer
.b
.b
;
239 dcc_offset
= tex
->dcc_offset
;
242 if (sctx
->chip_class
>= GFX9
) {
243 /* Mipmap level clears aren't implemented. */
244 assert(tex
->buffer
.b
.b
.last_level
== 0);
245 /* 4x and 8x MSAA needs a sophisticated compute shader for
246 * the clear. See AMDVLK. */
247 assert(tex
->buffer
.b
.b
.nr_storage_samples
<= 2);
248 clear_size
= tex
->surface
.dcc_size
;
250 unsigned num_layers
= util_num_layers(&tex
->buffer
.b
.b
, level
);
252 /* If this is 0, fast clear isn't possible. (can occur with MSAA) */
253 assert(tex
->surface
.u
.legacy
.level
[level
].dcc_fast_clear_size
);
254 /* Layered 4x and 8x MSAA DCC fast clears need to clear
255 * dcc_fast_clear_size bytes for each layer. A compute shader
256 * would be more efficient than separate per-layer clear operations.
258 assert(tex
->buffer
.b
.b
.nr_storage_samples
<= 2 || num_layers
== 1);
260 dcc_offset
+= tex
->surface
.u
.legacy
.level
[level
].dcc_offset
;
261 clear_size
= tex
->surface
.u
.legacy
.level
[level
].dcc_fast_clear_size
*
265 si_clear_buffer(sctx
, dcc_buffer
, dcc_offset
, clear_size
,
266 &clear_value
, 4, SI_COHERENCY_CB_META
, false);
269 /* Set the same micro tile mode as the destination of the last MSAA resolve.
270 * This allows hitting the MSAA resolve fast path, which requires that both
271 * src and dst micro tile modes match.
273 static void si_set_optimal_micro_tile_mode(struct si_screen
*sscreen
,
274 struct si_texture
*tex
)
276 if (tex
->buffer
.b
.is_shared
||
277 tex
->buffer
.b
.b
.nr_samples
<= 1 ||
278 tex
->surface
.micro_tile_mode
== tex
->last_msaa_resolve_target_micro_mode
)
281 assert(sscreen
->info
.chip_class
>= GFX9
||
282 tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
283 assert(tex
->buffer
.b
.b
.last_level
== 0);
285 if (sscreen
->info
.chip_class
>= GFX9
) {
286 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
287 assert(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
>= 4);
289 /* If you do swizzle_mode % 4, you'll get:
295 * Depth-sample order isn't allowed:
297 assert(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
% 4 != 0);
299 switch (tex
->last_msaa_resolve_target_micro_mode
) {
300 case RADEON_MICRO_MODE_DISPLAY
:
301 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
302 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 2; /* D */
304 case RADEON_MICRO_MODE_THIN
:
305 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
306 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 1; /* S */
308 case RADEON_MICRO_MODE_ROTATED
:
309 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
310 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 3; /* R */
313 assert(!"unexpected micro mode");
316 } else if (sscreen
->info
.chip_class
>= GFX7
) {
317 /* These magic numbers were copied from addrlib. It doesn't use
318 * any definitions for them either. They are all 2D_TILED_THIN1
319 * modes with different bpp and micro tile mode.
321 switch (tex
->last_msaa_resolve_target_micro_mode
) {
322 case RADEON_MICRO_MODE_DISPLAY
:
323 tex
->surface
.u
.legacy
.tiling_index
[0] = 10;
325 case RADEON_MICRO_MODE_THIN
:
326 tex
->surface
.u
.legacy
.tiling_index
[0] = 14;
328 case RADEON_MICRO_MODE_ROTATED
:
329 tex
->surface
.u
.legacy
.tiling_index
[0] = 28;
331 default: /* depth, thick */
332 assert(!"unexpected micro mode");
336 switch (tex
->last_msaa_resolve_target_micro_mode
) {
337 case RADEON_MICRO_MODE_DISPLAY
:
338 switch (tex
->surface
.bpe
) {
340 tex
->surface
.u
.legacy
.tiling_index
[0] = 10;
343 tex
->surface
.u
.legacy
.tiling_index
[0] = 11;
346 tex
->surface
.u
.legacy
.tiling_index
[0] = 12;
350 case RADEON_MICRO_MODE_THIN
:
351 switch (tex
->surface
.bpe
) {
353 tex
->surface
.u
.legacy
.tiling_index
[0] = 14;
356 tex
->surface
.u
.legacy
.tiling_index
[0] = 15;
359 tex
->surface
.u
.legacy
.tiling_index
[0] = 16;
362 tex
->surface
.u
.legacy
.tiling_index
[0] = 17;
366 default: /* depth, thick */
367 assert(!"unexpected micro mode");
372 tex
->surface
.micro_tile_mode
= tex
->last_msaa_resolve_target_micro_mode
;
374 p_atomic_inc(&sscreen
->dirty_tex_counter
);
377 static void si_do_fast_color_clear(struct si_context
*sctx
,
379 const union pipe_color_union
*color
)
381 struct pipe_framebuffer_state
*fb
= &sctx
->framebuffer
.state
;
384 /* This function is broken in BE, so just disable this path for now */
385 #ifdef PIPE_ARCH_BIG_ENDIAN
389 if (sctx
->render_cond
)
392 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
393 struct si_texture
*tex
;
394 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
399 /* if this colorbuffer is not being cleared */
400 if (!(*buffers
& clear_bit
))
403 unsigned level
= fb
->cbufs
[i
]->u
.tex
.level
;
407 tex
= (struct si_texture
*)fb
->cbufs
[i
]->texture
;
409 /* TODO: GFX9: Implement DCC fast clear for level 0 of
410 * mipmapped textures. Mipmapped DCC has to clear a rectangular
411 * area of DCC for level 0 (because the whole miptree is
412 * organized in a 2D plane).
414 if (sctx
->chip_class
>= GFX9
&&
415 tex
->buffer
.b
.b
.last_level
> 0)
418 /* the clear is allowed if all layers are bound */
419 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
420 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->buffer
.b
.b
, 0)) {
424 /* only supported on tiled surfaces */
425 if (tex
->surface
.is_linear
) {
429 /* shared textures can't use fast clear without an explicit flush,
430 * because there is no way to communicate the clear color among
433 if (tex
->buffer
.b
.is_shared
&&
434 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
437 if (sctx
->chip_class
<= GFX8
&&
438 tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
439 !sctx
->screen
->info
.htile_cmask_support_1d_tiling
)
442 /* Use a slow clear for small surfaces where the cost of
443 * the eliminate pass can be higher than the benefit of fast
444 * clear. The closed driver does this, but the numbers may differ.
446 * This helps on both dGPUs and APUs, even small APUs like Mullins.
448 bool too_small
= tex
->buffer
.b
.b
.nr_samples
<= 1 &&
449 tex
->buffer
.b
.b
.width0
*
450 tex
->buffer
.b
.b
.height0
<= 512 * 512;
451 bool eliminate_needed
= false;
452 bool fmask_decompress_needed
= false;
454 /* Fast clear is the most appropriate place to enable DCC for
455 * displayable surfaces.
457 if (sctx
->family
== CHIP_STONEY
&& !too_small
) {
458 vi_separate_dcc_try_enable(sctx
, tex
);
460 /* RB+ isn't supported with a CMASK clear only on Stoney,
461 * so all clears are considered to be hypothetically slow
462 * clears, which is weighed when determining whether to
463 * enable separate DCC.
465 if (tex
->dcc_gather_statistics
) /* only for Stoney */
466 tex
->num_slow_clears
++;
469 /* Try to clear DCC first, otherwise try CMASK. */
470 if (vi_dcc_enabled(tex
, 0)) {
471 uint32_t reset_value
;
473 if (sctx
->screen
->debug_flags
& DBG(NO_DCC_CLEAR
))
476 /* This can happen with mipmapping or MSAA. */
477 if (sctx
->chip_class
== GFX8
&&
478 !tex
->surface
.u
.legacy
.level
[level
].dcc_fast_clear_size
)
481 if (!vi_get_fast_clear_parameters(tex
->buffer
.b
.b
.format
,
482 fb
->cbufs
[i
]->format
,
487 if (eliminate_needed
&& too_small
)
490 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
491 if (tex
->buffer
.b
.b
.nr_samples
>= 2 && tex
->cmask_buffer
) {
492 /* TODO: This doesn't work with MSAA. */
493 if (eliminate_needed
)
496 uint32_t clear_value
= 0xCCCCCCCC;
497 si_clear_buffer(sctx
, &tex
->cmask_buffer
->b
.b
,
498 tex
->cmask_offset
, tex
->surface
.cmask_size
,
499 &clear_value
, 4, SI_COHERENCY_CB_META
, false);
500 fmask_decompress_needed
= true;
503 vi_dcc_clear_level(sctx
, tex
, 0, reset_value
);
504 tex
->separate_dcc_dirty
= true;
509 /* 128-bit formats are unusupported */
510 if (tex
->surface
.bpe
> 8) {
514 /* RB+ doesn't work with CMASK fast clear on Stoney. */
515 if (sctx
->family
== CHIP_STONEY
)
518 /* ensure CMASK is enabled */
519 si_alloc_separate_cmask(sctx
->screen
, tex
);
520 if (!tex
->cmask_buffer
)
523 /* Do the fast clear. */
524 uint32_t clear_value
= 0;
525 si_clear_buffer(sctx
, &tex
->cmask_buffer
->b
.b
,
526 tex
->cmask_offset
, tex
->surface
.cmask_size
,
527 &clear_value
, 4, SI_COHERENCY_CB_META
, false);
528 eliminate_needed
= true;
531 if ((eliminate_needed
|| fmask_decompress_needed
) &&
532 !(tex
->dirty_level_mask
& (1 << level
))) {
533 tex
->dirty_level_mask
|= 1 << level
;
534 p_atomic_inc(&sctx
->screen
->compressed_colortex_counter
);
537 /* We can change the micro tile mode before a full clear. */
538 si_set_optimal_micro_tile_mode(sctx
->screen
, tex
);
540 *buffers
&= ~clear_bit
;
542 /* Chips with DCC constant encoding don't need to set the clear
543 * color registers for DCC clear values 0 and 1.
545 if (sctx
->screen
->has_dcc_constant_encode
&& !eliminate_needed
)
548 if (si_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
)) {
549 sctx
->framebuffer
.dirty_cbufs
|= 1 << i
;
550 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
555 static void si_clear(struct pipe_context
*ctx
, unsigned buffers
,
556 const union pipe_color_union
*color
,
557 double depth
, unsigned stencil
)
559 struct si_context
*sctx
= (struct si_context
*)ctx
;
560 struct pipe_framebuffer_state
*fb
= &sctx
->framebuffer
.state
;
561 struct pipe_surface
*zsbuf
= fb
->zsbuf
;
562 struct si_texture
*zstex
=
563 zsbuf
? (struct si_texture
*)zsbuf
->texture
: NULL
;
565 if (buffers
& PIPE_CLEAR_COLOR
) {
566 si_do_fast_color_clear(sctx
, &buffers
, color
);
568 return; /* all buffers have been fast cleared */
570 /* These buffers cannot use fast clear, make sure to disable expansion. */
571 for (unsigned i
= 0; i
< fb
->nr_cbufs
; i
++) {
572 struct si_texture
*tex
;
574 /* If not clearing this buffer, skip. */
575 if (!(buffers
& (PIPE_CLEAR_COLOR0
<< i
)) || !fb
->cbufs
[i
])
578 tex
= (struct si_texture
*)fb
->cbufs
[i
]->texture
;
579 if (tex
->surface
.fmask_size
== 0)
580 tex
->dirty_level_mask
&= ~(1 << fb
->cbufs
[i
]->u
.tex
.level
);
585 si_htile_enabled(zstex
, zsbuf
->u
.tex
.level
) &&
586 zsbuf
->u
.tex
.first_layer
== 0 &&
587 zsbuf
->u
.tex
.last_layer
== util_max_layer(&zstex
->buffer
.b
.b
, 0)) {
588 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
589 if (buffers
& PIPE_CLEAR_DEPTH
&&
590 (!zstex
->tc_compatible_htile
||
591 depth
== 0 || depth
== 1)) {
592 /* Need to disable EXPCLEAR temporarily if clearing
594 if (!zstex
->depth_cleared
|| zstex
->depth_clear_value
!= depth
) {
595 sctx
->db_depth_disable_expclear
= true;
598 if (zstex
->depth_clear_value
!= (float)depth
) {
599 /* Update DB_DEPTH_CLEAR. */
600 zstex
->depth_clear_value
= depth
;
601 sctx
->framebuffer
.dirty_zsbuf
= true;
602 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
604 sctx
->db_depth_clear
= true;
605 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
608 /* TC-compatible HTILE only supports stencil clears to 0. */
609 if (buffers
& PIPE_CLEAR_STENCIL
&&
610 (!zstex
->tc_compatible_htile
|| stencil
== 0)) {
613 /* Need to disable EXPCLEAR temporarily if clearing
615 if (!zstex
->stencil_cleared
|| zstex
->stencil_clear_value
!= stencil
) {
616 sctx
->db_stencil_disable_expclear
= true;
619 if (zstex
->stencil_clear_value
!= (uint8_t)stencil
) {
620 /* Update DB_STENCIL_CLEAR. */
621 zstex
->stencil_clear_value
= stencil
;
622 sctx
->framebuffer
.dirty_zsbuf
= true;
623 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
625 sctx
->db_stencil_clear
= true;
626 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
629 /* TODO: Find out what's wrong here. Fast depth clear leads to
630 * corruption in ARK: Survival Evolved, but that may just be
631 * a coincidence and the root cause is elsewhere.
633 * The corruption can be fixed by putting the DB flush before
634 * or after the depth clear. (surprisingly)
636 * https://bugs.freedesktop.org/show_bug.cgi?id=102955 (apitrace)
638 * This hack decreases back-to-back ClearDepth performance.
640 if ((sctx
->db_depth_clear
|| sctx
->db_stencil_clear
) &&
641 sctx
->screen
->options
.clear_db_cache_before_clear
)
642 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB
;
645 si_blitter_begin(sctx
, SI_CLEAR
);
646 util_blitter_clear(sctx
->blitter
, fb
->width
, fb
->height
,
647 util_framebuffer_get_num_layers(fb
),
648 buffers
, color
, depth
, stencil
);
649 si_blitter_end(sctx
);
651 if (sctx
->db_depth_clear
) {
652 sctx
->db_depth_clear
= false;
653 sctx
->db_depth_disable_expclear
= false;
654 zstex
->depth_cleared
= true;
655 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
658 if (sctx
->db_stencil_clear
) {
659 sctx
->db_stencil_clear
= false;
660 sctx
->db_stencil_disable_expclear
= false;
661 zstex
->stencil_cleared
= true;
662 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
666 static void si_clear_render_target(struct pipe_context
*ctx
,
667 struct pipe_surface
*dst
,
668 const union pipe_color_union
*color
,
669 unsigned dstx
, unsigned dsty
,
670 unsigned width
, unsigned height
,
671 bool render_condition_enabled
)
673 struct si_context
*sctx
= (struct si_context
*)ctx
;
674 struct si_texture
*sdst
= (struct si_texture
*)dst
->texture
;
676 if (dst
->texture
->nr_samples
<= 1 && !sdst
->dcc_offset
) {
677 si_compute_clear_render_target(ctx
, dst
, color
, dstx
, dsty
, width
,
678 height
, render_condition_enabled
);
682 si_blitter_begin(sctx
, SI_CLEAR_SURFACE
|
683 (render_condition_enabled
? 0 : SI_DISABLE_RENDER_COND
));
684 util_blitter_clear_render_target(sctx
->blitter
, dst
, color
,
685 dstx
, dsty
, width
, height
);
686 si_blitter_end(sctx
);
689 static void si_clear_depth_stencil(struct pipe_context
*ctx
,
690 struct pipe_surface
*dst
,
691 unsigned clear_flags
,
694 unsigned dstx
, unsigned dsty
,
695 unsigned width
, unsigned height
,
696 bool render_condition_enabled
)
698 struct si_context
*sctx
= (struct si_context
*)ctx
;
700 si_blitter_begin(sctx
, SI_CLEAR_SURFACE
|
701 (render_condition_enabled
? 0 : SI_DISABLE_RENDER_COND
));
702 util_blitter_clear_depth_stencil(sctx
->blitter
, dst
, clear_flags
, depth
, stencil
,
703 dstx
, dsty
, width
, height
);
704 si_blitter_end(sctx
);
707 static void si_clear_texture(struct pipe_context
*pipe
,
708 struct pipe_resource
*tex
,
710 const struct pipe_box
*box
,
713 struct pipe_screen
*screen
= pipe
->screen
;
714 struct si_texture
*stex
= (struct si_texture
*)tex
;
715 struct pipe_surface tmpl
= {{0}};
716 struct pipe_surface
*sf
;
717 const struct util_format_description
*desc
=
718 util_format_description(tex
->format
);
720 tmpl
.format
= tex
->format
;
721 tmpl
.u
.tex
.first_layer
= box
->z
;
722 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
723 tmpl
.u
.tex
.level
= level
;
724 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
728 if (stex
->is_depth
) {
733 /* Depth is always present. */
734 clear
= PIPE_CLEAR_DEPTH
;
735 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
737 if (stex
->surface
.has_stencil
) {
738 clear
|= PIPE_CLEAR_STENCIL
;
739 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
742 si_clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
744 box
->width
, box
->height
, false);
746 union pipe_color_union color
;
748 /* pipe_color_union requires the full vec4 representation. */
749 if (util_format_is_pure_uint(tex
->format
))
750 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
751 else if (util_format_is_pure_sint(tex
->format
))
752 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
754 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
756 if (screen
->is_format_supported(screen
, tex
->format
,
758 PIPE_BIND_RENDER_TARGET
)) {
759 si_clear_render_target(pipe
, sf
, &color
,
761 box
->width
, box
->height
, false);
763 /* Software fallback - just for R9G9B9E5_FLOAT */
764 util_clear_render_target(pipe
, sf
, &color
,
766 box
->width
, box
->height
);
769 pipe_surface_reference(&sf
, NULL
);
772 void si_init_clear_functions(struct si_context
*sctx
)
774 sctx
->b
.clear_render_target
= si_clear_render_target
;
775 sctx
->b
.clear_texture
= si_clear_texture
;
777 if (sctx
->has_graphics
) {
778 sctx
->b
.clear
= si_clear
;
779 sctx
->b
.clear_depth_stencil
= si_clear_depth_stencil
;