src/gallium/drivers/radeonsi/si_compute.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "util/u_memory.h"
  26 #include "radeon/r600_pipe_common.h"
  27 #include "radeon/radeon_elf_util.h"
  28 #include "radeon/radeon_llvm_util.h"
  29
  30 #include "radeon/r600_cs.h"
  31 #include "si_pipe.h"
  32 #include "si_shader.h"
  33 #include "sid.h"
  34
  35 #define MAX_GLOBAL_BUFFERS 20
  36
  37 struct si_compute {
  38         struct si_context *ctx;
  39
  40         unsigned local_size;
  41         unsigned private_size;
  42         unsigned input_size;
  43         struct si_shader shader;
  44         unsigned num_user_sgprs;
  45
  46         struct r600_resource *input_buffer;
  47         struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
  48
  49 #if HAVE_LLVM < 0x0306
  50         unsigned num_kernels;
  51         struct si_shader *kernels;
  52         LLVMContextRef llvm_ctx;
  53 #endif
  54 };
  55
  56 static void init_scratch_buffer(struct si_context *sctx, struct si_compute *program)
  57 {
  58         unsigned scratch_bytes = 0;
  59         uint64_t scratch_buffer_va;
  60         unsigned i;
  61
  62         /* Compute the scratch buffer size using the maximum number of waves.
  63          * This way we don't need to recompute it for each kernel launch. */
  64         unsigned scratch_waves = 32 * sctx->screen->b.info.max_compute_units;
  65         for (i = 0; i < program->shader.binary.global_symbol_count; i++) {
  66                 unsigned offset =
  67                                 program->shader.binary.global_symbol_offsets[i];
  68                 unsigned scratch_bytes_needed;
  69
  70                 si_shader_binary_read_config(sctx->screen,
  71                                                 &program->shader, offset);
  72                 scratch_bytes_needed = program->shader.scratch_bytes_per_wave;
  73                 scratch_bytes = MAX2(scratch_bytes, scratch_bytes_needed);
  74         }
  75
  76         if (scratch_bytes == 0)
  77                 return;
  78
  79         program->shader.scratch_bo =
  80                                 si_resource_create_custom(sctx->b.b.screen,
  81                                 PIPE_USAGE_DEFAULT,
  82                                 scratch_bytes * scratch_waves);
  83
  84         scratch_buffer_va = program->shader.scratch_bo->gpu_address;
  85
  86         /* apply_scratch_relocs needs scratch_bytes_per_wave to be set
  87          * to the maximum bytes needed, so it can compute the stride
  88          * correctly.
  89          */
  90         program->shader.scratch_bytes_per_wave = scratch_bytes;
  91
  92         /* Patch the shader with the scratch buffer address. */
  93         si_shader_apply_scratch_relocs(sctx,
  94                                 &program->shader, scratch_buffer_va);
  95 }
  96
  97 static void *si_create_compute_state(
  98         struct pipe_context *ctx,
  99         const struct pipe_compute_state *cso)
 100 {
 101         struct si_context *sctx = (struct si_context *)ctx;
 102         struct si_compute *program = CALLOC_STRUCT(si_compute);
 103         const struct pipe_llvm_program_header *header;
 104         const char *code;
 105
 106         header = cso->prog;
 107         code = cso->prog + sizeof(struct pipe_llvm_program_header);
 108
 109         program->ctx = sctx;
 110         program->local_size = cso->req_local_mem;
 111         program->private_size = cso->req_private_mem;
 112         program->input_size = cso->req_input_mem;
 113
 114 #if HAVE_LLVM < 0x0306
 115         {
 116                 unsigned i;
 117                 program->llvm_ctx = LLVMContextCreate();
 118                 program->num_kernels = radeon_llvm_get_num_kernels(program->llvm_ctx,
 119                                         code, header->num_bytes);
 120                 program->kernels = CALLOC(sizeof(struct si_shader),
 121                                                         program->num_kernels);
 122                 for (i = 0; i < program->num_kernels; i++) {
 123                         LLVMModuleRef mod = radeon_llvm_get_kernel_module(program->llvm_ctx, i,
 124                                                         code, header->num_bytes);
 125                         si_compile_llvm(sctx->screen, &program->kernels[i], sctx->tm,
 126                                         mod, &sctx->b.debug, TGSI_PROCESSOR_COMPUTE);
 127                         LLVMDisposeModule(mod);
 128                 }
 129         }
 130 #else
 131
 132         radeon_elf_read(code, header->num_bytes, &program->shader.binary);
 133
 134         /* init_scratch_buffer patches the shader code with the scratch address,
 135          * so we need to call it before si_shader_binary_read() which uploads
 136          * the shader code to the GPU.
 137          */
 138         init_scratch_buffer(sctx, program);
 139         si_shader_binary_read(sctx->screen, &program->shader, &sctx->b.debug,
 140                               TGSI_PROCESSOR_COMPUTE);
 141         si_shader_binary_upload(sctx->screen, &program->shader);
 142
 143 #endif
 144         program->input_buffer = si_resource_create_custom(sctx->b.b.screen,
 145                 PIPE_USAGE_IMMUTABLE, program->input_size);
 146
 147         return program;
 148 }
 149
 150 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
 151 {
 152         struct si_context *sctx = (struct si_context*)ctx;
 153         sctx->cs_shader_state.program = (struct si_compute*)state;
 154 }
 155
 156 static void si_set_global_binding(
 157         struct pipe_context *ctx, unsigned first, unsigned n,
 158         struct pipe_resource **resources,
 159         uint32_t **handles)
 160 {
 161         unsigned i;
 162         struct si_context *sctx = (struct si_context*)ctx;
 163         struct si_compute *program = sctx->cs_shader_state.program;
 164
 165         if (!resources) {
 166                 for (i = first; i < first + n; i++) {
 167                         pipe_resource_reference(&program->global_buffers[i], NULL);
 168                 }
 169                 return;
 170         }
 171
 172         for (i = first; i < first + n; i++) {
 173                 uint64_t va;
 174                 uint32_t offset;
 175                 pipe_resource_reference(&program->global_buffers[i], resources[i]);
 176                 va = r600_resource(resources[i])->gpu_address;
 177                 offset = util_le32_to_cpu(*handles[i]);
 178                 va += offset;
 179                 va = util_cpu_to_le64(va);
 180                 memcpy(handles[i], &va, sizeof(va));
 181         }
 182 }
 183
 184 /**
 185  * This function computes the value for R_00B860_COMPUTE_TMPRING_SIZE.WAVES
 186  * /p block_layout is the number of threads in each work group.
 187  * /p grid layout is the number of work groups.
 188  */
 189 static unsigned compute_num_waves_for_scratch(
 190                 const struct radeon_info *info,
 191                 const uint *block_layout,
 192                 const uint *grid_layout)
 193 {
 194         unsigned num_sh = MAX2(info->max_sh_per_se, 1);
 195         unsigned num_se = MAX2(info->max_se, 1);
 196         unsigned num_blocks = 1;
 197         unsigned threads_per_block = 1;
 198         unsigned waves_per_block;
 199         unsigned waves_per_sh;
 200         unsigned waves;
 201         unsigned scratch_waves;
 202         unsigned i;
 203
 204         for (i = 0; i < 3; i++) {
 205                 threads_per_block *= block_layout[i];
 206                 num_blocks *= grid_layout[i];
 207         }
 208
 209         waves_per_block = align(threads_per_block, 64) / 64;
 210         waves = waves_per_block * num_blocks;
 211         waves_per_sh = align(waves, num_sh * num_se) / (num_sh * num_se);
 212         scratch_waves = waves_per_sh * num_sh * num_se;
 213
 214         if (waves_per_block > waves_per_sh) {
 215                 scratch_waves = waves_per_block * num_sh * num_se;
 216         }
 217
 218         return scratch_waves;
 219 }
 220
 221 static void si_launch_grid(
 222                 struct pipe_context *ctx,
 223                 const uint *block_layout, const uint *grid_layout,
 224                 uint32_t pc, const void *input)
 225 {
 226         struct si_context *sctx = (struct si_context*)ctx;
 227         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 228         struct si_compute *program = sctx->cs_shader_state.program;
 229         struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
 230         struct r600_resource *input_buffer = program->input_buffer;
 231         unsigned kernel_args_size;
 232         unsigned num_work_size_bytes = 36;
 233         uint32_t kernel_args_offset = 0;
 234         uint32_t *kernel_args;
 235         uint64_t kernel_args_va;
 236         uint64_t scratch_buffer_va = 0;
 237         uint64_t shader_va;
 238         unsigned i;
 239         struct si_shader *shader = &program->shader;
 240         unsigned lds_blocks;
 241         unsigned num_waves_for_scratch;
 242
 243 #if HAVE_LLVM < 0x0306
 244         shader = &program->kernels[pc];
 245 #endif
 246
 247
 248         radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0) | PKT3_SHADER_TYPE_S(1));
 249         radeon_emit(cs, 0x80000000);
 250         radeon_emit(cs, 0x80000000);
 251
 252         sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
 253                          SI_CONTEXT_INV_GLOBAL_L2 |
 254                          SI_CONTEXT_INV_ICACHE |
 255                          SI_CONTEXT_INV_SMEM_L1 |
 256                          SI_CONTEXT_FLUSH_WITH_INV_L2 |
 257                          SI_CONTEXT_FLAG_COMPUTE;
 258         si_emit_cache_flush(sctx, NULL);
 259
 260         pm4->compute_pkt = true;
 261
 262 #if HAVE_LLVM >= 0x0306
 263         /* Read the config information */
 264         si_shader_binary_read_config(sctx->screen, shader, pc);
 265 #endif
 266
 267         /* Upload the kernel arguments */
 268
 269         /* The extra num_work_size_bytes are for work group / work item size information */
 270         kernel_args_size = program->input_size + num_work_size_bytes + 8 /* For scratch va */;
 271
 272         kernel_args = sctx->b.ws->buffer_map(input_buffer->buf,
 273                         sctx->b.gfx.cs, PIPE_TRANSFER_WRITE);
 274         for (i = 0; i < 3; i++) {
 275                 kernel_args[i] = grid_layout[i];
 276                 kernel_args[i + 3] = grid_layout[i] * block_layout[i];
 277                 kernel_args[i + 6] = block_layout[i];
 278         }
 279
 280         num_waves_for_scratch = compute_num_waves_for_scratch(
 281                 &sctx->screen->b.info, block_layout, grid_layout);
 282
 283         memcpy(kernel_args + (num_work_size_bytes / 4), input, program->input_size);
 284
 285         if (shader->scratch_bytes_per_wave > 0) {
 286
 287                 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
 288                             "Total Scratch: %u bytes\n", num_waves_for_scratch,
 289                             shader->scratch_bytes_per_wave,
 290                             shader->scratch_bytes_per_wave *
 291                             num_waves_for_scratch);
 292
 293                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 294                                           shader->scratch_bo,
 295                                           RADEON_USAGE_READWRITE,
 296                                           RADEON_PRIO_SCRATCH_BUFFER);
 297
 298                 scratch_buffer_va = shader->scratch_bo->gpu_address;
 299         }
 300
 301         for (i = 0; i < (kernel_args_size / 4); i++) {
 302                 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
 303                         kernel_args[i]);
 304         }
 305
 306         kernel_args_va = input_buffer->gpu_address;
 307         kernel_args_va += kernel_args_offset;
 308
 309         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, input_buffer,
 310                                   RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
 311
 312         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0, kernel_args_va);
 313         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 4, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) | S_008F04_STRIDE(0));
 314         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 8, scratch_buffer_va);
 315         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 12,
 316                 S_008F04_BASE_ADDRESS_HI(scratch_buffer_va >> 32)
 317                 |  S_008F04_STRIDE(shader->scratch_bytes_per_wave / 64));
 318
 319         si_pm4_set_reg(pm4, R_00B810_COMPUTE_START_X, 0);
 320         si_pm4_set_reg(pm4, R_00B814_COMPUTE_START_Y, 0);
 321         si_pm4_set_reg(pm4, R_00B818_COMPUTE_START_Z, 0);
 322
 323         si_pm4_set_reg(pm4, R_00B81C_COMPUTE_NUM_THREAD_X,
 324                                 S_00B81C_NUM_THREAD_FULL(block_layout[0]));
 325         si_pm4_set_reg(pm4, R_00B820_COMPUTE_NUM_THREAD_Y,
 326                                 S_00B820_NUM_THREAD_FULL(block_layout[1]));
 327         si_pm4_set_reg(pm4, R_00B824_COMPUTE_NUM_THREAD_Z,
 328                                 S_00B824_NUM_THREAD_FULL(block_layout[2]));
 329
 330         /* Global buffers */
 331         for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
 332                 struct r600_resource *buffer =
 333                                 (struct r600_resource*)program->global_buffers[i];
 334                 if (!buffer) {
 335                         continue;
 336                 }
 337                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
 338                                           RADEON_USAGE_READWRITE,
 339                                           RADEON_PRIO_COMPUTE_GLOBAL);
 340         }
 341
 342         /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
 343          * and is now per pipe, so it should be handled in the
 344          * kernel if we want to use something other than the default value,
 345          * which is now 0x22f.
 346          */
 347         if (sctx->b.chip_class <= SI) {
 348                 /* XXX: This should be:
 349                  * (number of compute units) * 4 * (waves per simd) - 1 */
 350
 351                 si_pm4_set_reg(pm4, R_00B82C_COMPUTE_MAX_WAVE_ID,
 352                                                 0x190 /* Default value */);
 353         }
 354
 355         shader_va = shader->bo->gpu_address;
 356
 357 #if HAVE_LLVM >= 0x0306
 358         shader_va += pc;
 359 #endif
 360         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
 361                                   RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
 362         si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
 363         si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40);
 364
 365         si_pm4_set_reg(pm4, R_00B848_COMPUTE_PGM_RSRC1, shader->rsrc1);
 366
 367         lds_blocks = shader->lds_size;
 368         /* XXX: We are over allocating LDS.  For SI, the shader reports LDS in
 369          * blocks of 256 bytes, so if there are 4 bytes lds allocated in
 370          * the shader and 4 bytes allocated by the state tracker, then
 371          * we will set LDS_SIZE to 512 bytes rather than 256.
 372          */
 373         if (sctx->b.chip_class <= SI) {
 374                 lds_blocks += align(program->local_size, 256) >> 8;
 375         } else {
 376                 lds_blocks += align(program->local_size, 512) >> 9;
 377         }
 378
 379         assert(lds_blocks <= 0xFF);
 380
 381         shader->rsrc2 &= C_00B84C_LDS_SIZE;
 382         shader->rsrc2 |=  S_00B84C_LDS_SIZE(lds_blocks);
 383
 384         si_pm4_set_reg(pm4, R_00B84C_COMPUTE_PGM_RSRC2, shader->rsrc2);
 385         si_pm4_set_reg(pm4, R_00B854_COMPUTE_RESOURCE_LIMITS, 0);
 386
 387         si_pm4_set_reg(pm4, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0,
 388                 S_00B858_SH0_CU_EN(0xffff /* Default value */)
 389                 | S_00B858_SH1_CU_EN(0xffff /* Default value */))
 390                 ;
 391
 392         si_pm4_set_reg(pm4, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1,
 393                 S_00B85C_SH0_CU_EN(0xffff /* Default value */)
 394                 | S_00B85C_SH1_CU_EN(0xffff /* Default value */))
 395                 ;
 396
 397         num_waves_for_scratch =
 398                 MIN2(num_waves_for_scratch,
 399                      32 * sctx->screen->b.info.max_compute_units);
 400         si_pm4_set_reg(pm4, R_00B860_COMPUTE_TMPRING_SIZE,
 401                 /* The maximum value for WAVES is 32 * num CU.
 402                  * If you program this value incorrectly, the GPU will hang if
 403                  * COMPUTE_PGM_RSRC2.SCRATCH_EN is enabled.
 404                  */
 405                 S_00B860_WAVES(num_waves_for_scratch)
 406                 | S_00B860_WAVESIZE(shader->scratch_bytes_per_wave >> 10))
 407                 ;
 408
 409         si_pm4_cmd_begin(pm4, PKT3_DISPATCH_DIRECT);
 410         si_pm4_cmd_add(pm4, grid_layout[0]); /* Thread groups DIM_X */
 411         si_pm4_cmd_add(pm4, grid_layout[1]); /* Thread groups DIM_Y */
 412         si_pm4_cmd_add(pm4, grid_layout[2]); /* Thread gropus DIM_Z */
 413         si_pm4_cmd_add(pm4, 1); /* DISPATCH_INITIATOR */
 414         si_pm4_cmd_end(pm4, false);
 415
 416         si_pm4_emit(sctx, pm4);
 417
 418 #if 0
 419         fprintf(stderr, "cdw: %i\n", sctx->cs->cdw);
 420         for (i = 0; i < sctx->cs->cdw; i++) {
 421                 fprintf(stderr, "%4i : 0x%08X\n", i, sctx->cs->buf[i]);
 422         }
 423 #endif
 424
 425         si_pm4_free_state(sctx, pm4, ~0);
 426
 427         sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
 428                          SI_CONTEXT_INV_VMEM_L1 |
 429                          SI_CONTEXT_INV_GLOBAL_L2 |
 430                          SI_CONTEXT_INV_ICACHE |
 431                          SI_CONTEXT_INV_SMEM_L1 |
 432                          SI_CONTEXT_FLAG_COMPUTE;
 433         si_emit_cache_flush(sctx, NULL);
 434 }
 435
 436
 437 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
 438         struct si_compute *program = (struct si_compute *)state;
 439
 440         if (!state) {
 441                 return;
 442         }
 443
 444 #if HAVE_LLVM < 0x0306
 445         if (program->kernels) {
 446                 for (int i = 0; i < program->num_kernels; i++){
 447                         if (program->kernels[i].bo){
 448                                 si_shader_destroy(&program->kernels[i]);
 449                         }
 450                 }
 451                 FREE(program->kernels);
 452         }
 453
 454         if (program->llvm_ctx){
 455                 LLVMContextDispose(program->llvm_ctx);
 456         }
 457 #else
 458         FREE(program->shader.binary.config);
 459         FREE(program->shader.binary.rodata);
 460         FREE(program->shader.binary.global_symbol_offsets);
 461         si_shader_destroy(&program->shader);
 462 #endif
 463
 464         pipe_resource_reference(
 465                 (struct pipe_resource **)&program->input_buffer, NULL);
 466
 467         FREE(program);
 468 }
 469
 470 static void si_set_compute_resources(struct pipe_context * ctx_,
 471                 unsigned start, unsigned count,
 472                 struct pipe_surface ** surfaces) { }
 473
 474 void si_init_compute_functions(struct si_context *sctx)
 475 {
 476         sctx->b.b.create_compute_state = si_create_compute_state;
 477         sctx->b.b.delete_compute_state = si_delete_compute_state;
 478         sctx->b.b.bind_compute_state = si_bind_compute_state;
 479 /*       ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
 480         sctx->b.b.set_compute_resources = si_set_compute_resources;
 481         sctx->b.b.set_global_binding = si_set_global_binding;
 482         sctx->b.b.launch_grid = si_launch_grid;
 483 }