2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "tgsi/tgsi_parse.h"
26 #include "util/u_memory.h"
27 #include "util/u_upload_mgr.h"
29 #include "amd_kernel_code_t.h"
30 #include "radeon/r600_cs.h"
32 #include "si_compute.h"
35 struct dispatch_packet
{
38 uint16_t workgroup_size_x
;
39 uint16_t workgroup_size_y
;
40 uint16_t workgroup_size_z
;
45 uint32_t private_segment_size
;
46 uint32_t group_segment_size
;
47 uint64_t kernel_object
;
48 uint64_t kernarg_address
;
52 static const amd_kernel_code_t
*si_compute_get_code_object(
53 const struct si_compute
*program
,
54 uint64_t symbol_offset
)
56 if (!program
->use_code_object_v2
) {
59 return (const amd_kernel_code_t
*)
60 (program
->shader
.binary
.code
+ symbol_offset
);
63 static void code_object_to_config(const amd_kernel_code_t
*code_object
,
64 struct si_shader_config
*out_config
) {
66 uint32_t rsrc1
= code_object
->compute_pgm_resource_registers
;
67 uint32_t rsrc2
= code_object
->compute_pgm_resource_registers
>> 32;
68 out_config
->num_sgprs
= code_object
->wavefront_sgpr_count
;
69 out_config
->num_vgprs
= code_object
->workitem_vgpr_count
;
70 out_config
->float_mode
= G_00B028_FLOAT_MODE(rsrc1
);
71 out_config
->rsrc1
= rsrc1
;
72 out_config
->lds_size
= MAX2(out_config
->lds_size
, G_00B84C_LDS_SIZE(rsrc2
));
73 out_config
->rsrc2
= rsrc2
;
74 out_config
->scratch_bytes_per_wave
=
75 align(code_object
->workitem_private_segment_byte_size
* 64, 1024);
78 /* Asynchronous compute shader compilation. */
79 static void si_create_compute_state_async(void *job
, int thread_index
)
81 struct si_compute
*program
= (struct si_compute
*)job
;
82 struct si_shader
*shader
= &program
->shader
;
83 struct si_shader_selector sel
;
84 LLVMTargetMachineRef tm
;
85 struct pipe_debug_callback
*debug
= &program
->compiler_ctx_state
.debug
;
87 if (thread_index
>= 0) {
88 assert(thread_index
< ARRAY_SIZE(program
->screen
->tm
));
89 tm
= program
->screen
->tm
[thread_index
];
93 tm
= program
->compiler_ctx_state
.tm
;
96 memset(&sel
, 0, sizeof(sel
));
98 sel
.screen
= program
->screen
;
99 tgsi_scan_shader(program
->tokens
, &sel
.info
);
100 sel
.tokens
= program
->tokens
;
101 sel
.type
= PIPE_SHADER_COMPUTE
;
102 sel
.local_size
= program
->local_size
;
103 si_get_active_slot_masks(&sel
.info
,
104 &program
->active_const_and_shader_buffers
,
105 &program
->active_samplers_and_images
);
107 program
->shader
.selector
= &sel
;
108 program
->shader
.is_monolithic
= true;
109 program
->uses_grid_size
= sel
.info
.uses_grid_size
;
110 program
->uses_block_size
= sel
.info
.uses_block_size
;
111 program
->uses_bindless_samplers
= sel
.info
.uses_bindless_samplers
;
112 program
->uses_bindless_images
= sel
.info
.uses_bindless_images
;
114 if (si_shader_create(program
->screen
, tm
, &program
->shader
, debug
)) {
115 program
->shader
.compilation_failed
= true;
117 bool scratch_enabled
= shader
->config
.scratch_bytes_per_wave
> 0;
118 unsigned user_sgprs
= SI_NUM_RESOURCE_SGPRS
+
119 (sel
.info
.uses_grid_size
? 3 : 0) +
120 (sel
.info
.uses_block_size
? 3 : 0);
122 shader
->config
.rsrc1
=
123 S_00B848_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
124 S_00B848_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
125 S_00B848_DX10_CLAMP(1) |
126 S_00B848_FLOAT_MODE(shader
->config
.float_mode
);
128 shader
->config
.rsrc2
=
129 S_00B84C_USER_SGPR(user_sgprs
) |
130 S_00B84C_SCRATCH_EN(scratch_enabled
) |
131 S_00B84C_TGID_X_EN(sel
.info
.uses_block_id
[0]) |
132 S_00B84C_TGID_Y_EN(sel
.info
.uses_block_id
[1]) |
133 S_00B84C_TGID_Z_EN(sel
.info
.uses_block_id
[2]) |
134 S_00B84C_TIDIG_COMP_CNT(sel
.info
.uses_thread_id
[2] ? 2 :
135 sel
.info
.uses_thread_id
[1] ? 1 : 0) |
136 S_00B84C_LDS_SIZE(shader
->config
.lds_size
);
138 program
->variable_group_size
=
139 sel
.info
.properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] == 0;
142 FREE(program
->tokens
);
143 program
->shader
.selector
= NULL
;
146 static void *si_create_compute_state(
147 struct pipe_context
*ctx
,
148 const struct pipe_compute_state
*cso
)
150 struct si_context
*sctx
= (struct si_context
*)ctx
;
151 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
152 struct si_compute
*program
= CALLOC_STRUCT(si_compute
);
154 program
->screen
= (struct si_screen
*)ctx
->screen
;
155 program
->ir_type
= cso
->ir_type
;
156 program
->local_size
= cso
->req_local_mem
;
157 program
->private_size
= cso
->req_private_mem
;
158 program
->input_size
= cso
->req_input_mem
;
159 program
->use_code_object_v2
= HAVE_LLVM
>= 0x0400 &&
160 cso
->ir_type
== PIPE_SHADER_IR_NATIVE
;
162 if (cso
->ir_type
== PIPE_SHADER_IR_TGSI
) {
163 program
->tokens
= tgsi_dup_tokens(cso
->prog
);
164 if (!program
->tokens
) {
169 program
->compiler_ctx_state
.tm
= sctx
->tm
;
170 program
->compiler_ctx_state
.debug
= sctx
->b
.debug
;
171 program
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
172 p_atomic_inc(&sscreen
->b
.num_shaders_created
);
173 util_queue_fence_init(&program
->ready
);
175 if ((sctx
->b
.debug
.debug_message
&& !sctx
->b
.debug
.async
) ||
177 r600_can_dump_shader(&sscreen
->b
, PIPE_SHADER_COMPUTE
))
178 si_create_compute_state_async(program
, -1);
180 util_queue_add_job(&sscreen
->shader_compiler_queue
,
181 program
, &program
->ready
,
182 si_create_compute_state_async
, NULL
);
184 const struct pipe_llvm_program_header
*header
;
187 code
= cso
->prog
+ sizeof(struct pipe_llvm_program_header
);
189 ac_elf_read(code
, header
->num_bytes
, &program
->shader
.binary
);
190 if (program
->use_code_object_v2
) {
191 const amd_kernel_code_t
*code_object
=
192 si_compute_get_code_object(program
, 0);
193 code_object_to_config(code_object
, &program
->shader
.config
);
195 si_shader_binary_read_config(&program
->shader
.binary
,
196 &program
->shader
.config
, 0);
198 si_shader_dump(sctx
->screen
, &program
->shader
, &sctx
->b
.debug
,
199 PIPE_SHADER_COMPUTE
, stderr
, true);
200 if (si_shader_binary_upload(sctx
->screen
, &program
->shader
) < 0) {
201 fprintf(stderr
, "LLVM failed to upload shader\n");
210 static void si_bind_compute_state(struct pipe_context
*ctx
, void *state
)
212 struct si_context
*sctx
= (struct si_context
*)ctx
;
213 struct si_compute
*program
= (struct si_compute
*)state
;
215 sctx
->cs_shader_state
.program
= program
;
219 /* Wait because we need active slot usage masks. */
220 if (program
->ir_type
== PIPE_SHADER_IR_TGSI
)
221 util_queue_fence_wait(&program
->ready
);
223 si_set_active_descriptors(sctx
,
224 SI_DESCS_FIRST_COMPUTE
+
225 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
,
226 program
->active_const_and_shader_buffers
);
227 si_set_active_descriptors(sctx
,
228 SI_DESCS_FIRST_COMPUTE
+
229 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
,
230 program
->active_samplers_and_images
);
233 static void si_set_global_binding(
234 struct pipe_context
*ctx
, unsigned first
, unsigned n
,
235 struct pipe_resource
**resources
,
239 struct si_context
*sctx
= (struct si_context
*)ctx
;
240 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
242 assert(first
+ n
<= MAX_GLOBAL_BUFFERS
);
245 for (i
= 0; i
< n
; i
++) {
246 pipe_resource_reference(&program
->global_buffers
[first
+ i
], NULL
);
251 for (i
= 0; i
< n
; i
++) {
254 pipe_resource_reference(&program
->global_buffers
[first
+ i
], resources
[i
]);
255 va
= r600_resource(resources
[i
])->gpu_address
;
256 offset
= util_le32_to_cpu(*handles
[i
]);
258 va
= util_cpu_to_le64(va
);
259 memcpy(handles
[i
], &va
, sizeof(va
));
263 static void si_initialize_compute(struct si_context
*sctx
)
265 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
268 radeon_set_sh_reg_seq(cs
, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0
, 2);
269 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
270 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
271 radeon_emit(cs
, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
273 if (sctx
->b
.chip_class
>= CIK
) {
274 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
275 radeon_set_sh_reg_seq(cs
,
276 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2
, 2);
277 radeon_emit(cs
, S_00B864_SH0_CU_EN(0xffff) |
278 S_00B864_SH1_CU_EN(0xffff));
279 radeon_emit(cs
, S_00B868_SH0_CU_EN(0xffff) |
280 S_00B868_SH1_CU_EN(0xffff));
283 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
284 * and is now per pipe, so it should be handled in the
285 * kernel if we want to use something other than the default value,
286 * which is now 0x22f.
288 if (sctx
->b
.chip_class
<= SI
) {
289 /* XXX: This should be:
290 * (number of compute units) * 4 * (waves per simd) - 1 */
292 radeon_set_sh_reg(cs
, R_00B82C_COMPUTE_MAX_WAVE_ID
,
293 0x190 /* Default value */);
296 /* Set the pointer to border colors. */
297 bc_va
= sctx
->border_color_buffer
->gpu_address
;
299 if (sctx
->b
.chip_class
>= CIK
) {
300 radeon_set_uconfig_reg_seq(cs
, R_030E00_TA_CS_BC_BASE_ADDR
, 2);
301 radeon_emit(cs
, bc_va
>> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
302 radeon_emit(cs
, bc_va
>> 40); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
304 if (sctx
->screen
->b
.info
.drm_major
== 3 ||
305 (sctx
->screen
->b
.info
.drm_major
== 2 &&
306 sctx
->screen
->b
.info
.drm_minor
>= 48)) {
307 radeon_set_config_reg(cs
, R_00950C_TA_CS_BC_BASE_ADDR
,
312 sctx
->cs_shader_state
.emitted_program
= NULL
;
313 sctx
->cs_shader_state
.initialized
= true;
316 static bool si_setup_compute_scratch_buffer(struct si_context
*sctx
,
317 struct si_shader
*shader
,
318 struct si_shader_config
*config
)
320 uint64_t scratch_bo_size
, scratch_needed
;
322 scratch_needed
= config
->scratch_bytes_per_wave
* sctx
->scratch_waves
;
323 if (sctx
->compute_scratch_buffer
)
324 scratch_bo_size
= sctx
->compute_scratch_buffer
->b
.b
.width0
;
326 if (scratch_bo_size
< scratch_needed
) {
327 r600_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
329 sctx
->compute_scratch_buffer
= (struct r600_resource
*)
330 r600_aligned_buffer_create(&sctx
->screen
->b
.b
,
331 R600_RESOURCE_FLAG_UNMAPPABLE
,
333 scratch_needed
, 256);
335 if (!sctx
->compute_scratch_buffer
)
339 if (sctx
->compute_scratch_buffer
!= shader
->scratch_bo
&& scratch_needed
) {
340 uint64_t scratch_va
= sctx
->compute_scratch_buffer
->gpu_address
;
342 si_shader_apply_scratch_relocs(shader
, scratch_va
);
344 if (si_shader_binary_upload(sctx
->screen
, shader
))
347 r600_resource_reference(&shader
->scratch_bo
,
348 sctx
->compute_scratch_buffer
);
354 static bool si_switch_compute_shader(struct si_context
*sctx
,
355 struct si_compute
*program
,
356 struct si_shader
*shader
,
357 const amd_kernel_code_t
*code_object
,
360 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
361 struct si_shader_config inline_config
= {0};
362 struct si_shader_config
*config
;
365 if (sctx
->cs_shader_state
.emitted_program
== program
&&
366 sctx
->cs_shader_state
.offset
== offset
)
369 if (program
->ir_type
== PIPE_SHADER_IR_TGSI
) {
370 config
= &shader
->config
;
374 config
= &inline_config
;
376 code_object_to_config(code_object
, config
);
378 si_shader_binary_read_config(&shader
->binary
, config
, offset
);
381 lds_blocks
= config
->lds_size
;
382 /* XXX: We are over allocating LDS. For SI, the shader reports
383 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
384 * allocated in the shader and 4 bytes allocated by the state
385 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
387 if (sctx
->b
.chip_class
<= SI
) {
388 lds_blocks
+= align(program
->local_size
, 256) >> 8;
390 lds_blocks
+= align(program
->local_size
, 512) >> 9;
393 /* TODO: use si_multiwave_lds_size_workaround */
394 assert(lds_blocks
<= 0xFF);
396 config
->rsrc2
&= C_00B84C_LDS_SIZE
;
397 config
->rsrc2
|= S_00B84C_LDS_SIZE(lds_blocks
);
400 if (!si_setup_compute_scratch_buffer(sctx
, shader
, config
))
403 if (shader
->scratch_bo
) {
404 COMPUTE_DBG(sctx
->screen
, "Waves: %u; Scratch per wave: %u bytes; "
405 "Total Scratch: %u bytes\n", sctx
->scratch_waves
,
406 config
->scratch_bytes_per_wave
,
407 config
->scratch_bytes_per_wave
*
408 sctx
->scratch_waves
);
410 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
411 shader
->scratch_bo
, RADEON_USAGE_READWRITE
,
412 RADEON_PRIO_SCRATCH_BUFFER
);
415 /* Prefetch the compute shader to TC L2.
417 * We should also prefetch graphics shaders if a compute dispatch was
418 * the last command, and the compute shader if a draw call was the last
419 * command. However, that would add more complexity and we're likely
420 * to get a shader state change in that case anyway.
422 if (sctx
->b
.chip_class
>= CIK
) {
423 cik_prefetch_TC_L2_async(sctx
, &program
->shader
.bo
->b
.b
,
424 0, program
->shader
.bo
->b
.b
.width0
);
427 shader_va
= shader
->bo
->gpu_address
+ offset
;
428 if (program
->use_code_object_v2
) {
429 /* Shader code is placed after the amd_kernel_code_t
431 shader_va
+= sizeof(amd_kernel_code_t
);
434 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, shader
->bo
,
435 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
437 radeon_set_sh_reg_seq(cs
, R_00B830_COMPUTE_PGM_LO
, 2);
438 radeon_emit(cs
, shader_va
>> 8);
439 radeon_emit(cs
, shader_va
>> 40);
441 radeon_set_sh_reg_seq(cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
442 radeon_emit(cs
, config
->rsrc1
);
443 radeon_emit(cs
, config
->rsrc2
);
445 COMPUTE_DBG(sctx
->screen
, "COMPUTE_PGM_RSRC1: 0x%08x "
446 "COMPUTE_PGM_RSRC2: 0x%08x\n", config
->rsrc1
, config
->rsrc2
);
448 radeon_set_sh_reg(cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
449 S_00B860_WAVES(sctx
->scratch_waves
)
450 | S_00B860_WAVESIZE(config
->scratch_bytes_per_wave
>> 10));
452 sctx
->cs_shader_state
.emitted_program
= program
;
453 sctx
->cs_shader_state
.offset
= offset
;
454 sctx
->cs_shader_state
.uses_scratch
=
455 config
->scratch_bytes_per_wave
!= 0;
460 static void setup_scratch_rsrc_user_sgprs(struct si_context
*sctx
,
461 const amd_kernel_code_t
*code_object
,
464 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
465 uint64_t scratch_va
= sctx
->compute_scratch_buffer
->gpu_address
;
467 unsigned max_private_element_size
= AMD_HSA_BITS_GET(
468 code_object
->code_properties
,
469 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE
);
471 uint32_t scratch_dword0
= scratch_va
& 0xffffffff;
472 uint32_t scratch_dword1
=
473 S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
474 S_008F04_SWIZZLE_ENABLE(1);
476 /* Disable address clamping */
477 uint32_t scratch_dword2
= 0xffffffff;
478 uint32_t scratch_dword3
=
479 S_008F0C_INDEX_STRIDE(3) |
480 S_008F0C_ADD_TID_ENABLE(1);
482 if (sctx
->b
.chip_class
>= GFX9
) {
483 assert(max_private_element_size
== 1); /* always 4 bytes on GFX9 */
485 scratch_dword3
|= S_008F0C_ELEMENT_SIZE(max_private_element_size
);
487 if (sctx
->b
.chip_class
< VI
) {
488 /* BUF_DATA_FORMAT is ignored, but it cannot be
489 * BUF_DATA_FORMAT_INVALID. */
491 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8
);
495 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
497 radeon_emit(cs
, scratch_dword0
);
498 radeon_emit(cs
, scratch_dword1
);
499 radeon_emit(cs
, scratch_dword2
);
500 radeon_emit(cs
, scratch_dword3
);
503 static void si_setup_user_sgprs_co_v2(struct si_context
*sctx
,
504 const amd_kernel_code_t
*code_object
,
505 const struct pipe_grid_info
*info
,
506 uint64_t kernel_args_va
)
508 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
509 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
511 static const enum amd_code_property_mask_t workgroup_count_masks
[] = {
512 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X
,
513 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y
,
514 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
517 unsigned i
, user_sgpr
= 0;
518 if (AMD_HSA_BITS_GET(code_object
->code_properties
,
519 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER
)) {
520 if (code_object
->workitem_private_segment_byte_size
> 0) {
521 setup_scratch_rsrc_user_sgprs(sctx
, code_object
,
527 if (AMD_HSA_BITS_GET(code_object
->code_properties
,
528 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR
)) {
529 struct dispatch_packet dispatch
;
530 unsigned dispatch_offset
;
531 struct r600_resource
*dispatch_buf
= NULL
;
532 uint64_t dispatch_va
;
534 /* Upload dispatch ptr */
535 memset(&dispatch
, 0, sizeof(dispatch
));
537 dispatch
.workgroup_size_x
= info
->block
[0];
538 dispatch
.workgroup_size_y
= info
->block
[1];
539 dispatch
.workgroup_size_z
= info
->block
[2];
541 dispatch
.grid_size_x
= info
->grid
[0] * info
->block
[0];
542 dispatch
.grid_size_y
= info
->grid
[1] * info
->block
[1];
543 dispatch
.grid_size_z
= info
->grid
[2] * info
->block
[2];
545 dispatch
.private_segment_size
= program
->private_size
;
546 dispatch
.group_segment_size
= program
->local_size
;
548 dispatch
.kernarg_address
= kernel_args_va
;
550 u_upload_data(sctx
->b
.b
.const_uploader
, 0, sizeof(dispatch
),
551 256, &dispatch
, &dispatch_offset
,
552 (struct pipe_resource
**)&dispatch_buf
);
555 fprintf(stderr
, "Error: Failed to allocate dispatch "
558 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, dispatch_buf
,
559 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
);
561 dispatch_va
= dispatch_buf
->gpu_address
+ dispatch_offset
;
563 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
565 radeon_emit(cs
, dispatch_va
);
566 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(dispatch_va
>> 32) |
569 r600_resource_reference(&dispatch_buf
, NULL
);
573 if (AMD_HSA_BITS_GET(code_object
->code_properties
,
574 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR
)) {
575 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
577 radeon_emit(cs
, kernel_args_va
);
578 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI (kernel_args_va
>> 32) |
583 for (i
= 0; i
< 3 && user_sgpr
< 16; i
++) {
584 if (code_object
->code_properties
& workgroup_count_masks
[i
]) {
585 radeon_set_sh_reg_seq(cs
,
586 R_00B900_COMPUTE_USER_DATA_0
+
588 radeon_emit(cs
, info
->grid
[i
]);
594 static bool si_upload_compute_input(struct si_context
*sctx
,
595 const amd_kernel_code_t
*code_object
,
596 const struct pipe_grid_info
*info
)
598 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
599 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
600 struct r600_resource
*input_buffer
= NULL
;
601 unsigned kernel_args_size
;
602 unsigned num_work_size_bytes
= program
->use_code_object_v2
? 0 : 36;
603 uint32_t kernel_args_offset
= 0;
604 uint32_t *kernel_args
;
605 void *kernel_args_ptr
;
606 uint64_t kernel_args_va
;
609 /* The extra num_work_size_bytes are for work group / work item size information */
610 kernel_args_size
= program
->input_size
+ num_work_size_bytes
;
612 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, kernel_args_size
,
613 sctx
->screen
->b
.info
.tcc_cache_line_size
,
615 (struct pipe_resource
**)&input_buffer
, &kernel_args_ptr
);
617 if (unlikely(!kernel_args_ptr
))
620 kernel_args
= (uint32_t*)kernel_args_ptr
;
621 kernel_args_va
= input_buffer
->gpu_address
+ kernel_args_offset
;
624 for (i
= 0; i
< 3; i
++) {
625 kernel_args
[i
] = info
->grid
[i
];
626 kernel_args
[i
+ 3] = info
->grid
[i
] * info
->block
[i
];
627 kernel_args
[i
+ 6] = info
->block
[i
];
631 memcpy(kernel_args
+ (num_work_size_bytes
/ 4), info
->input
,
632 program
->input_size
);
635 for (i
= 0; i
< (kernel_args_size
/ 4); i
++) {
636 COMPUTE_DBG(sctx
->screen
, "input %u : %u\n", i
,
641 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, input_buffer
,
642 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
);
645 si_setup_user_sgprs_co_v2(sctx
, code_object
, info
, kernel_args_va
);
647 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
648 radeon_emit(cs
, kernel_args_va
);
649 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI (kernel_args_va
>> 32) |
653 r600_resource_reference(&input_buffer
, NULL
);
658 static void si_setup_tgsi_grid(struct si_context
*sctx
,
659 const struct pipe_grid_info
*info
)
661 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
662 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
663 unsigned grid_size_reg
= R_00B900_COMPUTE_USER_DATA_0
+
664 4 * SI_NUM_RESOURCE_SGPRS
;
665 unsigned block_size_reg
= grid_size_reg
+
666 /* 12 bytes = 3 dwords. */
667 12 * program
->uses_grid_size
;
669 if (info
->indirect
) {
670 if (program
->uses_grid_size
) {
671 uint64_t base_va
= r600_resource(info
->indirect
)->gpu_address
;
672 uint64_t va
= base_va
+ info
->indirect_offset
;
675 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
676 (struct r600_resource
*)info
->indirect
,
677 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
679 for (i
= 0; i
< 3; ++i
) {
680 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
681 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
682 COPY_DATA_DST_SEL(COPY_DATA_REG
));
683 radeon_emit(cs
, (va
+ 4 * i
));
684 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
685 radeon_emit(cs
, (grid_size_reg
>> 2) + i
);
690 if (program
->uses_grid_size
) {
691 radeon_set_sh_reg_seq(cs
, grid_size_reg
, 3);
692 radeon_emit(cs
, info
->grid
[0]);
693 radeon_emit(cs
, info
->grid
[1]);
694 radeon_emit(cs
, info
->grid
[2]);
696 if (program
->variable_group_size
&& program
->uses_block_size
) {
697 radeon_set_sh_reg_seq(cs
, block_size_reg
, 3);
698 radeon_emit(cs
, info
->block
[0]);
699 radeon_emit(cs
, info
->block
[1]);
700 radeon_emit(cs
, info
->block
[2]);
705 static void si_emit_dispatch_packets(struct si_context
*sctx
,
706 const struct pipe_grid_info
*info
)
708 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
709 bool render_cond_bit
= sctx
->b
.render_cond
&& !sctx
->b
.render_cond_force_off
;
710 unsigned waves_per_threadgroup
=
711 DIV_ROUND_UP(info
->block
[0] * info
->block
[1] * info
->block
[2], 64);
713 radeon_set_sh_reg(cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
714 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup
% 4 == 0));
716 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
717 radeon_emit(cs
, S_00B81C_NUM_THREAD_FULL(info
->block
[0]));
718 radeon_emit(cs
, S_00B820_NUM_THREAD_FULL(info
->block
[1]));
719 radeon_emit(cs
, S_00B824_NUM_THREAD_FULL(info
->block
[2]));
721 unsigned dispatch_initiator
=
722 S_00B800_COMPUTE_SHADER_EN(1) |
723 S_00B800_FORCE_START_AT_000(1) |
724 /* If the KMD allows it (there is a KMD hw register for it),
725 * allow launching waves out-of-order. (same as Vulkan) */
726 S_00B800_ORDER_MODE(sctx
->b
.chip_class
>= CIK
);
728 if (info
->indirect
) {
729 uint64_t base_va
= r600_resource(info
->indirect
)->gpu_address
;
731 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
732 (struct r600_resource
*)info
->indirect
,
733 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
735 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
736 PKT3_SHADER_TYPE_S(1));
738 radeon_emit(cs
, base_va
);
739 radeon_emit(cs
, base_va
>> 32);
741 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, render_cond_bit
) |
742 PKT3_SHADER_TYPE_S(1));
743 radeon_emit(cs
, info
->indirect_offset
);
744 radeon_emit(cs
, dispatch_initiator
);
746 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, render_cond_bit
) |
747 PKT3_SHADER_TYPE_S(1));
748 radeon_emit(cs
, info
->grid
[0]);
749 radeon_emit(cs
, info
->grid
[1]);
750 radeon_emit(cs
, info
->grid
[2]);
751 radeon_emit(cs
, dispatch_initiator
);
756 static void si_launch_grid(
757 struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
759 struct si_context
*sctx
= (struct si_context
*)ctx
;
760 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
761 const amd_kernel_code_t
*code_object
=
762 si_compute_get_code_object(program
, info
->pc
);
764 /* HW bug workaround when CS threadgroups > 256 threads and async
765 * compute isn't used, i.e. only one compute job can run at a time.
766 * If async compute is possible, the threadgroup size must be limited
767 * to 256 threads on all queues to avoid the bug.
768 * Only SI and certain CIK chips are affected.
770 bool cs_regalloc_hang
=
771 (sctx
->b
.chip_class
== SI
||
772 sctx
->b
.family
== CHIP_BONAIRE
||
773 sctx
->b
.family
== CHIP_KABINI
) &&
774 info
->block
[0] * info
->block
[1] * info
->block
[2] > 256;
776 if (cs_regalloc_hang
)
777 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
778 SI_CONTEXT_CS_PARTIAL_FLUSH
;
780 if (program
->ir_type
== PIPE_SHADER_IR_TGSI
&&
781 program
->shader
.compilation_failed
)
784 si_decompress_compute_textures(sctx
);
786 /* Add buffer sizes for memory checking in need_cs_space. */
787 r600_context_add_resource_size(ctx
, &program
->shader
.bo
->b
.b
);
788 /* TODO: add the scratch buffer */
790 if (info
->indirect
) {
791 r600_context_add_resource_size(ctx
, info
->indirect
);
793 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
794 if (sctx
->b
.chip_class
<= VI
&&
795 r600_resource(info
->indirect
)->TC_L2_dirty
) {
796 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
797 r600_resource(info
->indirect
)->TC_L2_dirty
= false;
801 si_need_cs_space(sctx
);
803 if (!sctx
->cs_shader_state
.initialized
)
804 si_initialize_compute(sctx
);
807 si_emit_cache_flush(sctx
);
809 if (!si_switch_compute_shader(sctx
, program
, &program
->shader
,
810 code_object
, info
->pc
))
813 si_upload_compute_shader_descriptors(sctx
);
814 si_emit_compute_shader_userdata(sctx
);
816 if (si_is_atom_dirty(sctx
, sctx
->atoms
.s
.render_cond
)) {
817 sctx
->atoms
.s
.render_cond
->emit(&sctx
->b
,
818 sctx
->atoms
.s
.render_cond
);
819 si_set_atom_dirty(sctx
, sctx
->atoms
.s
.render_cond
, false);
822 if ((program
->input_size
||
823 program
->ir_type
== PIPE_SHADER_IR_NATIVE
) &&
824 unlikely(!si_upload_compute_input(sctx
, code_object
, info
))) {
829 for (i
= 0; i
< MAX_GLOBAL_BUFFERS
; i
++) {
830 struct r600_resource
*buffer
=
831 (struct r600_resource
*)program
->global_buffers
[i
];
835 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, buffer
,
836 RADEON_USAGE_READWRITE
,
837 RADEON_PRIO_COMPUTE_GLOBAL
);
840 if (program
->ir_type
== PIPE_SHADER_IR_TGSI
)
841 si_setup_tgsi_grid(sctx
, info
);
843 si_ce_pre_draw_synchronization(sctx
);
845 si_emit_dispatch_packets(sctx
, info
);
847 si_ce_post_draw_synchronization(sctx
);
849 sctx
->compute_is_busy
= true;
850 sctx
->b
.num_compute_calls
++;
851 if (sctx
->cs_shader_state
.uses_scratch
)
852 sctx
->b
.num_spill_compute_calls
++;
854 if (cs_regalloc_hang
)
855 sctx
->b
.flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
859 static void si_delete_compute_state(struct pipe_context
*ctx
, void* state
){
860 struct si_compute
*program
= (struct si_compute
*)state
;
861 struct si_context
*sctx
= (struct si_context
*)ctx
;
867 if (program
->ir_type
== PIPE_SHADER_IR_TGSI
) {
868 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
,
870 util_queue_fence_destroy(&program
->ready
);
873 if (program
== sctx
->cs_shader_state
.program
)
874 sctx
->cs_shader_state
.program
= NULL
;
876 if (program
== sctx
->cs_shader_state
.emitted_program
)
877 sctx
->cs_shader_state
.emitted_program
= NULL
;
879 si_shader_destroy(&program
->shader
);
883 static void si_set_compute_resources(struct pipe_context
* ctx_
,
884 unsigned start
, unsigned count
,
885 struct pipe_surface
** surfaces
) { }
887 void si_init_compute_functions(struct si_context
*sctx
)
889 sctx
->b
.b
.create_compute_state
= si_create_compute_state
;
890 sctx
->b
.b
.delete_compute_state
= si_delete_compute_state
;
891 sctx
->b
.b
.bind_compute_state
= si_bind_compute_state
;
892 /* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
893 sctx
->b
.b
.set_compute_resources
= si_set_compute_resources
;
894 sctx
->b
.b
.set_global_binding
= si_set_global_binding
;
895 sctx
->b
.b
.launch_grid
= si_launch_grid
;