src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "compiler/nir/nir.h"
  26 #include "radeon/radeon_uvd_enc.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_video.h"
  29 #include "si_pipe.h"
  30 #include "util/u_screen.h"
  31 #include "util/u_video.h"
  32 #include "vl/vl_decoder.h"
  33 #include "vl/vl_video_buffer.h"
  34 #include <sys/utsname.h>
  35
  36 static const char *si_get_vendor(struct pipe_screen *pscreen)
  37 {
  38    /* Don't change this. Games such as Alien Isolation are broken if this
  39     * returns "Advanced Micro Devices, Inc."
  40     */
  41    return "X.Org";
  42 }
  43
  44 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  45 {
  46    return "AMD";
  47 }
  48
  49 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  50 {
  51    struct si_screen *sscreen = (struct si_screen *)pscreen;
  52
  53    switch (param) {
  54    /* Supported features (boolean caps). */
  55    case PIPE_CAP_ACCELERATED:
  56    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  57    case PIPE_CAP_ANISOTROPIC_FILTER:
  58    case PIPE_CAP_POINT_SPRITE:
  59    case PIPE_CAP_OCCLUSION_QUERY:
  60    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  61    case PIPE_CAP_TEXTURE_SHADOW_LOD:
  62    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  63    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  64    case PIPE_CAP_TEXTURE_SWIZZLE:
  65    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  66    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
  67    case PIPE_CAP_SHADER_STENCIL_EXPORT:
  68    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  69    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  70    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  71    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  72    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  73    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  74    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
  75    case PIPE_CAP_VERTEX_SHADER_SATURATE:
  76    case PIPE_CAP_SEAMLESS_CUBE_MAP:
  77    case PIPE_CAP_PRIMITIVE_RESTART:
  78    case PIPE_CAP_CONDITIONAL_RENDER:
  79    case PIPE_CAP_TEXTURE_BARRIER:
  80    case PIPE_CAP_INDEP_BLEND_ENABLE:
  81    case PIPE_CAP_INDEP_BLEND_FUNC:
  82    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  83    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  84    case PIPE_CAP_START_INSTANCE:
  85    case PIPE_CAP_NPOT_TEXTURES:
  86    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  87    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  88    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  89    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  90    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  91    case PIPE_CAP_TGSI_INSTANCEID:
  92    case PIPE_CAP_COMPUTE:
  93    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  94    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
  95    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
  96    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  97    case PIPE_CAP_CUBE_MAP_ARRAY:
  98    case PIPE_CAP_SAMPLE_SHADING:
  99    case PIPE_CAP_DRAW_INDIRECT:
 100    case PIPE_CAP_CLIP_HALFZ:
 101    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 102    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 103    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 104    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 105    case PIPE_CAP_TGSI_TEXCOORD:
 106    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 107    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 108    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 109    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 110    case PIPE_CAP_SHAREABLE_SHADERS:
 111    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 112    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 113    case PIPE_CAP_TEXTURE_QUERY_LOD:
 114    case PIPE_CAP_TEXTURE_GATHER_SM5:
 115    case PIPE_CAP_TGSI_TXQS:
 116    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 117    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 118    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 119    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 120    case PIPE_CAP_INVALIDATE_BUFFER:
 121    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 122    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 123    case PIPE_CAP_QUERY_MEMORY_INFO:
 124    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 125    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 126    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 127    case PIPE_CAP_GENERATE_MIPMAP:
 128    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 129    case PIPE_CAP_STRING_MARKER:
 130    case PIPE_CAP_CLEAR_TEXTURE:
 131    case PIPE_CAP_CULL_DISTANCE:
 132    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 133    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 134    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 135    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 136    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 137    case PIPE_CAP_DOUBLES:
 138    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 139    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 140    case PIPE_CAP_BINDLESS_TEXTURE:
 141    case PIPE_CAP_QUERY_TIMESTAMP:
 142    case PIPE_CAP_QUERY_TIME_ELAPSED:
 143    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 144    case PIPE_CAP_MEMOBJ:
 145    case PIPE_CAP_LOAD_CONSTBUF:
 146    case PIPE_CAP_INT64:
 147    case PIPE_CAP_INT64_DIVMOD:
 148    case PIPE_CAP_TGSI_CLOCK:
 149    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 150    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 151    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 152    case PIPE_CAP_TGSI_BALLOT:
 153    case PIPE_CAP_TGSI_VOTE:
 154    case PIPE_CAP_FBFETCH:
 155    case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
 156    case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 157    case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA:
 158    case PIPE_CAP_TGSI_DIV:
 159    case PIPE_CAP_PACKED_UNIFORMS:
 160    case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 161    case PIPE_CAP_GL_SPIRV:
 162    case PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES:
 163    case PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL:
 164    case PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE:
 165       return 1;
 166
 167    case PIPE_CAP_QUERY_SO_OVERFLOW:
 168       return !sscreen->use_ngg_streamout;
 169
 170    case PIPE_CAP_POST_DEPTH_COVERAGE:
 171       return sscreen->info.chip_class >= GFX10;
 172
 173    case PIPE_CAP_GRAPHICS:
 174       return sscreen->info.has_graphics;
 175
 176    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 177       return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 178
 179    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 180       return sscreen->info.has_gpu_reset_status_query;
 181
 182    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 183       return sscreen->info.has_2d_tiling;
 184
 185    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 186       return SI_MAP_BUFFER_ALIGNMENT;
 187
 188    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 189    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 190    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 191    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 192    case PIPE_CAP_MAX_VERTEX_STREAMS:
 193    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 194    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 195       return 4;
 196
 197    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 198    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 199       if (!sscreen->info.has_indirect_compute_dispatch)
 200          return 420;
 201       return 460;
 202
 203    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 204       /* Optimal number for good TexSubImage performance on Polaris10. */
 205       return 64 * 1024 * 1024;
 206
 207    case PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE:
 208       return 4096 * 1024;
 209
 210    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 211    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 212       /* Align it down to 256 bytes. I've chosen the number randomly. */
 213       return ROUND_DOWN_TO(MIN2(sscreen->info.max_alloc_size, INT_MAX), 256);
 214
 215    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 216    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 217    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 218       return LLVM_VERSION_MAJOR < 9 && !sscreen->info.has_unaligned_shader_loads;
 219
 220    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 221       return sscreen->info.has_sparse_vm_mappings ? RADEON_SPARSE_PAGE_SIZE : 0;
 222
 223    case PIPE_CAP_UMA:
 224    case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
 225       return 0;
 226
 227    case PIPE_CAP_FENCE_SIGNAL:
 228       return sscreen->info.has_syncobj;
 229
 230    case PIPE_CAP_CONSTBUF0_FLAGS:
 231       return SI_RESOURCE_FLAG_32BIT;
 232
 233    case PIPE_CAP_NATIVE_FENCE_FD:
 234       return sscreen->info.has_fence_to_handle;
 235
 236    case PIPE_CAP_DRAW_PARAMETERS:
 237    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 238    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 239       return sscreen->has_draw_indirect_multi;
 240
 241    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 242       return 30;
 243
 244    case PIPE_CAP_MAX_VARYINGS:
 245       return 32;
 246
 247    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 248       return sscreen->info.chip_class <= GFX8 ? PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 249
 250    /* Stream output. */
 251    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 252    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 253       return 32 * 4;
 254
 255    /* Geometry shader output. */
 256    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 257       /* gfx9 has to report 256 to make piglit/gs-max-output pass.
 258        * gfx8 and earlier can do 1024.
 259        */
 260       return 256;
 261    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 262       return 4095;
 263    case PIPE_CAP_MAX_GS_INVOCATIONS:
 264       /* The closed driver exposes 127, but 125 is the greatest
 265        * number that works. */
 266       return 125;
 267
 268    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 269       return 2048;
 270
 271    /* Texturing. */
 272    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 273       return 16384;
 274    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 275       return 15; /* 16384 */
 276    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 277       if (sscreen->info.chip_class >= GFX10)
 278          return 14;
 279       /* textures support 8192, but layered rendering supports 2048 */
 280       return 12;
 281    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 282       if (sscreen->info.chip_class >= GFX10)
 283          return 8192;
 284       /* textures support 8192, but layered rendering supports 2048 */
 285       return 2048;
 286
 287    /* Viewports and render targets. */
 288    case PIPE_CAP_MAX_VIEWPORTS:
 289       return SI_MAX_VIEWPORTS;
 290    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 291    case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 292    case PIPE_CAP_MAX_RENDER_TARGETS:
 293       return 8;
 294    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 295       return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
 296
 297    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 298    case PIPE_CAP_MIN_TEXEL_OFFSET:
 299       return -32;
 300
 301    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 302    case PIPE_CAP_MAX_TEXEL_OFFSET:
 303       return 31;
 304
 305    case PIPE_CAP_ENDIANNESS:
 306       return PIPE_ENDIAN_LITTLE;
 307
 308    case PIPE_CAP_VENDOR_ID:
 309       return ATI_VENDOR_ID;
 310    case PIPE_CAP_DEVICE_ID:
 311       return sscreen->info.pci_id;
 312    case PIPE_CAP_VIDEO_MEMORY:
 313       return sscreen->info.vram_size >> 20;
 314    case PIPE_CAP_PCI_GROUP:
 315       return sscreen->info.pci_domain;
 316    case PIPE_CAP_PCI_BUS:
 317       return sscreen->info.pci_bus;
 318    case PIPE_CAP_PCI_DEVICE:
 319       return sscreen->info.pci_dev;
 320    case PIPE_CAP_PCI_FUNCTION:
 321       return sscreen->info.pci_func;
 322    case PIPE_CAP_TGSI_ATOMINC_WRAP:
 323       return LLVM_VERSION_MAJOR >= 10;
 324
 325    default:
 326       return u_pipe_screen_get_param_defaults(pscreen, param);
 327    }
 328 }
 329
 330 static float si_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 331 {
 332    switch (param) {
 333    case PIPE_CAPF_MAX_LINE_WIDTH:
 334    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 335       /* This depends on the quant mode, though the precise interactions
 336        * are unknown. */
 337       return 2048;
 338    case PIPE_CAPF_MAX_POINT_WIDTH:
 339    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 340       return SI_MAX_POINT_SIZE;
 341    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 342       return 16.0f;
 343    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 344       return 16.0f;
 345    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 346    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 347    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 348       return 0.0f;
 349    }
 350    return 0.0f;
 351 }
 352
 353 static int si_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_type shader,
 354                                enum pipe_shader_cap param)
 355 {
 356    struct si_screen *sscreen = (struct si_screen *)pscreen;
 357
 358    switch (shader) {
 359    case PIPE_SHADER_FRAGMENT:
 360    case PIPE_SHADER_VERTEX:
 361    case PIPE_SHADER_GEOMETRY:
 362    case PIPE_SHADER_TESS_CTRL:
 363    case PIPE_SHADER_TESS_EVAL:
 364       break;
 365    case PIPE_SHADER_COMPUTE:
 366       switch (param) {
 367       case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 368          int ir = 1 << PIPE_SHADER_IR_NATIVE;
 369
 370          if (sscreen->info.has_indirect_compute_dispatch)
 371             ir |= 1 << PIPE_SHADER_IR_NIR;
 372
 373          return ir;
 374       }
 375       default:
 376          /* If compute shaders don't require a special value
 377           * for this cap, we can return the same value we
 378           * do for other shader types. */
 379          break;
 380       }
 381       break;
 382    default:
 383       return 0;
 384    }
 385
 386    switch (param) {
 387    /* Shader limits. */
 388    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 389    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 390    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 391    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 392    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 393       return 16384;
 394    case PIPE_SHADER_CAP_MAX_INPUTS:
 395       return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 396    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 397       return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 398    case PIPE_SHADER_CAP_MAX_TEMPS:
 399       return 256; /* Max native temporaries. */
 400    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 401       return si_get_param(pscreen, PIPE_CAP_MAX_SHADER_BUFFER_SIZE);
 402    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 403       return SI_NUM_CONST_BUFFERS;
 404    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 405    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 406       return SI_NUM_SAMPLERS;
 407    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 408       return SI_NUM_SHADER_BUFFERS;
 409    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 410       return SI_NUM_IMAGES;
 411    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 412       return 0;
 413    case PIPE_SHADER_CAP_PREFERRED_IR:
 414       return PIPE_SHADER_IR_NIR;
 415    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 416       return 4;
 417
 418    /* Supported boolean features. */
 419    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 420    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 421    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 422    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 423    case PIPE_SHADER_CAP_INTEGERS:
 424    case PIPE_SHADER_CAP_INT64_ATOMICS:
 425    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 426    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 427    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 428    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 429    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 430    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 431       return 1;
 432
 433    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 434       /* TODO: Indirect indexing of GS inputs is unimplemented. */
 435       if (shader == PIPE_SHADER_GEOMETRY)
 436          return 0;
 437
 438       if (shader == PIPE_SHADER_VERTEX && !sscreen->llvm_has_working_vgpr_indexing)
 439          return 0;
 440
 441       /* TCS and TES load inputs directly from LDS or offchip
 442        * memory, so indirect indexing is always supported.
 443        * PS has to support indirect indexing, because we can't
 444        * lower that to TEMPs for INTERP instructions.
 445        */
 446       return 1;
 447
 448    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 449       return sscreen->llvm_has_working_vgpr_indexing ||
 450              /* TCS stores outputs directly to memory. */
 451              shader == PIPE_SHADER_TESS_CTRL;
 452
 453    /* Unsupported boolean features. */
 454    case PIPE_SHADER_CAP_FP16:
 455    case PIPE_SHADER_CAP_SUBROUTINES:
 456    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 457    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 458    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 459       return 0;
 460    }
 461    return 0;
 462 }
 463
 464 static const struct nir_shader_compiler_options nir_options = {
 465    .lower_scmp = true,
 466    .lower_flrp32 = true,
 467    .lower_flrp64 = true,
 468    .lower_fsat = true,
 469    .lower_fdiv = true,
 470    .lower_bitfield_insert_to_bitfield_select = true,
 471    .lower_bitfield_extract = true,
 472    .lower_sub = true,
 473    .fuse_ffma = true,
 474    .lower_fmod = true,
 475    .lower_pack_snorm_4x8 = true,
 476    .lower_pack_unorm_4x8 = true,
 477    .lower_unpack_snorm_2x16 = true,
 478    .lower_unpack_snorm_4x8 = true,
 479    .lower_unpack_unorm_2x16 = true,
 480    .lower_unpack_unorm_4x8 = true,
 481    .lower_extract_byte = true,
 482    .lower_extract_word = true,
 483    .lower_rotate = true,
 484    .lower_to_scalar = true,
 485    .optimize_sample_mask_in = true,
 486    .max_unroll_iterations = 32,
 487    .use_interpolated_input_intrinsics = true,
 488 };
 489
 490 static const void *si_get_compiler_options(struct pipe_screen *screen, enum pipe_shader_ir ir,
 491                                            enum pipe_shader_type shader)
 492 {
 493    assert(ir == PIPE_SHADER_IR_NIR);
 494    return &nir_options;
 495 }
 496
 497 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 498 {
 499    ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 500 }
 501
 502 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 503 {
 504    struct si_screen *sscreen = (struct si_screen *)pscreen;
 505
 506    ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 507 }
 508
 509 static const char *si_get_name(struct pipe_screen *pscreen)
 510 {
 511    struct si_screen *sscreen = (struct si_screen *)pscreen;
 512
 513    return sscreen->renderer_string;
 514 }
 515
 516 static int si_get_video_param_no_decode(struct pipe_screen *screen, enum pipe_video_profile profile,
 517                                         enum pipe_video_entrypoint entrypoint,
 518                                         enum pipe_video_cap param)
 519 {
 520    switch (param) {
 521    case PIPE_VIDEO_CAP_SUPPORTED:
 522       return vl_profile_supported(screen, profile, entrypoint);
 523    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 524       return 1;
 525    case PIPE_VIDEO_CAP_MAX_WIDTH:
 526    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 527       return vl_video_buffer_max_size(screen);
 528    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 529       return PIPE_FORMAT_NV12;
 530    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 531       return false;
 532    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 533       return false;
 534    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 535       return true;
 536    case PIPE_VIDEO_CAP_MAX_LEVEL:
 537       return vl_level_supported(screen, profile);
 538    default:
 539       return 0;
 540    }
 541 }
 542
 543 static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profile profile,
 544                               enum pipe_video_entrypoint entrypoint, enum pipe_video_cap param)
 545 {
 546    struct si_screen *sscreen = (struct si_screen *)screen;
 547    enum pipe_video_format codec = u_reduce_video_profile(profile);
 548
 549    if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 550       switch (param) {
 551       case PIPE_VIDEO_CAP_SUPPORTED:
 552          return (
 553             (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 554              (sscreen->info.family >= CHIP_RAVEN || si_vce_is_fw_version_supported(sscreen))) ||
 555             (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 556              (sscreen->info.family >= CHIP_RAVEN || si_radeon_uvd_enc_supported(sscreen))) ||
 557             (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 && sscreen->info.family >= CHIP_RENOIR));
 558       case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 559          return 1;
 560       case PIPE_VIDEO_CAP_MAX_WIDTH:
 561          return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 562       case PIPE_VIDEO_CAP_MAX_HEIGHT:
 563          return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 564       case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 565          return PIPE_FORMAT_NV12;
 566       case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 567          return false;
 568       case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 569          return false;
 570       case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 571          return true;
 572       case PIPE_VIDEO_CAP_STACKED_FRAMES:
 573          return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 574       default:
 575          return 0;
 576       }
 577    }
 578
 579    switch (param) {
 580    case PIPE_VIDEO_CAP_SUPPORTED:
 581       switch (codec) {
 582       case PIPE_VIDEO_FORMAT_MPEG12:
 583          return profile != PIPE_VIDEO_PROFILE_MPEG1;
 584       case PIPE_VIDEO_FORMAT_MPEG4:
 585          return 1;
 586       case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 587          if ((sscreen->info.family == CHIP_POLARIS10 || sscreen->info.family == CHIP_POLARIS11) &&
 588              sscreen->info.uvd_fw_version < UVD_FW_1_66_16) {
 589             RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 590             return false;
 591          }
 592          return true;
 593       case PIPE_VIDEO_FORMAT_VC1:
 594          return true;
 595       case PIPE_VIDEO_FORMAT_HEVC:
 596          /* Carrizo only supports HEVC Main */
 597          if (sscreen->info.family >= CHIP_STONEY)
 598             return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 599                     profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 600          else if (sscreen->info.family >= CHIP_CARRIZO)
 601             return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 602          return false;
 603       case PIPE_VIDEO_FORMAT_JPEG:
 604          if (sscreen->info.family >= CHIP_RAVEN)
 605             return true;
 606          if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 607             return false;
 608          if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
 609             RVID_ERR("No MJPEG support for the kernel version\n");
 610             return false;
 611          }
 612          return true;
 613       case PIPE_VIDEO_FORMAT_VP9:
 614          if (sscreen->info.family < CHIP_RAVEN)
 615             return false;
 616          return true;
 617       default:
 618          return false;
 619       }
 620    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 621       return 1;
 622    case PIPE_VIDEO_CAP_MAX_WIDTH:
 623       switch (codec) {
 624       case PIPE_VIDEO_FORMAT_HEVC:
 625       case PIPE_VIDEO_FORMAT_VP9:
 626          return (sscreen->info.family < CHIP_RENOIR)
 627                    ? ((sscreen->info.family < CHIP_TONGA) ? 2048 : 4096)
 628                    : 8192;
 629       default:
 630          return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 631       }
 632    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 633       switch (codec) {
 634       case PIPE_VIDEO_FORMAT_HEVC:
 635       case PIPE_VIDEO_FORMAT_VP9:
 636          return (sscreen->info.family < CHIP_RENOIR)
 637                    ? ((sscreen->info.family < CHIP_TONGA) ? 1152 : 4096)
 638                    : 4352;
 639       default:
 640          return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 641       }
 642    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 643       if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 644          return PIPE_FORMAT_P010;
 645       else if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 646          return PIPE_FORMAT_P016;
 647       else
 648          return PIPE_FORMAT_NV12;
 649
 650    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 651    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 652       enum pipe_video_format format = u_reduce_video_profile(profile);
 653
 654       if (format == PIPE_VIDEO_FORMAT_HEVC)
 655          return false; // The firmware doesn't support interlaced HEVC.
 656       else if (format == PIPE_VIDEO_FORMAT_JPEG)
 657          return false;
 658       else if (format == PIPE_VIDEO_FORMAT_VP9)
 659          return false;
 660       return true;
 661    }
 662    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 663       return true;
 664    case PIPE_VIDEO_CAP_MAX_LEVEL:
 665       switch (profile) {
 666       case PIPE_VIDEO_PROFILE_MPEG1:
 667          return 0;
 668       case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 669       case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 670          return 3;
 671       case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 672          return 3;
 673       case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 674          return 5;
 675       case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 676          return 1;
 677       case PIPE_VIDEO_PROFILE_VC1_MAIN:
 678          return 2;
 679       case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 680          return 4;
 681       case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 682       case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 683       case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 684          return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 685       case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 686       case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 687          return 186;
 688       default:
 689          return 0;
 690       }
 691    default:
 692       return 0;
 693    }
 694 }
 695
 696 static bool si_vid_is_format_supported(struct pipe_screen *screen, enum pipe_format format,
 697                                        enum pipe_video_profile profile,
 698                                        enum pipe_video_entrypoint entrypoint)
 699 {
 700    /* HEVC 10 bit decoding should use P010 instead of NV12 if possible */
 701    if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 702       return (format == PIPE_FORMAT_NV12) || (format == PIPE_FORMAT_P010) ||
 703              (format == PIPE_FORMAT_P016);
 704
 705    /* Vp9 profile 2 supports 10 bit decoding using P016 */
 706    if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 707       return format == PIPE_FORMAT_P016;
 708
 709    /* we can only handle this one with UVD */
 710    if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 711       return format == PIPE_FORMAT_NV12;
 712
 713    return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 714 }
 715
 716 static unsigned get_max_threads_per_block(struct si_screen *screen, enum pipe_shader_ir ir_type)
 717 {
 718    if (ir_type == PIPE_SHADER_IR_NATIVE)
 719       return 256;
 720
 721    /* LLVM 10 only supports 1024 threads per block. */
 722    return 1024;
 723 }
 724
 725 static int si_get_compute_param(struct pipe_screen *screen, enum pipe_shader_ir ir_type,
 726                                 enum pipe_compute_cap param, void *ret)
 727 {
 728    struct si_screen *sscreen = (struct si_screen *)screen;
 729
 730    // TODO: select these params by asic
 731    switch (param) {
 732    case PIPE_COMPUTE_CAP_IR_TARGET: {
 733       const char *gpu, *triple;
 734
 735       triple = "amdgcn-mesa-mesa3d";
 736       gpu = ac_get_llvm_processor_name(sscreen->info.family);
 737       if (ret) {
 738          sprintf(ret, "%s-%s", gpu, triple);
 739       }
 740       /* +2 for dash and terminating NIL byte */
 741       return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 742    }
 743    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 744       if (ret) {
 745          uint64_t *grid_dimension = ret;
 746          grid_dimension[0] = 3;
 747       }
 748       return 1 * sizeof(uint64_t);
 749
 750    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 751       if (ret) {
 752          uint64_t *grid_size = ret;
 753          grid_size[0] = 65535;
 754          grid_size[1] = 65535;
 755          grid_size[2] = 65535;
 756       }
 757       return 3 * sizeof(uint64_t);
 758
 759    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 760       if (ret) {
 761          uint64_t *block_size = ret;
 762          unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 763          block_size[0] = threads_per_block;
 764          block_size[1] = threads_per_block;
 765          block_size[2] = threads_per_block;
 766       }
 767       return 3 * sizeof(uint64_t);
 768
 769    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 770       if (ret) {
 771          uint64_t *max_threads_per_block = ret;
 772          *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 773       }
 774       return sizeof(uint64_t);
 775    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 776       if (ret) {
 777          uint32_t *address_bits = ret;
 778          address_bits[0] = 64;
 779       }
 780       return 1 * sizeof(uint32_t);
 781
 782    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 783       if (ret) {
 784          uint64_t *max_global_size = ret;
 785          uint64_t max_mem_alloc_size;
 786
 787          si_get_compute_param(screen, ir_type, PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 788                               &max_mem_alloc_size);
 789
 790          /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 791           * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 792           * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 793           * make sure we never report more than
 794           * 4 * MAX_MEM_ALLOC_SIZE.
 795           */
 796          *max_global_size =
 797             MIN2(4 * max_mem_alloc_size, MAX2(sscreen->info.gart_size, sscreen->info.vram_size));
 798       }
 799       return sizeof(uint64_t);
 800
 801    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 802       if (ret) {
 803          uint64_t *max_local_size = ret;
 804          /* Value reported by the closed source driver. */
 805          *max_local_size = 32768;
 806       }
 807       return sizeof(uint64_t);
 808
 809    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 810       if (ret) {
 811          uint64_t *max_input_size = ret;
 812          /* Value reported by the closed source driver. */
 813          *max_input_size = 1024;
 814       }
 815       return sizeof(uint64_t);
 816
 817    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 818       if (ret) {
 819          uint64_t *max_mem_alloc_size = ret;
 820
 821          *max_mem_alloc_size = sscreen->info.max_alloc_size;
 822       }
 823       return sizeof(uint64_t);
 824
 825    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 826       if (ret) {
 827          uint32_t *max_clock_frequency = ret;
 828          *max_clock_frequency = sscreen->info.max_shader_clock;
 829       }
 830       return sizeof(uint32_t);
 831
 832    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 833       if (ret) {
 834          uint32_t *max_compute_units = ret;
 835          *max_compute_units = sscreen->info.num_good_compute_units;
 836       }
 837       return sizeof(uint32_t);
 838
 839    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 840       if (ret) {
 841          uint32_t *images_supported = ret;
 842          *images_supported = 0;
 843       }
 844       return sizeof(uint32_t);
 845    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 846       break; /* unused */
 847    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 848       if (ret) {
 849          uint32_t *subgroup_size = ret;
 850          *subgroup_size = sscreen->compute_wave_size;
 851       }
 852       return sizeof(uint32_t);
 853    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 854       if (ret) {
 855          uint64_t *max_variable_threads_per_block = ret;
 856          if (ir_type == PIPE_SHADER_IR_NATIVE)
 857             *max_variable_threads_per_block = 0;
 858          else
 859             *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 860       }
 861       return sizeof(uint64_t);
 862    }
 863
 864    fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 865    return 0;
 866 }
 867
 868 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 869 {
 870    struct si_screen *sscreen = (struct si_screen *)screen;
 871
 872    return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 873           sscreen->info.clock_crystal_freq;
 874 }
 875
 876 static void si_query_memory_info(struct pipe_screen *screen, struct pipe_memory_info *info)
 877 {
 878    struct si_screen *sscreen = (struct si_screen *)screen;
 879    struct radeon_winsys *ws = sscreen->ws;
 880    unsigned vram_usage, gtt_usage;
 881
 882    info->total_device_memory = sscreen->info.vram_size / 1024;
 883    info->total_staging_memory = sscreen->info.gart_size / 1024;
 884
 885    /* The real TTM memory usage is somewhat random, because:
 886     *
 887     * 1) TTM delays freeing memory, because it can only free it after
 888     *    fences expire.
 889     *
 890     * 2) The memory usage can be really low if big VRAM evictions are
 891     *    taking place, but the real usage is well above the size of VRAM.
 892     *
 893     * Instead, return statistics of this process.
 894     */
 895    vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
 896    gtt_usage = ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
 897
 898    info->avail_device_memory =
 899       vram_usage <= info->total_device_memory ? info->total_device_memory - vram_usage : 0;
 900    info->avail_staging_memory =
 901       gtt_usage <= info->total_staging_memory ? info->total_staging_memory - gtt_usage : 0;
 902
 903    info->device_memory_evicted = ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 904
 905    if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 4)
 906       info->nr_device_memory_evictions = ws->query_value(ws, RADEON_NUM_EVICTIONS);
 907    else
 908       /* Just return the number of evicted 64KB pages. */
 909       info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 910 }
 911
 912 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 913 {
 914    struct si_screen *sscreen = (struct si_screen *)pscreen;
 915
 916    return sscreen->disk_shader_cache;
 917 }
 918
 919 static void si_init_renderer_string(struct si_screen *sscreen)
 920 {
 921    char first_name[256], second_name[32] = {}, kernel_version[128] = {};
 922    struct utsname uname_data;
 923
 924    if (sscreen->info.marketing_name) {
 925       snprintf(first_name, sizeof(first_name), "%s", sscreen->info.marketing_name);
 926       snprintf(second_name, sizeof(second_name), "%s, ", sscreen->info.name);
 927    } else {
 928       snprintf(first_name, sizeof(first_name), "AMD %s", sscreen->info.name);
 929    }
 930
 931    if (uname(&uname_data) == 0)
 932       snprintf(kernel_version, sizeof(kernel_version), ", %s", uname_data.release);
 933
 934    snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 935             "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING ")", first_name, second_name,
 936             sscreen->info.drm_major, sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 937             kernel_version);
 938 }
 939
 940 void si_init_screen_get_functions(struct si_screen *sscreen)
 941 {
 942    sscreen->b.get_name = si_get_name;
 943    sscreen->b.get_vendor = si_get_vendor;
 944    sscreen->b.get_device_vendor = si_get_device_vendor;
 945    sscreen->b.get_param = si_get_param;
 946    sscreen->b.get_paramf = si_get_paramf;
 947    sscreen->b.get_compute_param = si_get_compute_param;
 948    sscreen->b.get_timestamp = si_get_timestamp;
 949    sscreen->b.get_shader_param = si_get_shader_param;
 950    sscreen->b.get_compiler_options = si_get_compiler_options;
 951    sscreen->b.get_device_uuid = si_get_device_uuid;
 952    sscreen->b.get_driver_uuid = si_get_driver_uuid;
 953    sscreen->b.query_memory_info = si_query_memory_info;
 954    sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 955
 956    if (sscreen->info.has_hw_decode) {
 957       sscreen->b.get_video_param = si_get_video_param;
 958       sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 959    } else {
 960       sscreen->b.get_video_param = si_get_video_param_no_decode;
 961       sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 962    }
 963
 964    si_init_renderer_string(sscreen);
 965 }