src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_shader.h"
  26 #include "si_public.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_llvm_emit.h"
  30 #include "radeon/radeon_uvd.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_suballoc.h"
  33 #include "vl/vl_decoder.h"
  34
  35 /*
  36  * pipe_context
  37  */
  38 static void si_destroy_context(struct pipe_context *context)
  39 {
  40         struct si_context *sctx = (struct si_context *)context;
  41         int i;
  42
  43         si_dec_framebuffer_counters(&sctx->framebuffer.state);
  44
  45         si_release_all_descriptors(sctx);
  46
  47         if (sctx->ce_suballocator)
  48                 u_suballocator_destroy(sctx->ce_suballocator);
  49
  50         pipe_resource_reference(&sctx->esgs_ring, NULL);
  51         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  52         pipe_resource_reference(&sctx->tf_ring, NULL);
  53         pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
  54         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  55         r600_resource_reference(&sctx->border_color_buffer, NULL);
  56         free(sctx->border_color_table);
  57         r600_resource_reference(&sctx->scratch_buffer, NULL);
  58         r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
  59         sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
  60
  61         si_pm4_free_state(sctx, sctx->init_config, ~0);
  62         if (sctx->init_config_gs_rings)
  63                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  64         for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
  65                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  66
  67         if (sctx->fixed_func_tcs_shader.cso)
  68                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  69         if (sctx->custom_dsa_flush)
  70                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  71         if (sctx->custom_blend_resolve)
  72                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  73         if (sctx->custom_blend_decompress)
  74                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  75         if (sctx->custom_blend_fastclear)
  76                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  77         if (sctx->custom_blend_dcc_decompress)
  78                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
  79         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  80
  81         if (sctx->blitter)
  82                 util_blitter_destroy(sctx->blitter);
  83
  84         r600_common_context_cleanup(&sctx->b);
  85
  86         LLVMDisposeTargetMachine(sctx->tm);
  87
  88         r600_resource_reference(&sctx->trace_buf, NULL);
  89         r600_resource_reference(&sctx->last_trace_buf, NULL);
  90         free(sctx->last_ib);
  91         if (sctx->last_bo_list) {
  92                 for (i = 0; i < sctx->last_bo_count; i++)
  93                         pb_reference(&sctx->last_bo_list[i].buf, NULL);
  94                 free(sctx->last_bo_list);
  95         }
  96         FREE(sctx);
  97 }
  98
  99 static enum pipe_reset_status
 100 si_amdgpu_get_reset_status(struct pipe_context *ctx)
 101 {
 102         struct si_context *sctx = (struct si_context *)ctx;
 103
 104         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
 105 }
 106
 107 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 108                                               void *priv, unsigned flags)
 109 {
 110         struct si_context *sctx = CALLOC_STRUCT(si_context);
 111         struct si_screen* sscreen = (struct si_screen *)screen;
 112         struct radeon_winsys *ws = sscreen->b.ws;
 113         LLVMTargetRef r600_target;
 114         const char *triple = "amdgcn--";
 115         int shader, i;
 116
 117         if (!sctx)
 118                 return NULL;
 119
 120         if (sscreen->b.debug_flags & DBG_CHECK_VM)
 121                 flags |= PIPE_CONTEXT_DEBUG;
 122
 123         sctx->b.b.screen = screen; /* this must be set first */
 124         sctx->b.b.priv = priv;
 125         sctx->b.b.destroy = si_destroy_context;
 126         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 127         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 128         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 129
 130         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 131                 goto fail;
 132
 133         if (sscreen->b.info.drm_major == 3)
 134                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 135
 136         si_init_blit_functions(sctx);
 137         si_init_compute_functions(sctx);
 138         si_init_cp_dma_functions(sctx);
 139         si_init_debug_functions(sctx);
 140
 141         if (sscreen->b.info.has_uvd) {
 142                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 143                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 144         } else {
 145                 sctx->b.b.create_video_codec = vl_create_decoder;
 146                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 147         }
 148
 149         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 150                                        si_context_gfx_flush, sctx);
 151
 152         if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib) {
 153                 sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
 154                 if (!sctx->ce_ib)
 155                         goto fail;
 156
 157                 if (ws->cs_add_const_preamble_ib) {
 158                         sctx->ce_preamble_ib =
 159                                    ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
 160
 161                         if (!sctx->ce_preamble_ib)
 162                                 goto fail;
 163                 }
 164
 165                 sctx->ce_suballocator =
 166                                 u_suballocator_create(&sctx->b.b, 1024 * 1024,
 167                                                       PIPE_BIND_CUSTOM,
 168                                                       PIPE_USAGE_DEFAULT, FALSE);
 169                 if (!sctx->ce_suballocator)
 170                         goto fail;
 171         }
 172
 173         sctx->b.gfx.flush = si_context_gfx_flush;
 174
 175         /* Border colors. */
 176         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 177                                           sizeof(*sctx->border_color_table));
 178         if (!sctx->border_color_table)
 179                 goto fail;
 180
 181         sctx->border_color_buffer = (struct r600_resource*)
 182                 pipe_buffer_create(screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT,
 183                                    SI_MAX_BORDER_COLORS *
 184                                    sizeof(*sctx->border_color_table));
 185         if (!sctx->border_color_buffer)
 186                 goto fail;
 187
 188         sctx->border_color_map =
 189                 ws->buffer_map(sctx->border_color_buffer->buf,
 190                                NULL, PIPE_TRANSFER_WRITE);
 191         if (!sctx->border_color_map)
 192                 goto fail;
 193
 194         si_init_all_descriptors(sctx);
 195         si_init_state_functions(sctx);
 196         si_init_shader_functions(sctx);
 197
 198         if (sctx->b.chip_class >= CIK)
 199                 cik_init_sdma_functions(sctx);
 200         else
 201                 si_init_dma_functions(sctx);
 202
 203         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 204                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 205
 206         sctx->blitter = util_blitter_create(&sctx->b.b);
 207         if (sctx->blitter == NULL)
 208                 goto fail;
 209         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 210
 211         sctx->sample_mask.sample_mask = 0xffff;
 212
 213         /* these must be last */
 214         si_begin_new_cs(sctx);
 215         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 216
 217         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 218          * with a NULL buffer). We need to use a dummy buffer instead. */
 219         if (sctx->b.chip_class == CIK) {
 220                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 221                                                                  PIPE_USAGE_DEFAULT, 16);
 222                 if (!sctx->null_const_buf.buffer)
 223                         goto fail;
 224                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 225
 226                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 227                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 228                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 229                                                               &sctx->null_const_buf);
 230                         }
 231                 }
 232
 233                 /* Clear the NULL constant buffer, because loads should return zeros. */
 234                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 235                                      sctx->null_const_buf.buffer->width0, 0,
 236                                      R600_COHERENCY_SHADER);
 237         }
 238
 239         /* XXX: This is the maximum value allowed.  I'm not sure how to compute
 240          * this for non-cs shaders.  Using the wrong value here can result in
 241          * GPU lockups, but the maximum value seems to always work.
 242          */
 243         sctx->scratch_waves = 32 * sscreen->b.info.num_good_compute_units;
 244
 245         /* Initialize LLVM TargetMachine */
 246         r600_target = radeon_llvm_get_r600_target(triple);
 247         sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
 248                                            r600_get_llvm_processor_name(sscreen->b.family),
 249 #if HAVE_LLVM >= 0x0308
 250                                            sscreen->b.debug_flags & DBG_SI_SCHED ?
 251                                                 "+DumpCode,+vgpr-spilling,+si-scheduler" :
 252 #endif
 253                                                 "+DumpCode,+vgpr-spilling",
 254                                            LLVMCodeGenLevelDefault,
 255                                            LLVMRelocDefault,
 256                                            LLVMCodeModelDefault);
 257
 258         return &sctx->b.b;
 259 fail:
 260         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 261         si_destroy_context(&sctx->b.b);
 262         return NULL;
 263 }
 264
 265 /*
 266  * pipe_screen
 267  */
 268
 269 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 270 {
 271         struct si_screen *sscreen = (struct si_screen *)pscreen;
 272
 273         switch (param) {
 274         /* Supported features (boolean caps). */
 275         case PIPE_CAP_TWO_SIDED_STENCIL:
 276         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 277         case PIPE_CAP_ANISOTROPIC_FILTER:
 278         case PIPE_CAP_POINT_SPRITE:
 279         case PIPE_CAP_OCCLUSION_QUERY:
 280         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 281         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 282         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 283         case PIPE_CAP_TEXTURE_SWIZZLE:
 284         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 285         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 286         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 287         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 288         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 289         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 290         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 291         case PIPE_CAP_SM3:
 292         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 293         case PIPE_CAP_PRIMITIVE_RESTART:
 294         case PIPE_CAP_CONDITIONAL_RENDER:
 295         case PIPE_CAP_TEXTURE_BARRIER:
 296         case PIPE_CAP_INDEP_BLEND_ENABLE:
 297         case PIPE_CAP_INDEP_BLEND_FUNC:
 298         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 299         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 300         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 301         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 302         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 303         case PIPE_CAP_USER_INDEX_BUFFERS:
 304         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 305         case PIPE_CAP_START_INSTANCE:
 306         case PIPE_CAP_NPOT_TEXTURES:
 307         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 308         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 309         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 310         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 311         case PIPE_CAP_TGSI_INSTANCEID:
 312         case PIPE_CAP_COMPUTE:
 313         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 314         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 315         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 316         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 317         case PIPE_CAP_CUBE_MAP_ARRAY:
 318         case PIPE_CAP_SAMPLE_SHADING:
 319         case PIPE_CAP_DRAW_INDIRECT:
 320         case PIPE_CAP_CLIP_HALFZ:
 321         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 322         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 323         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 324         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 325         case PIPE_CAP_TGSI_TEXCOORD:
 326         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 327         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 328         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 329         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 330         case PIPE_CAP_SHAREABLE_SHADERS:
 331         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 332         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 333         case PIPE_CAP_TEXTURE_QUERY_LOD:
 334         case PIPE_CAP_TEXTURE_GATHER_SM5:
 335         case PIPE_CAP_TGSI_TXQS:
 336         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 337         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 338         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 339         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 340         case PIPE_CAP_INVALIDATE_BUFFER:
 341         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 342         case PIPE_CAP_QUERY_MEMORY_INFO:
 343         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 344         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 345         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 346                 return 1;
 347
 348         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 349                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 350
 351         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 352                 return (sscreen->b.info.drm_major == 2 &&
 353                         sscreen->b.info.drm_minor >= 43) ||
 354                        sscreen->b.info.drm_major == 3;
 355
 356         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 357                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 358                 return sscreen->b.chip_class < CIK ||
 359                        (sscreen->b.info.drm_major == 2 &&
 360                         sscreen->b.info.drm_minor >= 35) ||
 361                        sscreen->b.info.drm_major == 3;
 362
 363         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 364                 return R600_MAP_BUFFER_ALIGNMENT;
 365
 366         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 367         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 368         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 369                 return 4;
 370         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 371                 return HAVE_LLVM >= 0x0309 ? 4 : 0;
 372
 373         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 374                 if (pscreen->get_shader_param(pscreen, PIPE_SHADER_COMPUTE,
 375                                               PIPE_SHADER_CAP_SUPPORTED_IRS) &
 376                     (1 << PIPE_SHADER_IR_TGSI))
 377                         return 430;
 378                 return HAVE_LLVM >= 0x0309 ? 420 :
 379                        HAVE_LLVM >= 0x0307 ? 410 : 330;
 380
 381         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 382                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 383
 384         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 385                 return 0;
 386
 387         /* Unsupported features. */
 388         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 389         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 390         case PIPE_CAP_USER_VERTEX_BUFFERS:
 391         case PIPE_CAP_FAKE_SW_MSAA:
 392         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 393         case PIPE_CAP_VERTEXID_NOBASE:
 394         case PIPE_CAP_CLEAR_TEXTURE:
 395         case PIPE_CAP_DRAW_PARAMETERS:
 396         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 397         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 398         case PIPE_CAP_GENERATE_MIPMAP:
 399         case PIPE_CAP_STRING_MARKER:
 400         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 401         case PIPE_CAP_CULL_DISTANCE:
 402         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 403         case PIPE_CAP_TGSI_VOTE:
 404                 return 0;
 405
 406         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 407                 return 30;
 408
 409         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 410                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 411
 412         /* Stream output. */
 413         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 414                 return sscreen->b.has_streamout ? 4 : 0;
 415         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 416                 return sscreen->b.has_streamout ? 1 : 0;
 417         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 418         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 419                 return sscreen->b.has_streamout ? 32*4 : 0;
 420
 421         /* Geometry shader output. */
 422         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 423                 return 1024;
 424         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 425                 return 4095;
 426         case PIPE_CAP_MAX_VERTEX_STREAMS:
 427                 return 4;
 428
 429         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 430                 return 2048;
 431
 432         /* Texturing. */
 433         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 434         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 435                 return 15; /* 16384 */
 436         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 437                 /* textures support 8192, but layered rendering supports 2048 */
 438                 return 12;
 439         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 440                 /* textures support 8192, but layered rendering supports 2048 */
 441                 return 2048;
 442
 443         /* Render targets. */
 444         case PIPE_CAP_MAX_RENDER_TARGETS:
 445                 return 8;
 446
 447         case PIPE_CAP_MAX_VIEWPORTS:
 448                 return R600_MAX_VIEWPORTS;
 449
 450         /* Timer queries, present when the clock frequency is non zero. */
 451         case PIPE_CAP_QUERY_TIMESTAMP:
 452         case PIPE_CAP_QUERY_TIME_ELAPSED:
 453                 return sscreen->b.info.clock_crystal_freq != 0;
 454
 455         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 456         case PIPE_CAP_MIN_TEXEL_OFFSET:
 457                 return -32;
 458
 459         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 460         case PIPE_CAP_MAX_TEXEL_OFFSET:
 461                 return 31;
 462
 463         case PIPE_CAP_ENDIANNESS:
 464                 return PIPE_ENDIAN_LITTLE;
 465
 466         case PIPE_CAP_VENDOR_ID:
 467                 return ATI_VENDOR_ID;
 468         case PIPE_CAP_DEVICE_ID:
 469                 return sscreen->b.info.pci_id;
 470         case PIPE_CAP_ACCELERATED:
 471                 return 1;
 472         case PIPE_CAP_VIDEO_MEMORY:
 473                 return sscreen->b.info.vram_size >> 20;
 474         case PIPE_CAP_UMA:
 475                 return 0;
 476         case PIPE_CAP_PCI_GROUP:
 477                 return sscreen->b.info.pci_domain;
 478         case PIPE_CAP_PCI_BUS:
 479                 return sscreen->b.info.pci_bus;
 480         case PIPE_CAP_PCI_DEVICE:
 481                 return sscreen->b.info.pci_dev;
 482         case PIPE_CAP_PCI_FUNCTION:
 483                 return sscreen->b.info.pci_func;
 484         }
 485         return 0;
 486 }
 487
 488 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 489 {
 490         struct si_screen *sscreen = (struct si_screen *)pscreen;
 491
 492         switch(shader)
 493         {
 494         case PIPE_SHADER_FRAGMENT:
 495         case PIPE_SHADER_VERTEX:
 496         case PIPE_SHADER_GEOMETRY:
 497                 break;
 498         case PIPE_SHADER_TESS_CTRL:
 499         case PIPE_SHADER_TESS_EVAL:
 500                 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
 501                 if (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2)
 502                         return 0;
 503                 break;
 504         case PIPE_SHADER_COMPUTE:
 505                 switch (param) {
 506                 case PIPE_SHADER_CAP_PREFERRED_IR:
 507                         return PIPE_SHADER_IR_NATIVE;
 508
 509                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 510                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 511
 512                         /* Old kernels disallowed some register writes for SI
 513                          * that are used for indirect dispatches. */
 514                         if (HAVE_LLVM >= 0x309 && (sscreen->b.chip_class >= CIK ||
 515                                                    sscreen->b.info.drm_major == 3 ||
 516                                                    (sscreen->b.info.drm_major == 2 &&
 517                                                     sscreen->b.info.drm_minor >= 45)))
 518                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 519
 520                         return ir;
 521                 }
 522                 case PIPE_SHADER_CAP_DOUBLES:
 523                         return HAVE_LLVM >= 0x0307;
 524
 525                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 526                         uint64_t max_const_buffer_size;
 527                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 528                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 529                                 &max_const_buffer_size);
 530                         return max_const_buffer_size;
 531                 }
 532                 default:
 533                         /* If compute shaders don't require a special value
 534                          * for this cap, we can return the same value we
 535                          * do for other shader types. */
 536                         break;
 537                 }
 538                 break;
 539         default:
 540                 return 0;
 541         }
 542
 543         switch (param) {
 544         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 545         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 546         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 547         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 548                 return 16384;
 549         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 550                 return 32;
 551         case PIPE_SHADER_CAP_MAX_INPUTS:
 552                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 553         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 554                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 555         case PIPE_SHADER_CAP_MAX_TEMPS:
 556                 return 256; /* Max native temporaries. */
 557         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 558                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 559         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 560                 return SI_NUM_CONST_BUFFERS;
 561         case PIPE_SHADER_CAP_MAX_PREDS:
 562                 return 0; /* FIXME */
 563         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 564                 return 1;
 565         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 566                 return 1;
 567         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 568                 /* Indirection of geometry shader input dimension is not
 569                  * handled yet
 570                  */
 571                 return shader != PIPE_SHADER_GEOMETRY;
 572         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 573         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 574         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 575                 return 1;
 576         case PIPE_SHADER_CAP_INTEGERS:
 577                 return 1;
 578         case PIPE_SHADER_CAP_SUBROUTINES:
 579                 return 0;
 580         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 581         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 582                 return SI_NUM_SAMPLERS;
 583         case PIPE_SHADER_CAP_PREFERRED_IR:
 584                 return PIPE_SHADER_IR_TGSI;
 585         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 586                 return 0;
 587         case PIPE_SHADER_CAP_DOUBLES:
 588                 return HAVE_LLVM >= 0x0307;
 589         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 590         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 591                 return 0;
 592         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 593         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 594                 return 1;
 595         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 596                 return 32;
 597         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 598                 return HAVE_LLVM >= 0x0309 ? SI_NUM_SHADER_BUFFERS : 0;
 599         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 600                 return HAVE_LLVM >= 0x0309 ? SI_NUM_IMAGES : 0;
 601         }
 602         return 0;
 603 }
 604
 605 static void si_destroy_screen(struct pipe_screen* pscreen)
 606 {
 607         struct si_screen *sscreen = (struct si_screen *)pscreen;
 608         struct si_shader_part *parts[] = {
 609                 sscreen->vs_prologs,
 610                 sscreen->vs_epilogs,
 611                 sscreen->tcs_epilogs,
 612                 sscreen->ps_prologs,
 613                 sscreen->ps_epilogs
 614         };
 615         unsigned i;
 616
 617         if (!sscreen)
 618                 return;
 619
 620         if (!sscreen->b.ws->unref(sscreen->b.ws))
 621                 return;
 622
 623         /* Free shader parts. */
 624         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 625                 while (parts[i]) {
 626                         struct si_shader_part *part = parts[i];
 627
 628                         parts[i] = part->next;
 629                         radeon_shader_binary_clean(&part->binary);
 630                         FREE(part);
 631                 }
 632         }
 633         pipe_mutex_destroy(sscreen->shader_parts_mutex);
 634         si_destroy_shader_cache(sscreen);
 635         r600_destroy_common_screen(&sscreen->b);
 636 }
 637
 638 static bool si_init_gs_info(struct si_screen *sscreen)
 639 {
 640         switch (sscreen->b.family) {
 641         case CHIP_OLAND:
 642         case CHIP_HAINAN:
 643         case CHIP_KAVERI:
 644         case CHIP_KABINI:
 645         case CHIP_MULLINS:
 646         case CHIP_ICELAND:
 647         case CHIP_CARRIZO:
 648         case CHIP_STONEY:
 649                 sscreen->gs_table_depth = 16;
 650                 return true;
 651         case CHIP_TAHITI:
 652         case CHIP_PITCAIRN:
 653         case CHIP_VERDE:
 654         case CHIP_BONAIRE:
 655         case CHIP_HAWAII:
 656         case CHIP_TONGA:
 657         case CHIP_FIJI:
 658         case CHIP_POLARIS10:
 659         case CHIP_POLARIS11:
 660                 sscreen->gs_table_depth = 32;
 661                 return true;
 662         default:
 663                 return false;
 664         }
 665 }
 666
 667 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 668 {
 669         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 670
 671         if (!sscreen) {
 672                 return NULL;
 673         }
 674
 675         /* Set functions first. */
 676         sscreen->b.b.context_create = si_create_context;
 677         sscreen->b.b.destroy = si_destroy_screen;
 678         sscreen->b.b.get_param = si_get_param;
 679         sscreen->b.b.get_shader_param = si_get_shader_param;
 680         sscreen->b.b.is_format_supported = si_is_format_supported;
 681         sscreen->b.b.resource_create = r600_resource_create_common;
 682
 683         si_init_screen_state_functions(sscreen);
 684
 685         if (!r600_common_screen_init(&sscreen->b, ws) ||
 686             !si_init_gs_info(sscreen) ||
 687             !si_init_shader_cache(sscreen)) {
 688                 FREE(sscreen);
 689                 return NULL;
 690         }
 691
 692         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", FALSE))
 693                 si_init_perfcounters(sscreen);
 694
 695         sscreen->b.has_cp_dma = true;
 696         sscreen->b.has_streamout = true;
 697         pipe_mutex_init(sscreen->shader_parts_mutex);
 698         sscreen->use_monolithic_shaders =
 699                 HAVE_LLVM < 0x0308 ||
 700                 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
 701
 702         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 703                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 704
 705         /* Create the auxiliary context. This must be done last. */
 706         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
 707
 708         if (sscreen->b.debug_flags & DBG_TEST_DMA)
 709                 r600_test_dma(&sscreen->b);
 710
 711         return &sscreen->b.b;
 712 }