2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "si_shader.h"
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
38 #define SI_BIG_ENDIAN 0
41 #define ATI_VENDOR_ID 0x1002
42 #define SI_PRIM_DISCARD_DEBUG 0
43 #define SI_NOT_QUERY 0xffffffff
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_MAX_POINT_SIZE 2048
53 #define SI_GS_PER_ES 128
54 /* Alignment for optimal CP DMA performance. */
55 #define SI_CPDMA_ALIGNMENT 32
57 /* Tunables for compute-based clear_buffer and copy_buffer: */
58 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
59 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
60 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
62 /* Pipeline & streamout query controls. */
63 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
64 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
65 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
66 /* Instruction cache. */
67 #define SI_CONTEXT_INV_ICACHE (1 << 3)
68 /* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0)
69 * GFX10: This also invalidates the L1 shader array cache. */
70 #define SI_CONTEXT_INV_SCACHE (1 << 4)
71 /* Vector cache. (GFX6-9: vector L1; GFX10: vector L0)
72 * GFX10: This also invalidates the L1 shader array cache. */
73 #define SI_CONTEXT_INV_VCACHE (1 << 5)
74 /* L2 cache + L2 metadata cache writeback & invalidate.
75 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
76 #define SI_CONTEXT_INV_L2 (1 << 6)
77 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
78 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
79 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
80 #define SI_CONTEXT_WB_L2 (1 << 7)
81 /* Writeback & invalidate the L2 metadata cache only. It can only be coupled with
82 * a CB or DB flush. */
83 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
84 /* Framebuffer caches. */
85 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
86 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
87 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
88 /* Engine synchronization. */
89 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
90 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
91 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
92 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
93 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
95 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
96 #define SI_PREFETCH_LS (1 << 1)
97 #define SI_PREFETCH_HS (1 << 2)
98 #define SI_PREFETCH_ES (1 << 3)
99 #define SI_PREFETCH_GS (1 << 4)
100 #define SI_PREFETCH_VS (1 << 5)
101 #define SI_PREFETCH_PS (1 << 6)
103 #define SI_MAX_BORDER_COLORS 4096
104 #define SI_MAX_VIEWPORTS 16
105 #define SIX_BITS 0x3F
106 #define SI_MAP_BUFFER_ALIGNMENT 64
107 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
109 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
110 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
111 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
112 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
113 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
114 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
115 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
116 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
117 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
118 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
122 DCC_CLEAR_COLOR_0000
= 0x00000000,
123 DCC_CLEAR_COLOR_0001
= 0x40404040,
124 DCC_CLEAR_COLOR_1110
= 0x80808080,
125 DCC_CLEAR_COLOR_1111
= 0xC0C0C0C0,
126 DCC_CLEAR_COLOR_REG
= 0x20202020,
127 DCC_UNCOMPRESSED
= 0xFFFFFFFF,
130 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
134 /* Shader logging options: */
135 DBG_VS
= PIPE_SHADER_VERTEX
,
136 DBG_PS
= PIPE_SHADER_FRAGMENT
,
137 DBG_GS
= PIPE_SHADER_GEOMETRY
,
138 DBG_TCS
= PIPE_SHADER_TESS_CTRL
,
139 DBG_TES
= PIPE_SHADER_TESS_EVAL
,
140 DBG_CS
= PIPE_SHADER_COMPUTE
,
146 /* Shader compiler options the shader cache should be aware of: */
147 DBG_FS_CORRECT_DERIVS_AFTER_KILL
,
157 /* Shader compiler options (with no effect on the shader cache): */
159 DBG_MONOLITHIC_SHADERS
,
162 /* Information logging options: */
168 /* Driver options: */
176 /* 3D engine options: */
200 DBG_TEST_VMFAULT_SDMA
,
201 DBG_TEST_VMFAULT_SHADER
,
208 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
209 #define DBG(name) (1ull << DBG_##name)
211 enum si_cache_policy
{
213 L2_STREAM
, /* same as SLC=1 */
214 L2_LRU
, /* same as SLC=0 */
218 SI_COHERENCY_NONE
, /* no cache flushes needed */
220 SI_COHERENCY_CB_META
,
225 struct si_shader_context
;
227 struct u_suballocator
;
229 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
233 struct threaded_resource b
;
235 /* Winsys objects. */
236 struct pb_buffer
*buf
;
237 uint64_t gpu_address
;
238 /* Memory usage if the buffer placement is optimal. */
242 /* Resource properties. */
244 unsigned bo_alignment
;
245 enum radeon_bo_domain domains
;
246 enum radeon_bo_flag flags
;
247 unsigned bind_history
;
248 int max_forced_staging_uploads
;
250 /* The buffer range which is initialized (with a write transfer,
251 * streamout, DMA, or as a random access target). The rest of
252 * the buffer is considered invalid and can be mapped unsynchronized.
254 * This allows unsychronized mapping of a buffer range which hasn't
255 * been used yet. It's for applications which forget to use
256 * the unsynchronized map flag and expect the driver to figure it out.
258 struct util_range valid_buffer_range
;
260 /* For buffers only. This indicates that a write operation has been
261 * performed by TC L2, but the cache hasn't been flushed.
262 * Any hw block which doesn't use or bypasses TC L2 should check this
263 * flag and flush the cache before using the buffer.
265 * For example, TC L2 must be flushed if a buffer which has been
266 * modified by a shader store instruction is about to be used as
267 * an index buffer. The reason is that VGT DMA index fetching doesn't
272 /* Whether this resource is referenced by bindless handles. */
273 bool texture_handle_allocated
;
274 bool image_handle_allocated
;
276 /* Whether the resource has been exported via resource_get_handle. */
277 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
281 struct threaded_transfer b
;
282 struct si_resource
*staging
;
287 struct si_resource buffer
;
289 struct radeon_surf surface
;
291 struct si_texture
*flushed_depth_texture
;
293 /* One texture allocation can contain these buffers:
294 * - image (pixel data)
295 * - FMASK buffer (MSAA compression)
296 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
297 * - HTILE buffer (Z/S compression and fast Z/S clear)
298 * - DCC buffer (color compression and new fast color clear)
299 * - displayable DCC buffer (if the DCC buffer is not displayable)
300 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
302 uint64_t fmask_offset
;
303 uint64_t cmask_offset
;
304 uint64_t cmask_base_address_reg
;
305 struct si_resource
*cmask_buffer
;
306 uint64_t dcc_offset
; /* 0 = disabled */
307 uint64_t display_dcc_offset
;
308 uint64_t dcc_retile_map_offset
;
309 unsigned cb_color_info
; /* fast clear enable bit */
310 unsigned color_clear_value
[2];
311 unsigned last_msaa_resolve_target_micro_mode
;
312 unsigned num_level0_transfers
;
314 /* Depth buffer compression and fast clear. */
315 uint64_t htile_offset
;
316 float depth_clear_value
;
317 uint16_t dirty_level_mask
; /* each bit says if that mipmap is compressed */
318 uint16_t stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
319 enum pipe_format db_render_format
:16;
320 uint8_t stencil_clear_value
;
321 bool tc_compatible_htile
:1;
322 bool htile_stencil_disabled
:1;
323 bool depth_cleared
:1; /* if it was cleared at least once */
324 bool stencil_cleared
:1; /* if it was cleared at least once */
325 bool upgraded_depth
:1; /* upgraded from unorm to Z32_FLOAT */
327 bool db_compatible
:1;
331 /* We need to track DCC dirtiness, because st/dri usually calls
332 * flush_resource twice per frame (not a bug) and we don't wanna
333 * decompress DCC twice. Also, the dirty tracking must be done even
334 * if DCC isn't used, because it's required by the DCC usage analysis
335 * for a possible future enablement.
337 bool separate_dcc_dirty
:1;
338 /* Statistics gathering for the DCC enablement heuristic. */
339 bool dcc_gather_statistics
:1;
340 /* Counter that should be non-zero if the texture is bound to a
343 unsigned framebuffers_bound
;
344 /* Whether the texture is a displayable back buffer and needs DCC
345 * decompression, which is expensive. Therefore, it's enabled only
346 * if statistics suggest that it will pay off and it's allocated
347 * separately. It can't be bound as a sampler by apps. Limited to
348 * target == 2D and last_level == 0. If enabled, dcc_offset contains
349 * the absolute GPUVM address, not the relative one.
351 struct si_resource
*dcc_separate_buffer
;
352 /* When DCC is temporarily disabled, the separate buffer is here. */
353 struct si_resource
*last_dcc_separate_buffer
;
354 /* Estimate of how much this color buffer is written to in units of
355 * full-screen draws: ps_invocations / (width * height)
356 * Shader kills, late Z, and blending with trivial discards make it
357 * inaccurate (we need to count CB updates, not PS invocations).
359 unsigned ps_draw_ratio
;
360 /* The number of clears since the last DCC usage analysis. */
361 unsigned num_slow_clears
;
365 struct pipe_surface base
;
367 /* These can vary with block-compressed textures. */
371 bool color_initialized
:1;
372 bool depth_initialized
:1;
374 /* Misc. color flags. */
375 bool color_is_int8
:1;
376 bool color_is_int10
:1;
377 bool dcc_incompatible
:1;
379 /* Color registers. */
380 unsigned cb_color_info
;
381 unsigned cb_color_view
;
382 unsigned cb_color_attrib
;
383 unsigned cb_color_attrib2
; /* GFX9 and later */
384 unsigned cb_color_attrib3
; /* GFX10 and later */
385 unsigned cb_dcc_control
; /* GFX8 and later */
386 unsigned spi_shader_col_format
:8; /* no blending, no alpha-to-coverage. */
387 unsigned spi_shader_col_format_alpha
:8; /* alpha-to-coverage */
388 unsigned spi_shader_col_format_blend
:8; /* blending without alpha. */
389 unsigned spi_shader_col_format_blend_alpha
:8; /* blending with alpha. */
392 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE */
393 uint64_t db_stencil_base
;
394 uint64_t db_htile_data_base
;
395 unsigned db_depth_info
;
397 unsigned db_z_info2
; /* GFX9 only */
398 unsigned db_depth_view
;
399 unsigned db_depth_size
;
400 unsigned db_depth_slice
;
401 unsigned db_stencil_info
;
402 unsigned db_stencil_info2
; /* GFX9 only */
403 unsigned db_htile_surface
;
406 struct si_mmio_counter
{
411 union si_mmio_counters
{
413 /* For global GPU load including SDMA. */
414 struct si_mmio_counter gpu
;
417 struct si_mmio_counter spi
;
418 struct si_mmio_counter gui
;
419 struct si_mmio_counter ta
;
420 struct si_mmio_counter gds
;
421 struct si_mmio_counter vgt
;
422 struct si_mmio_counter ia
;
423 struct si_mmio_counter sx
;
424 struct si_mmio_counter wd
;
425 struct si_mmio_counter bci
;
426 struct si_mmio_counter sc
;
427 struct si_mmio_counter pa
;
428 struct si_mmio_counter db
;
429 struct si_mmio_counter cp
;
430 struct si_mmio_counter cb
;
433 struct si_mmio_counter sdma
;
436 struct si_mmio_counter pfp
;
437 struct si_mmio_counter meq
;
438 struct si_mmio_counter me
;
439 struct si_mmio_counter surf_sync
;
440 struct si_mmio_counter cp_dma
;
441 struct si_mmio_counter scratch_ram
;
446 struct si_memory_object
{
447 struct pipe_memory_object b
;
448 struct pb_buffer
*buf
;
452 /* Saved CS data for debugging features. */
453 struct radeon_saved_cs
{
457 struct radeon_bo_list_item
*bo_list
;
462 struct pipe_screen b
;
463 struct radeon_winsys
*ws
;
464 struct disk_cache
*disk_shader_cache
;
466 struct radeon_info info
;
467 uint64_t debug_flags
;
468 char renderer_string
[183];
470 void (*make_texture_descriptor
)(
471 struct si_screen
*screen
,
472 struct si_texture
*tex
,
474 enum pipe_texture_target target
,
475 enum pipe_format pipe_format
,
476 const unsigned char state_swizzle
[4],
477 unsigned first_level
, unsigned last_level
,
478 unsigned first_layer
, unsigned last_layer
,
479 unsigned width
, unsigned height
, unsigned depth
,
481 uint32_t *fmask_state
);
483 unsigned pa_sc_raster_config
;
484 unsigned pa_sc_raster_config_1
;
485 unsigned se_tile_repeat
;
486 unsigned gs_table_depth
;
487 unsigned tess_offchip_block_dw_size
;
488 unsigned tess_offchip_ring_size
;
489 unsigned tess_factor_ring_size
;
490 unsigned vgt_hs_offchip_param
;
491 unsigned eqaa_force_coverage_samples
;
492 unsigned eqaa_force_z_samples
;
493 unsigned eqaa_force_color_samples
;
494 bool has_draw_indirect_multi
;
495 bool has_out_of_order_rast
;
496 bool assume_no_z_fights
;
497 bool commutative_blend_add
;
498 bool has_gfx9_scissor_bug
;
499 bool has_msaa_sample_loc_bug
;
500 bool has_ls_vgpr_init_bug
;
503 bool llvm_has_working_vgpr_indexing
;
505 bool use_ngg_streamout
;
508 #define OPT_BOOL(name, dflt, description) bool name:1;
509 #include "si_debug_options.h"
512 /* Whether shaders are monolithic (1-part) or separate (3-part). */
513 bool use_monolithic_shaders
;
515 bool rbplus_allowed
; /* if RB+ is allowed */
516 bool dcc_msaa_allowed
;
517 bool cpdma_prefetch_writes_memory
;
519 struct slab_parent_pool pool_transfers
;
521 /* Texture filter settings. */
522 int force_aniso
; /* -1 = disabled */
524 /* Auxiliary context. Mainly used to initialize resources.
525 * It must be locked prior to using and flushed before unlocking. */
526 struct pipe_context
*aux_context
;
527 mtx_t aux_context_lock
;
529 /* This must be in the screen, because UE4 uses one context for
530 * compilation and another one for rendering.
532 unsigned num_compilations
;
533 /* Along with ST_DEBUG=precompile, this should show if applications
534 * are loading shaders on demand. This is a monotonic counter.
536 unsigned num_shaders_created
;
537 unsigned num_shader_cache_hits
;
539 /* GPU load thread. */
540 mtx_t gpu_load_mutex
;
541 thrd_t gpu_load_thread
;
542 union si_mmio_counters mmio_counters
;
543 volatile unsigned gpu_load_stop_thread
; /* bool */
545 /* Performance counters. */
546 struct si_perfcounters
*perfcounters
;
548 /* If pipe_screen wants to recompute and re-emit the framebuffer,
549 * sampler, and image states of all contexts, it should atomically
552 * Each context will compare this with its own last known value of
553 * the counter before drawing and re-emit the states accordingly.
555 unsigned dirty_tex_counter
;
556 unsigned dirty_buf_counter
;
558 /* Atomically increment this counter when an existing texture's
559 * metadata is enabled or disabled in a way that requires changing
560 * contexts' compressed texture binding masks.
562 unsigned compressed_colortex_counter
;
565 /* Context flags to set so that all writes from earlier jobs
566 * in the CP are seen by L2 clients.
570 /* Context flags to set so that all writes from earlier jobs
571 * that end in L2 are seen by CP.
576 mtx_t shader_parts_mutex
;
577 struct si_shader_part
*vs_prologs
;
578 struct si_shader_part
*tcs_epilogs
;
579 struct si_shader_part
*gs_prologs
;
580 struct si_shader_part
*ps_prologs
;
581 struct si_shader_part
*ps_epilogs
;
583 /* Shader cache in memory.
585 * Design & limitations:
586 * - The shader cache is per screen (= per process), never saved to
587 * disk, and skips redundant shader compilations from TGSI to bytecode.
588 * - It can only be used with one-variant-per-shader support, in which
589 * case only the main (typically middle) part of shaders is cached.
590 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
591 * variants of VS and TES are cached, so LS and ES aren't.
592 * - GS and CS aren't cached, but it's certainly possible to cache
595 mtx_t shader_cache_mutex
;
596 struct hash_table
*shader_cache
;
598 /* Shader compiler queue for multithreaded compilation. */
599 struct util_queue shader_compiler_queue
;
600 /* Use at most 3 normal compiler threads on quadcore and better.
601 * Hyperthreaded CPUs report the number of threads, but we want
602 * the number of cores. We only need this many threads for shader-db. */
603 struct ac_llvm_compiler compiler
[24]; /* used by the queue only */
605 struct util_queue shader_compiler_queue_low_priority
;
606 /* Use at most 2 low priority threads on quadcore and better.
607 * We want to minimize the impact on multithreaded Mesa. */
608 struct ac_llvm_compiler compiler_lowp
[10];
610 unsigned compute_wave_size
;
611 unsigned ps_wave_size
;
612 unsigned ge_wave_size
;
615 struct si_blend_color
{
616 struct pipe_blend_color state
;
620 struct si_sampler_view
{
621 struct pipe_sampler_view base
;
622 /* [0..7] = image descriptor
623 * [4..7] = buffer descriptor */
625 uint32_t fmask_state
[8];
626 const struct legacy_surf_level
*base_level_info
;
629 bool is_stencil_sampler
;
631 bool dcc_incompatible
;
634 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
636 struct si_sampler_state
{
641 uint32_t integer_val
[4];
642 uint32_t upgraded_depth_val
[4];
645 struct si_cs_shader_state
{
646 struct si_compute
*program
;
647 struct si_compute
*emitted_program
;
654 struct pipe_sampler_view
*views
[SI_NUM_SAMPLERS
];
655 struct si_sampler_state
*sampler_states
[SI_NUM_SAMPLERS
];
657 /* The i-th bit is set if that element is enabled (non-NULL resource). */
658 unsigned enabled_mask
;
659 uint32_t needs_depth_decompress_mask
;
660 uint32_t needs_color_decompress_mask
;
664 struct pipe_image_view views
[SI_NUM_IMAGES
];
665 uint32_t needs_color_decompress_mask
;
666 unsigned enabled_mask
;
669 struct si_framebuffer
{
670 struct pipe_framebuffer_state state
;
671 unsigned colorbuf_enabled_4bit
;
672 unsigned spi_shader_col_format
;
673 unsigned spi_shader_col_format_alpha
;
674 unsigned spi_shader_col_format_blend
;
675 unsigned spi_shader_col_format_blend_alpha
;
676 ubyte nr_samples
:5; /* at most 16xAA */
677 ubyte log_samples
:3; /* at most 4 = 16xAA */
678 ubyte nr_color_samples
; /* at most 8xAA */
679 ubyte compressed_cb_mask
;
680 ubyte uncompressed_cb_mask
;
682 ubyte color_is_int10
;
684 ubyte dcc_overwrite_combiner_watermark
;
685 ubyte min_bytes_per_pixel
;
688 bool CB_has_shader_readable_metadata
;
689 bool DB_has_shader_readable_metadata
;
690 bool all_DCC_pipe_aligned
;
694 /* This is the list we want to support. */
695 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH
,
696 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH
,
697 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH
,
700 struct si_signed_scissor
{
705 enum si_quant_mode quant_mode
;
708 struct si_viewports
{
709 struct pipe_viewport_state states
[SI_MAX_VIEWPORTS
];
710 struct si_signed_scissor as_scissor
[SI_MAX_VIEWPORTS
];
714 struct si_clip_state
{
715 struct pipe_clip_state state
;
719 struct si_streamout_target
{
720 struct pipe_stream_output_target b
;
722 /* The buffer where BUFFER_FILLED_SIZE is stored. */
723 struct si_resource
*buf_filled_size
;
724 unsigned buf_filled_size_offset
;
725 bool buf_filled_size_valid
;
727 unsigned stride_in_dw
;
730 struct si_streamout
{
733 unsigned enabled_mask
;
734 unsigned num_targets
;
735 struct si_streamout_target
*targets
[PIPE_MAX_SO_BUFFERS
];
737 unsigned append_bitmask
;
740 /* External state which comes from the vertex shader,
741 * it must be set explicitly when binding a shader. */
742 uint16_t *stride_in_dw
;
743 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
745 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
746 unsigned hw_enabled_mask
;
748 /* The state of VGT_STRMOUT_(CONFIG|EN). */
749 bool streamout_enabled
;
750 bool prims_gen_query_enabled
;
751 int num_prims_gen_queries
;
754 /* A shader state consists of the shader selector, which is a constant state
755 * object shared by multiple contexts and shouldn't be modified, and
756 * the current shader variant selected for this context.
758 struct si_shader_ctx_state
{
759 struct si_shader_selector
*cso
;
760 struct si_shader
*current
;
763 #define SI_NUM_VGT_PARAM_KEY_BITS 12
764 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
766 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
767 * Some fields are set by state-change calls, most are set by draw_vbo.
769 union si_vgt_param_key
{
771 #ifdef PIPE_ARCH_LITTLE_ENDIAN
773 unsigned uses_instancing
:1;
774 unsigned multi_instances_smaller_than_primgroup
:1;
775 unsigned primitive_restart
:1;
776 unsigned count_from_stream_output
:1;
777 unsigned line_stipple_enabled
:1;
778 unsigned uses_tess
:1;
779 unsigned tess_uses_prim_id
:1;
781 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
782 #else /* PIPE_ARCH_BIG_ENDIAN */
783 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
785 unsigned tess_uses_prim_id
:1;
786 unsigned uses_tess
:1;
787 unsigned line_stipple_enabled
:1;
788 unsigned count_from_stream_output
:1;
789 unsigned primitive_restart
:1;
790 unsigned multi_instances_smaller_than_primgroup
:1;
791 unsigned uses_instancing
:1;
798 #define SI_NUM_VGT_STAGES_KEY_BITS 4
799 #define SI_NUM_VGT_STAGES_STATES (1 << SI_NUM_VGT_STAGES_KEY_BITS)
801 /* The VGT_SHADER_STAGES key used to index the table of precomputed values.
802 * Some fields are set by state-change calls, most are set by draw_vbo.
804 union si_vgt_stages_key
{
806 #ifdef PIPE_ARCH_LITTLE_ENDIAN
809 unsigned ngg
:1; /* gfx10+ */
810 unsigned streamout
:1; /* only used with NGG */
811 unsigned _pad
:32 - SI_NUM_VGT_STAGES_KEY_BITS
;
812 #else /* PIPE_ARCH_BIG_ENDIAN */
813 unsigned _pad
:32 - SI_NUM_VGT_STAGES_KEY_BITS
;
814 unsigned streamout
:1;
823 struct si_texture_handle
827 struct pipe_sampler_view
*view
;
828 struct si_sampler_state sstate
;
831 struct si_image_handle
835 struct pipe_image_view view
;
839 struct pipe_reference reference
;
840 struct si_context
*ctx
;
841 struct radeon_saved_cs gfx
;
842 struct radeon_saved_cs compute
;
843 struct si_resource
*trace_buf
;
846 unsigned gfx_last_dw
;
847 unsigned compute_last_dw
;
852 struct si_sdma_upload
{
853 struct si_resource
*dst
;
854 struct si_resource
*src
;
861 struct pipe_context b
; /* base class */
863 enum radeon_family family
;
864 enum chip_class chip_class
;
866 struct radeon_winsys
*ws
;
867 struct radeon_winsys_ctx
*ctx
;
868 struct radeon_cmdbuf
*gfx_cs
; /* compute IB if graphics is disabled */
869 struct radeon_cmdbuf
*dma_cs
;
870 struct pipe_fence_handle
*last_gfx_fence
;
871 struct pipe_fence_handle
*last_sdma_fence
;
872 struct si_resource
*eop_bug_scratch
;
873 struct u_upload_mgr
*cached_gtt_allocator
;
874 struct threaded_context
*tc
;
875 struct u_suballocator
*allocator_zeroed_memory
;
876 struct slab_child_pool pool_transfers
;
877 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
878 struct pipe_device_reset_callback device_reset_callback
;
879 struct u_log_context
*log
;
880 void *query_result_shader
;
881 void *sh_query_result_shader
;
883 void (*emit_cache_flush
)(struct si_context
*ctx
);
885 struct blitter_context
*blitter
;
888 void *discard_rasterizer_state
;
889 void *custom_dsa_flush
;
890 void *custom_blend_resolve
;
891 void *custom_blend_fmask_decompress
;
892 void *custom_blend_eliminate_fastclear
;
893 void *custom_blend_dcc_decompress
;
895 void *vs_blit_pos_layered
;
897 void *vs_blit_color_layered
;
898 void *vs_blit_texcoord
;
899 void *cs_clear_buffer
;
900 void *cs_copy_buffer
;
902 void *cs_copy_image_1d_array
;
903 void *cs_clear_render_target
;
904 void *cs_clear_render_target_1d_array
;
906 struct si_screen
*screen
;
907 struct pipe_debug_callback debug
;
908 struct ac_llvm_compiler compiler
; /* only non-threaded compilation */
909 struct si_shader_ctx_state fixed_func_tcs_shader
;
910 /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
911 struct si_resource
*wait_mem_scratch
;
912 unsigned wait_mem_number
;
913 uint16_t prefetch_L2_mask
;
916 bool gfx_flush_in_progress
:1;
917 bool gfx_last_ib_is_busy
:1;
918 bool compute_is_busy
:1;
920 unsigned num_gfx_cs_flushes
;
921 unsigned initial_gfx_cs_size
;
922 unsigned last_dirty_tex_counter
;
923 unsigned last_dirty_buf_counter
;
924 unsigned last_compressed_colortex_counter
;
925 unsigned last_num_draw_calls
;
926 unsigned flags
; /* flush flags */
927 /* Current unaccounted memory usage. */
931 /* Compute-based primitive discard. */
932 unsigned prim_discard_vertex_count_threshold
;
933 struct pb_buffer
*gds
;
934 struct pb_buffer
*gds_oa
;
935 struct radeon_cmdbuf
*prim_discard_compute_cs
;
936 unsigned compute_gds_offset
;
937 struct si_shader
*compute_ib_last_shader
;
938 uint32_t compute_rewind_va
;
939 unsigned compute_num_prims_in_batch
;
940 bool preserve_prim_restart_gds_at_flush
;
941 /* index_ring is divided into 2 halves for doublebuffering. */
942 struct si_resource
*index_ring
;
943 unsigned index_ring_base
; /* offset of a per-IB portion */
944 unsigned index_ring_offset
; /* offset within a per-IB portion */
945 unsigned index_ring_size_per_ib
; /* max available size per IB */
946 bool prim_discard_compute_ib_initialized
;
947 /* For tracking the last execution barrier - it can be either
948 * a WRITE_DATA packet or a fence. */
949 uint32_t *last_pkt3_write_data
;
950 struct si_resource
*barrier_buf
;
951 unsigned barrier_buf_offset
;
952 struct pipe_fence_handle
*last_ib_barrier_fence
;
953 struct si_resource
*last_ib_barrier_buf
;
954 unsigned last_ib_barrier_buf_offset
;
956 /* Atoms (direct states). */
957 union si_state_atoms atoms
;
958 unsigned dirty_atoms
; /* mask */
959 /* PM4 states (precomputed immutable states) */
960 unsigned dirty_states
;
961 union si_state queued
;
962 union si_state emitted
;
964 /* Atom declarations. */
965 struct si_framebuffer framebuffer
;
966 unsigned sample_locs_num_samples
;
967 uint16_t sample_mask
;
968 unsigned last_cb_target_mask
;
969 struct si_blend_color blend_color
;
970 struct si_clip_state clip_state
;
971 struct si_shader_data shader_pointers
;
972 struct si_stencil_ref stencil_ref
;
973 struct pipe_scissor_state scissors
[SI_MAX_VIEWPORTS
];
974 struct si_streamout streamout
;
975 struct si_viewports viewports
;
976 unsigned num_window_rectangles
;
977 bool window_rectangles_include
;
978 struct pipe_scissor_state window_rectangles
[4];
980 /* Precomputed states. */
981 struct si_pm4_state
*init_config
;
982 struct si_pm4_state
*init_config_gs_rings
;
983 bool init_config_has_vgt_flush
;
984 struct si_pm4_state
*vgt_shader_config
[SI_NUM_VGT_STAGES_STATES
];
987 struct si_shader_ctx_state ps_shader
;
988 struct si_shader_ctx_state gs_shader
;
989 struct si_shader_ctx_state vs_shader
;
990 struct si_shader_ctx_state tcs_shader
;
991 struct si_shader_ctx_state tes_shader
;
992 struct si_shader_ctx_state cs_prim_discard_state
;
993 struct si_cs_shader_state cs_shader_state
;
995 /* shader information */
996 struct si_vertex_elements
*vertex_elements
;
997 unsigned sprite_coord_enable
;
998 unsigned cs_max_waves_per_sh
;
1000 bool do_update_shaders
;
1002 /* vertex buffer descriptors */
1003 uint32_t *vb_descriptors_gpu_list
;
1004 struct si_resource
*vb_descriptors_buffer
;
1005 unsigned vb_descriptors_offset
;
1007 /* shader descriptors */
1008 struct si_descriptors descriptors
[SI_NUM_DESCS
];
1009 unsigned descriptors_dirty
;
1010 unsigned shader_pointers_dirty
;
1011 unsigned shader_needs_decompress_mask
;
1012 struct si_buffer_resources rw_buffers
;
1013 struct si_buffer_resources const_and_shader_buffers
[SI_NUM_SHADERS
];
1014 struct si_samplers samplers
[SI_NUM_SHADERS
];
1015 struct si_images images
[SI_NUM_SHADERS
];
1016 bool bo_list_add_all_resident_resources
;
1017 bool bo_list_add_all_gfx_resources
;
1018 bool bo_list_add_all_compute_resources
;
1020 /* other shader resources */
1021 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on GFX7 */
1022 struct pipe_resource
*esgs_ring
;
1023 struct pipe_resource
*gsvs_ring
;
1024 struct pipe_resource
*tess_rings
;
1025 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
1026 struct si_resource
*border_color_buffer
;
1027 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
1028 unsigned border_color_count
;
1029 unsigned num_vs_blit_sgprs
;
1030 uint32_t vs_blit_sh_data
[SI_VS_BLIT_SGPRS_POS_TEXCOORD
];
1031 uint32_t cs_user_data
[4];
1033 /* Vertex and index buffers. */
1034 bool vertex_buffers_dirty
;
1035 bool vertex_buffer_pointer_dirty
;
1036 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
1037 uint16_t vertex_buffer_unaligned
; /* bitmask of not dword-aligned buffers */
1039 /* MSAA config state. */
1040 int ps_iter_samples
;
1041 bool ps_uses_fbfetch
;
1042 bool smoothing_enabled
;
1044 /* DB render state. */
1045 unsigned ps_db_shader_control
;
1046 unsigned dbcb_copy_sample
;
1047 bool dbcb_depth_copy_enabled
:1;
1048 bool dbcb_stencil_copy_enabled
:1;
1049 bool db_flush_depth_inplace
:1;
1050 bool db_flush_stencil_inplace
:1;
1051 bool db_depth_clear
:1;
1052 bool db_depth_disable_expclear
:1;
1053 bool db_stencil_clear
:1;
1054 bool db_stencil_disable_expclear
:1;
1055 bool occlusion_queries_disabled
:1;
1056 bool generate_mipmap_for_depth
:1;
1058 /* Emitted draw state. */
1059 bool gs_tri_strip_adj_fix
:1;
1061 bool prim_discard_cs_instancing
:1;
1063 int last_index_size
;
1064 int last_base_vertex
;
1065 int last_start_instance
;
1066 int last_instance_count
;
1068 int last_sh_base_reg
;
1069 int last_primitive_restart_en
;
1070 int last_restart_index
;
1072 int last_multi_vgt_param
;
1074 int last_flatshade_first
;
1075 int last_binning_enabled
;
1076 unsigned last_sc_line_stipple
;
1077 unsigned current_vs_state
;
1078 unsigned last_vs_state
;
1079 enum pipe_prim_type current_rast_prim
; /* primitive type after TES, GS */
1081 /* Scratch buffer */
1082 struct si_resource
*scratch_buffer
;
1083 unsigned scratch_waves
;
1084 unsigned spi_tmpring_size
;
1086 struct si_resource
*compute_scratch_buffer
;
1088 /* Emitted derived tessellation state. */
1089 /* Local shader (VS), or HS if LS-HS are merged. */
1090 struct si_shader
*last_ls
;
1091 struct si_shader_selector
*last_tcs
;
1092 int last_num_tcs_input_cp
;
1093 int last_tes_sh_base
;
1094 bool last_tess_uses_primid
;
1095 unsigned last_num_patches
;
1096 int last_ls_hs_config
;
1100 struct si_saved_cs
*current_saved_cs
;
1101 uint64_t dmesg_timestamp
;
1102 unsigned apitrace_call_number
;
1105 bool need_check_render_feedback
;
1106 bool decompression_enabled
;
1107 bool dpbb_force_off
;
1108 bool vs_writes_viewport_index
;
1109 bool vs_disables_clipping_viewport
;
1111 /* Precomputed IA_MULTI_VGT_PARAM */
1112 union si_vgt_param_key ia_multi_vgt_param_key
;
1113 unsigned ia_multi_vgt_param
[SI_NUM_VGT_PARAM_STATES
];
1115 /* Bindless descriptors. */
1116 struct si_descriptors bindless_descriptors
;
1117 struct util_idalloc bindless_used_slots
;
1118 unsigned num_bindless_descriptors
;
1119 bool bindless_descriptors_dirty
;
1120 bool graphics_bindless_pointer_dirty
;
1121 bool compute_bindless_pointer_dirty
;
1123 /* Allocated bindless handles */
1124 struct hash_table
*tex_handles
;
1125 struct hash_table
*img_handles
;
1127 /* Resident bindless handles */
1128 struct util_dynarray resident_tex_handles
;
1129 struct util_dynarray resident_img_handles
;
1131 /* Resident bindless handles which need decompression */
1132 struct util_dynarray resident_tex_needs_color_decompress
;
1133 struct util_dynarray resident_img_needs_color_decompress
;
1134 struct util_dynarray resident_tex_needs_depth_decompress
;
1136 /* Bindless state */
1137 bool uses_bindless_samplers
;
1138 bool uses_bindless_images
;
1140 /* MSAA sample locations.
1141 * The first index is the sample index.
1142 * The second index is the coordinate: X, Y. */
1150 struct pipe_resource
*sample_pos_buffer
;
1153 unsigned num_draw_calls
;
1154 unsigned num_decompress_calls
;
1155 unsigned num_mrt_draw_calls
;
1156 unsigned num_prim_restart_calls
;
1157 unsigned num_spill_draw_calls
;
1158 unsigned num_compute_calls
;
1159 unsigned num_spill_compute_calls
;
1160 unsigned num_dma_calls
;
1161 unsigned num_cp_dma_calls
;
1162 unsigned num_vs_flushes
;
1163 unsigned num_ps_flushes
;
1164 unsigned num_cs_flushes
;
1165 unsigned num_cb_cache_flushes
;
1166 unsigned num_db_cache_flushes
;
1167 unsigned num_L2_invalidates
;
1168 unsigned num_L2_writebacks
;
1169 unsigned num_resident_handles
;
1170 uint64_t num_alloc_tex_transfer_bytes
;
1171 unsigned last_tex_ps_draw_ratio
; /* for query */
1172 unsigned compute_num_verts_accepted
;
1173 unsigned compute_num_verts_rejected
;
1174 unsigned compute_num_verts_ineligible
; /* due to low vertex count */
1175 unsigned context_roll
;
1178 /* Maintain the list of active queries for pausing between IBs. */
1179 int num_occlusion_queries
;
1180 int num_perfect_occlusion_queries
;
1181 int num_pipeline_stat_queries
;
1182 struct list_head active_queries
;
1183 unsigned num_cs_dw_queries_suspend
;
1185 /* Render condition. */
1186 struct pipe_query
*render_cond
;
1187 unsigned render_cond_mode
;
1188 bool render_cond_invert
;
1189 bool render_cond_force_off
; /* for u_blitter */
1191 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1192 bool sdma_uploads_in_progress
;
1193 struct si_sdma_upload
*sdma_uploads
;
1194 unsigned num_sdma_uploads
;
1195 unsigned max_sdma_uploads
;
1197 /* Shader-based queries. */
1198 struct list_head shader_query_buffers
;
1199 unsigned num_active_shader_queries
;
1201 /* Statistics gathering for the DCC enablement heuristic. It can't be
1202 * in si_texture because si_texture can be shared by multiple
1203 * contexts. This is for back buffers only. We shouldn't get too many
1206 * X11 DRI3 rotates among a finite set of back buffers. They should
1207 * all fit in this array. If they don't, separate DCC might never be
1208 * enabled by DCC stat gathering.
1211 struct si_texture
*tex
;
1212 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1213 struct pipe_query
*ps_stats
[3];
1214 /* If all slots are used and another slot is needed,
1215 * the least recently used slot is evicted based on this. */
1216 int64_t last_use_timestamp
;
1220 /* Copy one resource to another using async DMA. */
1221 void (*dma_copy
)(struct pipe_context
*ctx
,
1222 struct pipe_resource
*dst
,
1224 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
1225 struct pipe_resource
*src
,
1227 const struct pipe_box
*src_box
);
1229 struct si_tracked_regs tracked_regs
;
1233 void cik_init_sdma_functions(struct si_context
*sctx
);
1236 enum si_blitter_op
/* bitmask */
1238 SI_SAVE_TEXTURES
= 1,
1239 SI_SAVE_FRAMEBUFFER
= 2,
1240 SI_SAVE_FRAGMENT_STATE
= 4,
1241 SI_DISABLE_RENDER_COND
= 8,
1244 void si_blitter_begin(struct si_context
*sctx
, enum si_blitter_op op
);
1245 void si_blitter_end(struct si_context
*sctx
);
1246 void si_init_blit_functions(struct si_context
*sctx
);
1247 void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
);
1248 void si_resource_copy_region(struct pipe_context
*ctx
,
1249 struct pipe_resource
*dst
,
1251 unsigned dstx
, unsigned dsty
, unsigned dstz
,
1252 struct pipe_resource
*src
,
1254 const struct pipe_box
*src_box
);
1255 void si_decompress_dcc(struct si_context
*sctx
, struct si_texture
*tex
);
1258 bool si_rings_is_buffer_referenced(struct si_context
*sctx
,
1259 struct pb_buffer
*buf
,
1260 enum radeon_bo_usage usage
);
1261 void *si_buffer_map_sync_with_rings(struct si_context
*sctx
,
1262 struct si_resource
*resource
,
1264 void si_init_resource_fields(struct si_screen
*sscreen
,
1265 struct si_resource
*res
,
1266 uint64_t size
, unsigned alignment
);
1267 bool si_alloc_resource(struct si_screen
*sscreen
,
1268 struct si_resource
*res
);
1269 struct pipe_resource
*pipe_aligned_buffer_create(struct pipe_screen
*screen
,
1270 unsigned flags
, unsigned usage
,
1271 unsigned size
, unsigned alignment
);
1272 struct si_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
,
1273 unsigned flags
, unsigned usage
,
1274 unsigned size
, unsigned alignment
);
1275 void si_replace_buffer_storage(struct pipe_context
*ctx
,
1276 struct pipe_resource
*dst
,
1277 struct pipe_resource
*src
);
1278 void si_init_screen_buffer_functions(struct si_screen
*sscreen
);
1279 void si_init_buffer_functions(struct si_context
*sctx
);
1282 enum pipe_format
si_simplify_cb_format(enum pipe_format format
);
1283 bool vi_alpha_is_on_msb(struct si_screen
*sscreen
, enum pipe_format format
);
1284 bool vi_dcc_clear_level(struct si_context
*sctx
,
1285 struct si_texture
*tex
,
1286 unsigned level
, unsigned clear_value
);
1287 void si_init_clear_functions(struct si_context
*sctx
);
1289 /* si_compute_blit.c */
1290 unsigned si_get_flush_flags(struct si_context
*sctx
, enum si_coherency coher
,
1291 enum si_cache_policy cache_policy
);
1292 void si_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1293 uint64_t offset
, uint64_t size
, uint32_t *clear_value
,
1294 uint32_t clear_value_size
, enum si_coherency coher
,
1296 void si_copy_buffer(struct si_context
*sctx
,
1297 struct pipe_resource
*dst
, struct pipe_resource
*src
,
1298 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
);
1299 void si_compute_copy_image(struct si_context
*sctx
,
1300 struct pipe_resource
*dst
,
1302 struct pipe_resource
*src
,
1304 unsigned dstx
, unsigned dsty
, unsigned dstz
,
1305 const struct pipe_box
*src_box
);
1306 void si_compute_clear_render_target(struct pipe_context
*ctx
,
1307 struct pipe_surface
*dstsurf
,
1308 const union pipe_color_union
*color
,
1309 unsigned dstx
, unsigned dsty
,
1310 unsigned width
, unsigned height
,
1311 bool render_condition_enabled
);
1312 void si_retile_dcc(struct si_context
*sctx
, struct si_texture
*tex
);
1313 void si_init_compute_blit_functions(struct si_context
*sctx
);
1316 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1317 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1318 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1319 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1320 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1321 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1322 SI_CPDMA_SKIP_SYNC_AFTER | \
1323 SI_CPDMA_SKIP_SYNC_BEFORE | \
1324 SI_CPDMA_SKIP_GFX_SYNC | \
1325 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1327 void si_cp_dma_wait_for_idle(struct si_context
*sctx
);
1328 void si_cp_dma_clear_buffer(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
,
1329 struct pipe_resource
*dst
, uint64_t offset
,
1330 uint64_t size
, unsigned value
, unsigned user_flags
,
1331 enum si_coherency coher
, enum si_cache_policy cache_policy
);
1332 void si_cp_dma_copy_buffer(struct si_context
*sctx
,
1333 struct pipe_resource
*dst
, struct pipe_resource
*src
,
1334 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
1335 unsigned user_flags
, enum si_coherency coher
,
1336 enum si_cache_policy cache_policy
);
1337 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
1338 uint64_t offset
, unsigned size
);
1339 void cik_emit_prefetch_L2(struct si_context
*sctx
, bool vertex_stage_only
);
1340 void si_test_gds(struct si_context
*sctx
);
1341 void si_cp_write_data(struct si_context
*sctx
, struct si_resource
*buf
,
1342 unsigned offset
, unsigned size
, unsigned dst_sel
,
1343 unsigned engine
, const void *data
);
1344 void si_cp_copy_data(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
,
1345 unsigned dst_sel
, struct si_resource
*dst
, unsigned dst_offset
,
1346 unsigned src_sel
, struct si_resource
*src
, unsigned src_offset
);
1349 void si_save_cs(struct radeon_winsys
*ws
, struct radeon_cmdbuf
*cs
,
1350 struct radeon_saved_cs
*saved
, bool get_buffer_list
);
1351 void si_clear_saved_cs(struct radeon_saved_cs
*saved
);
1352 void si_destroy_saved_cs(struct si_saved_cs
*scs
);
1353 void si_auto_log_cs(void *data
, struct u_log_context
*log
);
1354 void si_log_hw_flush(struct si_context
*sctx
);
1355 void si_log_draw_state(struct si_context
*sctx
, struct u_log_context
*log
);
1356 void si_log_compute_state(struct si_context
*sctx
, struct u_log_context
*log
);
1357 void si_init_debug_functions(struct si_context
*sctx
);
1358 void si_check_vm_faults(struct si_context
*sctx
,
1359 struct radeon_saved_cs
*saved
, enum ring_type ring
);
1360 bool si_replace_shader(unsigned num
, struct si_shader_binary
*binary
);
1363 void si_init_dma_functions(struct si_context
*sctx
);
1366 void si_dma_emit_timestamp(struct si_context
*sctx
, struct si_resource
*dst
,
1368 void si_sdma_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1369 uint64_t offset
, uint64_t size
, unsigned clear_value
);
1370 void si_need_dma_space(struct si_context
*ctx
, unsigned num_dw
,
1371 struct si_resource
*dst
, struct si_resource
*src
);
1372 void si_flush_dma_cs(struct si_context
*ctx
, unsigned flags
,
1373 struct pipe_fence_handle
**fence
);
1374 void si_screen_clear_buffer(struct si_screen
*sscreen
, struct pipe_resource
*dst
,
1375 uint64_t offset
, uint64_t size
, unsigned value
);
1378 void si_cp_release_mem(struct si_context
*ctx
, struct radeon_cmdbuf
*cs
,
1379 unsigned event
, unsigned event_flags
,
1380 unsigned dst_sel
, unsigned int_sel
, unsigned data_sel
,
1381 struct si_resource
*buf
, uint64_t va
,
1382 uint32_t new_fence
, unsigned query_type
);
1383 unsigned si_cp_write_fence_dwords(struct si_screen
*screen
);
1384 void si_cp_wait_mem(struct si_context
*ctx
, struct radeon_cmdbuf
*cs
,
1385 uint64_t va
, uint32_t ref
, uint32_t mask
, unsigned flags
);
1386 void si_init_fence_functions(struct si_context
*ctx
);
1387 void si_init_screen_fence_functions(struct si_screen
*screen
);
1388 struct pipe_fence_handle
*si_create_fence(struct pipe_context
*ctx
,
1389 struct tc_unflushed_batch_token
*tc_token
);
1392 void si_init_screen_get_functions(struct si_screen
*sscreen
);
1395 void si_flush_gfx_cs(struct si_context
*ctx
, unsigned flags
,
1396 struct pipe_fence_handle
**fence
);
1397 void si_allocate_gds(struct si_context
*ctx
);
1398 void si_begin_new_gfx_cs(struct si_context
*ctx
);
1399 void si_need_gfx_cs_space(struct si_context
*ctx
);
1400 void si_unref_sdma_uploads(struct si_context
*sctx
);
1403 void si_gpu_load_kill_thread(struct si_screen
*sscreen
);
1404 uint64_t si_begin_counter(struct si_screen
*sscreen
, unsigned type
);
1405 unsigned si_end_counter(struct si_screen
*sscreen
, unsigned type
,
1409 void si_emit_initial_compute_regs(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
);
1410 void si_init_compute_functions(struct si_context
*sctx
);
1412 /* si_compute_prim_discard.c */
1413 enum si_prim_discard_outcome
{
1414 SI_PRIM_DISCARD_ENABLED
,
1415 SI_PRIM_DISCARD_DISABLED
,
1416 SI_PRIM_DISCARD_DRAW_SPLIT
,
1419 void si_build_prim_discard_compute_shader(struct si_shader_context
*ctx
);
1420 enum si_prim_discard_outcome
1421 si_prepare_prim_discard_or_split_draw(struct si_context
*sctx
,
1422 const struct pipe_draw_info
*info
,
1423 bool primitive_restart
);
1424 void si_compute_signal_gfx(struct si_context
*sctx
);
1425 void si_dispatch_prim_discard_cs_and_draw(struct si_context
*sctx
,
1426 const struct pipe_draw_info
*info
,
1427 unsigned index_size
,
1428 unsigned base_vertex
,
1429 uint64_t input_indexbuf_va
,
1430 unsigned input_indexbuf_max_elements
);
1431 void si_initialize_prim_discard_tunables(struct si_context
*sctx
);
1433 /* si_perfcounters.c */
1434 void si_init_perfcounters(struct si_screen
*screen
);
1435 void si_destroy_perfcounters(struct si_screen
*screen
);
1438 bool si_check_device_reset(struct si_context
*sctx
);
1441 void si_init_screen_query_functions(struct si_screen
*sscreen
);
1442 void si_init_query_functions(struct si_context
*sctx
);
1443 void si_suspend_queries(struct si_context
*sctx
);
1444 void si_resume_queries(struct si_context
*sctx
);
1446 /* si_shaderlib_tgsi.c */
1447 void *si_get_blitter_vs(struct si_context
*sctx
, enum blitter_attrib_type type
,
1448 unsigned num_layers
);
1449 void *si_create_fixed_func_tcs(struct si_context
*sctx
);
1450 void *si_create_dma_compute_shader(struct pipe_context
*ctx
,
1451 unsigned num_dwords_per_thread
,
1452 bool dst_stream_cache_policy
, bool is_copy
);
1453 void *si_create_copy_image_compute_shader(struct pipe_context
*ctx
);
1454 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context
*ctx
);
1455 void *si_clear_render_target_shader(struct pipe_context
*ctx
);
1456 void *si_clear_render_target_shader_1d_array(struct pipe_context
*ctx
);
1457 void *si_create_dcc_retile_cs(struct pipe_context
*ctx
);
1458 void *si_create_query_result_cs(struct si_context
*sctx
);
1459 void *gfx10_create_sh_query_result_cs(struct si_context
*sctx
);
1462 void gfx10_init_query(struct si_context
*sctx
);
1463 void gfx10_destroy_query(struct si_context
*sctx
);
1466 void si_test_dma(struct si_screen
*sscreen
);
1468 /* si_test_clearbuffer.c */
1469 void si_test_dma_perf(struct si_screen
*sscreen
);
1472 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
1473 const struct pipe_video_codec
*templ
);
1475 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
1476 const struct pipe_video_buffer
*tmpl
);
1479 void si_update_vs_viewport_state(struct si_context
*ctx
);
1480 void si_init_viewport_functions(struct si_context
*ctx
);
1483 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
1484 struct si_texture
*dst
,
1485 unsigned dst_level
, unsigned dstx
,
1486 unsigned dsty
, unsigned dstz
,
1487 struct si_texture
*src
,
1489 const struct pipe_box
*src_box
);
1490 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
1491 struct si_texture
*tex
);
1492 void si_texture_discard_cmask(struct si_screen
*sscreen
,
1493 struct si_texture
*tex
);
1494 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1495 struct pipe_resource
*texture
);
1496 void si_print_texture_info(struct si_screen
*sscreen
,
1497 struct si_texture
*tex
, struct u_log_context
*log
);
1498 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1499 const struct pipe_resource
*templ
);
1500 bool vi_dcc_formats_compatible(struct si_screen
*sscreen
,
1501 enum pipe_format format1
,
1502 enum pipe_format format2
);
1503 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1505 enum pipe_format view_format
);
1506 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
1507 struct pipe_resource
*tex
,
1509 enum pipe_format view_format
);
1510 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1511 struct pipe_resource
*texture
,
1512 const struct pipe_surface
*templ
,
1513 unsigned width0
, unsigned height0
,
1514 unsigned width
, unsigned height
);
1515 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
1516 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
1517 struct si_texture
*tex
);
1518 void vi_separate_dcc_start_query(struct si_context
*sctx
,
1519 struct si_texture
*tex
);
1520 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
1521 struct si_texture
*tex
);
1522 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
1523 struct si_texture
*tex
);
1524 bool si_texture_disable_dcc(struct si_context
*sctx
,
1525 struct si_texture
*tex
);
1526 void si_init_screen_texture_functions(struct si_screen
*sscreen
);
1527 void si_init_context_texture_functions(struct si_context
*sctx
);
1534 static inline struct si_resource
*si_resource(struct pipe_resource
*r
)
1536 return (struct si_resource
*)r
;
1540 si_resource_reference(struct si_resource
**ptr
, struct si_resource
*res
)
1542 pipe_resource_reference((struct pipe_resource
**)ptr
,
1543 (struct pipe_resource
*)res
);
1547 si_texture_reference(struct si_texture
**ptr
, struct si_texture
*res
)
1549 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->buffer
.b
.b
);
1553 vi_dcc_enabled(struct si_texture
*tex
, unsigned level
)
1555 return tex
->dcc_offset
&& level
< tex
->surface
.num_dcc_levels
;
1558 static inline unsigned
1559 si_tile_mode_index(struct si_texture
*tex
, unsigned level
, bool stencil
)
1562 return tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
1564 return tex
->surface
.u
.legacy
.tiling_index
[level
];
1567 static inline unsigned
1568 si_get_minimum_num_gfx_cs_dwords(struct si_context
*sctx
)
1570 /* Don't count the needed CS space exactly and just use an upper bound.
1572 * Also reserve space for stopping queries at the end of IB, because
1573 * the number of active queries is unlimited in theory.
1575 return 2048 + sctx
->num_cs_dw_queries_suspend
;
1579 si_context_add_resource_size(struct si_context
*sctx
, struct pipe_resource
*r
)
1582 /* Add memory usage for need_gfx_cs_space */
1583 sctx
->vram
+= si_resource(r
)->vram_usage
;
1584 sctx
->gtt
+= si_resource(r
)->gart_usage
;
1589 si_invalidate_draw_sh_constants(struct si_context
*sctx
)
1591 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
1592 sctx
->last_instance_count
= SI_INSTANCE_COUNT_UNKNOWN
;
1595 static inline unsigned
1596 si_get_atom_bit(struct si_context
*sctx
, struct si_atom
*atom
)
1598 return 1 << (atom
- sctx
->atoms
.array
);
1602 si_set_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
, bool dirty
)
1604 unsigned bit
= si_get_atom_bit(sctx
, atom
);
1607 sctx
->dirty_atoms
|= bit
;
1609 sctx
->dirty_atoms
&= ~bit
;
1613 si_is_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1615 return (sctx
->dirty_atoms
& si_get_atom_bit(sctx
, atom
)) != 0;
1619 si_mark_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1621 si_set_atom_dirty(sctx
, atom
, true);
1624 static inline struct si_shader_ctx_state
*si_get_vs(struct si_context
*sctx
)
1626 if (sctx
->gs_shader
.cso
)
1627 return &sctx
->gs_shader
;
1628 if (sctx
->tes_shader
.cso
)
1629 return &sctx
->tes_shader
;
1631 return &sctx
->vs_shader
;
1634 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
1636 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1638 return vs
->cso
? &vs
->cso
->info
: NULL
;
1641 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
1643 if (sctx
->gs_shader
.cso
&&
1644 sctx
->gs_shader
.current
&&
1645 !sctx
->gs_shader
.current
->key
.as_ngg
)
1646 return sctx
->gs_shader
.cso
->gs_copy_shader
;
1648 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1649 return vs
->current
? vs
->current
: NULL
;
1652 static inline bool si_can_dump_shader(struct si_screen
*sscreen
,
1655 return sscreen
->debug_flags
& (1 << processor
);
1658 static inline bool si_get_strmout_en(struct si_context
*sctx
)
1660 return sctx
->streamout
.streamout_enabled
||
1661 sctx
->streamout
.prims_gen_query_enabled
;
1664 static inline unsigned
1665 si_optimal_tcc_alignment(struct si_context
*sctx
, unsigned upload_size
)
1667 unsigned alignment
, tcc_cache_line_size
;
1669 /* If the upload size is less than the cache line size (e.g. 16, 32),
1670 * the whole thing will fit into a cache line if we align it to its size.
1671 * The idea is that multiple small uploads can share a cache line.
1672 * If the upload size is greater, align it to the cache line size.
1674 alignment
= util_next_power_of_two(upload_size
);
1675 tcc_cache_line_size
= sctx
->screen
->info
.tcc_cache_line_size
;
1676 return MIN2(alignment
, tcc_cache_line_size
);
1680 si_saved_cs_reference(struct si_saved_cs
**dst
, struct si_saved_cs
*src
)
1682 if (pipe_reference(&(*dst
)->reference
, &src
->reference
))
1683 si_destroy_saved_cs(*dst
);
1689 si_make_CB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1690 bool shaders_read_metadata
, bool dcc_pipe_aligned
)
1692 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
|
1693 SI_CONTEXT_INV_VCACHE
;
1695 if (sctx
->chip_class
>= GFX10
) {
1696 if (shaders_read_metadata
)
1697 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1698 } else if (sctx
->chip_class
== GFX9
) {
1699 /* Single-sample color is coherent with shaders on GFX9, but
1700 * L2 metadata must be flushed if shaders read metadata.
1703 if (num_samples
>= 2 ||
1704 (shaders_read_metadata
&& !dcc_pipe_aligned
))
1705 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1706 else if (shaders_read_metadata
)
1707 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1710 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1715 si_make_DB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1716 bool include_stencil
, bool shaders_read_metadata
)
1718 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB
|
1719 SI_CONTEXT_INV_VCACHE
;
1721 if (sctx
->chip_class
>= GFX10
) {
1722 if (shaders_read_metadata
)
1723 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1724 } else if (sctx
->chip_class
== GFX9
) {
1725 /* Single-sample depth (not stencil) is coherent with shaders
1726 * on GFX9, but L2 metadata must be flushed if shaders read
1729 if (num_samples
>= 2 || include_stencil
)
1730 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1731 else if (shaders_read_metadata
)
1732 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1735 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1740 si_can_sample_zs(struct si_texture
*tex
, bool stencil_sampler
)
1742 return (stencil_sampler
&& tex
->can_sample_s
) ||
1743 (!stencil_sampler
&& tex
->can_sample_z
);
1747 si_htile_enabled(struct si_texture
*tex
, unsigned level
, unsigned zs_mask
)
1749 if (zs_mask
== PIPE_MASK_S
&& tex
->htile_stencil_disabled
)
1752 return tex
->htile_offset
&& level
== 0;
1756 vi_tc_compat_htile_enabled(struct si_texture
*tex
, unsigned level
, unsigned zs_mask
)
1758 assert(!tex
->tc_compatible_htile
|| tex
->htile_offset
);
1759 return tex
->tc_compatible_htile
&& si_htile_enabled(tex
, level
, zs_mask
);
1762 static inline unsigned si_get_ps_iter_samples(struct si_context
*sctx
)
1764 if (sctx
->ps_uses_fbfetch
)
1765 return sctx
->framebuffer
.nr_color_samples
;
1767 return MIN2(sctx
->ps_iter_samples
, sctx
->framebuffer
.nr_color_samples
);
1770 static inline unsigned si_get_total_colormask(struct si_context
*sctx
)
1772 if (sctx
->queued
.named
.rasterizer
->rasterizer_discard
)
1775 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1779 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
1780 sctx
->queued
.named
.blend
->cb_target_mask
;
1782 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
1783 colormask
&= ps
->colors_written_4bit
;
1784 else if (!ps
->colors_written_4bit
)
1785 colormask
= 0; /* color0 writes all cbufs, but it's not written */
1790 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1791 (1 << PIPE_PRIM_LINE_LOOP) | \
1792 (1 << PIPE_PRIM_LINE_STRIP) | \
1793 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1794 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1796 static inline bool util_prim_is_lines(unsigned prim
)
1798 return ((1 << prim
) & UTIL_ALL_PRIM_LINE_MODES
) != 0;
1801 static inline bool util_prim_is_points_or_lines(unsigned prim
)
1803 return ((1 << prim
) & (UTIL_ALL_PRIM_LINE_MODES
|
1804 (1 << PIPE_PRIM_POINTS
))) != 0;
1807 static inline bool util_rast_prim_is_triangles(unsigned prim
)
1809 return ((1 << prim
) & ((1 << PIPE_PRIM_TRIANGLES
) |
1810 (1 << PIPE_PRIM_TRIANGLE_STRIP
) |
1811 (1 << PIPE_PRIM_TRIANGLE_FAN
) |
1812 (1 << PIPE_PRIM_QUADS
) |
1813 (1 << PIPE_PRIM_QUAD_STRIP
) |
1814 (1 << PIPE_PRIM_POLYGON
) |
1815 (1 << PIPE_PRIM_TRIANGLES_ADJACENCY
) |
1816 (1 << PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
)));
1820 * Return true if there is enough memory in VRAM and GTT for the buffers
1823 * \param vram VRAM memory size not added to the buffer list yet
1824 * \param gtt GTT memory size not added to the buffer list yet
1827 radeon_cs_memory_below_limit(struct si_screen
*screen
,
1828 struct radeon_cmdbuf
*cs
,
1829 uint64_t vram
, uint64_t gtt
)
1831 vram
+= cs
->used_vram
;
1832 gtt
+= cs
->used_gart
;
1834 /* Anything that goes above the VRAM size should go to GTT. */
1835 if (vram
> screen
->info
.vram_size
)
1836 gtt
+= vram
- screen
->info
.vram_size
;
1838 /* Now we just need to check if we have enough GTT. */
1839 return gtt
< screen
->info
.gart_size
* 0.7;
1843 * Add a buffer to the buffer list for the given command stream (CS).
1845 * All buffers used by a CS must be added to the list. This tells the kernel
1846 * driver which buffers are used by GPU commands. Other buffers can
1847 * be swapped out (not accessible) during execution.
1849 * The buffer list becomes empty after every context flush and must be
1852 static inline void radeon_add_to_buffer_list(struct si_context
*sctx
,
1853 struct radeon_cmdbuf
*cs
,
1854 struct si_resource
*bo
,
1855 enum radeon_bo_usage usage
,
1856 enum radeon_bo_priority priority
)
1859 sctx
->ws
->cs_add_buffer(
1861 (enum radeon_bo_usage
)(usage
| RADEON_USAGE_SYNCHRONIZED
),
1862 bo
->domains
, priority
);
1866 * Same as above, but also checks memory usage and flushes the context
1869 * When this SHOULD NOT be used:
1871 * - if si_context_add_resource_size has been called for the buffer
1872 * followed by *_need_cs_space for checking the memory usage
1874 * - if si_need_dma_space has been called for the buffer
1876 * - when emitting state packets and draw packets (because preceding packets
1877 * can't be re-emitted at that point)
1879 * - if shader resource "enabled_mask" is not up-to-date or there is
1880 * a different constraint disallowing a context flush
1883 radeon_add_to_gfx_buffer_list_check_mem(struct si_context
*sctx
,
1884 struct si_resource
*bo
,
1885 enum radeon_bo_usage usage
,
1886 enum radeon_bo_priority priority
,
1890 !radeon_cs_memory_below_limit(sctx
->screen
, sctx
->gfx_cs
,
1891 sctx
->vram
+ bo
->vram_usage
,
1892 sctx
->gtt
+ bo
->gart_usage
))
1893 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1895 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, bo
, usage
, priority
);
1898 static inline bool si_compute_prim_discard_enabled(struct si_context
*sctx
)
1900 return sctx
->prim_discard_vertex_count_threshold
!= UINT_MAX
;
1903 static inline unsigned si_get_wave_size(struct si_screen
*sscreen
,
1904 enum pipe_shader_type shader_type
,
1907 if (shader_type
== PIPE_SHADER_COMPUTE
)
1908 return sscreen
->compute_wave_size
;
1909 else if (shader_type
== PIPE_SHADER_FRAGMENT
)
1910 return sscreen
->ps_wave_size
;
1911 else if ((shader_type
== PIPE_SHADER_TESS_EVAL
&& es
&& !ngg
) ||
1912 (shader_type
== PIPE_SHADER_GEOMETRY
&& !ngg
)) /* legacy GS only supports Wave64 */
1915 return sscreen
->ge_wave_size
;
1918 static inline unsigned si_get_shader_wave_size(struct si_shader
*shader
)
1920 return si_get_wave_size(shader
->selector
->screen
, shader
->selector
->type
,
1921 shader
->key
.as_ngg
, shader
->key
.as_es
);
1924 #define PRINT_ERR(fmt, args...) \
1925 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)