projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: Remove LDS layout user SGPR's from TES.
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "util/u_string.h"
43 #include "tgsi/tgsi_parse.h"
44 #include "tgsi/tgsi_build.h"
45 #include "tgsi/tgsi_util.h"
46 #include "tgsi/tgsi_dump.h"
47
48 #include "si_pipe.h"
49 #include "si_shader.h"
50 #include "sid.h"
51
52 #include <errno.h>
53
54 static const char *scratch_rsrc_dword0_symbol =
55 "SCRATCH_RSRC_DWORD0";
56
57 static const char *scratch_rsrc_dword1_symbol =
58 "SCRATCH_RSRC_DWORD1";
59
60 struct si_shader_output_values
61 {
62 LLVMValueRef values[4];
63 unsigned name;
64 unsigned sid;
65 };
66
67 struct si_shader_context
68 {
69 struct radeon_llvm_context radeon_bld;
70 struct si_shader *shader;
71 struct si_screen *screen;
72
73 unsigned type; /* PIPE_SHADER_* specifies the type of shader. */
74 bool is_gs_copy_shader;
75
76 /* Whether to generate the optimized shader variant compiled as a whole
77 * (without a prolog and epilog)
78 */
79 bool is_monolithic;
80
81 int param_streamout_config;
82 int param_streamout_write_index;
83 int param_streamout_offset[4];
84 int param_vertex_id;
85 int param_rel_auto_id;
86 int param_vs_prim_id;
87 int param_instance_id;
88 int param_vertex_index0;
89 int param_tes_u;
90 int param_tes_v;
91 int param_tes_rel_patch_id;
92 int param_tes_patch_id;
93 int param_es2gs_offset;
94 int param_oc_lds;
95
96 /* Sets a bit if the dynamic HS control word was 0x80000000. The bit is
97 * 0x800000 for VS, 0x1 for ES.
98 */
99 int param_tess_offchip;
100
101 LLVMTargetMachineRef tm;
102
103 unsigned uniform_md_kind;
104 LLVMValueRef const_md;
105 LLVMValueRef empty_md;
106 LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
107 LLVMValueRef lds;
108 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
109 LLVMValueRef shader_buffers[SI_NUM_SHADER_BUFFERS];
110 LLVMValueRef sampler_views[SI_NUM_SAMPLERS];
111 LLVMValueRef sampler_states[SI_NUM_SAMPLERS];
112 LLVMValueRef fmasks[SI_NUM_SAMPLERS];
113 LLVMValueRef images[SI_NUM_IMAGES];
114 LLVMValueRef so_buffers[4];
115 LLVMValueRef esgs_ring;
116 LLVMValueRef gsvs_ring[4];
117 LLVMValueRef gs_next_vertex[4];
118 LLVMValueRef return_value;
119
120 LLVMTypeRef voidt;
121 LLVMTypeRef i1;
122 LLVMTypeRef i8;
123 LLVMTypeRef i32;
124 LLVMTypeRef i64;
125 LLVMTypeRef i128;
126 LLVMTypeRef f32;
127 LLVMTypeRef v16i8;
128 LLVMTypeRef v2i32;
129 LLVMTypeRef v4i32;
130 LLVMTypeRef v4f32;
131 LLVMTypeRef v8i32;
132
133 LLVMValueRef shared_memory;
134 };
135
136 static struct si_shader_context *si_shader_context(
137 struct lp_build_tgsi_context *bld_base)
138 {
139 return (struct si_shader_context *)bld_base;
140 }
141
142 static void si_init_shader_ctx(struct si_shader_context *ctx,
143 struct si_screen *sscreen,
144 struct si_shader *shader,
145 LLVMTargetMachineRef tm);
146
147 /* Ideally pass the sample mask input to the PS epilog as v13, which
148 * is its usual location, so that the shader doesn't have to add v_mov.
149 */
150 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
151
152 /* The VS location of the PrimitiveID input is the same in the epilog,
153 * so that the main shader part doesn't have to move it.
154 */
155 #define VS_EPILOG_PRIMID_LOC 2
156
157 #define PERSPECTIVE_BASE 0
158 #define LINEAR_BASE 9
159
160 #define SAMPLE_OFFSET 0
161 #define CENTER_OFFSET 2
162 #define CENTROID_OFSET 4
163
164 #define USE_SGPR_MAX_SUFFIX_LEN 5
165 #define CONST_ADDR_SPACE 2
166 #define LOCAL_ADDR_SPACE 3
167 #define USER_SGPR_ADDR_SPACE 8
168
169
170 #define SENDMSG_GS 2
171 #define SENDMSG_GS_DONE 3
172
173 #define SENDMSG_GS_OP_NOP (0 << 4)
174 #define SENDMSG_GS_OP_CUT (1 << 4)
175 #define SENDMSG_GS_OP_EMIT (2 << 4)
176 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
177
178 /**
179 * Returns a unique index for a semantic name and index. The index must be
180 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
181 * calculated.
182 */
183 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
184 {
185 switch (semantic_name) {
186 case TGSI_SEMANTIC_POSITION:
187 return 0;
188 case TGSI_SEMANTIC_PSIZE:
189 return 1;
190 case TGSI_SEMANTIC_CLIPDIST:
191 assert(index <= 1);
192 return 2 + index;
193 case TGSI_SEMANTIC_GENERIC:
194 if (index <= 63-4)
195 return 4 + index;
196 else
197 /* same explanation as in the default statement,
198 * the only user hitting this is st/nine.
199 */
200 return 0;
201
202 /* patch indices are completely separate and thus start from 0 */
203 case TGSI_SEMANTIC_TESSOUTER:
204 return 0;
205 case TGSI_SEMANTIC_TESSINNER:
206 return 1;
207 case TGSI_SEMANTIC_PATCH:
208 return 2 + index;
209
210 default:
211 /* Don't fail here. The result of this function is only used
212 * for LS, TCS, TES, and GS, where legacy GL semantics can't
213 * occur, but this function is called for all vertex shaders
214 * before it's known whether LS will be compiled or not.
215 */
216 return 0;
217 }
218 }
219
220 /**
221 * Get the value of a shader input parameter and extract a bitfield.
222 */
223 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
224 unsigned param, unsigned rshift,
225 unsigned bitwidth)
226 {
227 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
228 LLVMValueRef value = LLVMGetParam(ctx->radeon_bld.main_fn,
229 param);
230
231 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
232 value = bitcast(&ctx->radeon_bld.soa.bld_base,
233 TGSI_TYPE_UNSIGNED, value);
234
235 if (rshift)
236 value = LLVMBuildLShr(gallivm->builder, value,
237 lp_build_const_int32(gallivm, rshift), "");
238
239 if (rshift + bitwidth < 32) {
240 unsigned mask = (1 << bitwidth) - 1;
241 value = LLVMBuildAnd(gallivm->builder, value,
242 lp_build_const_int32(gallivm, mask), "");
243 }
244
245 return value;
246 }
247
248 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
249 {
250 switch (ctx->type) {
251 case PIPE_SHADER_TESS_CTRL:
252 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
253
254 case PIPE_SHADER_TESS_EVAL:
255 return LLVMGetParam(ctx->radeon_bld.main_fn,
256 ctx->param_tes_rel_patch_id);
257
258 default:
259 assert(0);
260 return NULL;
261 }
262 }
263
264 /* Tessellation shaders pass outputs to the next shader using LDS.
265 *
266 * LS outputs = TCS inputs
267 * TCS outputs = TES inputs
268 *
269 * The LDS layout is:
270 * - TCS inputs for patch 0
271 * - TCS inputs for patch 1
272 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
273 * - ...
274 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
275 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
276 * - TCS outputs for patch 1
277 * - Per-patch TCS outputs for patch 1
278 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
279 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
280 * - ...
281 *
282 * All three shaders VS(LS), TCS, TES share the same LDS space.
283 */
284
285 static LLVMValueRef
286 get_tcs_in_patch_stride(struct si_shader_context *ctx)
287 {
288 if (ctx->type == PIPE_SHADER_VERTEX)
289 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
290 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
291 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
292 else {
293 assert(0);
294 return NULL;
295 }
296 }
297
298 static LLVMValueRef
299 get_tcs_out_patch_stride(struct si_shader_context *ctx)
300 {
301 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
302 }
303
304 static LLVMValueRef
305 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
306 {
307 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
308 unpack_param(ctx,
309 SI_PARAM_TCS_OUT_OFFSETS,
310 0, 16),
311 4);
312 }
313
314 static LLVMValueRef
315 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
316 {
317 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
318 unpack_param(ctx,
319 SI_PARAM_TCS_OUT_OFFSETS,
320 16, 16),
321 4);
322 }
323
324 static LLVMValueRef
325 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
326 {
327 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
328 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
329 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
330
331 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
332 }
333
334 static LLVMValueRef
335 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
336 {
337 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
338 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
339 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
340 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
341
342 return LLVMBuildAdd(gallivm->builder, patch0_offset,
343 LLVMBuildMul(gallivm->builder, patch_stride,
344 rel_patch_id, ""),
345 "");
346 }
347
348 static LLVMValueRef
349 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
350 {
351 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
352 LLVMValueRef patch0_patch_data_offset =
353 get_tcs_out_patch0_patch_data_offset(ctx);
354 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
355 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
356
357 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
358 LLVMBuildMul(gallivm->builder, patch_stride,
359 rel_patch_id, ""),
360 "");
361 }
362
363 static void build_indexed_store(struct si_shader_context *ctx,
364 LLVMValueRef base_ptr, LLVMValueRef index,
365 LLVMValueRef value)
366 {
367 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
368 struct gallivm_state *gallivm = bld_base->base.gallivm;
369 LLVMValueRef indices[2], pointer;
370
371 indices[0] = bld_base->uint_bld.zero;
372 indices[1] = index;
373
374 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
375 LLVMBuildStore(gallivm->builder, value, pointer);
376 }
377
378 /**
379 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
380 * It's equivalent to doing a load from &base_ptr[index].
381 *
382 * \param base_ptr Where the array starts.
383 * \param index The element index into the array.
384 * \param uniform Whether the base_ptr and index can be assumed to be
385 * dynamically uniform
386 */
387 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
388 LLVMValueRef base_ptr, LLVMValueRef index,
389 bool uniform)
390 {
391 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
392 struct gallivm_state *gallivm = bld_base->base.gallivm;
393 LLVMValueRef indices[2], pointer;
394
395 indices[0] = bld_base->uint_bld.zero;
396 indices[1] = index;
397
398 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
399 if (uniform)
400 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
401 return LLVMBuildLoad(gallivm->builder, pointer, "");
402 }
403
404 /**
405 * Do a load from &base_ptr[index], but also add a flag that it's loading
406 * a constant from a dynamically uniform index.
407 */
408 static LLVMValueRef build_indexed_load_const(
409 struct si_shader_context *ctx,
410 LLVMValueRef base_ptr, LLVMValueRef index)
411 {
412 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
413 LLVMSetMetadata(result, 1, ctx->const_md);
414 return result;
415 }
416
417 static LLVMValueRef get_instance_index_for_fetch(
418 struct radeon_llvm_context *radeon_bld,
419 unsigned param_start_instance, unsigned divisor)
420 {
421 struct si_shader_context *ctx =
422 si_shader_context(&radeon_bld->soa.bld_base);
423 struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm;
424
425 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
426 ctx->param_instance_id);
427
428 /* The division must be done before START_INSTANCE is added. */
429 if (divisor > 1)
430 result = LLVMBuildUDiv(gallivm->builder, result,
431 lp_build_const_int32(gallivm, divisor), "");
432
433 return LLVMBuildAdd(gallivm->builder, result,
434 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
435 }
436
437 static void declare_input_vs(
438 struct radeon_llvm_context *radeon_bld,
439 unsigned input_index,
440 const struct tgsi_full_declaration *decl)
441 {
442 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
443 struct gallivm_state *gallivm = base->gallivm;
444 struct si_shader_context *ctx =
445 si_shader_context(&radeon_bld->soa.bld_base);
446 unsigned divisor =
447 ctx->shader->key.vs.prolog.instance_divisors[input_index];
448
449 unsigned chan;
450
451 LLVMValueRef t_list_ptr;
452 LLVMValueRef t_offset;
453 LLVMValueRef t_list;
454 LLVMValueRef attribute_offset;
455 LLVMValueRef buffer_index;
456 LLVMValueRef args[3];
457 LLVMValueRef input;
458
459 /* Load the T list */
460 t_list_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
461
462 t_offset = lp_build_const_int32(gallivm, input_index);
463
464 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
465
466 /* Build the attribute offset */
467 attribute_offset = lp_build_const_int32(gallivm, 0);
468
469 if (!ctx->is_monolithic) {
470 buffer_index = LLVMGetParam(radeon_bld->main_fn,
471 ctx->param_vertex_index0 +
472 input_index);
473 } else if (divisor) {
474 /* Build index from instance ID, start instance and divisor */
475 ctx->shader->info.uses_instanceid = true;
476 buffer_index = get_instance_index_for_fetch(&ctx->radeon_bld,
477 SI_PARAM_START_INSTANCE,
478 divisor);
479 } else {
480 /* Load the buffer index for vertices. */
481 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
482 ctx->param_vertex_id);
483 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
484 SI_PARAM_BASE_VERTEX);
485 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
486 }
487
488 args[0] = t_list;
489 args[1] = attribute_offset;
490 args[2] = buffer_index;
491 input = lp_build_intrinsic(gallivm->builder,
492 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
493 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
494
495 /* Break up the vec4 into individual components */
496 for (chan = 0; chan < 4; chan++) {
497 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
498 /* XXX: Use a helper function for this. There is one in
499 * tgsi_llvm.c. */
500 ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
501 LLVMBuildExtractElement(gallivm->builder,
502 input, llvm_chan, "");
503 }
504 }
505
506 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
507 unsigned swizzle)
508 {
509 struct si_shader_context *ctx = si_shader_context(bld_base);
510
511 if (swizzle > 0)
512 return bld_base->uint_bld.zero;
513
514 switch (ctx->type) {
515 case PIPE_SHADER_VERTEX:
516 return LLVMGetParam(ctx->radeon_bld.main_fn,
517 ctx->param_vs_prim_id);
518 case PIPE_SHADER_TESS_CTRL:
519 return LLVMGetParam(ctx->radeon_bld.main_fn,
520 SI_PARAM_PATCH_ID);
521 case PIPE_SHADER_TESS_EVAL:
522 return LLVMGetParam(ctx->radeon_bld.main_fn,
523 ctx->param_tes_patch_id);
524 case PIPE_SHADER_GEOMETRY:
525 return LLVMGetParam(ctx->radeon_bld.main_fn,
526 SI_PARAM_PRIMITIVE_ID);
527 default:
528 assert(0);
529 return bld_base->uint_bld.zero;
530 }
531 }
532
533 /**
534 * Return the value of tgsi_ind_register for indexing.
535 * This is the indirect index with the constant offset added to it.
536 */
537 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
538 const struct tgsi_ind_register *ind,
539 int rel_index)
540 {
541 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
542 LLVMValueRef result;
543
544 result = ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
545 result = LLVMBuildLoad(gallivm->builder, result, "");
546 result = LLVMBuildAdd(gallivm->builder, result,
547 lp_build_const_int32(gallivm, rel_index), "");
548 return result;
549 }
550
551 /**
552 * Like get_indirect_index, but restricts the return value to a (possibly
553 * undefined) value inside [0..num).
554 */
555 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
556 const struct tgsi_ind_register *ind,
557 int rel_index, unsigned num)
558 {
559 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
560 LLVMBuilderRef builder = gallivm->builder;
561 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
562 LLVMValueRef c_max = LLVMConstInt(ctx->i32, num - 1, 0);
563 LLVMValueRef cc;
564
565 /* LLVM 3.8: If indirect resource indexing is used:
566 * - SI & CIK hang
567 * - VI crashes
568 */
569 if (HAVE_LLVM <= 0x0308)
570 return LLVMGetUndef(ctx->i32);
571
572 if (util_is_power_of_two(num)) {
573 result = LLVMBuildAnd(builder, result, c_max, "");
574 } else {
575 /* In theory, this MAX pattern should result in code that is
576 * as good as the bit-wise AND above.
577 *
578 * In practice, LLVM generates worse code (at the time of
579 * writing), because its value tracking is not strong enough.
580 */
581 cc = LLVMBuildICmp(builder, LLVMIntULE, result, c_max, "");
582 result = LLVMBuildSelect(builder, cc, result, c_max, "");
583 }
584
585 return result;
586 }
587
588
589 /**
590 * Calculate a dword address given an input or output register and a stride.
591 */
592 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
593 const struct tgsi_full_dst_register *dst,
594 const struct tgsi_full_src_register *src,
595 LLVMValueRef vertex_dw_stride,
596 LLVMValueRef base_addr)
597 {
598 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
599 struct tgsi_shader_info *info = &ctx->shader->selector->info;
600 ubyte *name, *index, *array_first;
601 int first, param;
602 struct tgsi_full_dst_register reg;
603
604 /* Set the register description. The address computation is the same
605 * for sources and destinations. */
606 if (src) {
607 reg.Register.File = src->Register.File;
608 reg.Register.Index = src->Register.Index;
609 reg.Register.Indirect = src->Register.Indirect;
610 reg.Register.Dimension = src->Register.Dimension;
611 reg.Indirect = src->Indirect;
612 reg.Dimension = src->Dimension;
613 reg.DimIndirect = src->DimIndirect;
614 } else
615 reg = *dst;
616
617 /* If the register is 2-dimensional (e.g. an array of vertices
618 * in a primitive), calculate the base address of the vertex. */
619 if (reg.Register.Dimension) {
620 LLVMValueRef index;
621
622 if (reg.Dimension.Indirect)
623 index = get_indirect_index(ctx, &reg.DimIndirect,
624 reg.Dimension.Index);
625 else
626 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
627
628 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
629 LLVMBuildMul(gallivm->builder, index,
630 vertex_dw_stride, ""), "");
631 }
632
633 /* Get information about the register. */
634 if (reg.Register.File == TGSI_FILE_INPUT) {
635 name = info->input_semantic_name;
636 index = info->input_semantic_index;
637 array_first = info->input_array_first;
638 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
639 name = info->output_semantic_name;
640 index = info->output_semantic_index;
641 array_first = info->output_array_first;
642 } else {
643 assert(0);
644 return NULL;
645 }
646
647 if (reg.Register.Indirect) {
648 /* Add the relative address of the element. */
649 LLVMValueRef ind_index;
650
651 if (reg.Indirect.ArrayID)
652 first = array_first[reg.Indirect.ArrayID];
653 else
654 first = reg.Register.Index;
655
656 ind_index = get_indirect_index(ctx, &reg.Indirect,
657 reg.Register.Index - first);
658
659 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
660 LLVMBuildMul(gallivm->builder, ind_index,
661 lp_build_const_int32(gallivm, 4), ""), "");
662
663 param = si_shader_io_get_unique_index(name[first], index[first]);
664 } else {
665 param = si_shader_io_get_unique_index(name[reg.Register.Index],
666 index[reg.Register.Index]);
667 }
668
669 /* Add the base address of the element. */
670 return LLVMBuildAdd(gallivm->builder, base_addr,
671 lp_build_const_int32(gallivm, param * 4), "");
672 }
673
674 /* The offchip buffer layout for TCS->TES is
675 *
676 * - attribute 0 of patch 0 vertex 0
677 * - attribute 0 of patch 0 vertex 1
678 * - attribute 0 of patch 0 vertex 2
679 * ...
680 * - attribute 0 of patch 1 vertex 0
681 * - attribute 0 of patch 1 vertex 1
682 * ...
683 * - attribute 1 of patch 0 vertex 0
684 * - attribute 1 of patch 0 vertex 1
685 * ...
686 * - per patch attribute 0 of patch 0
687 * - per patch attribute 0 of patch 1
688 * ...
689 *
690 * Note that every attribute has 4 components.
691 */
692 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
693 LLVMValueRef vertex_index,
694 LLVMValueRef param_index)
695 {
696 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
697 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
698 LLVMValueRef param_stride, constant16;
699
700 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
701 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
702 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
703 num_patches, "");
704
705 constant16 = lp_build_const_int32(gallivm, 16);
706 if (vertex_index) {
707 base_addr = LLVMBuildMul(gallivm->builder, get_rel_patch_id(ctx),
708 vertices_per_patch, "");
709
710 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
711 vertex_index, "");
712
713 param_stride = total_vertices;
714 } else {
715 base_addr = get_rel_patch_id(ctx);
716 param_stride = num_patches;
717 }
718
719 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
720 LLVMBuildMul(gallivm->builder, param_index,
721 param_stride, ""), "");
722
723 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
724
725 if (!vertex_index) {
726 LLVMValueRef patch_data_offset =
727 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
728
729 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
730 patch_data_offset, "");
731 }
732 return base_addr;
733 }
734
735 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
736 struct si_shader_context *ctx,
737 const struct tgsi_full_dst_register *dst,
738 const struct tgsi_full_src_register *src)
739 {
740 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
741 struct tgsi_shader_info *info = &ctx->shader->selector->info;
742 ubyte *name, *index, *array_first;
743 struct tgsi_full_src_register reg;
744 LLVMValueRef vertex_index = NULL;
745 LLVMValueRef param_index = NULL;
746 unsigned param_index_base, param_base;
747
748 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
749
750 if (reg.Register.Dimension) {
751
752 if (reg.Dimension.Indirect)
753 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
754 reg.Dimension.Index);
755 else
756 vertex_index = lp_build_const_int32(gallivm,
757 reg.Dimension.Index);
758 }
759
760 /* Get information about the register. */
761 if (reg.Register.File == TGSI_FILE_INPUT) {
762 name = info->input_semantic_name;
763 index = info->input_semantic_index;
764 array_first = info->input_array_first;
765 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
766 name = info->output_semantic_name;
767 index = info->output_semantic_index;
768 array_first = info->output_array_first;
769 } else {
770 assert(0);
771 return NULL;
772 }
773
774 if (reg.Register.Indirect) {
775 if (reg.Indirect.ArrayID)
776 param_base = array_first[reg.Indirect.ArrayID];
777 else
778 param_base = reg.Register.Index;
779
780 param_index = get_indirect_index(ctx, &reg.Indirect,
781 reg.Register.Index - param_base);
782
783 } else {
784 param_base = reg.Register.Index;
785 param_index = lp_build_const_int32(gallivm, 0);
786 }
787
788 param_index_base = si_shader_io_get_unique_index(name[param_base],
789 index[param_base]);
790
791 param_index = LLVMBuildAdd(gallivm->builder, param_index,
792 lp_build_const_int32(gallivm, param_index_base),
793 "");
794
795 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
796 }
797
798 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
799 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
800 * or v4i32 (num_channels=3,4). */
801 static void build_tbuffer_store(struct si_shader_context *ctx,
802 LLVMValueRef rsrc,
803 LLVMValueRef vdata,
804 unsigned num_channels,
805 LLVMValueRef vaddr,
806 LLVMValueRef soffset,
807 unsigned inst_offset,
808 unsigned dfmt,
809 unsigned nfmt,
810 unsigned offen,
811 unsigned idxen,
812 unsigned glc,
813 unsigned slc,
814 unsigned tfe)
815 {
816 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
817 LLVMValueRef args[] = {
818 rsrc,
819 vdata,
820 LLVMConstInt(ctx->i32, num_channels, 0),
821 vaddr,
822 soffset,
823 LLVMConstInt(ctx->i32, inst_offset, 0),
824 LLVMConstInt(ctx->i32, dfmt, 0),
825 LLVMConstInt(ctx->i32, nfmt, 0),
826 LLVMConstInt(ctx->i32, offen, 0),
827 LLVMConstInt(ctx->i32, idxen, 0),
828 LLVMConstInt(ctx->i32, glc, 0),
829 LLVMConstInt(ctx->i32, slc, 0),
830 LLVMConstInt(ctx->i32, tfe, 0)
831 };
832
833 /* The instruction offset field has 12 bits */
834 assert(offen || inst_offset < (1 << 12));
835
836 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
837 unsigned func = CLAMP(num_channels, 1, 3) - 1;
838 const char *types[] = {"i32", "v2i32", "v4i32"};
839 char name[256];
840 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
841
842 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
843 args, ARRAY_SIZE(args), 0);
844 }
845
846 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
847 LLVMValueRef rsrc,
848 LLVMValueRef vdata,
849 unsigned num_channels,
850 LLVMValueRef vaddr,
851 LLVMValueRef soffset,
852 unsigned inst_offset)
853 {
854 static unsigned dfmt[] = {
855 V_008F0C_BUF_DATA_FORMAT_32,
856 V_008F0C_BUF_DATA_FORMAT_32_32,
857 V_008F0C_BUF_DATA_FORMAT_32_32_32,
858 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
859 };
860 assert(num_channels >= 1 && num_channels <= 4);
861
862 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
863 inst_offset, dfmt[num_channels-1],
864 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
865 }
866
867 static LLVMValueRef build_buffer_load(struct si_shader_context *ctx,
868 LLVMValueRef rsrc,
869 int num_channels,
870 LLVMValueRef vindex,
871 LLVMValueRef voffset,
872 LLVMValueRef soffset,
873 unsigned inst_offset,
874 unsigned glc,
875 unsigned slc)
876 {
877 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
878 unsigned func = CLAMP(num_channels, 1, 3) - 1;
879
880 if (HAVE_LLVM >= 0x309) {
881 LLVMValueRef args[] = {
882 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, ""),
883 vindex ? vindex : LLVMConstInt(ctx->i32, 0, 0),
884 LLVMConstInt(ctx->i32, inst_offset, 0),
885 LLVMConstInt(ctx->i1, glc, 0),
886 LLVMConstInt(ctx->i1, slc, 0)
887 };
888
889 LLVMTypeRef types[] = {ctx->f32, LLVMVectorType(ctx->f32, 2),
890 ctx->v4f32};
891 const char *type_names[] = {"f32", "v2f32", "v4f32"};
892 char name[256];
893
894 if (voffset) {
895 args[2] = LLVMBuildAdd(gallivm->builder, args[2], voffset,
896 "");
897 }
898
899 if (soffset) {
900 args[2] = LLVMBuildAdd(gallivm->builder, args[2], soffset,
901 "");
902 }
903
904 snprintf(name, sizeof(name), "llvm.amdgcn.buffer.load.%s",
905 type_names[func]);
906
907 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
908 ARRAY_SIZE(args), LLVMReadOnlyAttribute |
909 LLVMNoUnwindAttribute);
910 } else {
911 LLVMValueRef args[] = {
912 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v16i8, ""),
913 voffset ? voffset : vindex,
914 soffset,
915 LLVMConstInt(ctx->i32, inst_offset, 0),
916 LLVMConstInt(ctx->i32, voffset ? 1 : 0, 0), // offen
917 LLVMConstInt(ctx->i32, vindex ? 1 : 0, 0), //idxen
918 LLVMConstInt(ctx->i32, glc, 0),
919 LLVMConstInt(ctx->i32, slc, 0),
920 LLVMConstInt(ctx->i32, 0, 0), // TFE
921 };
922
923 LLVMTypeRef types[] = {ctx->i32, LLVMVectorType(ctx->i32, 2),
924 ctx->v4i32};
925 const char *type_names[] = {"i32", "v2i32", "v4i32"};
926 const char *arg_type = "i32";
927 char name[256];
928
929 if (voffset && vindex) {
930 LLVMValueRef vaddr[] = {vindex, voffset};
931
932 arg_type = "v2i32";
933 args[1] = lp_build_gather_values(gallivm, vaddr, 2);
934 }
935
936 snprintf(name, sizeof(name), "llvm.SI.buffer.load.dword.%s.%s",
937 type_names[func], arg_type);
938
939 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
940 ARRAY_SIZE(args), LLVMReadOnlyAttribute |
941 LLVMNoUnwindAttribute);
942 }
943 }
944
945 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
946 enum tgsi_opcode_type type, unsigned swizzle,
947 LLVMValueRef buffer, LLVMValueRef offset,
948 LLVMValueRef base)
949 {
950 struct si_shader_context *ctx = si_shader_context(bld_base);
951 struct gallivm_state *gallivm = bld_base->base.gallivm;
952 LLVMValueRef value, value2;
953 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
954 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
955
956 if (swizzle == ~0) {
957 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
958 0, 1, 0);
959
960 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
961 }
962
963 if (type != TGSI_TYPE_DOUBLE) {
964 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
965 0, 1, 0);
966
967 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
968 return LLVMBuildExtractElement(gallivm->builder, value,
969 lp_build_const_int32(gallivm, swizzle), "");
970 }
971
972 value = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
973 swizzle * 4, 1, 0);
974
975 value2 = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
976 swizzle * 4 + 4, 1, 0);
977
978 return radeon_llvm_emit_fetch_double(bld_base, value, value2);
979 }
980
981 /**
982 * Load from LDS.
983 *
984 * \param type output value type
985 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
986 * \param dw_addr address in dwords
987 */
988 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
989 enum tgsi_opcode_type type, unsigned swizzle,
990 LLVMValueRef dw_addr)
991 {
992 struct si_shader_context *ctx = si_shader_context(bld_base);
993 struct gallivm_state *gallivm = bld_base->base.gallivm;
994 LLVMValueRef value;
995
996 if (swizzle == ~0) {
997 LLVMValueRef values[TGSI_NUM_CHANNELS];
998
999 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1000 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1001
1002 return lp_build_gather_values(bld_base->base.gallivm, values,
1003 TGSI_NUM_CHANNELS);
1004 }
1005
1006 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1007 lp_build_const_int32(gallivm, swizzle));
1008
1009 value = build_indexed_load(ctx, ctx->lds, dw_addr, false);
1010 if (type == TGSI_TYPE_DOUBLE) {
1011 LLVMValueRef value2;
1012 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1013 lp_build_const_int32(gallivm, swizzle + 1));
1014 value2 = build_indexed_load(ctx, ctx->lds, dw_addr, false);
1015 return radeon_llvm_emit_fetch_double(bld_base, value, value2);
1016 }
1017
1018 return LLVMBuildBitCast(gallivm->builder, value,
1019 tgsi2llvmtype(bld_base, type), "");
1020 }
1021
1022 /**
1023 * Store to LDS.
1024 *
1025 * \param swizzle offset (typically 0..3)
1026 * \param dw_addr address in dwords
1027 * \param value value to store
1028 */
1029 static void lds_store(struct lp_build_tgsi_context *bld_base,
1030 unsigned swizzle, LLVMValueRef dw_addr,
1031 LLVMValueRef value)
1032 {
1033 struct si_shader_context *ctx = si_shader_context(bld_base);
1034 struct gallivm_state *gallivm = bld_base->base.gallivm;
1035
1036 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1037 lp_build_const_int32(gallivm, swizzle));
1038
1039 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1040 build_indexed_store(ctx, ctx->lds,
1041 dw_addr, value);
1042 }
1043
1044 static LLVMValueRef fetch_input_tcs(
1045 struct lp_build_tgsi_context *bld_base,
1046 const struct tgsi_full_src_register *reg,
1047 enum tgsi_opcode_type type, unsigned swizzle)
1048 {
1049 struct si_shader_context *ctx = si_shader_context(bld_base);
1050 LLVMValueRef dw_addr, stride;
1051
1052 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
1053 dw_addr = get_tcs_in_current_patch_offset(ctx);
1054 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1055
1056 return lds_load(bld_base, type, swizzle, dw_addr);
1057 }
1058
1059 static LLVMValueRef fetch_output_tcs(
1060 struct lp_build_tgsi_context *bld_base,
1061 const struct tgsi_full_src_register *reg,
1062 enum tgsi_opcode_type type, unsigned swizzle)
1063 {
1064 struct si_shader_context *ctx = si_shader_context(bld_base);
1065 LLVMValueRef dw_addr, stride;
1066
1067 if (reg->Register.Dimension) {
1068 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1069 dw_addr = get_tcs_out_current_patch_offset(ctx);
1070 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1071 } else {
1072 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1073 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1074 }
1075
1076 return lds_load(bld_base, type, swizzle, dw_addr);
1077 }
1078
1079 static LLVMValueRef fetch_input_tes(
1080 struct lp_build_tgsi_context *bld_base,
1081 const struct tgsi_full_src_register *reg,
1082 enum tgsi_opcode_type type, unsigned swizzle)
1083 {
1084 struct si_shader_context *ctx = si_shader_context(bld_base);
1085 struct gallivm_state *gallivm = bld_base->base.gallivm;
1086 LLVMValueRef rw_buffers, buffer, base, addr;
1087
1088 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1089 SI_PARAM_RW_BUFFERS);
1090 buffer = build_indexed_load_const(ctx, rw_buffers,
1091 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1092
1093 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1094 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1095
1096 return buffer_load(bld_base, type, swizzle, buffer, base, addr);
1097 }
1098
1099 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1100 const struct tgsi_full_instruction *inst,
1101 const struct tgsi_opcode_info *info,
1102 LLVMValueRef dst[4])
1103 {
1104 struct si_shader_context *ctx = si_shader_context(bld_base);
1105 struct gallivm_state *gallivm = bld_base->base.gallivm;
1106 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
1107 unsigned chan_index;
1108 LLVMValueRef dw_addr, stride;
1109 LLVMValueRef rw_buffers, buffer, base, buf_addr;
1110 LLVMValueRef values[4];
1111
1112 /* Only handle per-patch and per-vertex outputs here.
1113 * Vectors will be lowered to scalars and this function will be called again.
1114 */
1115 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1116 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1117 radeon_llvm_emit_store(bld_base, inst, info, dst);
1118 return;
1119 }
1120
1121 if (reg->Register.Dimension) {
1122 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1123 dw_addr = get_tcs_out_current_patch_offset(ctx);
1124 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1125 } else {
1126 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1127 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1128 }
1129
1130 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1131 SI_PARAM_RW_BUFFERS);
1132 buffer = build_indexed_load_const(ctx, rw_buffers,
1133 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1134
1135 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1136 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1137
1138
1139 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1140 LLVMValueRef value = dst[chan_index];
1141
1142 if (inst->Instruction.Saturate)
1143 value = radeon_llvm_saturate(bld_base, value);
1144
1145 lds_store(bld_base, chan_index, dw_addr, value);
1146
1147 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1148 values[chan_index] = value;
1149
1150 if (inst->Dst[0].Register.WriteMask != 0xF) {
1151 build_tbuffer_store_dwords(ctx, buffer, value, 1,
1152 buf_addr, base,
1153 4 * chan_index);
1154 }
1155 }
1156
1157 if (inst->Dst[0].Register.WriteMask == 0xF) {
1158 LLVMValueRef value = lp_build_gather_values(bld_base->base.gallivm,
1159 values, 4);
1160 build_tbuffer_store_dwords(ctx, buffer, value, 4, buf_addr,
1161 base, 0);
1162 }
1163 }
1164
1165 static LLVMValueRef fetch_input_gs(
1166 struct lp_build_tgsi_context *bld_base,
1167 const struct tgsi_full_src_register *reg,
1168 enum tgsi_opcode_type type,
1169 unsigned swizzle)
1170 {
1171 struct lp_build_context *base = &bld_base->base;
1172 struct si_shader_context *ctx = si_shader_context(bld_base);
1173 struct si_shader *shader = ctx->shader;
1174 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1175 struct gallivm_state *gallivm = base->gallivm;
1176 LLVMValueRef vtx_offset;
1177 LLVMValueRef args[9];
1178 unsigned vtx_offset_param;
1179 struct tgsi_shader_info *info = &shader->selector->info;
1180 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1181 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1182 unsigned param;
1183 LLVMValueRef value;
1184
1185 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1186 return get_primitive_id(bld_base, swizzle);
1187
1188 if (!reg->Register.Dimension)
1189 return NULL;
1190
1191 if (swizzle == ~0) {
1192 LLVMValueRef values[TGSI_NUM_CHANNELS];
1193 unsigned chan;
1194 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1195 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1196 }
1197 return lp_build_gather_values(bld_base->base.gallivm, values,
1198 TGSI_NUM_CHANNELS);
1199 }
1200
1201 /* Get the vertex offset parameter */
1202 vtx_offset_param = reg->Dimension.Index;
1203 if (vtx_offset_param < 2) {
1204 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1205 } else {
1206 assert(vtx_offset_param < 6);
1207 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1208 }
1209 vtx_offset = lp_build_mul_imm(uint,
1210 LLVMGetParam(ctx->radeon_bld.main_fn,
1211 vtx_offset_param),
1212 4);
1213
1214 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1215 args[0] = ctx->esgs_ring;
1216 args[1] = vtx_offset;
1217 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
1218 args[3] = uint->zero;
1219 args[4] = uint->one; /* OFFEN */
1220 args[5] = uint->zero; /* IDXEN */
1221 args[6] = uint->one; /* GLC */
1222 args[7] = uint->zero; /* SLC */
1223 args[8] = uint->zero; /* TFE */
1224
1225 value = lp_build_intrinsic(gallivm->builder,
1226 "llvm.SI.buffer.load.dword.i32.i32",
1227 ctx->i32, args, 9,
1228 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
1229 if (type == TGSI_TYPE_DOUBLE) {
1230 LLVMValueRef value2;
1231 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
1232 value2 = lp_build_intrinsic(gallivm->builder,
1233 "llvm.SI.buffer.load.dword.i32.i32",
1234 ctx->i32, args, 9,
1235 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
1236 return radeon_llvm_emit_fetch_double(bld_base,
1237 value, value2);
1238 }
1239 return LLVMBuildBitCast(gallivm->builder,
1240 value,
1241 tgsi2llvmtype(bld_base, type), "");
1242 }
1243
1244 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1245 {
1246 switch (interpolate) {
1247 case TGSI_INTERPOLATE_CONSTANT:
1248 return 0;
1249
1250 case TGSI_INTERPOLATE_LINEAR:
1251 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1252 return SI_PARAM_LINEAR_SAMPLE;
1253 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1254 return SI_PARAM_LINEAR_CENTROID;
1255 else
1256 return SI_PARAM_LINEAR_CENTER;
1257 break;
1258 case TGSI_INTERPOLATE_COLOR:
1259 case TGSI_INTERPOLATE_PERSPECTIVE:
1260 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1261 return SI_PARAM_PERSP_SAMPLE;
1262 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1263 return SI_PARAM_PERSP_CENTROID;
1264 else
1265 return SI_PARAM_PERSP_CENTER;
1266 break;
1267 default:
1268 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1269 return -1;
1270 }
1271 }
1272
1273 /* This shouldn't be used by explicit INTERP opcodes. */
1274 static unsigned select_interp_param(struct si_shader_context *ctx,
1275 unsigned param)
1276 {
1277 if (!ctx->shader->key.ps.prolog.force_persample_interp ||
1278 !ctx->is_monolithic)
1279 return param;
1280
1281 /* If the shader doesn't use center/centroid, just return the parameter.
1282 *
1283 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
1284 * switch between center/centroid and sample without shader changes.
1285 */
1286 switch (param) {
1287 case SI_PARAM_PERSP_CENTROID:
1288 case SI_PARAM_PERSP_CENTER:
1289 return SI_PARAM_PERSP_SAMPLE;
1290
1291 case SI_PARAM_LINEAR_CENTROID:
1292 case SI_PARAM_LINEAR_CENTER:
1293 return SI_PARAM_LINEAR_SAMPLE;
1294
1295 default:
1296 return param;
1297 }
1298 }
1299
1300 /**
1301 * Interpolate a fragment shader input.
1302 *
1303 * @param ctx context
1304 * @param input_index index of the input in hardware
1305 * @param semantic_name TGSI_SEMANTIC_*
1306 * @param semantic_index semantic index
1307 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1308 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1309 * @param interp_param interpolation weights (i,j)
1310 * @param prim_mask SI_PARAM_PRIM_MASK
1311 * @param face SI_PARAM_FRONT_FACE
1312 * @param result the return value (4 components)
1313 */
1314 static void interp_fs_input(struct si_shader_context *ctx,
1315 unsigned input_index,
1316 unsigned semantic_name,
1317 unsigned semantic_index,
1318 unsigned num_interp_inputs,
1319 unsigned colors_read_mask,
1320 LLVMValueRef interp_param,
1321 LLVMValueRef prim_mask,
1322 LLVMValueRef face,
1323 LLVMValueRef result[4])
1324 {
1325 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
1326 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1327 struct gallivm_state *gallivm = base->gallivm;
1328 const char *intr_name;
1329 LLVMValueRef attr_number;
1330
1331 unsigned chan;
1332
1333 attr_number = lp_build_const_int32(gallivm, input_index);
1334
1335 /* fs.constant returns the param from the middle vertex, so it's not
1336 * really useful for flat shading. It's meant to be used for custom
1337 * interpolation (but the intrinsic can't fetch from the other two
1338 * vertices).
1339 *
1340 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1341 * to do the right thing. The only reason we use fs.constant is that
1342 * fs.interp cannot be used on integers, because they can be equal
1343 * to NaN.
1344 */
1345 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
1346
1347 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1348 ctx->shader->key.ps.prolog.color_two_side) {
1349 LLVMValueRef args[4];
1350 LLVMValueRef is_face_positive;
1351 LLVMValueRef back_attr_number;
1352
1353 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1354 * otherwise it's at offset "num_inputs".
1355 */
1356 unsigned back_attr_offset = num_interp_inputs;
1357 if (semantic_index == 1 && colors_read_mask & 0xf)
1358 back_attr_offset += 1;
1359
1360 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1361
1362 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1363 face, uint->zero, "");
1364
1365 args[2] = prim_mask;
1366 args[3] = interp_param;
1367 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1368 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1369 LLVMValueRef front, back;
1370
1371 args[0] = llvm_chan;
1372 args[1] = attr_number;
1373 front = lp_build_intrinsic(gallivm->builder, intr_name,
1374 ctx->f32, args, args[3] ? 4 : 3,
1375 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1376
1377 args[1] = back_attr_number;
1378 back = lp_build_intrinsic(gallivm->builder, intr_name,
1379 ctx->f32, args, args[3] ? 4 : 3,
1380 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1381
1382 result[chan] = LLVMBuildSelect(gallivm->builder,
1383 is_face_positive,
1384 front,
1385 back,
1386 "");
1387 }
1388 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1389 LLVMValueRef args[4];
1390
1391 args[0] = uint->zero;
1392 args[1] = attr_number;
1393 args[2] = prim_mask;
1394 args[3] = interp_param;
1395 result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
1396 ctx->f32, args, args[3] ? 4 : 3,
1397 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1398 result[1] =
1399 result[2] = lp_build_const_float(gallivm, 0.0f);
1400 result[3] = lp_build_const_float(gallivm, 1.0f);
1401 } else {
1402 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1403 LLVMValueRef args[4];
1404 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1405
1406 args[0] = llvm_chan;
1407 args[1] = attr_number;
1408 args[2] = prim_mask;
1409 args[3] = interp_param;
1410 result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
1411 ctx->f32, args, args[3] ? 4 : 3,
1412 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1413 }
1414 }
1415 }
1416
1417 static void declare_input_fs(
1418 struct radeon_llvm_context *radeon_bld,
1419 unsigned input_index,
1420 const struct tgsi_full_declaration *decl)
1421 {
1422 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
1423 struct si_shader_context *ctx =
1424 si_shader_context(&radeon_bld->soa.bld_base);
1425 struct si_shader *shader = ctx->shader;
1426 LLVMValueRef main_fn = radeon_bld->main_fn;
1427 LLVMValueRef interp_param = NULL;
1428 int interp_param_idx;
1429
1430 /* Get colors from input VGPRs (set by the prolog). */
1431 if (!ctx->is_monolithic &&
1432 decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1433 unsigned i = decl->Semantic.Index;
1434 unsigned colors_read = shader->selector->info.colors_read;
1435 unsigned mask = colors_read >> (i * 4);
1436 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1437 (i ? util_bitcount(colors_read & 0xf) : 0);
1438
1439 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
1440 mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1441 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
1442 mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1443 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
1444 mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1445 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
1446 mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1447 return;
1448 }
1449
1450 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1451 decl->Interp.Location);
1452 if (interp_param_idx == -1)
1453 return;
1454 else if (interp_param_idx) {
1455 interp_param_idx = select_interp_param(ctx,
1456 interp_param_idx);
1457 interp_param = LLVMGetParam(main_fn, interp_param_idx);
1458 }
1459
1460 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1461 decl->Semantic.Index, shader->selector->info.num_inputs,
1462 shader->selector->info.colors_read, interp_param,
1463 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1464 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1465 &radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)]);
1466 }
1467
1468 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1469 {
1470 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1471 SI_PARAM_ANCILLARY, 8, 4);
1472 }
1473
1474 /**
1475 * Set range metadata on an instruction. This can only be used on load and
1476 * call instructions. If you know an instruction can only produce the values
1477 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1478 * \p lo is the minimum value inclusive.
1479 * \p hi is the maximum value exclusive.
1480 */
1481 static void set_range_metadata(LLVMValueRef value, unsigned lo, unsigned hi)
1482 {
1483 const char *range_md_string = "range";
1484 LLVMValueRef range_md, md_args[2];
1485 LLVMTypeRef type = LLVMTypeOf(value);
1486 LLVMContextRef context = LLVMGetTypeContext(type);
1487 unsigned md_range_id = LLVMGetMDKindIDInContext(context,
1488 range_md_string, strlen(range_md_string));
1489
1490 md_args[0] = LLVMConstInt(type, lo, false);
1491 md_args[1] = LLVMConstInt(type, hi, false);
1492 range_md = LLVMMDNodeInContext(context, md_args, 2);
1493 LLVMSetMetadata(value, md_range_id, range_md);
1494 }
1495
1496 static LLVMValueRef get_thread_id(struct si_shader_context *ctx)
1497 {
1498 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1499 LLVMValueRef tid;
1500
1501 if (HAVE_LLVM < 0x0308) {
1502 tid = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid",
1503 ctx->i32, NULL, 0, LLVMReadNoneAttribute);
1504 } else {
1505 LLVMValueRef tid_args[2];
1506 tid_args[0] = lp_build_const_int32(gallivm, 0xffffffff);
1507 tid_args[1] = lp_build_const_int32(gallivm, 0);
1508 tid_args[1] = lp_build_intrinsic(gallivm->builder,
1509 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1510 tid_args, 2, LLVMReadNoneAttribute);
1511
1512 tid = lp_build_intrinsic(gallivm->builder,
1513 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1514 tid_args, 2, LLVMReadNoneAttribute);
1515 }
1516 set_range_metadata(tid, 0, 64);
1517 return tid;
1518 }
1519
1520 /**
1521 * Load a dword from a constant buffer.
1522 */
1523 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1524 LLVMValueRef offset, LLVMTypeRef return_type)
1525 {
1526 LLVMValueRef args[2] = {resource, offset};
1527
1528 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1529 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1530 }
1531
1532 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1533 {
1534 struct si_shader_context *ctx =
1535 si_shader_context(&radeon_bld->soa.bld_base);
1536 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1537 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1538 LLVMBuilderRef builder = gallivm->builder;
1539 LLVMValueRef desc = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1540 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS);
1541 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1542
1543 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1544 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1545 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1546
1547 LLVMValueRef pos[4] = {
1548 buffer_load_const(builder, resource, offset0, ctx->f32),
1549 buffer_load_const(builder, resource, offset1, ctx->f32),
1550 lp_build_const_float(gallivm, 0),
1551 lp_build_const_float(gallivm, 0)
1552 };
1553
1554 return lp_build_gather_values(gallivm, pos, 4);
1555 }
1556
1557 static void declare_system_value(
1558 struct radeon_llvm_context *radeon_bld,
1559 unsigned index,
1560 const struct tgsi_full_declaration *decl)
1561 {
1562 struct si_shader_context *ctx =
1563 si_shader_context(&radeon_bld->soa.bld_base);
1564 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1565 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1566 LLVMValueRef value = 0;
1567
1568 switch (decl->Semantic.Name) {
1569 case TGSI_SEMANTIC_INSTANCEID:
1570 value = LLVMGetParam(radeon_bld->main_fn,
1571 ctx->param_instance_id);
1572 break;
1573
1574 case TGSI_SEMANTIC_VERTEXID:
1575 value = LLVMBuildAdd(gallivm->builder,
1576 LLVMGetParam(radeon_bld->main_fn,
1577 ctx->param_vertex_id),
1578 LLVMGetParam(radeon_bld->main_fn,
1579 SI_PARAM_BASE_VERTEX), "");
1580 break;
1581
1582 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1583 value = LLVMGetParam(radeon_bld->main_fn,
1584 ctx->param_vertex_id);
1585 break;
1586
1587 case TGSI_SEMANTIC_BASEVERTEX:
1588 value = LLVMGetParam(radeon_bld->main_fn,
1589 SI_PARAM_BASE_VERTEX);
1590 break;
1591
1592 case TGSI_SEMANTIC_INVOCATIONID:
1593 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1594 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1595 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1596 value = LLVMGetParam(radeon_bld->main_fn,
1597 SI_PARAM_GS_INSTANCE_ID);
1598 else
1599 assert(!"INVOCATIONID not implemented");
1600 break;
1601
1602 case TGSI_SEMANTIC_POSITION:
1603 {
1604 LLVMValueRef pos[4] = {
1605 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1606 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1607 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1608 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1609 LLVMGetParam(radeon_bld->main_fn,
1610 SI_PARAM_POS_W_FLOAT)),
1611 };
1612 value = lp_build_gather_values(gallivm, pos, 4);
1613 break;
1614 }
1615
1616 case TGSI_SEMANTIC_FACE:
1617 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1618 break;
1619
1620 case TGSI_SEMANTIC_SAMPLEID:
1621 value = get_sample_id(radeon_bld);
1622 break;
1623
1624 case TGSI_SEMANTIC_SAMPLEPOS: {
1625 LLVMValueRef pos[4] = {
1626 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1627 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1628 lp_build_const_float(gallivm, 0),
1629 lp_build_const_float(gallivm, 0)
1630 };
1631 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1632 TGSI_OPCODE_FRC, pos[0]);
1633 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1634 TGSI_OPCODE_FRC, pos[1]);
1635 value = lp_build_gather_values(gallivm, pos, 4);
1636 break;
1637 }
1638
1639 case TGSI_SEMANTIC_SAMPLEMASK:
1640 /* This can only occur with the OpenGL Core profile, which
1641 * doesn't support smoothing.
1642 */
1643 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1644 break;
1645
1646 case TGSI_SEMANTIC_TESSCOORD:
1647 {
1648 LLVMValueRef coord[4] = {
1649 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1650 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1651 bld->zero,
1652 bld->zero
1653 };
1654
1655 /* For triangles, the vector should be (u, v, 1-u-v). */
1656 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1657 PIPE_PRIM_TRIANGLES)
1658 coord[2] = lp_build_sub(bld, bld->one,
1659 lp_build_add(bld, coord[0], coord[1]));
1660
1661 value = lp_build_gather_values(gallivm, coord, 4);
1662 break;
1663 }
1664
1665 case TGSI_SEMANTIC_VERTICESIN:
1666 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1667 break;
1668
1669 case TGSI_SEMANTIC_TESSINNER:
1670 case TGSI_SEMANTIC_TESSOUTER:
1671 {
1672 LLVMValueRef rw_buffers, buffer, base, addr;
1673 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1674
1675 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1676 SI_PARAM_RW_BUFFERS);
1677 buffer = build_indexed_load_const(ctx, rw_buffers,
1678 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1679
1680 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1681 addr = get_tcs_tes_buffer_address(ctx, NULL,
1682 lp_build_const_int32(gallivm, param));
1683
1684 value = buffer_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1685 ~0, buffer, base, addr);
1686
1687 break;
1688 }
1689
1690 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1691 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1692 {
1693 LLVMValueRef buf, slot, val[4];
1694 int i, offset;
1695
1696 slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS);
1697 buf = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1698 buf = build_indexed_load_const(ctx, buf, slot);
1699 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1700
1701 for (i = 0; i < 4; i++)
1702 val[i] = buffer_load_const(gallivm->builder, buf,
1703 lp_build_const_int32(gallivm, (offset + i) * 4),
1704 ctx->f32);
1705 value = lp_build_gather_values(gallivm, val, 4);
1706 break;
1707 }
1708
1709 case TGSI_SEMANTIC_PRIMID:
1710 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1711 break;
1712
1713 case TGSI_SEMANTIC_GRID_SIZE:
1714 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
1715 break;
1716
1717 case TGSI_SEMANTIC_BLOCK_SIZE:
1718 {
1719 LLVMValueRef values[3];
1720 unsigned i;
1721 unsigned *properties = ctx->shader->selector->info.properties;
1722 unsigned sizes[3] = {
1723 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1724 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1725 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1726 };
1727
1728 for (i = 0; i < 3; ++i)
1729 values[i] = lp_build_const_int32(gallivm, sizes[i]);
1730
1731 value = lp_build_gather_values(gallivm, values, 3);
1732 break;
1733 }
1734
1735 case TGSI_SEMANTIC_BLOCK_ID:
1736 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
1737 break;
1738
1739 case TGSI_SEMANTIC_THREAD_ID:
1740 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
1741 break;
1742
1743 #if HAVE_LLVM >= 0x0309
1744 case TGSI_SEMANTIC_HELPER_INVOCATION:
1745 value = lp_build_intrinsic(gallivm->builder,
1746 "llvm.amdgcn.ps.live",
1747 ctx->i1, NULL, 0,
1748 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1749 value = LLVMBuildNot(gallivm->builder, value, "");
1750 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1751 break;
1752 #endif
1753
1754 default:
1755 assert(!"unknown system value");
1756 return;
1757 }
1758
1759 radeon_bld->system_values[index] = value;
1760 }
1761
1762 static void declare_compute_memory(struct radeon_llvm_context *radeon_bld,
1763 const struct tgsi_full_declaration *decl)
1764 {
1765 struct si_shader_context *ctx =
1766 si_shader_context(&radeon_bld->soa.bld_base);
1767 struct si_shader_selector *sel = ctx->shader->selector;
1768 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1769
1770 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1771 LLVMValueRef var;
1772
1773 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1774 assert(decl->Range.First == decl->Range.Last);
1775 assert(!ctx->shared_memory);
1776
1777 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1778 LLVMArrayType(ctx->i8, sel->local_size),
1779 "compute_lds",
1780 LOCAL_ADDR_SPACE);
1781 LLVMSetAlignment(var, 4);
1782
1783 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1784 }
1785
1786 static LLVMValueRef fetch_constant(
1787 struct lp_build_tgsi_context *bld_base,
1788 const struct tgsi_full_src_register *reg,
1789 enum tgsi_opcode_type type,
1790 unsigned swizzle)
1791 {
1792 struct si_shader_context *ctx = si_shader_context(bld_base);
1793 struct lp_build_context *base = &bld_base->base;
1794 const struct tgsi_ind_register *ireg = &reg->Indirect;
1795 unsigned buf, idx;
1796
1797 LLVMValueRef addr, bufp;
1798 LLVMValueRef result;
1799
1800 if (swizzle == LP_CHAN_ALL) {
1801 unsigned chan;
1802 LLVMValueRef values[4];
1803 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1804 values[chan] = fetch_constant(bld_base, reg, type, chan);
1805
1806 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1807 }
1808
1809 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1810 idx = reg->Register.Index * 4 + swizzle;
1811
1812 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1813 if (type != TGSI_TYPE_DOUBLE)
1814 return bitcast(bld_base, type, ctx->constants[buf][idx]);
1815 else {
1816 return radeon_llvm_emit_fetch_double(bld_base,
1817 ctx->constants[buf][idx],
1818 ctx->constants[buf][idx + 1]);
1819 }
1820 }
1821
1822 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1823 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1824 LLVMValueRef index;
1825 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1826 reg->Dimension.Index,
1827 SI_NUM_CONST_BUFFERS);
1828 bufp = build_indexed_load_const(ctx, ptr, index);
1829 } else
1830 bufp = ctx->const_buffers[buf];
1831
1832 addr = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1833 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1834 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1835 addr = lp_build_add(&bld_base->uint_bld, addr,
1836 lp_build_const_int32(base->gallivm, idx * 4));
1837
1838 result = buffer_load_const(base->gallivm->builder, bufp,
1839 addr, ctx->f32);
1840
1841 if (type != TGSI_TYPE_DOUBLE)
1842 result = bitcast(bld_base, type, result);
1843 else {
1844 LLVMValueRef addr2, result2;
1845 addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1846 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1847 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1848 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1849 lp_build_const_int32(base->gallivm, idx * 4));
1850
1851 result2 = buffer_load_const(base->gallivm->builder, ctx->const_buffers[buf],
1852 addr2, ctx->f32);
1853
1854 result = radeon_llvm_emit_fetch_double(bld_base,
1855 result, result2);
1856 }
1857 return result;
1858 }
1859
1860 /* Upper 16 bits must be zero. */
1861 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1862 LLVMValueRef val[2])
1863 {
1864 return LLVMBuildOr(gallivm->builder, val[0],
1865 LLVMBuildShl(gallivm->builder, val[1],
1866 lp_build_const_int32(gallivm, 16),
1867 ""), "");
1868 }
1869
1870 /* Upper 16 bits are ignored and will be dropped. */
1871 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1872 LLVMValueRef val[2])
1873 {
1874 LLVMValueRef v[2] = {
1875 LLVMBuildAnd(gallivm->builder, val[0],
1876 lp_build_const_int32(gallivm, 0xffff), ""),
1877 val[1],
1878 };
1879 return si_llvm_pack_two_int16(gallivm, v);
1880 }
1881
1882 /* Initialize arguments for the shader export intrinsic */
1883 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1884 LLVMValueRef *values,
1885 unsigned target,
1886 LLVMValueRef *args)
1887 {
1888 struct si_shader_context *ctx = si_shader_context(bld_base);
1889 struct lp_build_context *uint =
1890 &ctx->radeon_bld.soa.bld_base.uint_bld;
1891 struct lp_build_context *base = &bld_base->base;
1892 struct gallivm_state *gallivm = base->gallivm;
1893 LLVMBuilderRef builder = base->gallivm->builder;
1894 LLVMValueRef val[4];
1895 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1896 unsigned chan;
1897 bool is_int8;
1898
1899 /* Default is 0xf. Adjusted below depending on the format. */
1900 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1901
1902 /* Specify whether the EXEC mask represents the valid mask */
1903 args[1] = uint->zero;
1904
1905 /* Specify whether this is the last export */
1906 args[2] = uint->zero;
1907
1908 /* Specify the target we are exporting */
1909 args[3] = lp_build_const_int32(base->gallivm, target);
1910
1911 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1912 const union si_shader_key *key = &ctx->shader->key;
1913 unsigned col_formats = key->ps.epilog.spi_shader_col_format;
1914 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1915
1916 assert(cbuf >= 0 && cbuf < 8);
1917 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1918 is_int8 = (key->ps.epilog.color_is_int8 >> cbuf) & 0x1;
1919 }
1920
1921 args[4] = uint->zero; /* COMPR flag */
1922 args[5] = base->undef;
1923 args[6] = base->undef;
1924 args[7] = base->undef;
1925 args[8] = base->undef;
1926
1927 switch (spi_shader_col_format) {
1928 case V_028714_SPI_SHADER_ZERO:
1929 args[0] = uint->zero; /* writemask */
1930 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
1931 break;
1932
1933 case V_028714_SPI_SHADER_32_R:
1934 args[0] = uint->one; /* writemask */
1935 args[5] = values[0];
1936 break;
1937
1938 case V_028714_SPI_SHADER_32_GR:
1939 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
1940 args[5] = values[0];
1941 args[6] = values[1];
1942 break;
1943
1944 case V_028714_SPI_SHADER_32_AR:
1945 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
1946 args[5] = values[0];
1947 args[8] = values[3];
1948 break;
1949
1950 case V_028714_SPI_SHADER_FP16_ABGR:
1951 args[4] = uint->one; /* COMPR flag */
1952
1953 for (chan = 0; chan < 2; chan++) {
1954 LLVMValueRef pack_args[2] = {
1955 values[2 * chan],
1956 values[2 * chan + 1]
1957 };
1958 LLVMValueRef packed;
1959
1960 packed = lp_build_intrinsic(base->gallivm->builder,
1961 "llvm.SI.packf16",
1962 ctx->i32, pack_args, 2,
1963 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1964 args[chan + 5] =
1965 LLVMBuildBitCast(base->gallivm->builder,
1966 packed, ctx->f32, "");
1967 }
1968 break;
1969
1970 case V_028714_SPI_SHADER_UNORM16_ABGR:
1971 for (chan = 0; chan < 4; chan++) {
1972 val[chan] = radeon_llvm_saturate(bld_base, values[chan]);
1973 val[chan] = LLVMBuildFMul(builder, val[chan],
1974 lp_build_const_float(gallivm, 65535), "");
1975 val[chan] = LLVMBuildFAdd(builder, val[chan],
1976 lp_build_const_float(gallivm, 0.5), "");
1977 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1978 ctx->i32, "");
1979 }
1980
1981 args[4] = uint->one; /* COMPR flag */
1982 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1983 si_llvm_pack_two_int16(gallivm, val));
1984 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1985 si_llvm_pack_two_int16(gallivm, val+2));
1986 break;
1987
1988 case V_028714_SPI_SHADER_SNORM16_ABGR:
1989 for (chan = 0; chan < 4; chan++) {
1990 /* Clamp between [-1, 1]. */
1991 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1992 values[chan],
1993 lp_build_const_float(gallivm, 1));
1994 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1995 val[chan],
1996 lp_build_const_float(gallivm, -1));
1997 /* Convert to a signed integer in [-32767, 32767]. */
1998 val[chan] = LLVMBuildFMul(builder, val[chan],
1999 lp_build_const_float(gallivm, 32767), "");
2000 /* If positive, add 0.5, else add -0.5. */
2001 val[chan] = LLVMBuildFAdd(builder, val[chan],
2002 LLVMBuildSelect(builder,
2003 LLVMBuildFCmp(builder, LLVMRealOGE,
2004 val[chan], base->zero, ""),
2005 lp_build_const_float(gallivm, 0.5),
2006 lp_build_const_float(gallivm, -0.5), ""), "");
2007 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2008 }
2009
2010 args[4] = uint->one; /* COMPR flag */
2011 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2012 si_llvm_pack_two_int32_as_int16(gallivm, val));
2013 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2014 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2015 break;
2016
2017 case V_028714_SPI_SHADER_UINT16_ABGR: {
2018 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2019 255 : 65535);
2020 /* Clamp. */
2021 for (chan = 0; chan < 4; chan++) {
2022 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2023 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
2024 val[chan], max);
2025 }
2026
2027 args[4] = uint->one; /* COMPR flag */
2028 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2029 si_llvm_pack_two_int16(gallivm, val));
2030 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2031 si_llvm_pack_two_int16(gallivm, val+2));
2032 break;
2033 }
2034
2035 case V_028714_SPI_SHADER_SINT16_ABGR: {
2036 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2037 127 : 32767);
2038 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
2039 -128 : -32768);
2040 /* Clamp. */
2041 for (chan = 0; chan < 4; chan++) {
2042 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2043 val[chan] = lp_build_emit_llvm_binary(bld_base,
2044 TGSI_OPCODE_IMIN,
2045 val[chan], max);
2046 val[chan] = lp_build_emit_llvm_binary(bld_base,
2047 TGSI_OPCODE_IMAX,
2048 val[chan], min);
2049 }
2050
2051 args[4] = uint->one; /* COMPR flag */
2052 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2053 si_llvm_pack_two_int32_as_int16(gallivm, val));
2054 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2055 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2056 break;
2057 }
2058
2059 case V_028714_SPI_SHADER_32_ABGR:
2060 memcpy(&args[5], values, sizeof(values[0]) * 4);
2061 break;
2062 }
2063 }
2064
2065 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2066 LLVMValueRef alpha)
2067 {
2068 struct si_shader_context *ctx = si_shader_context(bld_base);
2069 struct gallivm_state *gallivm = bld_base->base.gallivm;
2070
2071 if (ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2072 LLVMValueRef alpha_ref = LLVMGetParam(ctx->radeon_bld.main_fn,
2073 SI_PARAM_ALPHA_REF);
2074
2075 LLVMValueRef alpha_pass =
2076 lp_build_cmp(&bld_base->base,
2077 ctx->shader->key.ps.epilog.alpha_func,
2078 alpha, alpha_ref);
2079 LLVMValueRef arg =
2080 lp_build_select(&bld_base->base,
2081 alpha_pass,
2082 lp_build_const_float(gallivm, 1.0f),
2083 lp_build_const_float(gallivm, -1.0f));
2084
2085 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2086 ctx->voidt, &arg, 1, 0);
2087 } else {
2088 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
2089 ctx->voidt, NULL, 0, 0);
2090 }
2091 }
2092
2093 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2094 LLVMValueRef alpha,
2095 unsigned samplemask_param)
2096 {
2097 struct si_shader_context *ctx = si_shader_context(bld_base);
2098 struct gallivm_state *gallivm = bld_base->base.gallivm;
2099 LLVMValueRef coverage;
2100
2101 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2102 coverage = LLVMGetParam(ctx->radeon_bld.main_fn,
2103 samplemask_param);
2104 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
2105
2106 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
2107 ctx->i32,
2108 &coverage, 1, LLVMReadNoneAttribute);
2109
2110 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
2111 ctx->f32, "");
2112
2113 coverage = LLVMBuildFMul(gallivm->builder, coverage,
2114 lp_build_const_float(gallivm,
2115 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2116
2117 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
2118 }
2119
2120 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2121 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
2122 {
2123 struct si_shader_context *ctx = si_shader_context(bld_base);
2124 struct lp_build_context *base = &bld_base->base;
2125 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
2126 unsigned reg_index;
2127 unsigned chan;
2128 unsigned const_chan;
2129 LLVMValueRef base_elt;
2130 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
2131 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm,
2132 SI_VS_CONST_CLIP_PLANES);
2133 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
2134
2135 for (reg_index = 0; reg_index < 2; reg_index ++) {
2136 LLVMValueRef *args = pos[2 + reg_index];
2137
2138 args[5] =
2139 args[6] =
2140 args[7] =
2141 args[8] = lp_build_const_float(base->gallivm, 0.0f);
2142
2143 /* Compute dot products of position and user clip plane vectors */
2144 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2145 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2146 args[1] = lp_build_const_int32(base->gallivm,
2147 ((reg_index * 4 + chan) * 4 +
2148 const_chan) * 4);
2149 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
2150 args[1], ctx->f32);
2151 args[5 + chan] =
2152 lp_build_add(base, args[5 + chan],
2153 lp_build_mul(base, base_elt,
2154 out_elts[const_chan]));
2155 }
2156 }
2157
2158 args[0] = lp_build_const_int32(base->gallivm, 0xf);
2159 args[1] = uint->zero;
2160 args[2] = uint->zero;
2161 args[3] = lp_build_const_int32(base->gallivm,
2162 V_008DFC_SQ_EXP_POS + 2 + reg_index);
2163 args[4] = uint->zero;
2164 }
2165 }
2166
2167 static void si_dump_streamout(struct pipe_stream_output_info *so)
2168 {
2169 unsigned i;
2170
2171 if (so->num_outputs)
2172 fprintf(stderr, "STREAMOUT\n");
2173
2174 for (i = 0; i < so->num_outputs; i++) {
2175 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2176 so->output[i].start_component;
2177 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2178 i, so->output[i].output_buffer,
2179 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2180 so->output[i].register_index,
2181 mask & 1 ? "x" : "",
2182 mask & 2 ? "y" : "",
2183 mask & 4 ? "z" : "",
2184 mask & 8 ? "w" : "");
2185 }
2186 }
2187
2188 /* On SI, the vertex shader is responsible for writing streamout data
2189 * to buffers. */
2190 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2191 struct si_shader_output_values *outputs,
2192 unsigned noutput)
2193 {
2194 struct pipe_stream_output_info *so = &ctx->shader->selector->so;
2195 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
2196 LLVMBuilderRef builder = gallivm->builder;
2197 int i, j;
2198 struct lp_build_if_state if_ctx;
2199
2200 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2201 LLVMValueRef so_vtx_count =
2202 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2203
2204 LLVMValueRef tid = get_thread_id(ctx);
2205
2206 /* can_emit = tid < so_vtx_count; */
2207 LLVMValueRef can_emit =
2208 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2209
2210 LLVMValueRef stream_id =
2211 unpack_param(ctx, ctx->param_streamout_config, 24, 2);
2212
2213 /* Emit the streamout code conditionally. This actually avoids
2214 * out-of-bounds buffer access. The hw tells us via the SGPR
2215 * (so_vtx_count) which threads are allowed to emit streamout data. */
2216 lp_build_if(&if_ctx, gallivm, can_emit);
2217 {
2218 /* The buffer offset is computed as follows:
2219 * ByteOffset = streamout_offset[buffer_id]*4 +
2220 * (streamout_write_index + thread_id)*stride[buffer_id] +
2221 * attrib_offset
2222 */
2223
2224 LLVMValueRef so_write_index =
2225 LLVMGetParam(ctx->radeon_bld.main_fn,
2226 ctx->param_streamout_write_index);
2227
2228 /* Compute (streamout_write_index + thread_id). */
2229 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2230
2231 /* Compute the write offset for each enabled buffer. */
2232 LLVMValueRef so_write_offset[4] = {};
2233 for (i = 0; i < 4; i++) {
2234 if (!so->stride[i])
2235 continue;
2236
2237 LLVMValueRef so_offset = LLVMGetParam(ctx->radeon_bld.main_fn,
2238 ctx->param_streamout_offset[i]);
2239 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2240
2241 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2242 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2243 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2244 }
2245
2246 /* Write streamout data. */
2247 for (i = 0; i < so->num_outputs; i++) {
2248 unsigned buf_idx = so->output[i].output_buffer;
2249 unsigned reg = so->output[i].register_index;
2250 unsigned start = so->output[i].start_component;
2251 unsigned num_comps = so->output[i].num_components;
2252 unsigned stream = so->output[i].stream;
2253 LLVMValueRef out[4];
2254 struct lp_build_if_state if_ctx_stream;
2255
2256 assert(num_comps && num_comps <= 4);
2257 if (!num_comps || num_comps > 4)
2258 continue;
2259
2260 if (reg >= noutput)
2261 continue;
2262
2263 /* Load the output as int. */
2264 for (j = 0; j < num_comps; j++) {
2265 out[j] = LLVMBuildBitCast(builder,
2266 outputs[reg].values[start+j],
2267 ctx->i32, "");
2268 }
2269
2270 /* Pack the output. */
2271 LLVMValueRef vdata = NULL;
2272
2273 switch (num_comps) {
2274 case 1: /* as i32 */
2275 vdata = out[0];
2276 break;
2277 case 2: /* as v2i32 */
2278 case 3: /* as v4i32 (aligned to 4) */
2279 case 4: /* as v4i32 */
2280 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2281 for (j = 0; j < num_comps; j++) {
2282 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2283 LLVMConstInt(ctx->i32, j, 0), "");
2284 }
2285 break;
2286 }
2287
2288 LLVMValueRef can_emit_stream =
2289 LLVMBuildICmp(builder, LLVMIntEQ,
2290 stream_id,
2291 lp_build_const_int32(gallivm, stream), "");
2292
2293 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
2294 build_tbuffer_store_dwords(ctx, ctx->so_buffers[buf_idx],
2295 vdata, num_comps,
2296 so_write_offset[buf_idx],
2297 LLVMConstInt(ctx->i32, 0, 0),
2298 so->output[i].dst_offset*4);
2299 lp_build_endif(&if_ctx_stream);
2300 }
2301 }
2302 lp_build_endif(&if_ctx);
2303 }
2304
2305
2306 /* Generate export instructions for hardware VS shader stage */
2307 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2308 struct si_shader_output_values *outputs,
2309 unsigned noutput)
2310 {
2311 struct si_shader_context *ctx = si_shader_context(bld_base);
2312 struct si_shader *shader = ctx->shader;
2313 struct lp_build_context *base = &bld_base->base;
2314 struct lp_build_context *uint =
2315 &ctx->radeon_bld.soa.bld_base.uint_bld;
2316 LLVMValueRef args[9];
2317 LLVMValueRef pos_args[4][9] = { { 0 } };
2318 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2319 unsigned semantic_name, semantic_index;
2320 unsigned target;
2321 unsigned param_count = 0;
2322 unsigned pos_idx;
2323 int i;
2324
2325 if (outputs && ctx->shader->selector->so.num_outputs) {
2326 si_llvm_emit_streamout(ctx, outputs, noutput);
2327 }
2328
2329 for (i = 0; i < noutput; i++) {
2330 semantic_name = outputs[i].name;
2331 semantic_index = outputs[i].sid;
2332
2333 handle_semantic:
2334 /* Select the correct target */
2335 switch(semantic_name) {
2336 case TGSI_SEMANTIC_PSIZE:
2337 psize_value = outputs[i].values[0];
2338 continue;
2339 case TGSI_SEMANTIC_EDGEFLAG:
2340 edgeflag_value = outputs[i].values[0];
2341 continue;
2342 case TGSI_SEMANTIC_LAYER:
2343 layer_value = outputs[i].values[0];
2344 semantic_name = TGSI_SEMANTIC_GENERIC;
2345 goto handle_semantic;
2346 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2347 viewport_index_value = outputs[i].values[0];
2348 semantic_name = TGSI_SEMANTIC_GENERIC;
2349 goto handle_semantic;
2350 case TGSI_SEMANTIC_POSITION:
2351 target = V_008DFC_SQ_EXP_POS;
2352 break;
2353 case TGSI_SEMANTIC_COLOR:
2354 case TGSI_SEMANTIC_BCOLOR:
2355 target = V_008DFC_SQ_EXP_PARAM + param_count;
2356 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2357 shader->info.vs_output_param_offset[i] = param_count;
2358 param_count++;
2359 break;
2360 case TGSI_SEMANTIC_CLIPDIST:
2361 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2362 break;
2363 case TGSI_SEMANTIC_CLIPVERTEX:
2364 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2365 continue;
2366 case TGSI_SEMANTIC_PRIMID:
2367 case TGSI_SEMANTIC_FOG:
2368 case TGSI_SEMANTIC_TEXCOORD:
2369 case TGSI_SEMANTIC_GENERIC:
2370 target = V_008DFC_SQ_EXP_PARAM + param_count;
2371 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2372 shader->info.vs_output_param_offset[i] = param_count;
2373 param_count++;
2374 break;
2375 default:
2376 target = 0;
2377 fprintf(stderr,
2378 "Warning: SI unhandled vs output type:%d\n",
2379 semantic_name);
2380 }
2381
2382 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
2383
2384 if (target >= V_008DFC_SQ_EXP_POS &&
2385 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2386 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
2387 args, sizeof(args));
2388 } else {
2389 lp_build_intrinsic(base->gallivm->builder,
2390 "llvm.SI.export", ctx->voidt,
2391 args, 9, 0);
2392 }
2393
2394 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2395 semantic_name = TGSI_SEMANTIC_GENERIC;
2396 goto handle_semantic;
2397 }
2398 }
2399
2400 shader->info.nr_param_exports = param_count;
2401
2402 /* We need to add the position output manually if it's missing. */
2403 if (!pos_args[0][0]) {
2404 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
2405 pos_args[0][1] = uint->zero; /* EXEC mask */
2406 pos_args[0][2] = uint->zero; /* last export? */
2407 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
2408 pos_args[0][4] = uint->zero; /* COMPR flag */
2409 pos_args[0][5] = base->zero; /* X */
2410 pos_args[0][6] = base->zero; /* Y */
2411 pos_args[0][7] = base->zero; /* Z */
2412 pos_args[0][8] = base->one; /* W */
2413 }
2414
2415 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2416 if (shader->selector->info.writes_psize ||
2417 shader->selector->info.writes_edgeflag ||
2418 shader->selector->info.writes_viewport_index ||
2419 shader->selector->info.writes_layer) {
2420 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
2421 shader->selector->info.writes_psize |
2422 (shader->selector->info.writes_edgeflag << 1) |
2423 (shader->selector->info.writes_layer << 2) |
2424 (shader->selector->info.writes_viewport_index << 3));
2425 pos_args[1][1] = uint->zero; /* EXEC mask */
2426 pos_args[1][2] = uint->zero; /* last export? */
2427 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
2428 pos_args[1][4] = uint->zero; /* COMPR flag */
2429 pos_args[1][5] = base->zero; /* X */
2430 pos_args[1][6] = base->zero; /* Y */
2431 pos_args[1][7] = base->zero; /* Z */
2432 pos_args[1][8] = base->zero; /* W */
2433
2434 if (shader->selector->info.writes_psize)
2435 pos_args[1][5] = psize_value;
2436
2437 if (shader->selector->info.writes_edgeflag) {
2438 /* The output is a float, but the hw expects an integer
2439 * with the first bit containing the edge flag. */
2440 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2441 edgeflag_value,
2442 ctx->i32, "");
2443 edgeflag_value = lp_build_min(&bld_base->int_bld,
2444 edgeflag_value,
2445 bld_base->int_bld.one);
2446
2447 /* The LLVM intrinsic expects a float. */
2448 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
2449 edgeflag_value,
2450 ctx->f32, "");
2451 }
2452
2453 if (shader->selector->info.writes_layer)
2454 pos_args[1][7] = layer_value;
2455
2456 if (shader->selector->info.writes_viewport_index)
2457 pos_args[1][8] = viewport_index_value;
2458 }
2459
2460 for (i = 0; i < 4; i++)
2461 if (pos_args[i][0])
2462 shader->info.nr_pos_exports++;
2463
2464 pos_idx = 0;
2465 for (i = 0; i < 4; i++) {
2466 if (!pos_args[i][0])
2467 continue;
2468
2469 /* Specify the target we are exporting */
2470 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
2471
2472 if (pos_idx == shader->info.nr_pos_exports)
2473 /* Specify that this is the last export */
2474 pos_args[i][2] = uint->one;
2475
2476 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2477 ctx->voidt, pos_args[i], 9, 0);
2478 }
2479 }
2480
2481 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2482 {
2483 struct si_shader_context *ctx = si_shader_context(bld_base);
2484 struct gallivm_state *gallivm = bld_base->base.gallivm;
2485 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2486 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2487 uint64_t inputs;
2488
2489 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2490
2491 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
2492 buffer = build_indexed_load_const(ctx, rw_buffers,
2493 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
2494
2495 buffer_offset = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
2496
2497 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
2498 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2499 lds_vertex_stride, "");
2500 lds_base = get_tcs_in_current_patch_offset(ctx);
2501 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2502
2503 inputs = ctx->shader->key.tcs.epilog.inputs_to_copy;
2504 while (inputs) {
2505 unsigned i = u_bit_scan64(&inputs);
2506
2507 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2508 lp_build_const_int32(gallivm, 4 * i),
2509 "");
2510
2511 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2512 invocation_id,
2513 lp_build_const_int32(gallivm, i));
2514
2515 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2516 lds_ptr);
2517
2518 build_tbuffer_store_dwords(ctx, buffer, value, 4, buffer_addr,
2519 buffer_offset, 0);
2520 }
2521 }
2522
2523 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2524 LLVMValueRef rel_patch_id,
2525 LLVMValueRef invocation_id,
2526 LLVMValueRef tcs_out_current_patch_data_offset)
2527 {
2528 struct si_shader_context *ctx = si_shader_context(bld_base);
2529 struct gallivm_state *gallivm = bld_base->base.gallivm;
2530 struct si_shader *shader = ctx->shader;
2531 unsigned tess_inner_index, tess_outer_index;
2532 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2533 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2534 unsigned stride, outer_comps, inner_comps, i;
2535 struct lp_build_if_state if_ctx;
2536
2537 /* Do this only for invocation 0, because the tess levels are per-patch,
2538 * not per-vertex.
2539 *
2540 * This can't jump, because invocation 0 executes this. It should
2541 * at least mask out the loads and stores for other invocations.
2542 */
2543 lp_build_if(&if_ctx, gallivm,
2544 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2545 invocation_id, bld_base->uint_bld.zero, ""));
2546
2547 /* Determine the layout of one tess factor element in the buffer. */
2548 switch (shader->key.tcs.epilog.prim_mode) {
2549 case PIPE_PRIM_LINES:
2550 stride = 2; /* 2 dwords, 1 vec2 store */
2551 outer_comps = 2;
2552 inner_comps = 0;
2553 break;
2554 case PIPE_PRIM_TRIANGLES:
2555 stride = 4; /* 4 dwords, 1 vec4 store */
2556 outer_comps = 3;
2557 inner_comps = 1;
2558 break;
2559 case PIPE_PRIM_QUADS:
2560 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2561 outer_comps = 4;
2562 inner_comps = 2;
2563 break;
2564 default:
2565 assert(0);
2566 return;
2567 }
2568
2569 /* Load tess_inner and tess_outer from LDS.
2570 * Any invocation can write them, so we can't get them from a temporary.
2571 */
2572 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2573 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2574
2575 lds_base = tcs_out_current_patch_data_offset;
2576 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2577 lp_build_const_int32(gallivm,
2578 tess_inner_index * 4), "");
2579 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2580 lp_build_const_int32(gallivm,
2581 tess_outer_index * 4), "");
2582
2583 for (i = 0; i < outer_comps; i++)
2584 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2585 for (i = 0; i < inner_comps; i++)
2586 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2587
2588 /* Convert the outputs to vectors for stores. */
2589 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2590 vec1 = NULL;
2591
2592 if (stride > 4)
2593 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2594
2595 /* Get the buffer. */
2596 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2597 SI_PARAM_RW_BUFFERS);
2598 buffer = build_indexed_load_const(ctx, rw_buffers,
2599 lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
2600
2601 /* Get the offset. */
2602 tf_base = LLVMGetParam(ctx->radeon_bld.main_fn,
2603 SI_PARAM_TESS_FACTOR_OFFSET);
2604 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2605 lp_build_const_int32(gallivm, 4 * stride), "");
2606
2607 /* Store the outputs. */
2608 build_tbuffer_store_dwords(ctx, buffer, vec0,
2609 MIN2(stride, 4), byteoffset, tf_base, 0);
2610 if (vec1)
2611 build_tbuffer_store_dwords(ctx, buffer, vec1,
2612 stride - 4, byteoffset, tf_base, 16);
2613 lp_build_endif(&if_ctx);
2614 }
2615
2616 /* This only writes the tessellation factor levels. */
2617 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2618 {
2619 struct si_shader_context *ctx = si_shader_context(bld_base);
2620 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2621
2622 rel_patch_id = get_rel_patch_id(ctx);
2623 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2624 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2625
2626 if (!ctx->is_monolithic) {
2627 /* Return epilog parameters from this function. */
2628 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2629 LLVMValueRef ret = ctx->return_value;
2630 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2631 unsigned vgpr;
2632
2633 /* RW_BUFFERS pointer */
2634 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2635 SI_PARAM_RW_BUFFERS);
2636 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2637 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2638 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2639 bld_base->uint_bld.zero, "");
2640 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2641 bld_base->uint_bld.one, "");
2642 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2643 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2644
2645 /* Tess factor buffer soffset is after user SGPRs. */
2646 tf_soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2647 SI_PARAM_TESS_FACTOR_OFFSET);
2648 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2649 SI_TCS_NUM_USER_SGPR + 1, "");
2650
2651 /* VGPRs */
2652 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2653 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2654 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2655
2656 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2657 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2658 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2659 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2660 ctx->return_value = ret;
2661 return;
2662 }
2663
2664 si_copy_tcs_inputs(bld_base);
2665 si_write_tess_factors(bld_base, rel_patch_id, invocation_id, tf_lds_offset);
2666 }
2667
2668 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2669 {
2670 struct si_shader_context *ctx = si_shader_context(bld_base);
2671 struct si_shader *shader = ctx->shader;
2672 struct tgsi_shader_info *info = &shader->selector->info;
2673 struct gallivm_state *gallivm = bld_base->base.gallivm;
2674 unsigned i, chan;
2675 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
2676 ctx->param_rel_auto_id);
2677 LLVMValueRef vertex_dw_stride =
2678 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2679 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2680 vertex_dw_stride, "");
2681
2682 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2683 * its inputs from it. */
2684 for (i = 0; i < info->num_outputs; i++) {
2685 LLVMValueRef *out_ptr = ctx->radeon_bld.soa.outputs[i];
2686 unsigned name = info->output_semantic_name[i];
2687 unsigned index = info->output_semantic_index[i];
2688 int param = si_shader_io_get_unique_index(name, index);
2689 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2690 lp_build_const_int32(gallivm, param * 4), "");
2691
2692 for (chan = 0; chan < 4; chan++) {
2693 lds_store(bld_base, chan, dw_addr,
2694 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2695 }
2696 }
2697 }
2698
2699 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2700 {
2701 struct si_shader_context *ctx = si_shader_context(bld_base);
2702 struct gallivm_state *gallivm = bld_base->base.gallivm;
2703 struct si_shader *es = ctx->shader;
2704 struct tgsi_shader_info *info = &es->selector->info;
2705 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2706 ctx->param_es2gs_offset);
2707 unsigned chan;
2708 int i;
2709
2710 for (i = 0; i < info->num_outputs; i++) {
2711 LLVMValueRef *out_ptr =
2712 ctx->radeon_bld.soa.outputs[i];
2713 int param_index;
2714
2715 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2716 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2717 continue;
2718
2719 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2720 info->output_semantic_index[i]);
2721
2722 for (chan = 0; chan < 4; chan++) {
2723 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2724 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2725
2726 build_tbuffer_store(ctx,
2727 ctx->esgs_ring,
2728 out_val, 1,
2729 LLVMGetUndef(ctx->i32), soffset,
2730 (4 * param_index + chan) * 4,
2731 V_008F0C_BUF_DATA_FORMAT_32,
2732 V_008F0C_BUF_NUM_FORMAT_UINT,
2733 0, 0, 1, 1, 0);
2734 }
2735 }
2736 }
2737
2738 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2739 {
2740 struct si_shader_context *ctx = si_shader_context(bld_base);
2741 struct gallivm_state *gallivm = bld_base->base.gallivm;
2742 LLVMValueRef args[2];
2743
2744 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2745 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2746 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2747 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
2748 }
2749
2750 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2751 {
2752 struct si_shader_context *ctx = si_shader_context(bld_base);
2753 struct gallivm_state *gallivm = bld_base->base.gallivm;
2754 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2755 struct si_shader_output_values *outputs = NULL;
2756 int i,j;
2757
2758 assert(!ctx->is_gs_copy_shader);
2759
2760 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2761
2762 /* Vertex color clamping.
2763 *
2764 * This uses a state constant loaded in a user data SGPR and
2765 * an IF statement is added that clamps all colors if the constant
2766 * is true.
2767 */
2768 if (ctx->type == PIPE_SHADER_VERTEX) {
2769 struct lp_build_if_state if_ctx;
2770 LLVMValueRef cond = NULL;
2771 LLVMValueRef addr, val;
2772
2773 for (i = 0; i < info->num_outputs; i++) {
2774 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2775 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2776 continue;
2777
2778 /* We've found a color. */
2779 if (!cond) {
2780 /* The state is in the first bit of the user SGPR. */
2781 cond = LLVMGetParam(ctx->radeon_bld.main_fn,
2782 SI_PARAM_VS_STATE_BITS);
2783 cond = LLVMBuildTrunc(gallivm->builder, cond,
2784 ctx->i1, "");
2785 lp_build_if(&if_ctx, gallivm, cond);
2786 }
2787
2788 for (j = 0; j < 4; j++) {
2789 addr = ctx->radeon_bld.soa.outputs[i][j];
2790 val = LLVMBuildLoad(gallivm->builder, addr, "");
2791 val = radeon_llvm_saturate(bld_base, val);
2792 LLVMBuildStore(gallivm->builder, val, addr);
2793 }
2794 }
2795
2796 if (cond)
2797 lp_build_endif(&if_ctx);
2798 }
2799
2800 for (i = 0; i < info->num_outputs; i++) {
2801 outputs[i].name = info->output_semantic_name[i];
2802 outputs[i].sid = info->output_semantic_index[i];
2803
2804 for (j = 0; j < 4; j++)
2805 outputs[i].values[j] =
2806 LLVMBuildLoad(gallivm->builder,
2807 ctx->radeon_bld.soa.outputs[i][j],
2808 "");
2809 }
2810
2811 if (ctx->is_monolithic) {
2812 /* Export PrimitiveID when PS needs it. */
2813 if (si_vs_exports_prim_id(ctx->shader)) {
2814 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2815 outputs[i].sid = 0;
2816 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2817 get_primitive_id(bld_base, 0));
2818 outputs[i].values[1] = bld_base->base.undef;
2819 outputs[i].values[2] = bld_base->base.undef;
2820 outputs[i].values[3] = bld_base->base.undef;
2821 i++;
2822 }
2823 } else {
2824 /* Return the primitive ID from the LLVM function. */
2825 ctx->return_value =
2826 LLVMBuildInsertValue(gallivm->builder,
2827 ctx->return_value,
2828 bitcast(bld_base, TGSI_TYPE_FLOAT,
2829 get_primitive_id(bld_base, 0)),
2830 VS_EPILOG_PRIMID_LOC, "");
2831 }
2832
2833 si_llvm_export_vs(bld_base, outputs, i);
2834 FREE(outputs);
2835 }
2836
2837 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2838 LLVMValueRef depth, LLVMValueRef stencil,
2839 LLVMValueRef samplemask)
2840 {
2841 struct si_shader_context *ctx = si_shader_context(bld_base);
2842 struct lp_build_context *base = &bld_base->base;
2843 struct lp_build_context *uint = &bld_base->uint_bld;
2844 LLVMValueRef args[9];
2845 unsigned mask = 0;
2846
2847 assert(depth || stencil || samplemask);
2848
2849 args[1] = uint->one; /* whether the EXEC mask is valid */
2850 args[2] = uint->one; /* DONE bit */
2851
2852 /* Specify the target we are exporting */
2853 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2854
2855 args[4] = uint->zero; /* COMP flag */
2856 args[5] = base->undef; /* R, depth */
2857 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2858 args[7] = base->undef; /* B, sample mask */
2859 args[8] = base->undef; /* A, alpha to mask */
2860
2861 if (depth) {
2862 args[5] = depth;
2863 mask |= 0x1;
2864 }
2865
2866 if (stencil) {
2867 args[6] = stencil;
2868 mask |= 0x2;
2869 }
2870
2871 if (samplemask) {
2872 args[7] = samplemask;
2873 mask |= 0x4;
2874 }
2875
2876 /* SI (except OLAND) has a bug that it only looks
2877 * at the X writemask component. */
2878 if (ctx->screen->b.chip_class == SI &&
2879 ctx->screen->b.family != CHIP_OLAND)
2880 mask |= 0x1;
2881
2882 /* Specify which components to enable */
2883 args[0] = lp_build_const_int32(base->gallivm, mask);
2884
2885 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2886 ctx->voidt, args, 9, 0);
2887 }
2888
2889 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2890 LLVMValueRef *color, unsigned index,
2891 unsigned samplemask_param,
2892 bool is_last)
2893 {
2894 struct si_shader_context *ctx = si_shader_context(bld_base);
2895 struct lp_build_context *base = &bld_base->base;
2896 int i;
2897
2898 /* Clamp color */
2899 if (ctx->shader->key.ps.epilog.clamp_color)
2900 for (i = 0; i < 4; i++)
2901 color[i] = radeon_llvm_saturate(bld_base, color[i]);
2902
2903 /* Alpha to one */
2904 if (ctx->shader->key.ps.epilog.alpha_to_one)
2905 color[3] = base->one;
2906
2907 /* Alpha test */
2908 if (index == 0 &&
2909 ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
2910 si_alpha_test(bld_base, color[3]);
2911
2912 /* Line & polygon smoothing */
2913 if (ctx->shader->key.ps.epilog.poly_line_smoothing)
2914 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
2915 samplemask_param);
2916
2917 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2918 if (ctx->shader->key.ps.epilog.last_cbuf > 0) {
2919 LLVMValueRef args[8][9];
2920 int c, last = -1;
2921
2922 /* Get the export arguments, also find out what the last one is. */
2923 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
2924 si_llvm_init_export_args(bld_base, color,
2925 V_008DFC_SQ_EXP_MRT + c, args[c]);
2926 if (args[c][0] != bld_base->uint_bld.zero)
2927 last = c;
2928 }
2929
2930 /* Emit all exports. */
2931 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
2932 if (is_last && last == c) {
2933 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2934 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
2935 } else if (args[c][0] == bld_base->uint_bld.zero)
2936 continue; /* unnecessary NULL export */
2937
2938 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2939 ctx->voidt, args[c], 9, 0);
2940 }
2941 } else {
2942 LLVMValueRef args[9];
2943
2944 /* Export */
2945 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2946 args);
2947 if (is_last) {
2948 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2949 args[2] = bld_base->uint_bld.one; /* DONE bit */
2950 } else if (args[0] == bld_base->uint_bld.zero)
2951 return; /* unnecessary NULL export */
2952
2953 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2954 ctx->voidt, args, 9, 0);
2955 }
2956 }
2957
2958 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2959 {
2960 struct si_shader_context *ctx = si_shader_context(bld_base);
2961 struct lp_build_context *base = &bld_base->base;
2962 struct lp_build_context *uint = &bld_base->uint_bld;
2963 LLVMValueRef args[9];
2964
2965 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
2966 args[1] = uint->one; /* whether the EXEC mask is valid */
2967 args[2] = uint->one; /* DONE bit */
2968 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2969 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
2970 args[5] = uint->undef; /* R */
2971 args[6] = uint->undef; /* G */
2972 args[7] = uint->undef; /* B */
2973 args[8] = uint->undef; /* A */
2974
2975 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2976 ctx->voidt, args, 9, 0);
2977 }
2978
2979 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context *bld_base)
2980 {
2981 struct si_shader_context *ctx = si_shader_context(bld_base);
2982 struct si_shader *shader = ctx->shader;
2983 struct lp_build_context *base = &bld_base->base;
2984 struct tgsi_shader_info *info = &shader->selector->info;
2985 LLVMBuilderRef builder = base->gallivm->builder;
2986 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2987 int last_color_export = -1;
2988 int i;
2989
2990 /* Determine the last export. If MRTZ is present, it's always last.
2991 * Otherwise, find the last color export.
2992 */
2993 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask) {
2994 unsigned spi_format = shader->key.ps.epilog.spi_shader_col_format;
2995
2996 /* Don't export NULL and return if alpha-test is enabled. */
2997 if (shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS &&
2998 shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER &&
2999 (spi_format & 0xf) == 0)
3000 spi_format |= V_028714_SPI_SHADER_32_AR;
3001
3002 for (i = 0; i < info->num_outputs; i++) {
3003 unsigned index = info->output_semantic_index[i];
3004
3005 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR)
3006 continue;
3007
3008 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3009 if (shader->key.ps.epilog.last_cbuf > 0) {
3010 /* Just set this if any of the colorbuffers are enabled. */
3011 if (spi_format &
3012 ((1llu << (4 * (shader->key.ps.epilog.last_cbuf + 1))) - 1))
3013 last_color_export = i;
3014 continue;
3015 }
3016
3017 if ((spi_format >> (index * 4)) & 0xf)
3018 last_color_export = i;
3019 }
3020
3021 /* If there are no outputs, export NULL. */
3022 if (last_color_export == -1) {
3023 si_export_null(bld_base);
3024 return;
3025 }
3026 }
3027
3028 for (i = 0; i < info->num_outputs; i++) {
3029 unsigned semantic_name = info->output_semantic_name[i];
3030 unsigned semantic_index = info->output_semantic_index[i];
3031 unsigned j;
3032 LLVMValueRef color[4] = {};
3033
3034 /* Select the correct target */
3035 switch (semantic_name) {
3036 case TGSI_SEMANTIC_POSITION:
3037 depth = LLVMBuildLoad(builder,
3038 ctx->radeon_bld.soa.outputs[i][2], "");
3039 break;
3040 case TGSI_SEMANTIC_STENCIL:
3041 stencil = LLVMBuildLoad(builder,
3042 ctx->radeon_bld.soa.outputs[i][1], "");
3043 break;
3044 case TGSI_SEMANTIC_SAMPLEMASK:
3045 samplemask = LLVMBuildLoad(builder,
3046 ctx->radeon_bld.soa.outputs[i][0], "");
3047 break;
3048 case TGSI_SEMANTIC_COLOR:
3049 for (j = 0; j < 4; j++)
3050 color[j] = LLVMBuildLoad(builder,
3051 ctx->radeon_bld.soa.outputs[i][j], "");
3052
3053 si_export_mrt_color(bld_base, color, semantic_index,
3054 SI_PARAM_SAMPLE_COVERAGE,
3055 last_color_export == i);
3056 break;
3057 default:
3058 fprintf(stderr,
3059 "Warning: SI unhandled fs output type:%d\n",
3060 semantic_name);
3061 }
3062 }
3063
3064 if (depth || stencil || samplemask)
3065 si_export_mrt_z(bld_base, depth, stencil, samplemask);
3066 }
3067
3068 /**
3069 * Return PS outputs in this order:
3070 *
3071 * v[0:3] = color0.xyzw
3072 * v[4:7] = color1.xyzw
3073 * ...
3074 * vN+0 = Depth
3075 * vN+1 = Stencil
3076 * vN+2 = SampleMask
3077 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3078 *
3079 * The alpha-ref SGPR is returned via its original location.
3080 */
3081 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
3082 {
3083 struct si_shader_context *ctx = si_shader_context(bld_base);
3084 struct si_shader *shader = ctx->shader;
3085 struct lp_build_context *base = &bld_base->base;
3086 struct tgsi_shader_info *info = &shader->selector->info;
3087 LLVMBuilderRef builder = base->gallivm->builder;
3088 unsigned i, j, first_vgpr, vgpr;
3089
3090 LLVMValueRef color[8][4] = {};
3091 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3092 LLVMValueRef ret;
3093
3094 /* Read the output values. */
3095 for (i = 0; i < info->num_outputs; i++) {
3096 unsigned semantic_name = info->output_semantic_name[i];
3097 unsigned semantic_index = info->output_semantic_index[i];
3098
3099 switch (semantic_name) {
3100 case TGSI_SEMANTIC_COLOR:
3101 assert(semantic_index < 8);
3102 for (j = 0; j < 4; j++) {
3103 LLVMValueRef ptr = ctx->radeon_bld.soa.outputs[i][j];
3104 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3105 color[semantic_index][j] = result;
3106 }
3107 break;
3108 case TGSI_SEMANTIC_POSITION:
3109 depth = LLVMBuildLoad(builder,
3110 ctx->radeon_bld.soa.outputs[i][2], "");
3111 break;
3112 case TGSI_SEMANTIC_STENCIL:
3113 stencil = LLVMBuildLoad(builder,
3114 ctx->radeon_bld.soa.outputs[i][1], "");
3115 break;
3116 case TGSI_SEMANTIC_SAMPLEMASK:
3117 samplemask = LLVMBuildLoad(builder,
3118 ctx->radeon_bld.soa.outputs[i][0], "");
3119 break;
3120 default:
3121 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3122 semantic_name);
3123 }
3124 }
3125
3126 /* Fill the return structure. */
3127 ret = ctx->return_value;
3128
3129 /* Set SGPRs. */
3130 ret = LLVMBuildInsertValue(builder, ret,
3131 bitcast(bld_base, TGSI_TYPE_SIGNED,
3132 LLVMGetParam(ctx->radeon_bld.main_fn,
3133 SI_PARAM_ALPHA_REF)),
3134 SI_SGPR_ALPHA_REF, "");
3135
3136 /* Set VGPRs */
3137 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3138 for (i = 0; i < ARRAY_SIZE(color); i++) {
3139 if (!color[i][0])
3140 continue;
3141
3142 for (j = 0; j < 4; j++)
3143 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3144 }
3145 if (depth)
3146 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3147 if (stencil)
3148 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3149 if (samplemask)
3150 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3151
3152 /* Add the input sample mask for smoothing at the end. */
3153 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3154 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3155 ret = LLVMBuildInsertValue(builder, ret,
3156 LLVMGetParam(ctx->radeon_bld.main_fn,
3157 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3158
3159 ctx->return_value = ret;
3160 }
3161
3162 /**
3163 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3164 * buffer in number of elements and return it as an i32.
3165 */
3166 static LLVMValueRef get_buffer_size(
3167 struct lp_build_tgsi_context *bld_base,
3168 LLVMValueRef descriptor)
3169 {
3170 struct si_shader_context *ctx = si_shader_context(bld_base);
3171 struct gallivm_state *gallivm = bld_base->base.gallivm;
3172 LLVMBuilderRef builder = gallivm->builder;
3173 LLVMValueRef size =
3174 LLVMBuildExtractElement(builder, descriptor,
3175 lp_build_const_int32(gallivm, 6), "");
3176
3177 if (ctx->screen->b.chip_class >= VI) {
3178 /* On VI, the descriptor contains the size in bytes,
3179 * but TXQ must return the size in elements.
3180 * The stride is always non-zero for resources using TXQ.
3181 */
3182 LLVMValueRef stride =
3183 LLVMBuildExtractElement(builder, descriptor,
3184 lp_build_const_int32(gallivm, 5), "");
3185 stride = LLVMBuildLShr(builder, stride,
3186 lp_build_const_int32(gallivm, 16), "");
3187 stride = LLVMBuildAnd(builder, stride,
3188 lp_build_const_int32(gallivm, 0x3FFF), "");
3189
3190 size = LLVMBuildUDiv(builder, size, stride, "");
3191 }
3192
3193 return size;
3194 }
3195
3196 /**
3197 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
3198 * intrinsic names).
3199 */
3200 static void build_int_type_name(
3201 LLVMTypeRef type,
3202 char *buf, unsigned bufsize)
3203 {
3204 assert(bufsize >= 6);
3205
3206 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
3207 snprintf(buf, bufsize, "v%ui32",
3208 LLVMGetVectorSize(type));
3209 else
3210 strcpy(buf, "i32");
3211 }
3212
3213 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3214 struct lp_build_tgsi_context *bld_base,
3215 struct lp_build_emit_data *emit_data);
3216
3217 /* Prevent optimizations (at least of memory accesses) across the current
3218 * point in the program by emitting empty inline assembly that is marked as
3219 * having side effects.
3220 */
3221 static void emit_optimization_barrier(struct si_shader_context *ctx)
3222 {
3223 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
3224 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3225 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
3226 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3227 }
3228
3229 static void emit_waitcnt(struct si_shader_context *ctx)
3230 {
3231 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3232 LLVMBuilderRef builder = gallivm->builder;
3233 LLVMValueRef args[1] = {
3234 lp_build_const_int32(gallivm, 0xf70)
3235 };
3236 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3237 ctx->voidt, args, 1, LLVMNoUnwindAttribute);
3238 }
3239
3240 static void membar_emit(
3241 const struct lp_build_tgsi_action *action,
3242 struct lp_build_tgsi_context *bld_base,
3243 struct lp_build_emit_data *emit_data)
3244 {
3245 struct si_shader_context *ctx = si_shader_context(bld_base);
3246
3247 emit_waitcnt(ctx);
3248 }
3249
3250 static LLVMValueRef
3251 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3252 const struct tgsi_full_src_register *reg)
3253 {
3254 LLVMValueRef ind_index;
3255 LLVMValueRef rsrc_ptr;
3256
3257 if (!reg->Register.Indirect)
3258 return ctx->shader_buffers[reg->Register.Index];
3259
3260 ind_index = get_bounded_indirect_index(ctx, &reg->Indirect,
3261 reg->Register.Index,
3262 SI_NUM_SHADER_BUFFERS);
3263
3264 rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_SHADER_BUFFERS);
3265 return build_indexed_load_const(ctx, rsrc_ptr, ind_index);
3266 }
3267
3268 static bool tgsi_is_array_sampler(unsigned target)
3269 {
3270 return target == TGSI_TEXTURE_1D_ARRAY ||
3271 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3272 target == TGSI_TEXTURE_2D_ARRAY ||
3273 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3274 target == TGSI_TEXTURE_CUBE_ARRAY ||
3275 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3276 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3277 }
3278
3279 static bool tgsi_is_array_image(unsigned target)
3280 {
3281 return target == TGSI_TEXTURE_3D ||
3282 target == TGSI_TEXTURE_CUBE ||
3283 target == TGSI_TEXTURE_1D_ARRAY ||
3284 target == TGSI_TEXTURE_2D_ARRAY ||
3285 target == TGSI_TEXTURE_CUBE_ARRAY ||
3286 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3287 }
3288
3289 /**
3290 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3291 *
3292 * At least on Tonga, executing image stores on images with DCC enabled and
3293 * non-trivial can eventually lead to lockups. This can occur when an
3294 * application binds an image as read-only but then uses a shader that writes
3295 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3296 * program termination) in this case, but it doesn't cost much to be a bit
3297 * nicer: disabling DCC in the shader still leads to undefined results but
3298 * avoids the lockup.
3299 */
3300 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3301 LLVMValueRef rsrc)
3302 {
3303 if (ctx->screen->b.chip_class <= CIK) {
3304 return rsrc;
3305 } else {
3306 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
3307 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3308 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3309 LLVMValueRef tmp;
3310
3311 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3312 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3313 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3314 }
3315 }
3316
3317 /**
3318 * Load the resource descriptor for \p image.
3319 */
3320 static void
3321 image_fetch_rsrc(
3322 struct lp_build_tgsi_context *bld_base,
3323 const struct tgsi_full_src_register *image,
3324 bool dcc_off,
3325 LLVMValueRef *rsrc)
3326 {
3327 struct si_shader_context *ctx = si_shader_context(bld_base);
3328
3329 assert(image->Register.File == TGSI_FILE_IMAGE);
3330
3331 if (!image->Register.Indirect) {
3332 /* Fast path: use preloaded resources */
3333 *rsrc = ctx->images[image->Register.Index];
3334 } else {
3335 /* Indexing and manual load */
3336 LLVMValueRef ind_index;
3337 LLVMValueRef rsrc_ptr;
3338 LLVMValueRef tmp;
3339
3340 /* From the GL_ARB_shader_image_load_store extension spec:
3341 *
3342 * If a shader performs an image load, store, or atomic
3343 * operation using an image variable declared as an array,
3344 * and if the index used to select an individual element is
3345 * negative or greater than or equal to the size of the
3346 * array, the results of the operation are undefined but may
3347 * not lead to termination.
3348 */
3349 ind_index = get_bounded_indirect_index(ctx, &image->Indirect,
3350 image->Register.Index,
3351 SI_NUM_IMAGES);
3352
3353 rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_IMAGES);
3354 tmp = build_indexed_load_const(ctx, rsrc_ptr, ind_index);
3355 if (dcc_off)
3356 tmp = force_dcc_off(ctx, tmp);
3357 *rsrc = tmp;
3358 }
3359 }
3360
3361 static LLVMValueRef image_fetch_coords(
3362 struct lp_build_tgsi_context *bld_base,
3363 const struct tgsi_full_instruction *inst,
3364 unsigned src)
3365 {
3366 struct gallivm_state *gallivm = bld_base->base.gallivm;
3367 LLVMBuilderRef builder = gallivm->builder;
3368 unsigned target = inst->Memory.Texture;
3369 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3370 LLVMValueRef coords[4];
3371 LLVMValueRef tmp;
3372 int chan;
3373
3374 for (chan = 0; chan < num_coords; ++chan) {
3375 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3376 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3377 coords[chan] = tmp;
3378 }
3379
3380 if (num_coords == 1)
3381 return coords[0];
3382
3383 if (num_coords == 3) {
3384 /* LLVM has difficulties lowering 3-element vectors. */
3385 coords[3] = bld_base->uint_bld.undef;
3386 num_coords = 4;
3387 }
3388
3389 return lp_build_gather_values(gallivm, coords, num_coords);
3390 }
3391
3392 /**
3393 * Append the extra mode bits that are used by image load and store.
3394 */
3395 static void image_append_args(
3396 struct si_shader_context *ctx,
3397 struct lp_build_emit_data * emit_data,
3398 unsigned target,
3399 bool atomic)
3400 {
3401 const struct tgsi_full_instruction *inst = emit_data->inst;
3402 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3403 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3404
3405 emit_data->args[emit_data->arg_count++] = i1false; /* r128 */
3406 emit_data->args[emit_data->arg_count++] =
3407 tgsi_is_array_image(target) ? i1true : i1false; /* da */
3408 if (!atomic) {
3409 emit_data->args[emit_data->arg_count++] =
3410 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3411 i1true : i1false; /* glc */
3412 }
3413 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3414 }
3415
3416 /**
3417 * Given a 256 bit resource, extract the top half (which stores the buffer
3418 * resource in the case of textures and images).
3419 */
3420 static LLVMValueRef extract_rsrc_top_half(
3421 struct si_shader_context *ctx,
3422 LLVMValueRef rsrc)
3423 {
3424 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3425 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
3426 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
3427
3428 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, v2i128, "");
3429 rsrc = LLVMBuildExtractElement(gallivm->builder, rsrc, bld_base->uint_bld.one, "");
3430 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, "");
3431
3432 return rsrc;
3433 }
3434
3435 /**
3436 * Append the resource and indexing arguments for buffer intrinsics.
3437 *
3438 * \param rsrc the v4i32 buffer resource
3439 * \param index index into the buffer (stride-based)
3440 * \param offset byte offset into the buffer
3441 */
3442 static void buffer_append_args(
3443 struct si_shader_context *ctx,
3444 struct lp_build_emit_data *emit_data,
3445 LLVMValueRef rsrc,
3446 LLVMValueRef index,
3447 LLVMValueRef offset,
3448 bool atomic)
3449 {
3450 const struct tgsi_full_instruction *inst = emit_data->inst;
3451 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3452 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3453
3454 emit_data->args[emit_data->arg_count++] = rsrc;
3455 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3456 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3457 if (!atomic) {
3458 emit_data->args[emit_data->arg_count++] =
3459 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3460 i1true : i1false; /* glc */
3461 }
3462 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3463 }
3464
3465 static void load_fetch_args(
3466 struct lp_build_tgsi_context * bld_base,
3467 struct lp_build_emit_data * emit_data)
3468 {
3469 struct si_shader_context *ctx = si_shader_context(bld_base);
3470 struct gallivm_state *gallivm = bld_base->base.gallivm;
3471 const struct tgsi_full_instruction * inst = emit_data->inst;
3472 unsigned target = inst->Memory.Texture;
3473 LLVMValueRef rsrc;
3474
3475 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3476
3477 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3478 LLVMBuilderRef builder = gallivm->builder;
3479 LLVMValueRef offset;
3480 LLVMValueRef tmp;
3481
3482 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3483
3484 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3485 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3486
3487 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3488 offset, false);
3489 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3490 LLVMValueRef coords;
3491
3492 image_fetch_rsrc(bld_base, &inst->Src[0], false, &rsrc);
3493 coords = image_fetch_coords(bld_base, inst, 1);
3494
3495 if (target == TGSI_TEXTURE_BUFFER) {
3496 rsrc = extract_rsrc_top_half(ctx, rsrc);
3497 buffer_append_args(ctx, emit_data, rsrc, coords,
3498 bld_base->uint_bld.zero, false);
3499 } else {
3500 emit_data->args[0] = coords;
3501 emit_data->args[1] = rsrc;
3502 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3503 emit_data->arg_count = 3;
3504
3505 image_append_args(ctx, emit_data, target, false);
3506 }
3507 }
3508 }
3509
3510 static void load_emit_buffer(struct si_shader_context *ctx,
3511 struct lp_build_emit_data *emit_data)
3512 {
3513 const struct tgsi_full_instruction *inst = emit_data->inst;
3514 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3515 LLVMBuilderRef builder = gallivm->builder;
3516 uint writemask = inst->Dst[0].Register.WriteMask;
3517 uint count = util_last_bit(writemask);
3518 const char *intrinsic_name;
3519 LLVMTypeRef dst_type;
3520
3521 switch (count) {
3522 case 1:
3523 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3524 dst_type = ctx->f32;
3525 break;
3526 case 2:
3527 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3528 dst_type = LLVMVectorType(ctx->f32, 2);
3529 break;
3530 default: // 3 & 4
3531 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3532 dst_type = ctx->v4f32;
3533 count = 4;
3534 }
3535
3536 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3537 builder, intrinsic_name, dst_type,
3538 emit_data->args, emit_data->arg_count,
3539 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
3540 }
3541
3542 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3543 const struct tgsi_full_instruction *inst,
3544 LLVMTypeRef type, int arg)
3545 {
3546 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3547 LLVMBuilderRef builder = gallivm->builder;
3548 LLVMValueRef offset, ptr;
3549 int addr_space;
3550
3551 offset = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, arg, 0);
3552 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3553
3554 ptr = ctx->shared_memory;
3555 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3556 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3557 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3558
3559 return ptr;
3560 }
3561
3562 static void load_emit_memory(
3563 struct si_shader_context *ctx,
3564 struct lp_build_emit_data *emit_data)
3565 {
3566 const struct tgsi_full_instruction *inst = emit_data->inst;
3567 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
3568 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3569 LLVMBuilderRef builder = gallivm->builder;
3570 unsigned writemask = inst->Dst[0].Register.WriteMask;
3571 LLVMValueRef channels[4], ptr, derived_ptr, index;
3572 int chan;
3573
3574 ptr = get_memory_ptr(ctx, inst, base->elem_type, 1);
3575
3576 for (chan = 0; chan < 4; ++chan) {
3577 if (!(writemask & (1 << chan))) {
3578 channels[chan] = LLVMGetUndef(base->elem_type);
3579 continue;
3580 }
3581
3582 index = lp_build_const_int32(gallivm, chan);
3583 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3584 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3585 }
3586 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3587 }
3588
3589 static void load_emit(
3590 const struct lp_build_tgsi_action *action,
3591 struct lp_build_tgsi_context *bld_base,
3592 struct lp_build_emit_data *emit_data)
3593 {
3594 struct si_shader_context *ctx = si_shader_context(bld_base);
3595 struct gallivm_state *gallivm = bld_base->base.gallivm;
3596 LLVMBuilderRef builder = gallivm->builder;
3597 const struct tgsi_full_instruction * inst = emit_data->inst;
3598 char intrinsic_name[32];
3599 char coords_type[8];
3600
3601 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3602 load_emit_memory(ctx, emit_data);
3603 return;
3604 }
3605
3606 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3607 emit_waitcnt(ctx);
3608
3609 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3610 load_emit_buffer(ctx, emit_data);
3611 return;
3612 }
3613
3614 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3615 emit_data->output[emit_data->chan] =
3616 lp_build_intrinsic(
3617 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3618 emit_data->args, emit_data->arg_count,
3619 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
3620 } else {
3621 build_int_type_name(LLVMTypeOf(emit_data->args[0]),
3622 coords_type, sizeof(coords_type));
3623
3624 snprintf(intrinsic_name, sizeof(intrinsic_name),
3625 "llvm.amdgcn.image.load.%s", coords_type);
3626
3627 emit_data->output[emit_data->chan] =
3628 lp_build_intrinsic(
3629 builder, intrinsic_name, emit_data->dst_type,
3630 emit_data->args, emit_data->arg_count,
3631 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
3632 }
3633 }
3634
3635 static void store_fetch_args(
3636 struct lp_build_tgsi_context * bld_base,
3637 struct lp_build_emit_data * emit_data)
3638 {
3639 struct si_shader_context *ctx = si_shader_context(bld_base);
3640 struct gallivm_state *gallivm = bld_base->base.gallivm;
3641 LLVMBuilderRef builder = gallivm->builder;
3642 const struct tgsi_full_instruction * inst = emit_data->inst;
3643 struct tgsi_full_src_register memory;
3644 LLVMValueRef chans[4];
3645 LLVMValueRef data;
3646 LLVMValueRef rsrc;
3647 unsigned chan;
3648
3649 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3650
3651 for (chan = 0; chan < 4; ++chan) {
3652 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3653 }
3654 data = lp_build_gather_values(gallivm, chans, 4);
3655
3656 emit_data->args[emit_data->arg_count++] = data;
3657
3658 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3659
3660 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3661 LLVMValueRef offset;
3662 LLVMValueRef tmp;
3663
3664 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3665
3666 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3667 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3668
3669 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3670 offset, false);
3671 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3672 unsigned target = inst->Memory.Texture;
3673 LLVMValueRef coords;
3674
3675 coords = image_fetch_coords(bld_base, inst, 0);
3676
3677 if (target == TGSI_TEXTURE_BUFFER) {
3678 image_fetch_rsrc(bld_base, &memory, false, &rsrc);
3679
3680 rsrc = extract_rsrc_top_half(ctx, rsrc);
3681 buffer_append_args(ctx, emit_data, rsrc, coords,
3682 bld_base->uint_bld.zero, false);
3683 } else {
3684 emit_data->args[1] = coords;
3685 image_fetch_rsrc(bld_base, &memory, true, &emit_data->args[2]);
3686 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3687 emit_data->arg_count = 4;
3688
3689 image_append_args(ctx, emit_data, target, false);
3690 }
3691 }
3692 }
3693
3694 static void store_emit_buffer(
3695 struct si_shader_context *ctx,
3696 struct lp_build_emit_data *emit_data)
3697 {
3698 const struct tgsi_full_instruction *inst = emit_data->inst;
3699 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3700 LLVMBuilderRef builder = gallivm->builder;
3701 struct lp_build_context *uint_bld = &ctx->radeon_bld.soa.bld_base.uint_bld;
3702 LLVMValueRef base_data = emit_data->args[0];
3703 LLVMValueRef base_offset = emit_data->args[3];
3704 unsigned writemask = inst->Dst[0].Register.WriteMask;
3705
3706 while (writemask) {
3707 int start, count;
3708 const char *intrinsic_name;
3709 LLVMValueRef data;
3710 LLVMValueRef offset;
3711 LLVMValueRef tmp;
3712
3713 u_bit_scan_consecutive_range(&writemask, &start, &count);
3714
3715 /* Due to an LLVM limitation, split 3-element writes
3716 * into a 2-element and a 1-element write. */
3717 if (count == 3) {
3718 writemask |= 1 << (start + 2);
3719 count = 2;
3720 }
3721
3722 if (count == 4) {
3723 data = base_data;
3724 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3725 } else if (count == 2) {
3726 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3727
3728 tmp = LLVMBuildExtractElement(
3729 builder, base_data,
3730 lp_build_const_int32(gallivm, start), "");
3731 data = LLVMBuildInsertElement(
3732 builder, LLVMGetUndef(v2f32), tmp,
3733 uint_bld->zero, "");
3734
3735 tmp = LLVMBuildExtractElement(
3736 builder, base_data,
3737 lp_build_const_int32(gallivm, start + 1), "");
3738 data = LLVMBuildInsertElement(
3739 builder, data, tmp, uint_bld->one, "");
3740
3741 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3742 } else {
3743 assert(count == 1);
3744 data = LLVMBuildExtractElement(
3745 builder, base_data,
3746 lp_build_const_int32(gallivm, start), "");
3747 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3748 }
3749
3750 offset = base_offset;
3751 if (start != 0) {
3752 offset = LLVMBuildAdd(
3753 builder, offset,
3754 lp_build_const_int32(gallivm, start * 4), "");
3755 }
3756
3757 emit_data->args[0] = data;
3758 emit_data->args[3] = offset;
3759
3760 lp_build_intrinsic(
3761 builder, intrinsic_name, emit_data->dst_type,
3762 emit_data->args, emit_data->arg_count,
3763 LLVMNoUnwindAttribute);
3764 }
3765 }
3766
3767 static void store_emit_memory(
3768 struct si_shader_context *ctx,
3769 struct lp_build_emit_data *emit_data)
3770 {
3771 const struct tgsi_full_instruction *inst = emit_data->inst;
3772 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3773 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
3774 LLVMBuilderRef builder = gallivm->builder;
3775 unsigned writemask = inst->Dst[0].Register.WriteMask;
3776 LLVMValueRef ptr, derived_ptr, data, index;
3777 int chan;
3778
3779 ptr = get_memory_ptr(ctx, inst, base->elem_type, 0);
3780
3781 for (chan = 0; chan < 4; ++chan) {
3782 if (!(writemask & (1 << chan))) {
3783 continue;
3784 }
3785 data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 1, chan);
3786 index = lp_build_const_int32(gallivm, chan);
3787 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3788 LLVMBuildStore(builder, data, derived_ptr);
3789 }
3790 }
3791
3792 static void store_emit(
3793 const struct lp_build_tgsi_action *action,
3794 struct lp_build_tgsi_context *bld_base,
3795 struct lp_build_emit_data *emit_data)
3796 {
3797 struct si_shader_context *ctx = si_shader_context(bld_base);
3798 struct gallivm_state *gallivm = bld_base->base.gallivm;
3799 LLVMBuilderRef builder = gallivm->builder;
3800 const struct tgsi_full_instruction * inst = emit_data->inst;
3801 unsigned target = inst->Memory.Texture;
3802 char intrinsic_name[32];
3803 char coords_type[8];
3804
3805 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3806 store_emit_memory(ctx, emit_data);
3807 return;
3808 }
3809
3810 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3811 emit_waitcnt(ctx);
3812
3813 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3814 store_emit_buffer(ctx, emit_data);
3815 return;
3816 }
3817
3818 if (target == TGSI_TEXTURE_BUFFER) {
3819 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3820 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3821 emit_data->dst_type, emit_data->args, emit_data->arg_count,
3822 LLVMNoUnwindAttribute);
3823 } else {
3824 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
3825 coords_type, sizeof(coords_type));
3826 snprintf(intrinsic_name, sizeof(intrinsic_name),
3827 "llvm.amdgcn.image.store.%s", coords_type);
3828
3829 emit_data->output[emit_data->chan] =
3830 lp_build_intrinsic(
3831 builder, intrinsic_name, emit_data->dst_type,
3832 emit_data->args, emit_data->arg_count,
3833 LLVMNoUnwindAttribute);
3834 }
3835 }
3836
3837 static void atomic_fetch_args(
3838 struct lp_build_tgsi_context * bld_base,
3839 struct lp_build_emit_data * emit_data)
3840 {
3841 struct si_shader_context *ctx = si_shader_context(bld_base);
3842 struct gallivm_state *gallivm = bld_base->base.gallivm;
3843 LLVMBuilderRef builder = gallivm->builder;
3844 const struct tgsi_full_instruction * inst = emit_data->inst;
3845 LLVMValueRef data1, data2;
3846 LLVMValueRef rsrc;
3847 LLVMValueRef tmp;
3848
3849 emit_data->dst_type = bld_base->base.elem_type;
3850
3851 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
3852 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3853
3854 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3855 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
3856 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3857 }
3858
3859 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3860 * of arguments, which is reversed relative to TGSI (and GLSL)
3861 */
3862 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3863 emit_data->args[emit_data->arg_count++] = data2;
3864 emit_data->args[emit_data->arg_count++] = data1;
3865
3866 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3867 LLVMValueRef offset;
3868
3869 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3870
3871 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3872 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3873
3874 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3875 offset, true);
3876 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3877 unsigned target = inst->Memory.Texture;
3878 LLVMValueRef coords;
3879
3880 image_fetch_rsrc(bld_base, &inst->Src[0],
3881 target != TGSI_TEXTURE_BUFFER, &rsrc);
3882 coords = image_fetch_coords(bld_base, inst, 1);
3883
3884 if (target == TGSI_TEXTURE_BUFFER) {
3885 rsrc = extract_rsrc_top_half(ctx, rsrc);
3886 buffer_append_args(ctx, emit_data, rsrc, coords,
3887 bld_base->uint_bld.zero, true);
3888 } else {
3889 emit_data->args[emit_data->arg_count++] = coords;
3890 emit_data->args[emit_data->arg_count++] = rsrc;
3891
3892 image_append_args(ctx, emit_data, target, true);
3893 }
3894 }
3895 }
3896
3897 static void atomic_emit_memory(struct si_shader_context *ctx,
3898 struct lp_build_emit_data *emit_data) {
3899 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3900 LLVMBuilderRef builder = gallivm->builder;
3901 const struct tgsi_full_instruction * inst = emit_data->inst;
3902 LLVMValueRef ptr, result, arg;
3903
3904 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
3905
3906 arg = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 2, 0);
3907 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
3908
3909 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3910 LLVMValueRef new_data;
3911 new_data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base,
3912 inst, 3, 0);
3913
3914 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
3915
3916 #if HAVE_LLVM >= 0x309
3917 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
3918 LLVMAtomicOrderingSequentiallyConsistent,
3919 LLVMAtomicOrderingSequentiallyConsistent,
3920 false);
3921 #endif
3922
3923 result = LLVMBuildExtractValue(builder, result, 0, "");
3924 } else {
3925 LLVMAtomicRMWBinOp op;
3926
3927 switch(inst->Instruction.Opcode) {
3928 case TGSI_OPCODE_ATOMUADD:
3929 op = LLVMAtomicRMWBinOpAdd;
3930 break;
3931 case TGSI_OPCODE_ATOMXCHG:
3932 op = LLVMAtomicRMWBinOpXchg;
3933 break;
3934 case TGSI_OPCODE_ATOMAND:
3935 op = LLVMAtomicRMWBinOpAnd;
3936 break;
3937 case TGSI_OPCODE_ATOMOR:
3938 op = LLVMAtomicRMWBinOpOr;
3939 break;
3940 case TGSI_OPCODE_ATOMXOR:
3941 op = LLVMAtomicRMWBinOpXor;
3942 break;
3943 case TGSI_OPCODE_ATOMUMIN:
3944 op = LLVMAtomicRMWBinOpUMin;
3945 break;
3946 case TGSI_OPCODE_ATOMUMAX:
3947 op = LLVMAtomicRMWBinOpUMax;
3948 break;
3949 case TGSI_OPCODE_ATOMIMIN:
3950 op = LLVMAtomicRMWBinOpMin;
3951 break;
3952 case TGSI_OPCODE_ATOMIMAX:
3953 op = LLVMAtomicRMWBinOpMax;
3954 break;
3955 default:
3956 unreachable("unknown atomic opcode");
3957 }
3958
3959 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
3960 LLVMAtomicOrderingSequentiallyConsistent,
3961 false);
3962 }
3963 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
3964 }
3965
3966 static void atomic_emit(
3967 const struct lp_build_tgsi_action *action,
3968 struct lp_build_tgsi_context *bld_base,
3969 struct lp_build_emit_data *emit_data)
3970 {
3971 struct si_shader_context *ctx = si_shader_context(bld_base);
3972 struct gallivm_state *gallivm = bld_base->base.gallivm;
3973 LLVMBuilderRef builder = gallivm->builder;
3974 const struct tgsi_full_instruction * inst = emit_data->inst;
3975 char intrinsic_name[40];
3976 LLVMValueRef tmp;
3977
3978 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3979 atomic_emit_memory(ctx, emit_data);
3980 return;
3981 }
3982
3983 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
3984 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3985 snprintf(intrinsic_name, sizeof(intrinsic_name),
3986 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
3987 } else {
3988 char coords_type[8];
3989
3990 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
3991 coords_type, sizeof(coords_type));
3992 snprintf(intrinsic_name, sizeof(intrinsic_name),
3993 "llvm.amdgcn.image.atomic.%s.%s",
3994 action->intr_name, coords_type);
3995 }
3996
3997 tmp = lp_build_intrinsic(
3998 builder, intrinsic_name, bld_base->uint_bld.elem_type,
3999 emit_data->args, emit_data->arg_count,
4000 LLVMNoUnwindAttribute);
4001 emit_data->output[emit_data->chan] =
4002 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
4003 }
4004
4005 static void resq_fetch_args(
4006 struct lp_build_tgsi_context * bld_base,
4007 struct lp_build_emit_data * emit_data)
4008 {
4009 struct si_shader_context *ctx = si_shader_context(bld_base);
4010 struct gallivm_state *gallivm = bld_base->base.gallivm;
4011 const struct tgsi_full_instruction *inst = emit_data->inst;
4012 const struct tgsi_full_src_register *reg = &inst->Src[0];
4013
4014 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
4015
4016 if (reg->Register.File == TGSI_FILE_BUFFER) {
4017 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
4018 emit_data->arg_count = 1;
4019 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4020 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[0]);
4021 emit_data->arg_count = 1;
4022 } else {
4023 emit_data->args[0] = bld_base->uint_bld.zero; /* mip level */
4024 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[1]);
4025 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
4026 emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
4027 emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
4028 emit_data->args[5] = tgsi_is_array_image(inst->Memory.Texture) ?
4029 bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da */
4030 emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
4031 emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
4032 emit_data->args[8] = bld_base->uint_bld.zero; /* tfe */
4033 emit_data->args[9] = bld_base->uint_bld.zero; /* lwe */
4034 emit_data->arg_count = 10;
4035 }
4036 }
4037
4038 static void resq_emit(
4039 const struct lp_build_tgsi_action *action,
4040 struct lp_build_tgsi_context *bld_base,
4041 struct lp_build_emit_data *emit_data)
4042 {
4043 struct gallivm_state *gallivm = bld_base->base.gallivm;
4044 LLVMBuilderRef builder = gallivm->builder;
4045 const struct tgsi_full_instruction *inst = emit_data->inst;
4046 LLVMValueRef out;
4047
4048 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4049 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4050 lp_build_const_int32(gallivm, 2), "");
4051 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4052 out = get_buffer_size(bld_base, emit_data->args[0]);
4053 } else {
4054 out = lp_build_intrinsic(
4055 builder, "llvm.SI.getresinfo.i32", emit_data->dst_type,
4056 emit_data->args, emit_data->arg_count,
4057 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
4058
4059 /* Divide the number of layers by 6 to get the number of cubes. */
4060 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
4061 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
4062 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
4063
4064 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4065 z = LLVMBuildBitCast(builder, z, bld_base->uint_bld.elem_type, "");
4066 z = LLVMBuildSDiv(builder, z, imm6, "");
4067 z = LLVMBuildBitCast(builder, z, bld_base->base.elem_type, "");
4068 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4069 }
4070 }
4071
4072 emit_data->output[emit_data->chan] = out;
4073 }
4074
4075 static void set_tex_fetch_args(struct si_shader_context *ctx,
4076 struct lp_build_emit_data *emit_data,
4077 unsigned opcode, unsigned target,
4078 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4079 LLVMValueRef *param, unsigned count,
4080 unsigned dmask)
4081 {
4082 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4083 unsigned num_args;
4084 unsigned is_rect = target == TGSI_TEXTURE_RECT;
4085
4086 /* Pad to power of two vector */
4087 while (count < util_next_power_of_two(count))
4088 param[count++] = LLVMGetUndef(ctx->i32);
4089
4090 /* Texture coordinates. */
4091 if (count > 1)
4092 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
4093 else
4094 emit_data->args[0] = param[0];
4095
4096 /* Resource. */
4097 emit_data->args[1] = res_ptr;
4098 num_args = 2;
4099
4100 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
4101 emit_data->dst_type = ctx->v4i32;
4102 else {
4103 emit_data->dst_type = ctx->v4f32;
4104
4105 emit_data->args[num_args++] = samp_ptr;
4106 }
4107
4108 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
4109 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
4110 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
4111 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
4112 tgsi_is_array_sampler(target)); /* da */
4113 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
4114 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
4115 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
4116 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
4117
4118 emit_data->arg_count = num_args;
4119 }
4120
4121 static const struct lp_build_tgsi_action tex_action;
4122
4123 enum desc_type {
4124 DESC_IMAGE,
4125 DESC_FMASK,
4126 DESC_SAMPLER
4127 };
4128
4129 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
4130 {
4131 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
4132 CONST_ADDR_SPACE);
4133 }
4134
4135 /**
4136 * Load an image view, fmask view. or sampler state descriptor.
4137 */
4138 static LLVMValueRef get_sampler_desc_custom(struct si_shader_context *ctx,
4139 LLVMValueRef list, LLVMValueRef index,
4140 enum desc_type type)
4141 {
4142 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4143 LLVMBuilderRef builder = gallivm->builder;
4144
4145 switch (type) {
4146 case DESC_IMAGE:
4147 /* The image is at [0:7]. */
4148 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4149 break;
4150 case DESC_FMASK:
4151 /* The FMASK is at [8:15]. */
4152 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4153 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4154 break;
4155 case DESC_SAMPLER:
4156 /* The sampler state is at [12:15]. */
4157 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4158 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4159 list = LLVMBuildPointerCast(builder, list,
4160 const_array(ctx->v4i32, 0), "");
4161 break;
4162 }
4163
4164 return build_indexed_load_const(ctx, list, index);
4165 }
4166
4167 static LLVMValueRef get_sampler_desc(struct si_shader_context *ctx,
4168 LLVMValueRef index, enum desc_type type)
4169 {
4170 LLVMValueRef list = LLVMGetParam(ctx->radeon_bld.main_fn,
4171 SI_PARAM_SAMPLERS);
4172
4173 return get_sampler_desc_custom(ctx, list, index, type);
4174 }
4175
4176 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4177 *
4178 * SI-CI:
4179 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4180 * filtering manually. The driver sets img7 to a mask clearing
4181 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4182 * s_and_b32 samp0, samp0, img7
4183 *
4184 * VI:
4185 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4186 */
4187 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4188 LLVMValueRef res, LLVMValueRef samp)
4189 {
4190 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
4191 LLVMValueRef img7, samp0;
4192
4193 if (ctx->screen->b.chip_class >= VI)
4194 return samp;
4195
4196 img7 = LLVMBuildExtractElement(builder, res,
4197 LLVMConstInt(ctx->i32, 7, 0), "");
4198 samp0 = LLVMBuildExtractElement(builder, samp,
4199 LLVMConstInt(ctx->i32, 0, 0), "");
4200 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4201 return LLVMBuildInsertElement(builder, samp, samp0,
4202 LLVMConstInt(ctx->i32, 0, 0), "");
4203 }
4204
4205 static void tex_fetch_ptrs(
4206 struct lp_build_tgsi_context *bld_base,
4207 struct lp_build_emit_data *emit_data,
4208 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4209 {
4210 struct si_shader_context *ctx = si_shader_context(bld_base);
4211 const struct tgsi_full_instruction *inst = emit_data->inst;
4212 unsigned target = inst->Texture.Texture;
4213 unsigned sampler_src;
4214 unsigned sampler_index;
4215
4216 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4217 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
4218
4219 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
4220 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
4221 LLVMValueRef ind_index;
4222
4223 ind_index = get_bounded_indirect_index(ctx,
4224 &reg->Indirect,
4225 reg->Register.Index,
4226 SI_NUM_SAMPLERS);
4227
4228 *res_ptr = get_sampler_desc(ctx, ind_index, DESC_IMAGE);
4229
4230 if (target == TGSI_TEXTURE_2D_MSAA ||
4231 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4232 if (samp_ptr)
4233 *samp_ptr = NULL;
4234 if (fmask_ptr)
4235 *fmask_ptr = get_sampler_desc(ctx, ind_index, DESC_FMASK);
4236 } else {
4237 if (samp_ptr) {
4238 *samp_ptr = get_sampler_desc(ctx, ind_index, DESC_SAMPLER);
4239 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4240 }
4241 if (fmask_ptr)
4242 *fmask_ptr = NULL;
4243 }
4244 } else {
4245 *res_ptr = ctx->sampler_views[sampler_index];
4246 if (samp_ptr)
4247 *samp_ptr = ctx->sampler_states[sampler_index];
4248 if (fmask_ptr)
4249 *fmask_ptr = ctx->fmasks[sampler_index];
4250 }
4251 }
4252
4253 static void txq_fetch_args(
4254 struct lp_build_tgsi_context *bld_base,
4255 struct lp_build_emit_data *emit_data)
4256 {
4257 struct si_shader_context *ctx = si_shader_context(bld_base);
4258 struct gallivm_state *gallivm = bld_base->base.gallivm;
4259 LLVMBuilderRef builder = gallivm->builder;
4260 const struct tgsi_full_instruction *inst = emit_data->inst;
4261 unsigned target = inst->Texture.Texture;
4262 LLVMValueRef res_ptr;
4263 LLVMValueRef address;
4264
4265 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4266
4267 if (target == TGSI_TEXTURE_BUFFER) {
4268 /* Read the size from the buffer descriptor directly. */
4269 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4270 emit_data->args[0] = get_buffer_size(bld_base, res);
4271 return;
4272 }
4273
4274 /* Textures - set the mip level. */
4275 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4276
4277 set_tex_fetch_args(ctx, emit_data, TGSI_OPCODE_TXQ, target, res_ptr,
4278 NULL, &address, 1, 0xf);
4279 }
4280
4281 static void txq_emit(const struct lp_build_tgsi_action *action,
4282 struct lp_build_tgsi_context *bld_base,
4283 struct lp_build_emit_data *emit_data)
4284 {
4285 struct lp_build_context *base = &bld_base->base;
4286 unsigned target = emit_data->inst->Texture.Texture;
4287
4288 if (target == TGSI_TEXTURE_BUFFER) {
4289 /* Just return the buffer size. */
4290 emit_data->output[emit_data->chan] = emit_data->args[0];
4291 return;
4292 }
4293
4294 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4295 base->gallivm->builder, "llvm.SI.getresinfo.i32",
4296 emit_data->dst_type, emit_data->args, emit_data->arg_count,
4297 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
4298
4299 /* Divide the number of layers by 6 to get the number of cubes. */
4300 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4301 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4302 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
4303 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
4304 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
4305
4306 LLVMValueRef v4 = emit_data->output[emit_data->chan];
4307 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
4308 z = LLVMBuildSDiv(builder, z, six, "");
4309
4310 emit_data->output[emit_data->chan] =
4311 LLVMBuildInsertElement(builder, v4, z, two, "");
4312 }
4313 }
4314
4315 static void tex_fetch_args(
4316 struct lp_build_tgsi_context *bld_base,
4317 struct lp_build_emit_data *emit_data)
4318 {
4319 struct si_shader_context *ctx = si_shader_context(bld_base);
4320 struct gallivm_state *gallivm = bld_base->base.gallivm;
4321 const struct tgsi_full_instruction *inst = emit_data->inst;
4322 unsigned opcode = inst->Instruction.Opcode;
4323 unsigned target = inst->Texture.Texture;
4324 LLVMValueRef coords[5], derivs[6];
4325 LLVMValueRef address[16];
4326 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4327 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4328 unsigned count = 0;
4329 unsigned chan;
4330 unsigned num_deriv_channels = 0;
4331 bool has_offset = inst->Texture.NumOffsets > 0;
4332 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4333 unsigned dmask = 0xf;
4334
4335 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4336
4337 if (target == TGSI_TEXTURE_BUFFER) {
4338 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
4339
4340 /* Bitcast and truncate v8i32 to v16i8. */
4341 LLVMValueRef res = res_ptr;
4342 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
4343 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
4344 res = LLVMBuildBitCast(gallivm->builder, res, ctx->v16i8, "");
4345
4346 emit_data->dst_type = ctx->v4f32;
4347 emit_data->args[0] = res;
4348 emit_data->args[1] = bld_base->uint_bld.zero;
4349 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4350 emit_data->arg_count = 3;
4351 return;
4352 }
4353
4354 /* Fetch and project texture coordinates */
4355 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4356 for (chan = 0; chan < 3; chan++ ) {
4357 coords[chan] = lp_build_emit_fetch(bld_base,
4358 emit_data->inst, 0,
4359 chan);
4360 if (opcode == TGSI_OPCODE_TXP)
4361 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4362 TGSI_OPCODE_DIV,
4363 coords[chan],
4364 coords[3]);
4365 }
4366
4367 if (opcode == TGSI_OPCODE_TXP)
4368 coords[3] = bld_base->base.one;
4369
4370 /* Pack offsets. */
4371 if (has_offset && opcode != TGSI_OPCODE_TXF) {
4372 /* The offsets are six-bit signed integers packed like this:
4373 * X=[5:0], Y=[13:8], and Z=[21:16].
4374 */
4375 LLVMValueRef offset[3], pack;
4376
4377 assert(inst->Texture.NumOffsets == 1);
4378
4379 for (chan = 0; chan < 3; chan++) {
4380 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4381 emit_data->inst, 0, chan);
4382 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4383 lp_build_const_int32(gallivm, 0x3f), "");
4384 if (chan)
4385 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4386 lp_build_const_int32(gallivm, chan*8), "");
4387 }
4388
4389 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4390 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4391 address[count++] = pack;
4392 }
4393
4394 /* Pack LOD bias value */
4395 if (opcode == TGSI_OPCODE_TXB)
4396 address[count++] = coords[3];
4397 if (opcode == TGSI_OPCODE_TXB2)
4398 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4399
4400 /* Pack depth comparison value */
4401 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4402 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4403 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4404 } else {
4405 assert(ref_pos >= 0);
4406 address[count++] = coords[ref_pos];
4407 }
4408 }
4409
4410 /* Pack user derivatives */
4411 if (opcode == TGSI_OPCODE_TXD) {
4412 int param, num_src_deriv_channels;
4413
4414 switch (target) {
4415 case TGSI_TEXTURE_3D:
4416 num_src_deriv_channels = 3;
4417 num_deriv_channels = 3;
4418 break;
4419 case TGSI_TEXTURE_2D:
4420 case TGSI_TEXTURE_SHADOW2D:
4421 case TGSI_TEXTURE_RECT:
4422 case TGSI_TEXTURE_SHADOWRECT:
4423 case TGSI_TEXTURE_2D_ARRAY:
4424 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4425 num_src_deriv_channels = 2;
4426 num_deriv_channels = 2;
4427 break;
4428 case TGSI_TEXTURE_CUBE:
4429 case TGSI_TEXTURE_SHADOWCUBE:
4430 case TGSI_TEXTURE_CUBE_ARRAY:
4431 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4432 /* Cube derivatives will be converted to 2D. */
4433 num_src_deriv_channels = 3;
4434 num_deriv_channels = 2;
4435 break;
4436 case TGSI_TEXTURE_1D:
4437 case TGSI_TEXTURE_SHADOW1D:
4438 case TGSI_TEXTURE_1D_ARRAY:
4439 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4440 num_src_deriv_channels = 1;
4441 num_deriv_channels = 1;
4442 break;
4443 default:
4444 unreachable("invalid target");
4445 }
4446
4447 for (param = 0; param < 2; param++)
4448 for (chan = 0; chan < num_src_deriv_channels; chan++)
4449 derivs[param * num_src_deriv_channels + chan] =
4450 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4451 }
4452
4453 if (target == TGSI_TEXTURE_CUBE ||
4454 target == TGSI_TEXTURE_CUBE_ARRAY ||
4455 target == TGSI_TEXTURE_SHADOWCUBE ||
4456 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4457 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
4458
4459 if (opcode == TGSI_OPCODE_TXD)
4460 for (int i = 0; i < num_deriv_channels * 2; i++)
4461 address[count++] = derivs[i];
4462
4463 /* Pack texture coordinates */
4464 address[count++] = coords[0];
4465 if (num_coords > 1)
4466 address[count++] = coords[1];
4467 if (num_coords > 2)
4468 address[count++] = coords[2];
4469
4470 /* Pack LOD or sample index */
4471 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4472 address[count++] = coords[3];
4473 else if (opcode == TGSI_OPCODE_TXL2)
4474 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4475
4476 if (count > 16) {
4477 assert(!"Cannot handle more than 16 texture address parameters");
4478 count = 16;
4479 }
4480
4481 for (chan = 0; chan < count; chan++ ) {
4482 address[chan] = LLVMBuildBitCast(gallivm->builder,
4483 address[chan], ctx->i32, "");
4484 }
4485
4486 /* Adjust the sample index according to FMASK.
4487 *
4488 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4489 * which is the identity mapping. Each nibble says which physical sample
4490 * should be fetched to get that sample.
4491 *
4492 * For example, 0x11111100 means there are only 2 samples stored and
4493 * the second sample covers 3/4 of the pixel. When reading samples 0
4494 * and 1, return physical sample 0 (determined by the first two 0s
4495 * in FMASK), otherwise return physical sample 1.
4496 *
4497 * The sample index should be adjusted as follows:
4498 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4499 */
4500 if (target == TGSI_TEXTURE_2D_MSAA ||
4501 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4502 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4503 struct lp_build_emit_data txf_emit_data = *emit_data;
4504 LLVMValueRef txf_address[4];
4505 unsigned txf_count = count;
4506 struct tgsi_full_instruction inst = {};
4507
4508 memcpy(txf_address, address, sizeof(txf_address));
4509
4510 if (target == TGSI_TEXTURE_2D_MSAA) {
4511 txf_address[2] = bld_base->uint_bld.zero;
4512 }
4513 txf_address[3] = bld_base->uint_bld.zero;
4514
4515 /* Read FMASK using TXF. */
4516 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4517 inst.Texture.Texture = target;
4518 txf_emit_data.inst = &inst;
4519 txf_emit_data.chan = 0;
4520 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
4521 target, fmask_ptr, NULL,
4522 txf_address, txf_count, 0xf);
4523 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4524
4525 /* Initialize some constants. */
4526 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4527 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4528
4529 /* Apply the formula. */
4530 LLVMValueRef fmask =
4531 LLVMBuildExtractElement(gallivm->builder,
4532 txf_emit_data.output[0],
4533 uint_bld->zero, "");
4534
4535 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4536
4537 LLVMValueRef sample_index4 =
4538 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4539
4540 LLVMValueRef shifted_fmask =
4541 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4542
4543 LLVMValueRef final_sample =
4544 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4545
4546 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4547 * resource descriptor is 0 (invalid),
4548 */
4549 LLVMValueRef fmask_desc =
4550 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4551 ctx->v8i32, "");
4552
4553 LLVMValueRef fmask_word1 =
4554 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4555 uint_bld->one, "");
4556
4557 LLVMValueRef word1_is_nonzero =
4558 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4559 fmask_word1, uint_bld->zero, "");
4560
4561 /* Replace the MSAA sample index. */
4562 address[sample_chan] =
4563 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4564 final_sample, address[sample_chan], "");
4565 }
4566
4567 if (opcode == TGSI_OPCODE_TXF) {
4568 /* add tex offsets */
4569 if (inst->Texture.NumOffsets) {
4570 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4571 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
4572 const struct tgsi_texture_offset *off = inst->TexOffsets;
4573
4574 assert(inst->Texture.NumOffsets == 1);
4575
4576 switch (target) {
4577 case TGSI_TEXTURE_3D:
4578 address[2] = lp_build_add(uint_bld, address[2],
4579 bld->immediates[off->Index][off->SwizzleZ]);
4580 /* fall through */
4581 case TGSI_TEXTURE_2D:
4582 case TGSI_TEXTURE_SHADOW2D:
4583 case TGSI_TEXTURE_RECT:
4584 case TGSI_TEXTURE_SHADOWRECT:
4585 case TGSI_TEXTURE_2D_ARRAY:
4586 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4587 address[1] =
4588 lp_build_add(uint_bld, address[1],
4589 bld->immediates[off->Index][off->SwizzleY]);
4590 /* fall through */
4591 case TGSI_TEXTURE_1D:
4592 case TGSI_TEXTURE_SHADOW1D:
4593 case TGSI_TEXTURE_1D_ARRAY:
4594 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4595 address[0] =
4596 lp_build_add(uint_bld, address[0],
4597 bld->immediates[off->Index][off->SwizzleX]);
4598 break;
4599 /* texture offsets do not apply to other texture targets */
4600 }
4601 }
4602 }
4603
4604 if (opcode == TGSI_OPCODE_TG4) {
4605 unsigned gather_comp = 0;
4606
4607 /* DMASK was repurposed for GATHER4. 4 components are always
4608 * returned and DMASK works like a swizzle - it selects
4609 * the component to fetch. The only valid DMASK values are
4610 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4611 * (red,red,red,red) etc.) The ISA document doesn't mention
4612 * this.
4613 */
4614
4615 /* Get the component index from src1.x for Gather4. */
4616 if (!tgsi_is_shadow_target(target)) {
4617 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
4618 LLVMValueRef comp_imm;
4619 struct tgsi_src_register src1 = inst->Src[1].Register;
4620
4621 assert(src1.File == TGSI_FILE_IMMEDIATE);
4622
4623 comp_imm = imms[src1.Index][src1.SwizzleX];
4624 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4625 gather_comp = CLAMP(gather_comp, 0, 3);
4626 }
4627
4628 dmask = 1 << gather_comp;
4629 }
4630
4631 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
4632 samp_ptr, address, count, dmask);
4633 }
4634
4635 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4636 struct lp_build_tgsi_context *bld_base,
4637 struct lp_build_emit_data *emit_data)
4638 {
4639 struct si_shader_context *ctx = si_shader_context(bld_base);
4640 struct lp_build_context *base = &bld_base->base;
4641 unsigned opcode = emit_data->inst->Instruction.Opcode;
4642 unsigned target = emit_data->inst->Texture.Texture;
4643 char intr_name[127];
4644 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
4645 bool is_shadow = tgsi_is_shadow_target(target);
4646 char type[64];
4647 const char *name = "llvm.SI.image.sample";
4648 const char *infix = "";
4649
4650 if (target == TGSI_TEXTURE_BUFFER) {
4651 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4652 base->gallivm->builder,
4653 "llvm.SI.vs.load.input", emit_data->dst_type,
4654 emit_data->args, emit_data->arg_count,
4655 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
4656 return;
4657 }
4658
4659 switch (opcode) {
4660 case TGSI_OPCODE_TXF:
4661 name = target == TGSI_TEXTURE_2D_MSAA ||
4662 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4663 "llvm.SI.image.load" :
4664 "llvm.SI.image.load.mip";
4665 is_shadow = false;
4666 has_offset = false;
4667 break;
4668 case TGSI_OPCODE_LODQ:
4669 name = "llvm.SI.getlod";
4670 is_shadow = false;
4671 has_offset = false;
4672 break;
4673 case TGSI_OPCODE_TEX:
4674 case TGSI_OPCODE_TEX2:
4675 case TGSI_OPCODE_TXP:
4676 if (ctx->type != PIPE_SHADER_FRAGMENT)
4677 infix = ".lz";
4678 break;
4679 case TGSI_OPCODE_TXB:
4680 case TGSI_OPCODE_TXB2:
4681 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4682 infix = ".b";
4683 break;
4684 case TGSI_OPCODE_TXL:
4685 case TGSI_OPCODE_TXL2:
4686 infix = ".l";
4687 break;
4688 case TGSI_OPCODE_TXD:
4689 infix = ".d";
4690 break;
4691 case TGSI_OPCODE_TG4:
4692 name = "llvm.SI.gather4";
4693 infix = ".lz";
4694 break;
4695 default:
4696 assert(0);
4697 return;
4698 }
4699
4700 /* Add the type and suffixes .c, .o if needed. */
4701 build_int_type_name(LLVMTypeOf(emit_data->args[0]), type, sizeof(type));
4702 sprintf(intr_name, "%s%s%s%s.%s",
4703 name, is_shadow ? ".c" : "", infix,
4704 has_offset ? ".o" : "", type);
4705
4706 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4707 base->gallivm->builder, intr_name, emit_data->dst_type,
4708 emit_data->args, emit_data->arg_count,
4709 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
4710 }
4711
4712 static void si_llvm_emit_txqs(
4713 const struct lp_build_tgsi_action *action,
4714 struct lp_build_tgsi_context *bld_base,
4715 struct lp_build_emit_data *emit_data)
4716 {
4717 struct si_shader_context *ctx = si_shader_context(bld_base);
4718 struct gallivm_state *gallivm = bld_base->base.gallivm;
4719 LLVMBuilderRef builder = gallivm->builder;
4720 LLVMValueRef res, samples;
4721 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4722
4723 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4724
4725
4726 /* Read the samples from the descriptor directly. */
4727 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4728 samples = LLVMBuildExtractElement(
4729 builder, res,
4730 lp_build_const_int32(gallivm, 3), "");
4731 samples = LLVMBuildLShr(builder, samples,
4732 lp_build_const_int32(gallivm, 16), "");
4733 samples = LLVMBuildAnd(builder, samples,
4734 lp_build_const_int32(gallivm, 0xf), "");
4735 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
4736 samples, "");
4737
4738 emit_data->output[emit_data->chan] = samples;
4739 }
4740
4741 /*
4742 * SI implements derivatives using the local data store (LDS)
4743 * All writes to the LDS happen in all executing threads at
4744 * the same time. TID is the Thread ID for the current
4745 * thread and is a value between 0 and 63, representing
4746 * the thread's position in the wavefront.
4747 *
4748 * For the pixel shader threads are grouped into quads of four pixels.
4749 * The TIDs of the pixels of a quad are:
4750 *
4751 * +------+------+
4752 * |4n + 0|4n + 1|
4753 * +------+------+
4754 * |4n + 2|4n + 3|
4755 * +------+------+
4756 *
4757 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
4758 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
4759 * the current pixel's column, and masking with 0xfffffffe yields the TID
4760 * of the left pixel of the current pixel's row.
4761 *
4762 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
4763 * adding 2 yields the TID of the pixel below the top pixel.
4764 */
4765 /* masks for thread ID. */
4766 #define TID_MASK_TOP_LEFT 0xfffffffc
4767 #define TID_MASK_TOP 0xfffffffd
4768 #define TID_MASK_LEFT 0xfffffffe
4769
4770 static void si_llvm_emit_ddxy(
4771 const struct lp_build_tgsi_action *action,
4772 struct lp_build_tgsi_context *bld_base,
4773 struct lp_build_emit_data *emit_data)
4774 {
4775 struct si_shader_context *ctx = si_shader_context(bld_base);
4776 struct gallivm_state *gallivm = bld_base->base.gallivm;
4777 const struct tgsi_full_instruction *inst = emit_data->inst;
4778 unsigned opcode = inst->Instruction.Opcode;
4779 LLVMValueRef indices[2];
4780 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
4781 LLVMValueRef tl, trbl, result[4];
4782 LLVMValueRef tl_tid, trbl_tid;
4783 unsigned swizzle[4];
4784 unsigned c;
4785 int idx;
4786 unsigned mask;
4787
4788 indices[0] = bld_base->uint_bld.zero;
4789 indices[1] = get_thread_id(ctx);
4790 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
4791 indices, 2, "");
4792
4793 if (opcode == TGSI_OPCODE_DDX_FINE)
4794 mask = TID_MASK_LEFT;
4795 else if (opcode == TGSI_OPCODE_DDY_FINE)
4796 mask = TID_MASK_TOP;
4797 else
4798 mask = TID_MASK_TOP_LEFT;
4799
4800 tl_tid = LLVMBuildAnd(gallivm->builder, indices[1],
4801 lp_build_const_int32(gallivm, mask), "");
4802 indices[1] = tl_tid;
4803 load_ptr0 = LLVMBuildGEP(gallivm->builder, ctx->lds,
4804 indices, 2, "");
4805
4806 /* for DDX we want to next X pixel, DDY next Y pixel. */
4807 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
4808 trbl_tid = LLVMBuildAdd(gallivm->builder, indices[1],
4809 lp_build_const_int32(gallivm, idx), "");
4810 indices[1] = trbl_tid;
4811 load_ptr1 = LLVMBuildGEP(gallivm->builder, ctx->lds,
4812 indices, 2, "");
4813
4814 for (c = 0; c < 4; ++c) {
4815 unsigned i;
4816 LLVMValueRef val;
4817 LLVMValueRef args[2];
4818
4819 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
4820 for (i = 0; i < c; ++i) {
4821 if (swizzle[i] == swizzle[c]) {
4822 result[c] = result[i];
4823 break;
4824 }
4825 }
4826 if (i != c)
4827 continue;
4828
4829 val = LLVMBuildBitCast(gallivm->builder,
4830 lp_build_emit_fetch(bld_base, inst, 0, c),
4831 ctx->i32, "");
4832
4833 if ((HAVE_LLVM >= 0x0309) && ctx->screen->b.family >= CHIP_TONGA) {
4834
4835 args[0] = LLVMBuildMul(gallivm->builder, tl_tid,
4836 lp_build_const_int32(gallivm, 4), "");
4837 args[1] = val;
4838 tl = lp_build_intrinsic(gallivm->builder,
4839 "llvm.amdgcn.ds.bpermute", ctx->i32,
4840 args, 2, LLVMReadNoneAttribute);
4841
4842 args[0] = LLVMBuildMul(gallivm->builder, trbl_tid,
4843 lp_build_const_int32(gallivm, 4), "");
4844 trbl = lp_build_intrinsic(gallivm->builder,
4845 "llvm.amdgcn.ds.bpermute", ctx->i32,
4846 args, 2, LLVMReadNoneAttribute);
4847 } else {
4848 LLVMBuildStore(gallivm->builder, val, store_ptr);
4849 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
4850 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
4851 }
4852 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
4853 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
4854 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
4855 }
4856
4857 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
4858 }
4859
4860 /*
4861 * this takes an I,J coordinate pair,
4862 * and works out the X and Y derivatives.
4863 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
4864 */
4865 static LLVMValueRef si_llvm_emit_ddxy_interp(
4866 struct lp_build_tgsi_context *bld_base,
4867 LLVMValueRef interp_ij)
4868 {
4869 struct si_shader_context *ctx = si_shader_context(bld_base);
4870 struct gallivm_state *gallivm = bld_base->base.gallivm;
4871 LLVMValueRef indices[2];
4872 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
4873 LLVMValueRef tl, tr, bl, result[4];
4874 unsigned c;
4875
4876 indices[0] = bld_base->uint_bld.zero;
4877 indices[1] = get_thread_id(ctx);
4878 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
4879 indices, 2, "");
4880
4881 temp = LLVMBuildAnd(gallivm->builder, indices[1],
4882 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
4883
4884 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
4885 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
4886
4887 indices[1] = temp;
4888 load_ptr_x = LLVMBuildGEP(gallivm->builder, ctx->lds,
4889 indices, 2, "");
4890
4891 indices[1] = temp2;
4892 load_ptr_y = LLVMBuildGEP(gallivm->builder, ctx->lds,
4893 indices, 2, "");
4894
4895 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
4896 lp_build_const_int32(gallivm, 1), "");
4897 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, ctx->lds,
4898 indices, 2, "");
4899
4900 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
4901 lp_build_const_int32(gallivm, 2), "");
4902 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, ctx->lds,
4903 indices, 2, "");
4904
4905 for (c = 0; c < 2; ++c) {
4906 LLVMValueRef store_val;
4907 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
4908
4909 store_val = LLVMBuildExtractElement(gallivm->builder,
4910 interp_ij, c_ll, "");
4911 LLVMBuildStore(gallivm->builder,
4912 store_val,
4913 store_ptr);
4914
4915 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
4916 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
4917
4918 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
4919 tr = LLVMBuildBitCast(gallivm->builder, tr, ctx->f32, "");
4920
4921 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
4922
4923 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
4924 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
4925
4926 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
4927 bl = LLVMBuildBitCast(gallivm->builder, bl, ctx->f32, "");
4928
4929 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
4930 }
4931
4932 return lp_build_gather_values(gallivm, result, 4);
4933 }
4934
4935 static void interp_fetch_args(
4936 struct lp_build_tgsi_context *bld_base,
4937 struct lp_build_emit_data *emit_data)
4938 {
4939 struct si_shader_context *ctx = si_shader_context(bld_base);
4940 struct gallivm_state *gallivm = bld_base->base.gallivm;
4941 const struct tgsi_full_instruction *inst = emit_data->inst;
4942
4943 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
4944 /* offset is in second src, first two channels */
4945 emit_data->args[0] = lp_build_emit_fetch(bld_base,
4946 emit_data->inst, 1,
4947 TGSI_CHAN_X);
4948 emit_data->args[1] = lp_build_emit_fetch(bld_base,
4949 emit_data->inst, 1,
4950 TGSI_CHAN_Y);
4951 emit_data->arg_count = 2;
4952 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4953 LLVMValueRef sample_position;
4954 LLVMValueRef sample_id;
4955 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
4956
4957 /* fetch sample ID, then fetch its sample position,
4958 * and place into first two channels.
4959 */
4960 sample_id = lp_build_emit_fetch(bld_base,
4961 emit_data->inst, 1, TGSI_CHAN_X);
4962 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
4963 ctx->i32, "");
4964 sample_position = load_sample_position(&ctx->radeon_bld, sample_id);
4965
4966 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
4967 sample_position,
4968 lp_build_const_int32(gallivm, 0), "");
4969
4970 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
4971 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
4972 sample_position,
4973 lp_build_const_int32(gallivm, 1), "");
4974 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
4975 emit_data->arg_count = 2;
4976 }
4977 }
4978
4979 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
4980 struct lp_build_tgsi_context *bld_base,
4981 struct lp_build_emit_data *emit_data)
4982 {
4983 struct si_shader_context *ctx = si_shader_context(bld_base);
4984 struct si_shader *shader = ctx->shader;
4985 struct gallivm_state *gallivm = bld_base->base.gallivm;
4986 LLVMValueRef interp_param;
4987 const struct tgsi_full_instruction *inst = emit_data->inst;
4988 const char *intr_name;
4989 int input_index = inst->Src[0].Register.Index;
4990 int chan;
4991 int i;
4992 LLVMValueRef attr_number;
4993 LLVMValueRef params = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
4994 int interp_param_idx;
4995 unsigned interp = shader->selector->info.input_interpolate[input_index];
4996 unsigned location;
4997
4998 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
4999
5000 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5001 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
5002 location = TGSI_INTERPOLATE_LOC_CENTER;
5003 else
5004 location = TGSI_INTERPOLATE_LOC_CENTROID;
5005
5006 interp_param_idx = lookup_interp_param_index(interp, location);
5007 if (interp_param_idx == -1)
5008 return;
5009 else if (interp_param_idx)
5010 interp_param = LLVMGetParam(ctx->radeon_bld.main_fn, interp_param_idx);
5011 else
5012 interp_param = NULL;
5013
5014 attr_number = lp_build_const_int32(gallivm, input_index);
5015
5016 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5017 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5018 LLVMValueRef ij_out[2];
5019 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
5020
5021 /*
5022 * take the I then J parameters, and the DDX/Y for it, and
5023 * calculate the IJ inputs for the interpolator.
5024 * temp1 = ddx * offset/sample.x + I;
5025 * interp_param.I = ddy * offset/sample.y + temp1;
5026 * temp1 = ddx * offset/sample.x + J;
5027 * interp_param.J = ddy * offset/sample.y + temp1;
5028 */
5029 for (i = 0; i < 2; i++) {
5030 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
5031 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
5032 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
5033 ddxy_out, ix_ll, "");
5034 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
5035 ddxy_out, iy_ll, "");
5036 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
5037 interp_param, ix_ll, "");
5038 LLVMValueRef temp1, temp2;
5039
5040 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
5041 ctx->f32, "");
5042
5043 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
5044
5045 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
5046
5047 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
5048
5049 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
5050
5051 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
5052 temp2, ctx->i32, "");
5053 }
5054 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
5055 }
5056
5057 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
5058 for (chan = 0; chan < 2; chan++) {
5059 LLVMValueRef args[4];
5060 LLVMValueRef llvm_chan;
5061 unsigned schan;
5062
5063 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
5064 llvm_chan = lp_build_const_int32(gallivm, schan);
5065
5066 args[0] = llvm_chan;
5067 args[1] = attr_number;
5068 args[2] = params;
5069 args[3] = interp_param;
5070
5071 emit_data->output[chan] =
5072 lp_build_intrinsic(gallivm->builder, intr_name,
5073 ctx->f32, args, args[3] ? 4 : 3,
5074 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
5075 }
5076 }
5077
5078 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
5079 struct lp_build_emit_data *emit_data)
5080 {
5081 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
5082 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
5083 unsigned stream;
5084
5085 assert(src0.File == TGSI_FILE_IMMEDIATE);
5086
5087 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
5088 return stream;
5089 }
5090
5091 /* Emit one vertex from the geometry shader */
5092 static void si_llvm_emit_vertex(
5093 const struct lp_build_tgsi_action *action,
5094 struct lp_build_tgsi_context *bld_base,
5095 struct lp_build_emit_data *emit_data)
5096 {
5097 struct si_shader_context *ctx = si_shader_context(bld_base);
5098 struct lp_build_context *uint = &bld_base->uint_bld;
5099 struct si_shader *shader = ctx->shader;
5100 struct tgsi_shader_info *info = &shader->selector->info;
5101 struct gallivm_state *gallivm = bld_base->base.gallivm;
5102 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
5103 SI_PARAM_GS2VS_OFFSET);
5104 LLVMValueRef gs_next_vertex;
5105 LLVMValueRef can_emit, kill;
5106 LLVMValueRef args[2];
5107 unsigned chan;
5108 int i;
5109 unsigned stream;
5110
5111 stream = si_llvm_get_stream(bld_base, emit_data);
5112
5113 /* Write vertex attribute values to GSVS ring */
5114 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5115 ctx->gs_next_vertex[stream],
5116 "");
5117
5118 /* If this thread has already emitted the declared maximum number of
5119 * vertices, kill it: excessive vertex emissions are not supposed to
5120 * have any effect, and GS threads have no externally observable
5121 * effects other than emitting vertices.
5122 */
5123 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
5124 lp_build_const_int32(gallivm,
5125 shader->selector->gs_max_out_vertices), "");
5126 kill = lp_build_select(&bld_base->base, can_emit,
5127 lp_build_const_float(gallivm, 1.0f),
5128 lp_build_const_float(gallivm, -1.0f));
5129
5130 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
5131 ctx->voidt, &kill, 1, 0);
5132
5133 for (i = 0; i < info->num_outputs; i++) {
5134 LLVMValueRef *out_ptr =
5135 ctx->radeon_bld.soa.outputs[i];
5136
5137 for (chan = 0; chan < 4; chan++) {
5138 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5139 LLVMValueRef voffset =
5140 lp_build_const_int32(gallivm, (i * 4 + chan) *
5141 shader->selector->gs_max_out_vertices);
5142
5143 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5144 voffset = lp_build_mul_imm(uint, voffset, 4);
5145
5146 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5147
5148 build_tbuffer_store(ctx,
5149 ctx->gsvs_ring[stream],
5150 out_val, 1,
5151 voffset, soffset, 0,
5152 V_008F0C_BUF_DATA_FORMAT_32,
5153 V_008F0C_BUF_NUM_FORMAT_UINT,
5154 1, 0, 1, 1, 0);
5155 }
5156 }
5157 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5158 lp_build_const_int32(gallivm, 1));
5159
5160 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5161
5162 /* Signal vertex emission */
5163 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
5164 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
5165 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5166 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
5167 }
5168
5169 /* Cut one primitive from the geometry shader */
5170 static void si_llvm_emit_primitive(
5171 const struct lp_build_tgsi_action *action,
5172 struct lp_build_tgsi_context *bld_base,
5173 struct lp_build_emit_data *emit_data)
5174 {
5175 struct si_shader_context *ctx = si_shader_context(bld_base);
5176 struct gallivm_state *gallivm = bld_base->base.gallivm;
5177 LLVMValueRef args[2];
5178 unsigned stream;
5179
5180 /* Signal primitive cut */
5181 stream = si_llvm_get_stream(bld_base, emit_data);
5182 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
5183 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
5184 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5185 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
5186 }
5187
5188 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5189 struct lp_build_tgsi_context *bld_base,
5190 struct lp_build_emit_data *emit_data)
5191 {
5192 struct si_shader_context *ctx = si_shader_context(bld_base);
5193 struct gallivm_state *gallivm = bld_base->base.gallivm;
5194
5195 /* The real barrier instruction isn’t needed, because an entire patch
5196 * always fits into a single wave.
5197 */
5198 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
5199 emit_optimization_barrier(ctx);
5200 return;
5201 }
5202
5203 lp_build_intrinsic(gallivm->builder,
5204 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5205 : "llvm.AMDGPU.barrier.local",
5206 ctx->voidt, NULL, 0, LLVMNoUnwindAttribute);
5207 }
5208
5209 static const struct lp_build_tgsi_action tex_action = {
5210 .fetch_args = tex_fetch_args,
5211 .emit = build_tex_intrinsic,
5212 };
5213
5214 static const struct lp_build_tgsi_action interp_action = {
5215 .fetch_args = interp_fetch_args,
5216 .emit = build_interp_intrinsic,
5217 };
5218
5219 static void si_create_function(struct si_shader_context *ctx,
5220 LLVMTypeRef *returns, unsigned num_returns,
5221 LLVMTypeRef *params, unsigned num_params,
5222 int last_array_pointer, int last_sgpr)
5223 {
5224 int i;
5225
5226 radeon_llvm_create_func(&ctx->radeon_bld, returns, num_returns,
5227 params, num_params);
5228 radeon_llvm_shader_type(ctx->radeon_bld.main_fn, ctx->type);
5229 ctx->return_value = LLVMGetUndef(ctx->radeon_bld.return_type);
5230
5231 for (i = 0; i <= last_sgpr; ++i) {
5232 LLVMValueRef P = LLVMGetParam(ctx->radeon_bld.main_fn, i);
5233
5234 /* We tell llvm that array inputs are passed by value to allow Sinking pass
5235 * to move load. Inputs are constant so this is fine. */
5236 if (i <= last_array_pointer)
5237 LLVMAddAttribute(P, LLVMByValAttribute);
5238 else
5239 LLVMAddAttribute(P, LLVMInRegAttribute);
5240 }
5241 }
5242
5243 static void create_meta_data(struct si_shader_context *ctx)
5244 {
5245 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
5246 LLVMValueRef args[3];
5247
5248 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
5249 args[1] = 0;
5250 args[2] = lp_build_const_int32(gallivm, 1);
5251
5252 ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
5253
5254 ctx->uniform_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5255 "amdgpu.uniform", 14);
5256
5257 ctx->empty_md = LLVMMDNodeInContext(gallivm->context, NULL, 0);
5258 }
5259
5260 static void declare_streamout_params(struct si_shader_context *ctx,
5261 struct pipe_stream_output_info *so,
5262 LLVMTypeRef *params, LLVMTypeRef i32,
5263 unsigned *num_params)
5264 {
5265 int i;
5266
5267 /* Streamout SGPRs. */
5268 if (so->num_outputs) {
5269 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5270 params[ctx->param_streamout_config = (*num_params)++] = i32;
5271 else
5272 ctx->param_streamout_config = ctx->param_tess_offchip;
5273
5274 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5275 }
5276 /* A streamout buffer offset is loaded if the stride is non-zero. */
5277 for (i = 0; i < 4; i++) {
5278 if (!so->stride[i])
5279 continue;
5280
5281 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5282 }
5283 }
5284
5285 static unsigned llvm_get_type_size(LLVMTypeRef type)
5286 {
5287 LLVMTypeKind kind = LLVMGetTypeKind(type);
5288
5289 switch (kind) {
5290 case LLVMIntegerTypeKind:
5291 return LLVMGetIntTypeWidth(type) / 8;
5292 case LLVMFloatTypeKind:
5293 return 4;
5294 case LLVMPointerTypeKind:
5295 return 8;
5296 case LLVMVectorTypeKind:
5297 return LLVMGetVectorSize(type) *
5298 llvm_get_type_size(LLVMGetElementType(type));
5299 default:
5300 assert(0);
5301 return 0;
5302 }
5303 }
5304
5305 static void declare_tess_lds(struct si_shader_context *ctx)
5306 {
5307 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
5308 LLVMTypeRef i32 = ctx->radeon_bld.soa.bld_base.uint_bld.elem_type;
5309 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5310
5311 /* The actual size is computed outside of the shader to reduce
5312 * the number of shader variants. */
5313 ctx->lds =
5314 LLVMAddGlobalInAddressSpace(gallivm->module,
5315 LLVMArrayType(i32, lds_size / 4),
5316 "tess_lds",
5317 LOCAL_ADDR_SPACE);
5318 }
5319
5320 static void create_function(struct si_shader_context *ctx)
5321 {
5322 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5323 struct gallivm_state *gallivm = bld_base->base.gallivm;
5324 struct si_shader *shader = ctx->shader;
5325 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
5326 LLVMTypeRef returns[16+32*4];
5327 unsigned i, last_array_pointer, last_sgpr, num_params, num_return_sgprs;
5328 unsigned num_returns = 0;
5329
5330 v3i32 = LLVMVectorType(ctx->i32, 3);
5331
5332 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5333 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5334 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5335 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5336 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5337 last_array_pointer = SI_PARAM_SHADER_BUFFERS;
5338
5339 switch (ctx->type) {
5340 case PIPE_SHADER_VERTEX:
5341 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
5342 last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
5343 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5344 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5345 num_params = SI_PARAM_START_INSTANCE+1;
5346
5347 if (shader->key.vs.as_es) {
5348 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5349 } else if (shader->key.vs.as_ls) {
5350 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
5351 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
5352 } else {
5353 if (ctx->is_gs_copy_shader) {
5354 last_array_pointer = SI_PARAM_RW_BUFFERS;
5355 num_params = SI_PARAM_RW_BUFFERS+1;
5356 } else {
5357 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5358 num_params = SI_PARAM_VS_STATE_BITS+1;
5359 }
5360
5361 /* The locations of the other parameters are assigned dynamically. */
5362 declare_streamout_params(ctx, &shader->selector->so,
5363 params, ctx->i32, &num_params);
5364 }
5365
5366 last_sgpr = num_params-1;
5367
5368 /* VGPRs */
5369 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5370 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5371 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5372 params[ctx->param_instance_id = num_params++] = ctx->i32;
5373
5374 if (!ctx->is_monolithic &&
5375 !ctx->is_gs_copy_shader) {
5376 /* Vertex load indices. */
5377 ctx->param_vertex_index0 = num_params;
5378
5379 for (i = 0; i < shader->selector->info.num_inputs; i++)
5380 params[num_params++] = ctx->i32;
5381
5382 /* PrimitiveID output. */
5383 if (!shader->key.vs.as_es && !shader->key.vs.as_ls)
5384 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5385 returns[num_returns++] = ctx->f32;
5386 }
5387 break;
5388
5389 case PIPE_SHADER_TESS_CTRL:
5390 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5391 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5392 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5393 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5394 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5395 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5396 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5397
5398 /* VGPRs */
5399 params[SI_PARAM_PATCH_ID] = ctx->i32;
5400 params[SI_PARAM_REL_IDS] = ctx->i32;
5401 num_params = SI_PARAM_REL_IDS+1;
5402
5403 if (!ctx->is_monolithic) {
5404 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5405 * placed after the user SGPRs.
5406 */
5407 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5408 returns[num_returns++] = ctx->i32; /* SGPRs */
5409
5410 for (i = 0; i < 3; i++)
5411 returns[num_returns++] = ctx->f32; /* VGPRs */
5412 }
5413 break;
5414
5415 case PIPE_SHADER_TESS_EVAL:
5416 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5417 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5418
5419 if (shader->key.tes.as_es) {
5420 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5421 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5422 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5423 } else {
5424 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5425 declare_streamout_params(ctx, &shader->selector->so,
5426 params, ctx->i32, &num_params);
5427 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5428 }
5429 last_sgpr = num_params - 1;
5430
5431 /* VGPRs */
5432 params[ctx->param_tes_u = num_params++] = ctx->f32;
5433 params[ctx->param_tes_v = num_params++] = ctx->f32;
5434 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5435 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5436
5437 /* PrimitiveID output. */
5438 if (!ctx->is_monolithic && !shader->key.tes.as_es)
5439 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5440 returns[num_returns++] = ctx->f32;
5441 break;
5442
5443 case PIPE_SHADER_GEOMETRY:
5444 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5445 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5446 last_sgpr = SI_PARAM_GS_WAVE_ID;
5447
5448 /* VGPRs */
5449 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5450 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5451 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5452 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5453 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5454 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5455 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5456 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5457 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5458 break;
5459
5460 case PIPE_SHADER_FRAGMENT:
5461 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5462 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5463 last_sgpr = SI_PARAM_PRIM_MASK;
5464 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5465 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5466 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5467 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5468 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5469 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5470 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5471 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5472 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5473 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5474 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5475 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5476 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5477 params[SI_PARAM_ANCILLARY] = ctx->i32;
5478 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5479 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5480 num_params = SI_PARAM_POS_FIXED_PT+1;
5481
5482 if (!ctx->is_monolithic) {
5483 /* Color inputs from the prolog. */
5484 if (shader->selector->info.colors_read) {
5485 unsigned num_color_elements =
5486 util_bitcount(shader->selector->info.colors_read);
5487
5488 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5489 for (i = 0; i < num_color_elements; i++)
5490 params[num_params++] = ctx->f32;
5491 }
5492
5493 /* Outputs for the epilog. */
5494 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5495 num_returns =
5496 num_return_sgprs +
5497 util_bitcount(shader->selector->info.colors_written) * 4 +
5498 shader->selector->info.writes_z +
5499 shader->selector->info.writes_stencil +
5500 shader->selector->info.writes_samplemask +
5501 1 /* SampleMaskIn */;
5502
5503 num_returns = MAX2(num_returns,
5504 num_return_sgprs +
5505 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5506
5507 for (i = 0; i < num_return_sgprs; i++)
5508 returns[i] = ctx->i32;
5509 for (; i < num_returns; i++)
5510 returns[i] = ctx->f32;
5511 }
5512 break;
5513
5514 case PIPE_SHADER_COMPUTE:
5515 params[SI_PARAM_GRID_SIZE] = v3i32;
5516 params[SI_PARAM_BLOCK_ID] = v3i32;
5517 last_sgpr = SI_PARAM_BLOCK_ID;
5518
5519 params[SI_PARAM_THREAD_ID] = v3i32;
5520 num_params = SI_PARAM_THREAD_ID + 1;
5521 break;
5522 default:
5523 assert(0 && "unimplemented shader");
5524 return;
5525 }
5526
5527 assert(num_params <= ARRAY_SIZE(params));
5528
5529 si_create_function(ctx, returns, num_returns, params,
5530 num_params, last_array_pointer, last_sgpr);
5531
5532 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5533 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5534 !ctx->is_monolithic) {
5535 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
5536 "InitialPSInputAddr",
5537 S_0286D0_PERSP_SAMPLE_ENA(1) |
5538 S_0286D0_PERSP_CENTER_ENA(1) |
5539 S_0286D0_PERSP_CENTROID_ENA(1) |
5540 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5541 S_0286D0_LINEAR_CENTER_ENA(1) |
5542 S_0286D0_LINEAR_CENTROID_ENA(1) |
5543 S_0286D0_FRONT_FACE_ENA(1) |
5544 S_0286D0_POS_FIXED_PT_ENA(1));
5545 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5546 const unsigned *properties = shader->selector->info.properties;
5547 unsigned max_work_group_size =
5548 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5549 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5550 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5551
5552 assert(max_work_group_size);
5553
5554 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
5555 "amdgpu-max-work-group-size",
5556 max_work_group_size);
5557 }
5558
5559 shader->info.num_input_sgprs = 0;
5560 shader->info.num_input_vgprs = 0;
5561
5562 for (i = 0; i <= last_sgpr; ++i)
5563 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5564
5565 /* Unused fragment shader inputs are eliminated by the compiler,
5566 * so we don't know yet how many there will be.
5567 */
5568 if (ctx->type != PIPE_SHADER_FRAGMENT)
5569 for (; i < num_params; ++i)
5570 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5571
5572 if (bld_base->info &&
5573 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5574 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5575 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5576 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5577 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5578 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5579 ctx->lds =
5580 LLVMAddGlobalInAddressSpace(gallivm->module,
5581 LLVMArrayType(ctx->i32, 64),
5582 "ddxy_lds",
5583 LOCAL_ADDR_SPACE);
5584
5585 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.vs.as_ls) ||
5586 ctx->type == PIPE_SHADER_TESS_CTRL ||
5587 ctx->type == PIPE_SHADER_TESS_EVAL)
5588 declare_tess_lds(ctx);
5589 }
5590
5591 static void preload_constants(struct si_shader_context *ctx)
5592 {
5593 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5594 struct gallivm_state *gallivm = bld_base->base.gallivm;
5595 const struct tgsi_shader_info *info = bld_base->info;
5596 unsigned buf;
5597 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
5598
5599 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
5600 unsigned i, num_const = info->const_file_max[buf] + 1;
5601
5602 if (num_const == 0)
5603 continue;
5604
5605 /* Allocate space for the constant values */
5606 ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
5607
5608 /* Load the resource descriptor */
5609 ctx->const_buffers[buf] =
5610 build_indexed_load_const(ctx, ptr, lp_build_const_int32(gallivm, buf));
5611
5612 /* Load the constants, we rely on the code sinking to do the rest */
5613 for (i = 0; i < num_const * 4; ++i) {
5614 ctx->constants[buf][i] =
5615 buffer_load_const(gallivm->builder,
5616 ctx->const_buffers[buf],
5617 lp_build_const_int32(gallivm, i * 4),
5618 ctx->f32);
5619 }
5620 }
5621 }
5622
5623 static void preload_shader_buffers(struct si_shader_context *ctx)
5624 {
5625 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
5626 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_SHADER_BUFFERS);
5627 int buf, maxbuf;
5628
5629 maxbuf = MIN2(ctx->shader->selector->info.file_max[TGSI_FILE_BUFFER],
5630 SI_NUM_SHADER_BUFFERS - 1);
5631 for (buf = 0; buf <= maxbuf; ++buf) {
5632 ctx->shader_buffers[buf] =
5633 build_indexed_load_const(
5634 ctx, ptr, lp_build_const_int32(gallivm, buf));
5635 }
5636 }
5637
5638 static void preload_samplers(struct si_shader_context *ctx)
5639 {
5640 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5641 struct gallivm_state *gallivm = bld_base->base.gallivm;
5642 const struct tgsi_shader_info *info = bld_base->info;
5643 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
5644 LLVMValueRef offset;
5645
5646 if (num_samplers == 0)
5647 return;
5648
5649 /* Load the resources and samplers, we rely on the code sinking to do the rest */
5650 for (i = 0; i < num_samplers; ++i) {
5651 /* Resource */
5652 offset = lp_build_const_int32(gallivm, i);
5653 ctx->sampler_views[i] =
5654 get_sampler_desc(ctx, offset, DESC_IMAGE);
5655
5656 /* FMASK resource */
5657 if (info->is_msaa_sampler[i])
5658 ctx->fmasks[i] =
5659 get_sampler_desc(ctx, offset, DESC_FMASK);
5660 else {
5661 ctx->sampler_states[i] =
5662 get_sampler_desc(ctx, offset, DESC_SAMPLER);
5663 ctx->sampler_states[i] =
5664 sici_fix_sampler_aniso(ctx, ctx->sampler_views[i],
5665 ctx->sampler_states[i]);
5666 }
5667 }
5668 }
5669
5670 static void preload_images(struct si_shader_context *ctx)
5671 {
5672 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5673 struct tgsi_shader_info *info = &ctx->shader->selector->info;
5674 struct gallivm_state *gallivm = bld_base->base.gallivm;
5675 unsigned num_images = bld_base->info->file_max[TGSI_FILE_IMAGE] + 1;
5676 LLVMValueRef res_ptr;
5677 unsigned i;
5678
5679 if (num_images == 0)
5680 return;
5681
5682 res_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_IMAGES);
5683
5684 for (i = 0; i < num_images; ++i) {
5685 /* Rely on LLVM to shrink the load for buffer resources. */
5686 LLVMValueRef rsrc =
5687 build_indexed_load_const(ctx, res_ptr,
5688 lp_build_const_int32(gallivm, i));
5689
5690 if (info->images_writemask & (1 << i) &&
5691 !(info->images_buffers & (1 << i)))
5692 rsrc = force_dcc_off(ctx, rsrc);
5693
5694 ctx->images[i] = rsrc;
5695 }
5696 }
5697
5698 static void preload_streamout_buffers(struct si_shader_context *ctx)
5699 {
5700 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5701 struct gallivm_state *gallivm = bld_base->base.gallivm;
5702 unsigned i;
5703
5704 /* Streamout can only be used if the shader is compiled as VS. */
5705 if (!ctx->shader->selector->so.num_outputs ||
5706 (ctx->type == PIPE_SHADER_VERTEX &&
5707 (ctx->shader->key.vs.as_es ||
5708 ctx->shader->key.vs.as_ls)) ||
5709 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5710 ctx->shader->key.tes.as_es))
5711 return;
5712
5713 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
5714 SI_PARAM_RW_BUFFERS);
5715
5716 /* Load the resources, we rely on the code sinking to do the rest */
5717 for (i = 0; i < 4; ++i) {
5718 if (ctx->shader->selector->so.stride[i]) {
5719 LLVMValueRef offset = lp_build_const_int32(gallivm,
5720 SI_VS_STREAMOUT_BUF0 + i);
5721
5722 ctx->so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
5723 }
5724 }
5725 }
5726
5727 /**
5728 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5729 * for later use.
5730 */
5731 static void preload_ring_buffers(struct si_shader_context *ctx)
5732 {
5733 struct gallivm_state *gallivm =
5734 ctx->radeon_bld.soa.bld_base.base.gallivm;
5735
5736 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
5737 SI_PARAM_RW_BUFFERS);
5738
5739 if ((ctx->type == PIPE_SHADER_VERTEX &&
5740 ctx->shader->key.vs.as_es) ||
5741 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5742 ctx->shader->key.tes.as_es) ||
5743 ctx->type == PIPE_SHADER_GEOMETRY) {
5744 unsigned ring =
5745 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5746 : SI_ES_RING_ESGS;
5747 LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
5748
5749 ctx->esgs_ring =
5750 build_indexed_load_const(ctx, buf_ptr, offset);
5751 }
5752
5753 if (ctx->is_gs_copy_shader) {
5754 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_VS_RING_GSVS);
5755
5756 ctx->gsvs_ring[0] =
5757 build_indexed_load_const(ctx, buf_ptr, offset);
5758 }
5759 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5760 int i;
5761 for (i = 0; i < 4; i++) {
5762 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_GS_RING_GSVS0 + i);
5763
5764 ctx->gsvs_ring[i] =
5765 build_indexed_load_const(ctx, buf_ptr, offset);
5766 }
5767 }
5768 }
5769
5770 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5771 LLVMValueRef param_rw_buffers,
5772 unsigned param_pos_fixed_pt)
5773 {
5774 struct lp_build_tgsi_context *bld_base =
5775 &ctx->radeon_bld.soa.bld_base;
5776 struct gallivm_state *gallivm = bld_base->base.gallivm;
5777 LLVMBuilderRef builder = gallivm->builder;
5778 LLVMValueRef slot, desc, offset, row, bit, address[2];
5779
5780 /* Use the fixed-point gl_FragCoord input.
5781 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5782 * per coordinate to get the repeating effect.
5783 */
5784 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5785 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5786
5787 /* Load the buffer descriptor. */
5788 slot = lp_build_const_int32(gallivm, SI_PS_CONST_POLY_STIPPLE);
5789 desc = build_indexed_load_const(ctx, param_rw_buffers, slot);
5790
5791 /* The stipple pattern is 32x32, each row has 32 bits. */
5792 offset = LLVMBuildMul(builder, address[1],
5793 LLVMConstInt(ctx->i32, 4, 0), "");
5794 row = buffer_load_const(builder, desc, offset, ctx->i32);
5795 bit = LLVMBuildLShr(builder, row, address[0], "");
5796 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5797
5798 /* The intrinsic kills the thread if arg < 0. */
5799 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
5800 LLVMConstReal(ctx->f32, -1), "");
5801 lp_build_intrinsic(builder, "llvm.AMDGPU.kill", ctx->voidt, &bit, 1, 0);
5802 }
5803
5804 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
5805 struct si_shader_config *conf,
5806 unsigned symbol_offset)
5807 {
5808 unsigned i;
5809 const unsigned char *config =
5810 radeon_shader_binary_config_start(binary, symbol_offset);
5811
5812 /* XXX: We may be able to emit some of these values directly rather than
5813 * extracting fields to be emitted later.
5814 */
5815
5816 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5817 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5818 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5819 switch (reg) {
5820 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5821 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5822 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5823 case R_00B848_COMPUTE_PGM_RSRC1:
5824 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5825 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5826 conf->float_mode = G_00B028_FLOAT_MODE(value);
5827 conf->rsrc1 = value;
5828 break;
5829 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5830 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5831 break;
5832 case R_00B84C_COMPUTE_PGM_RSRC2:
5833 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5834 conf->rsrc2 = value;
5835 break;
5836 case R_0286CC_SPI_PS_INPUT_ENA:
5837 conf->spi_ps_input_ena = value;
5838 break;
5839 case R_0286D0_SPI_PS_INPUT_ADDR:
5840 conf->spi_ps_input_addr = value;
5841 break;
5842 case R_0286E8_SPI_TMPRING_SIZE:
5843 case R_00B860_COMPUTE_TMPRING_SIZE:
5844 /* WAVESIZE is in units of 256 dwords. */
5845 conf->scratch_bytes_per_wave =
5846 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
5847 break;
5848 default:
5849 {
5850 static bool printed;
5851
5852 if (!printed) {
5853 fprintf(stderr, "Warning: LLVM emitted unknown "
5854 "config register: 0x%x\n", reg);
5855 printed = true;
5856 }
5857 }
5858 break;
5859 }
5860
5861 if (!conf->spi_ps_input_addr)
5862 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5863 }
5864 }
5865
5866 void si_shader_apply_scratch_relocs(struct si_context *sctx,
5867 struct si_shader *shader,
5868 struct si_shader_config *config,
5869 uint64_t scratch_va)
5870 {
5871 unsigned i;
5872 uint32_t scratch_rsrc_dword0 = scratch_va;
5873 uint32_t scratch_rsrc_dword1 =
5874 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
5875 | S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
5876
5877 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5878 const struct radeon_shader_reloc *reloc =
5879 &shader->binary.relocs[i];
5880 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5881 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5882 &scratch_rsrc_dword0, 4);
5883 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5884 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5885 &scratch_rsrc_dword1, 4);
5886 }
5887 }
5888 }
5889
5890 static unsigned si_get_shader_binary_size(struct si_shader *shader)
5891 {
5892 unsigned size = shader->binary.code_size;
5893
5894 if (shader->prolog)
5895 size += shader->prolog->binary.code_size;
5896 if (shader->epilog)
5897 size += shader->epilog->binary.code_size;
5898 return size;
5899 }
5900
5901 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5902 {
5903 const struct radeon_shader_binary *prolog =
5904 shader->prolog ? &shader->prolog->binary : NULL;
5905 const struct radeon_shader_binary *epilog =
5906 shader->epilog ? &shader->epilog->binary : NULL;
5907 const struct radeon_shader_binary *mainb = &shader->binary;
5908 unsigned bo_size = si_get_shader_binary_size(shader) +
5909 (!epilog ? mainb->rodata_size : 0);
5910 unsigned char *ptr;
5911
5912 assert(!prolog || !prolog->rodata_size);
5913 assert((!prolog && !epilog) || !mainb->rodata_size);
5914 assert(!epilog || !epilog->rodata_size);
5915
5916 r600_resource_reference(&shader->bo, NULL);
5917 shader->bo = si_resource_create_custom(&sscreen->b.b,
5918 PIPE_USAGE_IMMUTABLE,
5919 bo_size);
5920 if (!shader->bo)
5921 return -ENOMEM;
5922
5923 /* Upload. */
5924 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
5925 PIPE_TRANSFER_READ_WRITE);
5926
5927 if (prolog) {
5928 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
5929 ptr += prolog->code_size;
5930 }
5931
5932 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
5933 ptr += mainb->code_size;
5934
5935 if (epilog)
5936 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
5937 else if (mainb->rodata_size > 0)
5938 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
5939
5940 sscreen->b.ws->buffer_unmap(shader->bo->buf);
5941 return 0;
5942 }
5943
5944 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
5945 struct pipe_debug_callback *debug,
5946 const char *name, FILE *file)
5947 {
5948 char *line, *p;
5949 unsigned i, count;
5950
5951 if (binary->disasm_string) {
5952 fprintf(file, "Shader %s disassembly:\n", name);
5953 fprintf(file, "%s", binary->disasm_string);
5954
5955 if (debug && debug->debug_message) {
5956 /* Very long debug messages are cut off, so send the
5957 * disassembly one line at a time. This causes more
5958 * overhead, but on the plus side it simplifies
5959 * parsing of resulting logs.
5960 */
5961 pipe_debug_message(debug, SHADER_INFO,
5962 "Shader Disassembly Begin");
5963
5964 line = binary->disasm_string;
5965 while (*line) {
5966 p = util_strchrnul(line, '\n');
5967 count = p - line;
5968
5969 if (count) {
5970 pipe_debug_message(debug, SHADER_INFO,
5971 "%.*s", count, line);
5972 }
5973
5974 if (!*p)
5975 break;
5976 line = p + 1;
5977 }
5978
5979 pipe_debug_message(debug, SHADER_INFO,
5980 "Shader Disassembly End");
5981 }
5982 } else {
5983 fprintf(file, "Shader %s binary:\n", name);
5984 for (i = 0; i < binary->code_size; i += 4) {
5985 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5986 binary->code[i + 3], binary->code[i + 2],
5987 binary->code[i + 1], binary->code[i]);
5988 }
5989 }
5990 }
5991
5992 static void si_shader_dump_stats(struct si_screen *sscreen,
5993 struct si_shader_config *conf,
5994 unsigned num_inputs,
5995 unsigned code_size,
5996 struct pipe_debug_callback *debug,
5997 unsigned processor,
5998 FILE *file)
5999 {
6000 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
6001 unsigned lds_per_wave = 0;
6002 unsigned max_simd_waves = 10;
6003
6004 /* Compute LDS usage for PS. */
6005 if (processor == PIPE_SHADER_FRAGMENT) {
6006 /* The minimum usage per wave is (num_inputs * 48). The maximum
6007 * usage is (num_inputs * 48 * 16).
6008 * We can get anything in between and it varies between waves.
6009 *
6010 * The 48 bytes per input for a single primitive is equal to
6011 * 4 bytes/component * 4 components/input * 3 points.
6012 *
6013 * Other stages don't know the size at compile time or don't
6014 * allocate LDS per wave, but instead they do it per thread group.
6015 */
6016 lds_per_wave = conf->lds_size * lds_increment +
6017 align(num_inputs * 48, lds_increment);
6018 }
6019
6020 /* Compute the per-SIMD wave counts. */
6021 if (conf->num_sgprs) {
6022 if (sscreen->b.chip_class >= VI)
6023 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
6024 else
6025 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
6026 }
6027
6028 if (conf->num_vgprs)
6029 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
6030
6031 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
6032 * that PS can use.
6033 */
6034 if (lds_per_wave)
6035 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
6036
6037 if (file != stderr ||
6038 r600_can_dump_shader(&sscreen->b, processor)) {
6039 if (processor == PIPE_SHADER_FRAGMENT) {
6040 fprintf(file, "*** SHADER CONFIG ***\n"
6041 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6042 "SPI_PS_INPUT_ENA = 0x%04x\n",
6043 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
6044 }
6045
6046 fprintf(file, "*** SHADER STATS ***\n"
6047 "SGPRS: %d\n"
6048 "VGPRS: %d\n"
6049 "Code Size: %d bytes\n"
6050 "LDS: %d blocks\n"
6051 "Scratch: %d bytes per wave\n"
6052 "Max Waves: %d\n"
6053 "********************\n",
6054 conf->num_sgprs, conf->num_vgprs, code_size,
6055 conf->lds_size, conf->scratch_bytes_per_wave,
6056 max_simd_waves);
6057 }
6058
6059 pipe_debug_message(debug, SHADER_INFO,
6060 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6061 "LDS: %d Scratch: %d Max Waves: %d",
6062 conf->num_sgprs, conf->num_vgprs, code_size,
6063 conf->lds_size, conf->scratch_bytes_per_wave,
6064 max_simd_waves);
6065 }
6066
6067 static const char *si_get_shader_name(struct si_shader *shader,
6068 unsigned processor)
6069 {
6070 switch (processor) {
6071 case PIPE_SHADER_VERTEX:
6072 if (shader->key.vs.as_es)
6073 return "Vertex Shader as ES";
6074 else if (shader->key.vs.as_ls)
6075 return "Vertex Shader as LS";
6076 else
6077 return "Vertex Shader as VS";
6078 case PIPE_SHADER_TESS_CTRL:
6079 return "Tessellation Control Shader";
6080 case PIPE_SHADER_TESS_EVAL:
6081 if (shader->key.tes.as_es)
6082 return "Tessellation Evaluation Shader as ES";
6083 else
6084 return "Tessellation Evaluation Shader as VS";
6085 case PIPE_SHADER_GEOMETRY:
6086 if (shader->gs_copy_shader == NULL)
6087 return "GS Copy Shader as VS";
6088 else
6089 return "Geometry Shader";
6090 case PIPE_SHADER_FRAGMENT:
6091 return "Pixel Shader";
6092 case PIPE_SHADER_COMPUTE:
6093 return "Compute Shader";
6094 default:
6095 return "Unknown Shader";
6096 }
6097 }
6098
6099 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6100 struct pipe_debug_callback *debug, unsigned processor,
6101 FILE *file)
6102 {
6103 if (file != stderr ||
6104 (r600_can_dump_shader(&sscreen->b, processor) &&
6105 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6106 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6107
6108 if (shader->prolog)
6109 si_shader_dump_disassembly(&shader->prolog->binary,
6110 debug, "prolog", file);
6111
6112 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6113
6114 if (shader->epilog)
6115 si_shader_dump_disassembly(&shader->epilog->binary,
6116 debug, "epilog", file);
6117 fprintf(file, "\n");
6118 }
6119
6120 si_shader_dump_stats(sscreen, &shader->config,
6121 shader->selector ? shader->selector->info.num_inputs : 0,
6122 si_get_shader_binary_size(shader), debug, processor,
6123 file);
6124 }
6125
6126 int si_compile_llvm(struct si_screen *sscreen,
6127 struct radeon_shader_binary *binary,
6128 struct si_shader_config *conf,
6129 LLVMTargetMachineRef tm,
6130 LLVMModuleRef mod,
6131 struct pipe_debug_callback *debug,
6132 unsigned processor,
6133 const char *name)
6134 {
6135 int r = 0;
6136 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6137
6138 if (r600_can_dump_shader(&sscreen->b, processor)) {
6139 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6140
6141 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6142 fprintf(stderr, "%s LLVM IR:\n\n", name);
6143 LLVMDumpModule(mod);
6144 fprintf(stderr, "\n");
6145 }
6146 }
6147
6148 if (!si_replace_shader(count, binary)) {
6149 r = radeon_llvm_compile(mod, binary,
6150 r600_get_llvm_processor_name(sscreen->b.family), tm,
6151 debug);
6152 if (r)
6153 return r;
6154 }
6155
6156 si_shader_binary_read_config(binary, conf, 0);
6157
6158 /* Enable 64-bit and 16-bit denormals, because there is no performance
6159 * cost.
6160 *
6161 * If denormals are enabled, all floating-point output modifiers are
6162 * ignored.
6163 *
6164 * Don't enable denormals for 32-bit floats, because:
6165 * - Floating-point output modifiers would be ignored by the hw.
6166 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6167 * have to stop using those.
6168 * - SI & CI would be very slow.
6169 */
6170 conf->float_mode |= V_00B028_FP_64_DENORMS;
6171
6172 FREE(binary->config);
6173 FREE(binary->global_symbol_offsets);
6174 binary->config = NULL;
6175 binary->global_symbol_offsets = NULL;
6176
6177 /* Some shaders can't have rodata because their binaries can be
6178 * concatenated.
6179 */
6180 if (binary->rodata_size &&
6181 (processor == PIPE_SHADER_VERTEX ||
6182 processor == PIPE_SHADER_TESS_CTRL ||
6183 processor == PIPE_SHADER_TESS_EVAL ||
6184 processor == PIPE_SHADER_FRAGMENT)) {
6185 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6186 return -EINVAL;
6187 }
6188
6189 return r;
6190 }
6191
6192 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6193 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
6194 struct si_shader_context *ctx,
6195 struct si_shader *gs,
6196 struct pipe_debug_callback *debug)
6197 {
6198 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
6199 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
6200 struct lp_build_context *uint = &bld_base->uint_bld;
6201 struct si_shader_output_values *outputs;
6202 struct tgsi_shader_info *gsinfo = &gs->selector->info;
6203 LLVMValueRef args[9];
6204 int i, r;
6205
6206 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6207
6208 si_init_shader_ctx(ctx, sscreen, ctx->shader, ctx->tm);
6209 ctx->type = PIPE_SHADER_VERTEX;
6210 ctx->is_gs_copy_shader = true;
6211
6212 create_meta_data(ctx);
6213 create_function(ctx);
6214 preload_streamout_buffers(ctx);
6215 preload_ring_buffers(ctx);
6216
6217 args[0] = ctx->gsvs_ring[0];
6218 args[1] = lp_build_mul_imm(uint,
6219 LLVMGetParam(ctx->radeon_bld.main_fn,
6220 ctx->param_vertex_id),
6221 4);
6222 args[3] = uint->zero;
6223 args[4] = uint->one; /* OFFEN */
6224 args[5] = uint->zero; /* IDXEN */
6225 args[6] = uint->one; /* GLC */
6226 args[7] = uint->one; /* SLC */
6227 args[8] = uint->zero; /* TFE */
6228
6229 /* Fetch vertex data from GSVS ring */
6230 for (i = 0; i < gsinfo->num_outputs; ++i) {
6231 unsigned chan;
6232
6233 outputs[i].name = gsinfo->output_semantic_name[i];
6234 outputs[i].sid = gsinfo->output_semantic_index[i];
6235
6236 for (chan = 0; chan < 4; chan++) {
6237 args[2] = lp_build_const_int32(gallivm,
6238 (i * 4 + chan) *
6239 gs->selector->gs_max_out_vertices * 16 * 4);
6240
6241 outputs[i].values[chan] =
6242 LLVMBuildBitCast(gallivm->builder,
6243 lp_build_intrinsic(gallivm->builder,
6244 "llvm.SI.buffer.load.dword.i32.i32",
6245 ctx->i32, args, 9,
6246 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
6247 ctx->f32, "");
6248 }
6249 }
6250
6251 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6252
6253 LLVMBuildRet(gallivm->builder, ctx->return_value);
6254
6255 /* Dump LLVM IR before any optimization passes */
6256 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6257 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6258 LLVMDumpModule(bld_base->base.gallivm->module);
6259
6260 radeon_llvm_finalize_module(&ctx->radeon_bld);
6261
6262 r = si_compile_llvm(sscreen, &ctx->shader->binary,
6263 &ctx->shader->config, ctx->tm,
6264 bld_base->base.gallivm->module,
6265 debug, PIPE_SHADER_GEOMETRY,
6266 "GS Copy Shader");
6267 if (!r) {
6268 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6269 fprintf(stderr, "GS Copy Shader:\n");
6270 si_shader_dump(sscreen, ctx->shader, debug,
6271 PIPE_SHADER_GEOMETRY, stderr);
6272 r = si_shader_binary_upload(sscreen, ctx->shader);
6273 }
6274
6275 radeon_llvm_dispose(&ctx->radeon_bld);
6276
6277 FREE(outputs);
6278 return r;
6279 }
6280
6281 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
6282 {
6283 int i;
6284
6285 fprintf(f, "SHADER KEY\n");
6286
6287 switch (shader) {
6288 case PIPE_SHADER_VERTEX:
6289 fprintf(f, " instance_divisors = {");
6290 for (i = 0; i < ARRAY_SIZE(key->vs.prolog.instance_divisors); i++)
6291 fprintf(f, !i ? "%u" : ", %u",
6292 key->vs.prolog.instance_divisors[i]);
6293 fprintf(f, "}\n");
6294 fprintf(f, " as_es = %u\n", key->vs.as_es);
6295 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
6296 fprintf(f, " export_prim_id = %u\n", key->vs.epilog.export_prim_id);
6297 break;
6298
6299 case PIPE_SHADER_TESS_CTRL:
6300 fprintf(f, " prim_mode = %u\n", key->tcs.epilog.prim_mode);
6301 break;
6302
6303 case PIPE_SHADER_TESS_EVAL:
6304 fprintf(f, " as_es = %u\n", key->tes.as_es);
6305 fprintf(f, " export_prim_id = %u\n", key->tes.epilog.export_prim_id);
6306 break;
6307
6308 case PIPE_SHADER_GEOMETRY:
6309 case PIPE_SHADER_COMPUTE:
6310 break;
6311
6312 case PIPE_SHADER_FRAGMENT:
6313 fprintf(f, " prolog.color_two_side = %u\n", key->ps.prolog.color_two_side);
6314 fprintf(f, " prolog.poly_stipple = %u\n", key->ps.prolog.poly_stipple);
6315 fprintf(f, " prolog.force_persample_interp = %u\n", key->ps.prolog.force_persample_interp);
6316 fprintf(f, " epilog.spi_shader_col_format = 0x%x\n", key->ps.epilog.spi_shader_col_format);
6317 fprintf(f, " epilog.color_is_int8 = 0x%X\n", key->ps.epilog.color_is_int8);
6318 fprintf(f, " epilog.last_cbuf = %u\n", key->ps.epilog.last_cbuf);
6319 fprintf(f, " epilog.alpha_func = %u\n", key->ps.epilog.alpha_func);
6320 fprintf(f, " epilog.alpha_to_one = %u\n", key->ps.epilog.alpha_to_one);
6321 fprintf(f, " epilog.poly_line_smoothing = %u\n", key->ps.epilog.poly_line_smoothing);
6322 fprintf(f, " epilog.clamp_color = %u\n", key->ps.epilog.clamp_color);
6323 break;
6324
6325 default:
6326 assert(0);
6327 }
6328 }
6329
6330 static void si_init_shader_ctx(struct si_shader_context *ctx,
6331 struct si_screen *sscreen,
6332 struct si_shader *shader,
6333 LLVMTargetMachineRef tm)
6334 {
6335 struct lp_build_tgsi_context *bld_base;
6336 struct lp_build_tgsi_action tmpl = {};
6337
6338 memset(ctx, 0, sizeof(*ctx));
6339 radeon_llvm_context_init(&ctx->radeon_bld, "amdgcn--");
6340 ctx->tm = tm;
6341 ctx->screen = sscreen;
6342 if (shader && shader->selector)
6343 ctx->type = shader->selector->info.processor;
6344 else
6345 ctx->type = -1;
6346 ctx->shader = shader;
6347
6348 ctx->voidt = LLVMVoidTypeInContext(ctx->radeon_bld.gallivm.context);
6349 ctx->i1 = LLVMInt1TypeInContext(ctx->radeon_bld.gallivm.context);
6350 ctx->i8 = LLVMInt8TypeInContext(ctx->radeon_bld.gallivm.context);
6351 ctx->i32 = LLVMInt32TypeInContext(ctx->radeon_bld.gallivm.context);
6352 ctx->i64 = LLVMInt64TypeInContext(ctx->radeon_bld.gallivm.context);
6353 ctx->i128 = LLVMIntTypeInContext(ctx->radeon_bld.gallivm.context, 128);
6354 ctx->f32 = LLVMFloatTypeInContext(ctx->radeon_bld.gallivm.context);
6355 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
6356 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
6357 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
6358 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
6359 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
6360
6361 bld_base = &ctx->radeon_bld.soa.bld_base;
6362 if (shader && shader->selector)
6363 bld_base->info = &shader->selector->info;
6364 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6365
6366 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6367 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6368 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6369
6370 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6371 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6372 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6373 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6374 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6375 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6376 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6377 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6378 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6379 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6380 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6381 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6382 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6383 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6384
6385 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6386 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6387 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6388 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6389 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6390 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6391
6392 tmpl.fetch_args = atomic_fetch_args;
6393 tmpl.emit = atomic_emit;
6394 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6395 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6396 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6397 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6398 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6399 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6400 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6401 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6402 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6403 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6404 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6405 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6406 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6407 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6408 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6409 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6410 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6411 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6412 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6413 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6414
6415 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6416
6417 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6418 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6419 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6420 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6421
6422 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6423 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6424 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6425
6426 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
6427 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
6428 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
6429 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
6430 }
6431
6432 int si_compile_tgsi_shader(struct si_screen *sscreen,
6433 LLVMTargetMachineRef tm,
6434 struct si_shader *shader,
6435 bool is_monolithic,
6436 struct pipe_debug_callback *debug)
6437 {
6438 struct si_shader_selector *sel = shader->selector;
6439 struct si_shader_context ctx;
6440 struct lp_build_tgsi_context *bld_base;
6441 LLVMModuleRef mod;
6442 int r = 0;
6443
6444 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6445 * conversion fails. */
6446 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
6447 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
6448 si_dump_shader_key(sel->type, &shader->key, stderr);
6449 tgsi_dump(sel->tokens, 0);
6450 si_dump_streamout(&sel->so);
6451 }
6452
6453 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6454 ctx.is_monolithic = is_monolithic;
6455
6456 shader->info.uses_instanceid = sel->info.uses_instanceid;
6457
6458 bld_base = &ctx.radeon_bld.soa.bld_base;
6459 ctx.radeon_bld.load_system_value = declare_system_value;
6460
6461 switch (ctx.type) {
6462 case PIPE_SHADER_VERTEX:
6463 ctx.radeon_bld.load_input = declare_input_vs;
6464 if (shader->key.vs.as_ls)
6465 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6466 else if (shader->key.vs.as_es)
6467 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6468 else
6469 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6470 break;
6471 case PIPE_SHADER_TESS_CTRL:
6472 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6473 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6474 bld_base->emit_store = store_output_tcs;
6475 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6476 break;
6477 case PIPE_SHADER_TESS_EVAL:
6478 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6479 if (shader->key.tes.as_es)
6480 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6481 else
6482 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6483 break;
6484 case PIPE_SHADER_GEOMETRY:
6485 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6486 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6487 break;
6488 case PIPE_SHADER_FRAGMENT:
6489 ctx.radeon_bld.load_input = declare_input_fs;
6490 if (is_monolithic)
6491 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
6492 else
6493 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6494 break;
6495 case PIPE_SHADER_COMPUTE:
6496 ctx.radeon_bld.declare_memory_region = declare_compute_memory;
6497 break;
6498 default:
6499 assert(!"Unsupported shader type");
6500 return -1;
6501 }
6502
6503 create_meta_data(&ctx);
6504 create_function(&ctx);
6505 preload_constants(&ctx);
6506 preload_shader_buffers(&ctx);
6507 preload_samplers(&ctx);
6508 preload_images(&ctx);
6509 preload_streamout_buffers(&ctx);
6510 preload_ring_buffers(&ctx);
6511
6512 if (ctx.is_monolithic && sel->type == PIPE_SHADER_FRAGMENT &&
6513 shader->key.ps.prolog.poly_stipple) {
6514 LLVMValueRef list = LLVMGetParam(ctx.radeon_bld.main_fn,
6515 SI_PARAM_RW_BUFFERS);
6516 si_llvm_emit_polygon_stipple(&ctx, list,
6517 SI_PARAM_POS_FIXED_PT);
6518 }
6519
6520 if (ctx.type == PIPE_SHADER_GEOMETRY) {
6521 int i;
6522 for (i = 0; i < 4; i++) {
6523 ctx.gs_next_vertex[i] =
6524 lp_build_alloca(bld_base->base.gallivm,
6525 ctx.i32, "");
6526 }
6527 }
6528
6529 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6530 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6531 goto out;
6532 }
6533
6534 LLVMBuildRet(bld_base->base.gallivm->builder, ctx.return_value);
6535 mod = bld_base->base.gallivm->module;
6536
6537 /* Dump LLVM IR before any optimization passes */
6538 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6539 r600_can_dump_shader(&sscreen->b, ctx.type))
6540 LLVMDumpModule(mod);
6541
6542 radeon_llvm_finalize_module(&ctx.radeon_bld);
6543
6544 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6545 mod, debug, ctx.type, "TGSI shader");
6546 if (r) {
6547 fprintf(stderr, "LLVM failed to compile shader\n");
6548 goto out;
6549 }
6550
6551 radeon_llvm_dispose(&ctx.radeon_bld);
6552
6553 /* Add the scratch offset to input SGPRs. */
6554 if (shader->config.scratch_bytes_per_wave)
6555 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6556
6557 /* Calculate the number of fragment input VGPRs. */
6558 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6559 shader->info.num_input_vgprs = 0;
6560 shader->info.face_vgpr_index = -1;
6561
6562 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6563 shader->info.num_input_vgprs += 2;
6564 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6565 shader->info.num_input_vgprs += 2;
6566 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6567 shader->info.num_input_vgprs += 2;
6568 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6569 shader->info.num_input_vgprs += 3;
6570 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6571 shader->info.num_input_vgprs += 2;
6572 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6573 shader->info.num_input_vgprs += 2;
6574 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6575 shader->info.num_input_vgprs += 2;
6576 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6577 shader->info.num_input_vgprs += 1;
6578 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6579 shader->info.num_input_vgprs += 1;
6580 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6581 shader->info.num_input_vgprs += 1;
6582 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6583 shader->info.num_input_vgprs += 1;
6584 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6585 shader->info.num_input_vgprs += 1;
6586 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6587 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6588 shader->info.num_input_vgprs += 1;
6589 }
6590 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
6591 shader->info.num_input_vgprs += 1;
6592 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6593 shader->info.num_input_vgprs += 1;
6594 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6595 shader->info.num_input_vgprs += 1;
6596 }
6597
6598 if (ctx.type == PIPE_SHADER_GEOMETRY) {
6599 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
6600 shader->gs_copy_shader->selector = shader->selector;
6601 ctx.shader = shader->gs_copy_shader;
6602 if ((r = si_generate_gs_copy_shader(sscreen, &ctx,
6603 shader, debug))) {
6604 free(shader->gs_copy_shader);
6605 shader->gs_copy_shader = NULL;
6606 goto out;
6607 }
6608 }
6609
6610 out:
6611 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
6612 FREE(ctx.constants[i]);
6613 return r;
6614 }
6615
6616 /**
6617 * Create, compile and return a shader part (prolog or epilog).
6618 *
6619 * \param sscreen screen
6620 * \param list list of shader parts of the same category
6621 * \param key shader part key
6622 * \param tm LLVM target machine
6623 * \param debug debug callback
6624 * \param compile the callback responsible for compilation
6625 * \return non-NULL on success
6626 */
6627 static struct si_shader_part *
6628 si_get_shader_part(struct si_screen *sscreen,
6629 struct si_shader_part **list,
6630 union si_shader_part_key *key,
6631 LLVMTargetMachineRef tm,
6632 struct pipe_debug_callback *debug,
6633 bool (*compile)(struct si_screen *,
6634 LLVMTargetMachineRef,
6635 struct pipe_debug_callback *,
6636 struct si_shader_part *))
6637 {
6638 struct si_shader_part *result;
6639
6640 pipe_mutex_lock(sscreen->shader_parts_mutex);
6641
6642 /* Find existing. */
6643 for (result = *list; result; result = result->next) {
6644 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6645 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6646 return result;
6647 }
6648 }
6649
6650 /* Compile a new one. */
6651 result = CALLOC_STRUCT(si_shader_part);
6652 result->key = *key;
6653 if (!compile(sscreen, tm, debug, result)) {
6654 FREE(result);
6655 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6656 return NULL;
6657 }
6658
6659 result->next = *list;
6660 *list = result;
6661 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6662 return result;
6663 }
6664
6665 /**
6666 * Create a vertex shader prolog.
6667 *
6668 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6669 * All inputs are returned unmodified. The vertex load indices are
6670 * stored after them, which will used by the API VS for fetching inputs.
6671 *
6672 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6673 * input_v0,
6674 * input_v1,
6675 * input_v2,
6676 * input_v3,
6677 * (VertexID + BaseVertex),
6678 * (InstanceID + StartInstance),
6679 * (InstanceID / 2 + StartInstance)
6680 */
6681 static bool si_compile_vs_prolog(struct si_screen *sscreen,
6682 LLVMTargetMachineRef tm,
6683 struct pipe_debug_callback *debug,
6684 struct si_shader_part *out)
6685 {
6686 union si_shader_part_key *key = &out->key;
6687 struct si_shader shader = {};
6688 struct si_shader_context ctx;
6689 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6690 LLVMTypeRef *params, *returns;
6691 LLVMValueRef ret, func;
6692 int last_sgpr, num_params, num_returns, i;
6693 bool status = true;
6694
6695 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
6696 ctx.type = PIPE_SHADER_VERTEX;
6697 ctx.param_vertex_id = key->vs_prolog.num_input_sgprs;
6698 ctx.param_instance_id = key->vs_prolog.num_input_sgprs + 3;
6699
6700 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6701 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
6702 sizeof(LLVMTypeRef));
6703 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
6704 key->vs_prolog.last_input + 1) *
6705 sizeof(LLVMTypeRef));
6706 num_params = 0;
6707 num_returns = 0;
6708
6709 /* Declare input and output SGPRs. */
6710 num_params = 0;
6711 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6712 params[num_params++] = ctx.i32;
6713 returns[num_returns++] = ctx.i32;
6714 }
6715 last_sgpr = num_params - 1;
6716
6717 /* 4 preloaded VGPRs (outputs must be floats) */
6718 for (i = 0; i < 4; i++) {
6719 params[num_params++] = ctx.i32;
6720 returns[num_returns++] = ctx.f32;
6721 }
6722
6723 /* Vertex load indices. */
6724 for (i = 0; i <= key->vs_prolog.last_input; i++)
6725 returns[num_returns++] = ctx.f32;
6726
6727 /* Create the function. */
6728 si_create_function(&ctx, returns, num_returns, params,
6729 num_params, -1, last_sgpr);
6730 func = ctx.radeon_bld.main_fn;
6731
6732 /* Copy inputs to outputs. This should be no-op, as the registers match,
6733 * but it will prevent the compiler from overwriting them unintentionally.
6734 */
6735 ret = ctx.return_value;
6736 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6737 LLVMValueRef p = LLVMGetParam(func, i);
6738 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6739 }
6740 for (i = num_params - 4; i < num_params; i++) {
6741 LLVMValueRef p = LLVMGetParam(func, i);
6742 p = LLVMBuildBitCast(gallivm->builder, p, ctx.f32, "");
6743 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6744 }
6745
6746 /* Compute vertex load indices from instance divisors. */
6747 for (i = 0; i <= key->vs_prolog.last_input; i++) {
6748 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
6749 LLVMValueRef index;
6750
6751 if (divisor) {
6752 /* InstanceID / Divisor + StartInstance */
6753 index = get_instance_index_for_fetch(&ctx.radeon_bld,
6754 SI_SGPR_START_INSTANCE,
6755 divisor);
6756 } else {
6757 /* VertexID + BaseVertex */
6758 index = LLVMBuildAdd(gallivm->builder,
6759 LLVMGetParam(func, ctx.param_vertex_id),
6760 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
6761 }
6762
6763 index = LLVMBuildBitCast(gallivm->builder, index, ctx.f32, "");
6764 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
6765 num_params++, "");
6766 }
6767
6768 /* Compile. */
6769 LLVMBuildRet(gallivm->builder, ret);
6770 radeon_llvm_finalize_module(&ctx.radeon_bld);
6771
6772 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6773 gallivm->module, debug, ctx.type,
6774 "Vertex Shader Prolog"))
6775 status = false;
6776
6777 radeon_llvm_dispose(&ctx.radeon_bld);
6778 return status;
6779 }
6780
6781 /**
6782 * Compile the vertex shader epilog. This is also used by the tessellation
6783 * evaluation shader compiled as VS.
6784 *
6785 * The input is PrimitiveID.
6786 *
6787 * If PrimitiveID is required by the pixel shader, export it.
6788 * Otherwise, do nothing.
6789 */
6790 static bool si_compile_vs_epilog(struct si_screen *sscreen,
6791 LLVMTargetMachineRef tm,
6792 struct pipe_debug_callback *debug,
6793 struct si_shader_part *out)
6794 {
6795 union si_shader_part_key *key = &out->key;
6796 struct si_shader_context ctx;
6797 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6798 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
6799 LLVMTypeRef params[5];
6800 int num_params, i;
6801 bool status = true;
6802
6803 si_init_shader_ctx(&ctx, sscreen, NULL, tm);
6804 ctx.type = PIPE_SHADER_VERTEX;
6805
6806 /* Declare input VGPRs. */
6807 num_params = key->vs_epilog.states.export_prim_id ?
6808 (VS_EPILOG_PRIMID_LOC + 1) : 0;
6809 assert(num_params <= ARRAY_SIZE(params));
6810
6811 for (i = 0; i < num_params; i++)
6812 params[i] = ctx.f32;
6813
6814 /* Create the function. */
6815 si_create_function(&ctx, NULL, 0, params, num_params,
6816 -1, -1);
6817
6818 /* Emit exports. */
6819 if (key->vs_epilog.states.export_prim_id) {
6820 struct lp_build_context *base = &bld_base->base;
6821 struct lp_build_context *uint = &bld_base->uint_bld;
6822 LLVMValueRef args[9];
6823
6824 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
6825 args[1] = uint->zero; /* whether the EXEC mask is valid */
6826 args[2] = uint->zero; /* DONE bit */
6827 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
6828 key->vs_epilog.prim_id_param_offset);
6829 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
6830 args[5] = LLVMGetParam(ctx.radeon_bld.main_fn,
6831 VS_EPILOG_PRIMID_LOC); /* X */
6832 args[6] = uint->undef; /* Y */
6833 args[7] = uint->undef; /* Z */
6834 args[8] = uint->undef; /* W */
6835
6836 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
6837 LLVMVoidTypeInContext(base->gallivm->context),
6838 args, 9, 0);
6839 }
6840
6841 /* Compile. */
6842 LLVMBuildRet(gallivm->builder, ctx.return_value);
6843 radeon_llvm_finalize_module(&ctx.radeon_bld);
6844
6845 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6846 gallivm->module, debug, ctx.type,
6847 "Vertex Shader Epilog"))
6848 status = false;
6849
6850 radeon_llvm_dispose(&ctx.radeon_bld);
6851 return status;
6852 }
6853
6854 /**
6855 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
6856 */
6857 static bool si_get_vs_epilog(struct si_screen *sscreen,
6858 LLVMTargetMachineRef tm,
6859 struct si_shader *shader,
6860 struct pipe_debug_callback *debug,
6861 struct si_vs_epilog_bits *states)
6862 {
6863 union si_shader_part_key epilog_key;
6864
6865 memset(&epilog_key, 0, sizeof(epilog_key));
6866 epilog_key.vs_epilog.states = *states;
6867
6868 /* Set up the PrimitiveID output. */
6869 if (shader->key.vs.epilog.export_prim_id) {
6870 unsigned index = shader->selector->info.num_outputs;
6871 unsigned offset = shader->info.nr_param_exports++;
6872
6873 epilog_key.vs_epilog.prim_id_param_offset = offset;
6874 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
6875 shader->info.vs_output_param_offset[index] = offset;
6876 }
6877
6878 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
6879 &epilog_key, tm, debug,
6880 si_compile_vs_epilog);
6881 return shader->epilog != NULL;
6882 }
6883
6884 /**
6885 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
6886 */
6887 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
6888 LLVMTargetMachineRef tm,
6889 struct si_shader *shader,
6890 struct pipe_debug_callback *debug)
6891 {
6892 struct tgsi_shader_info *info = &shader->selector->info;
6893 union si_shader_part_key prolog_key;
6894 unsigned i;
6895
6896 /* Get the prolog. */
6897 memset(&prolog_key, 0, sizeof(prolog_key));
6898 prolog_key.vs_prolog.states = shader->key.vs.prolog;
6899 prolog_key.vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6900 prolog_key.vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6901
6902 /* The prolog is a no-op if there are no inputs. */
6903 if (info->num_inputs) {
6904 shader->prolog =
6905 si_get_shader_part(sscreen, &sscreen->vs_prologs,
6906 &prolog_key, tm, debug,
6907 si_compile_vs_prolog);
6908 if (!shader->prolog)
6909 return false;
6910 }
6911
6912 /* Get the epilog. */
6913 if (!shader->key.vs.as_es && !shader->key.vs.as_ls &&
6914 !si_get_vs_epilog(sscreen, tm, shader, debug,
6915 &shader->key.vs.epilog))
6916 return false;
6917
6918 /* Set the instanceID flag. */
6919 for (i = 0; i < info->num_inputs; i++)
6920 if (prolog_key.vs_prolog.states.instance_divisors[i])
6921 shader->info.uses_instanceid = true;
6922
6923 return true;
6924 }
6925
6926 /**
6927 * Select and compile (or reuse) TES parts (epilog).
6928 */
6929 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
6930 LLVMTargetMachineRef tm,
6931 struct si_shader *shader,
6932 struct pipe_debug_callback *debug)
6933 {
6934 if (shader->key.tes.as_es)
6935 return true;
6936
6937 /* TES compiled as VS. */
6938 return si_get_vs_epilog(sscreen, tm, shader, debug,
6939 &shader->key.tes.epilog);
6940 }
6941
6942 /**
6943 * Compile the TCS epilog. This writes tesselation factors to memory based on
6944 * the output primitive type of the tesselator (determined by TES).
6945 */
6946 static bool si_compile_tcs_epilog(struct si_screen *sscreen,
6947 LLVMTargetMachineRef tm,
6948 struct pipe_debug_callback *debug,
6949 struct si_shader_part *out)
6950 {
6951 union si_shader_part_key *key = &out->key;
6952 struct si_shader shader = {};
6953 struct si_shader_context ctx;
6954 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6955 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
6956 LLVMTypeRef params[16];
6957 LLVMValueRef func;
6958 int last_array_pointer, last_sgpr, num_params;
6959 bool status = true;
6960
6961 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
6962 ctx.type = PIPE_SHADER_TESS_CTRL;
6963 shader.key.tcs.epilog = key->tcs_epilog.states;
6964
6965 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
6966 params[SI_PARAM_RW_BUFFERS] = const_array(ctx.v16i8, SI_NUM_RW_BUFFERS);
6967 last_array_pointer = SI_PARAM_RW_BUFFERS;
6968 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
6969 params[SI_PARAM_SAMPLERS] = ctx.i64;
6970 params[SI_PARAM_IMAGES] = ctx.i64;
6971 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
6972 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx.i32;
6973 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx.i32;
6974 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx.i32;
6975 params[SI_PARAM_TCS_IN_LAYOUT] = ctx.i32;
6976 params[ctx.param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx.i32;
6977 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx.i32;
6978 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
6979 num_params = last_sgpr + 1;
6980
6981 params[num_params++] = ctx.i32; /* patch index within the wave (REL_PATCH_ID) */
6982 params[num_params++] = ctx.i32; /* invocation ID within the patch */
6983 params[num_params++] = ctx.i32; /* LDS offset where tess factors should be loaded from */
6984
6985 /* Create the function. */
6986 si_create_function(&ctx, NULL, 0, params, num_params,
6987 last_array_pointer, last_sgpr);
6988 declare_tess_lds(&ctx);
6989 func = ctx.radeon_bld.main_fn;
6990
6991 si_write_tess_factors(bld_base,
6992 LLVMGetParam(func, last_sgpr + 1),
6993 LLVMGetParam(func, last_sgpr + 2),
6994 LLVMGetParam(func, last_sgpr + 3));
6995
6996 /* Compile. */
6997 LLVMBuildRet(gallivm->builder, ctx.return_value);
6998 radeon_llvm_finalize_module(&ctx.radeon_bld);
6999
7000 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7001 gallivm->module, debug, ctx.type,
7002 "Tessellation Control Shader Epilog"))
7003 status = false;
7004
7005 radeon_llvm_dispose(&ctx.radeon_bld);
7006 return status;
7007 }
7008
7009 /**
7010 * Select and compile (or reuse) TCS parts (epilog).
7011 */
7012 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7013 LLVMTargetMachineRef tm,
7014 struct si_shader *shader,
7015 struct pipe_debug_callback *debug)
7016 {
7017 union si_shader_part_key epilog_key;
7018
7019 /* Get the epilog. */
7020 memset(&epilog_key, 0, sizeof(epilog_key));
7021 epilog_key.tcs_epilog.states = shader->key.tcs.epilog;
7022
7023 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7024 &epilog_key, tm, debug,
7025 si_compile_tcs_epilog);
7026 return shader->epilog != NULL;
7027 }
7028
7029 /**
7030 * Compile the pixel shader prolog. This handles:
7031 * - two-side color selection and interpolation
7032 * - overriding interpolation parameters for the API PS
7033 * - polygon stippling
7034 *
7035 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7036 * overriden by other states. (e.g. per-sample interpolation)
7037 * Interpolated colors are stored after the preloaded VGPRs.
7038 */
7039 static bool si_compile_ps_prolog(struct si_screen *sscreen,
7040 LLVMTargetMachineRef tm,
7041 struct pipe_debug_callback *debug,
7042 struct si_shader_part *out)
7043 {
7044 union si_shader_part_key *key = &out->key;
7045 struct si_shader shader = {};
7046 struct si_shader_context ctx;
7047 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7048 LLVMTypeRef *params;
7049 LLVMValueRef ret, func;
7050 int last_sgpr, num_params, num_returns, i, num_color_channels;
7051 bool status = true;
7052
7053 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7054 ctx.type = PIPE_SHADER_FRAGMENT;
7055 shader.key.ps.prolog = key->ps_prolog.states;
7056
7057 /* Number of inputs + 8 color elements. */
7058 params = alloca((key->ps_prolog.num_input_sgprs +
7059 key->ps_prolog.num_input_vgprs + 8) *
7060 sizeof(LLVMTypeRef));
7061
7062 /* Declare inputs. */
7063 num_params = 0;
7064 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7065 params[num_params++] = ctx.i32;
7066 last_sgpr = num_params - 1;
7067
7068 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7069 params[num_params++] = ctx.f32;
7070
7071 /* Declare outputs (same as inputs + add colors if needed) */
7072 num_returns = num_params;
7073 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7074 for (i = 0; i < num_color_channels; i++)
7075 params[num_returns++] = ctx.f32;
7076
7077 /* Create the function. */
7078 si_create_function(&ctx, params, num_returns, params,
7079 num_params, -1, last_sgpr);
7080 func = ctx.radeon_bld.main_fn;
7081
7082 /* Copy inputs to outputs. This should be no-op, as the registers match,
7083 * but it will prevent the compiler from overwriting them unintentionally.
7084 */
7085 ret = ctx.return_value;
7086 for (i = 0; i < num_params; i++) {
7087 LLVMValueRef p = LLVMGetParam(func, i);
7088 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7089 }
7090
7091 /* Polygon stippling. */
7092 if (key->ps_prolog.states.poly_stipple) {
7093 /* POS_FIXED_PT is always last. */
7094 unsigned pos = key->ps_prolog.num_input_sgprs +
7095 key->ps_prolog.num_input_vgprs - 1;
7096 LLVMValueRef ptr[2], list;
7097
7098 /* Get the pointer to rw buffers. */
7099 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
7100 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
7101 list = lp_build_gather_values(gallivm, ptr, 2);
7102 list = LLVMBuildBitCast(gallivm->builder, list, ctx.i64, "");
7103 list = LLVMBuildIntToPtr(gallivm->builder, list,
7104 const_array(ctx.v16i8, SI_NUM_RW_BUFFERS), "");
7105
7106 si_llvm_emit_polygon_stipple(&ctx, list, pos);
7107 }
7108
7109 /* Interpolate colors. */
7110 for (i = 0; i < 2; i++) {
7111 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7112 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7113 key->ps_prolog.face_vgpr_index;
7114 LLVMValueRef interp[2], color[4];
7115 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7116
7117 if (!writemask)
7118 continue;
7119
7120 /* If the interpolation qualifier is not CONSTANT (-1). */
7121 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7122 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7123 key->ps_prolog.color_interp_vgpr_index[i];
7124
7125 interp[0] = LLVMGetParam(func, interp_vgpr);
7126 interp[1] = LLVMGetParam(func, interp_vgpr + 1);
7127 interp_ij = lp_build_gather_values(gallivm, interp, 2);
7128 interp_ij = LLVMBuildBitCast(gallivm->builder, interp_ij,
7129 ctx.v2i32, "");
7130 }
7131
7132 /* Use the absolute location of the input. */
7133 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7134
7135 if (key->ps_prolog.states.color_two_side) {
7136 face = LLVMGetParam(func, face_vgpr);
7137 face = LLVMBuildBitCast(gallivm->builder, face, ctx.i32, "");
7138 }
7139
7140 interp_fs_input(&ctx,
7141 key->ps_prolog.color_attr_index[i],
7142 TGSI_SEMANTIC_COLOR, i,
7143 key->ps_prolog.num_interp_inputs,
7144 key->ps_prolog.colors_read, interp_ij,
7145 prim_mask, face, color);
7146
7147 while (writemask) {
7148 unsigned chan = u_bit_scan(&writemask);
7149 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
7150 num_params++, "");
7151 }
7152 }
7153
7154 /* Force per-sample interpolation. */
7155 if (key->ps_prolog.states.force_persample_interp) {
7156 unsigned i, base = key->ps_prolog.num_input_sgprs;
7157 LLVMValueRef persp_sample[2], linear_sample[2];
7158
7159 /* Read PERSP_SAMPLE. */
7160 for (i = 0; i < 2; i++)
7161 persp_sample[i] = LLVMGetParam(func, base + i);
7162 /* Overwrite PERSP_CENTER. */
7163 for (i = 0; i < 2; i++)
7164 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7165 persp_sample[i], base + 2 + i, "");
7166 /* Overwrite PERSP_CENTROID. */
7167 for (i = 0; i < 2; i++)
7168 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7169 persp_sample[i], base + 4 + i, "");
7170 /* Read LINEAR_SAMPLE. */
7171 for (i = 0; i < 2; i++)
7172 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7173 /* Overwrite LINEAR_CENTER. */
7174 for (i = 0; i < 2; i++)
7175 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7176 linear_sample[i], base + 8 + i, "");
7177 /* Overwrite LINEAR_CENTROID. */
7178 for (i = 0; i < 2; i++)
7179 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7180 linear_sample[i], base + 10 + i, "");
7181 }
7182
7183 /* Compile. */
7184 LLVMBuildRet(gallivm->builder, ret);
7185 radeon_llvm_finalize_module(&ctx.radeon_bld);
7186
7187 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7188 gallivm->module, debug, ctx.type,
7189 "Fragment Shader Prolog"))
7190 status = false;
7191
7192 radeon_llvm_dispose(&ctx.radeon_bld);
7193 return status;
7194 }
7195
7196 /**
7197 * Compile the pixel shader epilog. This handles everything that must be
7198 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7199 */
7200 static bool si_compile_ps_epilog(struct si_screen *sscreen,
7201 LLVMTargetMachineRef tm,
7202 struct pipe_debug_callback *debug,
7203 struct si_shader_part *out)
7204 {
7205 union si_shader_part_key *key = &out->key;
7206 struct si_shader shader = {};
7207 struct si_shader_context ctx;
7208 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7209 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
7210 LLVMTypeRef params[16+8*4+3];
7211 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7212 int last_array_pointer, last_sgpr, num_params, i;
7213 bool status = true;
7214
7215 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7216 ctx.type = PIPE_SHADER_FRAGMENT;
7217 shader.key.ps.epilog = key->ps_epilog.states;
7218
7219 /* Declare input SGPRs. */
7220 params[SI_PARAM_RW_BUFFERS] = ctx.i64;
7221 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
7222 params[SI_PARAM_SAMPLERS] = ctx.i64;
7223 params[SI_PARAM_IMAGES] = ctx.i64;
7224 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
7225 params[SI_PARAM_ALPHA_REF] = ctx.f32;
7226 last_array_pointer = -1;
7227 last_sgpr = SI_PARAM_ALPHA_REF;
7228
7229 /* Declare input VGPRs. */
7230 num_params = (last_sgpr + 1) +
7231 util_bitcount(key->ps_epilog.colors_written) * 4 +
7232 key->ps_epilog.writes_z +
7233 key->ps_epilog.writes_stencil +
7234 key->ps_epilog.writes_samplemask;
7235
7236 num_params = MAX2(num_params,
7237 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7238
7239 assert(num_params <= ARRAY_SIZE(params));
7240
7241 for (i = last_sgpr + 1; i < num_params; i++)
7242 params[i] = ctx.f32;
7243
7244 /* Create the function. */
7245 si_create_function(&ctx, NULL, 0, params, num_params,
7246 last_array_pointer, last_sgpr);
7247 /* Disable elimination of unused inputs. */
7248 radeon_llvm_add_attribute(ctx.radeon_bld.main_fn,
7249 "InitialPSInputAddr", 0xffffff);
7250
7251 /* Process colors. */
7252 unsigned vgpr = last_sgpr + 1;
7253 unsigned colors_written = key->ps_epilog.colors_written;
7254 int last_color_export = -1;
7255
7256 /* Find the last color export. */
7257 if (!key->ps_epilog.writes_z &&
7258 !key->ps_epilog.writes_stencil &&
7259 !key->ps_epilog.writes_samplemask) {
7260 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7261
7262 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7263 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7264 /* Just set this if any of the colorbuffers are enabled. */
7265 if (spi_format &
7266 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7267 last_color_export = 0;
7268 } else {
7269 for (i = 0; i < 8; i++)
7270 if (colors_written & (1 << i) &&
7271 (spi_format >> (i * 4)) & 0xf)
7272 last_color_export = i;
7273 }
7274 }
7275
7276 while (colors_written) {
7277 LLVMValueRef color[4];
7278 int mrt = u_bit_scan(&colors_written);
7279
7280 for (i = 0; i < 4; i++)
7281 color[i] = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7282
7283 si_export_mrt_color(bld_base, color, mrt,
7284 num_params - 1,
7285 mrt == last_color_export);
7286 }
7287
7288 /* Process depth, stencil, samplemask. */
7289 if (key->ps_epilog.writes_z)
7290 depth = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7291 if (key->ps_epilog.writes_stencil)
7292 stencil = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7293 if (key->ps_epilog.writes_samplemask)
7294 samplemask = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7295
7296 if (depth || stencil || samplemask)
7297 si_export_mrt_z(bld_base, depth, stencil, samplemask);
7298 else if (last_color_export == -1)
7299 si_export_null(bld_base);
7300
7301 /* Compile. */
7302 LLVMBuildRetVoid(gallivm->builder);
7303 radeon_llvm_finalize_module(&ctx.radeon_bld);
7304
7305 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7306 gallivm->module, debug, ctx.type,
7307 "Fragment Shader Epilog"))
7308 status = false;
7309
7310 radeon_llvm_dispose(&ctx.radeon_bld);
7311 return status;
7312 }
7313
7314 /**
7315 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7316 */
7317 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7318 LLVMTargetMachineRef tm,
7319 struct si_shader *shader,
7320 struct pipe_debug_callback *debug)
7321 {
7322 struct tgsi_shader_info *info = &shader->selector->info;
7323 union si_shader_part_key prolog_key;
7324 union si_shader_part_key epilog_key;
7325 unsigned i;
7326
7327 /* Get the prolog. */
7328 memset(&prolog_key, 0, sizeof(prolog_key));
7329 prolog_key.ps_prolog.states = shader->key.ps.prolog;
7330 prolog_key.ps_prolog.colors_read = info->colors_read;
7331 prolog_key.ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7332 prolog_key.ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
7333
7334 if (info->colors_read) {
7335 unsigned *color = shader->selector->color_attr_index;
7336
7337 if (shader->key.ps.prolog.color_two_side) {
7338 /* BCOLORs are stored after the last input. */
7339 prolog_key.ps_prolog.num_interp_inputs = info->num_inputs;
7340 prolog_key.ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
7341 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
7342 }
7343
7344 for (i = 0; i < 2; i++) {
7345 unsigned location = info->input_interpolate_loc[color[i]];
7346
7347 if (!(info->colors_read & (0xf << i*4)))
7348 continue;
7349
7350 prolog_key.ps_prolog.color_attr_index[i] = color[i];
7351
7352 /* Force per-sample interpolation for the colors here. */
7353 if (shader->key.ps.prolog.force_persample_interp)
7354 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7355
7356 switch (info->input_interpolate[color[i]]) {
7357 case TGSI_INTERPOLATE_CONSTANT:
7358 prolog_key.ps_prolog.color_interp_vgpr_index[i] = -1;
7359 break;
7360 case TGSI_INTERPOLATE_PERSPECTIVE:
7361 case TGSI_INTERPOLATE_COLOR:
7362 switch (location) {
7363 case TGSI_INTERPOLATE_LOC_SAMPLE:
7364 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 0;
7365 shader->config.spi_ps_input_ena |=
7366 S_0286CC_PERSP_SAMPLE_ENA(1);
7367 break;
7368 case TGSI_INTERPOLATE_LOC_CENTER:
7369 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 2;
7370 shader->config.spi_ps_input_ena |=
7371 S_0286CC_PERSP_CENTER_ENA(1);
7372 break;
7373 case TGSI_INTERPOLATE_LOC_CENTROID:
7374 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 4;
7375 shader->config.spi_ps_input_ena |=
7376 S_0286CC_PERSP_CENTROID_ENA(1);
7377 break;
7378 default:
7379 assert(0);
7380 }
7381 break;
7382 case TGSI_INTERPOLATE_LINEAR:
7383 switch (location) {
7384 case TGSI_INTERPOLATE_LOC_SAMPLE:
7385 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 6;
7386 shader->config.spi_ps_input_ena |=
7387 S_0286CC_LINEAR_SAMPLE_ENA(1);
7388 break;
7389 case TGSI_INTERPOLATE_LOC_CENTER:
7390 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 8;
7391 shader->config.spi_ps_input_ena |=
7392 S_0286CC_LINEAR_CENTER_ENA(1);
7393 break;
7394 case TGSI_INTERPOLATE_LOC_CENTROID:
7395 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 10;
7396 shader->config.spi_ps_input_ena |=
7397 S_0286CC_LINEAR_CENTROID_ENA(1);
7398 break;
7399 default:
7400 assert(0);
7401 }
7402 break;
7403 default:
7404 assert(0);
7405 }
7406 }
7407 }
7408
7409 /* The prolog is a no-op if these aren't set. */
7410 if (prolog_key.ps_prolog.colors_read ||
7411 prolog_key.ps_prolog.states.force_persample_interp ||
7412 prolog_key.ps_prolog.states.poly_stipple) {
7413 shader->prolog =
7414 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7415 &prolog_key, tm, debug,
7416 si_compile_ps_prolog);
7417 if (!shader->prolog)
7418 return false;
7419 }
7420
7421 /* Get the epilog. */
7422 memset(&epilog_key, 0, sizeof(epilog_key));
7423 epilog_key.ps_epilog.colors_written = info->colors_written;
7424 epilog_key.ps_epilog.writes_z = info->writes_z;
7425 epilog_key.ps_epilog.writes_stencil = info->writes_stencil;
7426 epilog_key.ps_epilog.writes_samplemask = info->writes_samplemask;
7427 epilog_key.ps_epilog.states = shader->key.ps.epilog;
7428
7429 shader->epilog =
7430 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7431 &epilog_key, tm, debug,
7432 si_compile_ps_epilog);
7433 if (!shader->epilog)
7434 return false;
7435
7436 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7437 if (shader->key.ps.prolog.poly_stipple) {
7438 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7439 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7440 }
7441
7442 /* Set up the enable bits for per-sample shading if needed. */
7443 if (shader->key.ps.prolog.force_persample_interp) {
7444 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7445 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena)) {
7446 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7447 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7448 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7449 }
7450 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7451 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena)) {
7452 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7453 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7454 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7455 }
7456 }
7457
7458 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7459 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7460 !(shader->config.spi_ps_input_ena & 0xf)) {
7461 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7462 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7463 }
7464
7465 /* At least one pair of interpolation weights must be enabled. */
7466 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7467 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7468 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7469 }
7470
7471 /* The sample mask input is always enabled, because the API shader always
7472 * passes it through to the epilog. Disable it here if it's unused.
7473 */
7474 if (!shader->key.ps.epilog.poly_line_smoothing &&
7475 !shader->selector->info.reads_samplemask)
7476 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7477
7478 return true;
7479 }
7480
7481 static void si_fix_num_sgprs(struct si_shader *shader)
7482 {
7483 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7484
7485 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7486 }
7487
7488 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7489 struct si_shader *shader,
7490 struct pipe_debug_callback *debug)
7491 {
7492 struct si_shader *mainp = shader->selector->main_shader_part;
7493 int r;
7494
7495 /* LS, ES, VS are compiled on demand if the main part hasn't been
7496 * compiled for that stage.
7497 */
7498 if (!mainp ||
7499 (shader->selector->type == PIPE_SHADER_VERTEX &&
7500 (shader->key.vs.as_es != mainp->key.vs.as_es ||
7501 shader->key.vs.as_ls != mainp->key.vs.as_ls)) ||
7502 (shader->selector->type == PIPE_SHADER_TESS_EVAL &&
7503 shader->key.tes.as_es != mainp->key.tes.as_es) ||
7504 (shader->selector->type == PIPE_SHADER_TESS_CTRL &&
7505 shader->key.tcs.epilog.inputs_to_copy) ||
7506 shader->selector->type == PIPE_SHADER_COMPUTE) {
7507 /* Monolithic shader (compiled as a whole, has many variants,
7508 * may take a long time to compile).
7509 */
7510 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7511 if (r)
7512 return r;
7513 } else {
7514 /* The shader consists of 2-3 parts:
7515 *
7516 * - the middle part is the user shader, it has 1 variant only
7517 * and it was compiled during the creation of the shader
7518 * selector
7519 * - the prolog part is inserted at the beginning
7520 * - the epilog part is inserted at the end
7521 *
7522 * The prolog and epilog have many (but simple) variants.
7523 */
7524
7525 /* Copy the compiled TGSI shader data over. */
7526 shader->is_binary_shared = true;
7527 shader->binary = mainp->binary;
7528 shader->config = mainp->config;
7529 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7530 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7531 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7532 memcpy(shader->info.vs_output_param_offset,
7533 mainp->info.vs_output_param_offset,
7534 sizeof(mainp->info.vs_output_param_offset));
7535 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7536 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7537 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7538
7539 /* Select prologs and/or epilogs. */
7540 switch (shader->selector->type) {
7541 case PIPE_SHADER_VERTEX:
7542 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7543 return -1;
7544 break;
7545 case PIPE_SHADER_TESS_CTRL:
7546 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7547 return -1;
7548 break;
7549 case PIPE_SHADER_TESS_EVAL:
7550 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
7551 return -1;
7552 break;
7553 case PIPE_SHADER_FRAGMENT:
7554 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
7555 return -1;
7556
7557 /* Make sure we have at least as many VGPRs as there
7558 * are allocated inputs.
7559 */
7560 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7561 shader->info.num_input_vgprs);
7562 break;
7563 }
7564
7565 /* Update SGPR and VGPR counts. */
7566 if (shader->prolog) {
7567 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7568 shader->prolog->config.num_sgprs);
7569 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7570 shader->prolog->config.num_vgprs);
7571 }
7572 if (shader->epilog) {
7573 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7574 shader->epilog->config.num_sgprs);
7575 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7576 shader->epilog->config.num_vgprs);
7577 }
7578 }
7579
7580 si_fix_num_sgprs(shader);
7581 si_shader_dump(sscreen, shader, debug, shader->selector->info.processor,
7582 stderr);
7583
7584 /* Upload. */
7585 r = si_shader_binary_upload(sscreen, shader);
7586 if (r) {
7587 fprintf(stderr, "LLVM failed to upload shader\n");
7588 return r;
7589 }
7590
7591 return 0;
7592 }
7593
7594 void si_shader_destroy(struct si_shader *shader)
7595 {
7596 if (shader->gs_copy_shader) {
7597 si_shader_destroy(shader->gs_copy_shader);
7598 FREE(shader->gs_copy_shader);
7599 }
7600
7601 if (shader->scratch_bo)
7602 r600_resource_reference(&shader->scratch_bo, NULL);
7603
7604 r600_resource_reference(&shader->bo, NULL);
7605
7606 if (!shader->is_binary_shared)
7607 radeon_shader_binary_clean(&shader->binary);
7608 }