radeonsi: Remove LDS layout user SGPR's from TES.
authorBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Mon, 9 May 2016 23:05:32 +0000 (01:05 +0200)
committerBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Thu, 26 May 2016 20:07:04 +0000 (22:07 +0200)
They are unused.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
src/gallium/drivers/radeonsi/si_shader.c
src/gallium/drivers/radeonsi/si_shader.h
src/gallium/drivers/radeonsi/si_state_draw.c

index 6694f00ca3ca453bf07f645100e099860e081097..11c7c38e5d4342a179cd83c125116e37a02c3020 100644 (file)
@@ -5414,9 +5414,7 @@ static void create_function(struct si_shader_context *ctx)
 
        case PIPE_SHADER_TESS_EVAL:
                params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
-               params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
-               params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
-               num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
+               num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
 
                if (shader->key.tes.as_es) {
                        params[ctx->param_oc_lds = num_params++] = ctx->i32;
index 67b457bf64b8083c2a2f47bdcff426af62e975e0..9425b1e1b2c728491d8a1277b6a7dca9421718ec 100644 (file)
@@ -108,12 +108,12 @@ enum {
 
        /* both TCS and TES */
        SI_SGPR_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS,
-       SI_SGPR_TCS_OUT_OFFSETS,
-       SI_SGPR_TCS_OUT_LAYOUT,
        SI_TES_NUM_USER_SGPR,
 
        /* TCS only */
-       SI_SGPR_TCS_IN_LAYOUT = SI_TES_NUM_USER_SGPR,
+       SI_SGPR_TCS_OUT_OFFSETS = SI_TES_NUM_USER_SGPR,
+       SI_SGPR_TCS_OUT_LAYOUT,
+       SI_SGPR_TCS_IN_LAYOUT,
        SI_TCS_NUM_USER_SGPR,
 
        /* GS limits */
@@ -155,26 +155,27 @@ enum {
         */
        SI_PARAM_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_PARAMS, /* for TCS & TES */
 
+       /* TCS only parameters. */
+
        /* Offsets where TCS outputs and TCS patch outputs live in LDS:
         *   [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
         *   [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
         */
-       SI_PARAM_TCS_OUT_OFFSETS, /* for TCS & TES */
+       SI_PARAM_TCS_OUT_OFFSETS,
 
        /* Layout of TCS outputs / TES inputs:
         *   [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
         *   [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
         *   [26:31] = gl_PatchVerticesIn, max = 32
         */
-       SI_PARAM_TCS_OUT_LAYOUT, /* for TCS & TES */
+       SI_PARAM_TCS_OUT_LAYOUT,
 
        /* Layout of LS outputs / TCS inputs
         *   [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
         *   [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
         */
-       SI_PARAM_TCS_IN_LAYOUT,  /* TCS only */
+       SI_PARAM_TCS_IN_LAYOUT,
 
-       /* TCS only parameters. */
        SI_PARAM_TCS_OC_LDS,
        SI_PARAM_TESS_FACTOR_OFFSET,
        SI_PARAM_PATCH_ID,
index e14a1c983f719ff5120aec9408efc5c03b5fa4b2..6fe2619d6013db41a842818a2c678e653990c2e7 100644 (file)
@@ -201,10 +201,8 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
        radeon_emit(cs, tcs_in_layout);
 
        /* Set them for TES. */
-       radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
+       radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 1);
        radeon_emit(cs, offchip_layout);
-       radeon_emit(cs, tcs_out_offsets);
-       radeon_emit(cs, tcs_out_layout | (num_tcs_output_cp << 26));
 }
 
 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)