2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_shader_internal.h"
28 #include "tgsi/tgsi_build.h"
29 #include "tgsi/tgsi_util.h"
30 #include "ac_llvm_util.h"
32 static void tex_fetch_ptrs(struct lp_build_tgsi_context
*bld_base
,
33 struct lp_build_emit_data
*emit_data
,
34 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
,
35 LLVMValueRef
*fmask_ptr
);
38 * Given a v8i32 resource descriptor for a buffer, extract the size of the
39 * buffer in number of elements and return it as an i32.
41 static LLVMValueRef
get_buffer_size(
42 struct lp_build_tgsi_context
*bld_base
,
43 LLVMValueRef descriptor
)
45 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
46 LLVMBuilderRef builder
= ctx
->ac
.builder
;
48 LLVMBuildExtractElement(builder
, descriptor
,
49 LLVMConstInt(ctx
->i32
, 2, 0), "");
51 if (ctx
->screen
->info
.chip_class
== VI
) {
52 /* On VI, the descriptor contains the size in bytes,
53 * but TXQ must return the size in elements.
54 * The stride is always non-zero for resources using TXQ.
57 LLVMBuildExtractElement(builder
, descriptor
,
59 stride
= LLVMBuildLShr(builder
, stride
,
60 LLVMConstInt(ctx
->i32
, 16, 0), "");
61 stride
= LLVMBuildAnd(builder
, stride
,
62 LLVMConstInt(ctx
->i32
, 0x3FFF, 0), "");
64 size
= LLVMBuildUDiv(builder
, size
, stride
, "");
71 shader_buffer_fetch_rsrc(struct si_shader_context
*ctx
,
72 const struct tgsi_full_src_register
*reg
,
77 if (!reg
->Register
.Indirect
) {
78 index
= LLVMConstInt(ctx
->i32
, reg
->Register
.Index
, false);
80 index
= si_get_indirect_index(ctx
, ®
->Indirect
,
81 1, reg
->Register
.Index
);
85 return ctx
->abi
.load_ubo(&ctx
->abi
, index
);
87 return ctx
->abi
.load_ssbo(&ctx
->abi
, index
, false);
90 static enum ac_image_dim
91 ac_texture_dim_from_tgsi_target(struct si_screen
*screen
, enum tgsi_texture_type target
)
95 case TGSI_TEXTURE_SHADOW1D
:
96 if (screen
->info
.chip_class
>= GFX9
)
100 case TGSI_TEXTURE_SHADOW2D
:
101 case TGSI_TEXTURE_RECT
:
102 case TGSI_TEXTURE_SHADOWRECT
:
104 case TGSI_TEXTURE_3D
:
106 case TGSI_TEXTURE_CUBE
:
107 case TGSI_TEXTURE_SHADOWCUBE
:
108 case TGSI_TEXTURE_CUBE_ARRAY
:
109 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
110 return ac_image_cube
;
111 case TGSI_TEXTURE_1D_ARRAY
:
112 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
113 if (screen
->info
.chip_class
>= GFX9
)
114 return ac_image_2darray
;
115 return ac_image_1darray
;
116 case TGSI_TEXTURE_2D_ARRAY
:
117 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
118 return ac_image_2darray
;
119 case TGSI_TEXTURE_2D_MSAA
:
120 return ac_image_2dmsaa
;
121 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
122 return ac_image_2darraymsaa
;
124 unreachable("unhandled texture type");
128 static enum ac_image_dim
129 ac_image_dim_from_tgsi_target(struct si_screen
*screen
, enum tgsi_texture_type target
)
131 enum ac_image_dim dim
= ac_texture_dim_from_tgsi_target(screen
, target
);
133 /* Match the resource type set in the descriptor. */
134 if (dim
== ac_image_cube
||
135 (screen
->info
.chip_class
<= VI
&& dim
== ac_image_3d
))
136 dim
= ac_image_2darray
;
137 else if (target
== TGSI_TEXTURE_2D
&& screen
->info
.chip_class
>= GFX9
) {
138 /* When a single layer of a 3D texture is bound, the shader
139 * will refer to a 2D target, but the descriptor has a 3D type.
140 * Since the HW ignores BASE_ARRAY in this case, we need to
141 * send 3 coordinates. This doesn't hurt when the underlying
151 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
153 * At least on Tonga, executing image stores on images with DCC enabled and
154 * non-trivial can eventually lead to lockups. This can occur when an
155 * application binds an image as read-only but then uses a shader that writes
156 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
157 * program termination) in this case, but it doesn't cost much to be a bit
158 * nicer: disabling DCC in the shader still leads to undefined results but
161 static LLVMValueRef
force_dcc_off(struct si_shader_context
*ctx
,
164 if (ctx
->screen
->info
.chip_class
<= CIK
) {
167 LLVMValueRef i32_6
= LLVMConstInt(ctx
->i32
, 6, 0);
168 LLVMValueRef i32_C
= LLVMConstInt(ctx
->i32
, C_008F28_COMPRESSION_EN
, 0);
171 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, rsrc
, i32_6
, "");
172 tmp
= LLVMBuildAnd(ctx
->ac
.builder
, tmp
, i32_C
, "");
173 return LLVMBuildInsertElement(ctx
->ac
.builder
, rsrc
, tmp
, i32_6
, "");
177 LLVMValueRef
si_load_image_desc(struct si_shader_context
*ctx
,
178 LLVMValueRef list
, LLVMValueRef index
,
179 enum ac_descriptor_type desc_type
, bool dcc_off
,
182 LLVMBuilderRef builder
= ctx
->ac
.builder
;
185 if (desc_type
== AC_DESC_BUFFER
) {
186 index
= ac_build_imad(&ctx
->ac
, index
, LLVMConstInt(ctx
->i32
, 2, 0),
188 list
= LLVMBuildPointerCast(builder
, list
,
189 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
191 assert(desc_type
== AC_DESC_IMAGE
);
195 rsrc
= ac_build_load_to_sgpr_uint_wraparound(&ctx
->ac
, list
, index
);
197 rsrc
= ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
199 if (desc_type
== AC_DESC_IMAGE
&& dcc_off
)
200 rsrc
= force_dcc_off(ctx
, rsrc
);
205 * Load the resource descriptor for \p image.
209 struct lp_build_tgsi_context
*bld_base
,
210 const struct tgsi_full_src_register
*image
,
211 bool is_store
, unsigned target
,
214 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
215 LLVMValueRef rsrc_ptr
= LLVMGetParam(ctx
->main_fn
,
216 ctx
->param_samplers_and_images
);
218 bool dcc_off
= is_store
;
220 if (!image
->Register
.Indirect
) {
221 const struct tgsi_shader_info
*info
= bld_base
->info
;
222 unsigned images_writemask
= info
->images_store
|
225 index
= LLVMConstInt(ctx
->i32
,
226 si_get_image_slot(image
->Register
.Index
), 0);
228 if (images_writemask
& (1 << image
->Register
.Index
))
231 /* From the GL_ARB_shader_image_load_store extension spec:
233 * If a shader performs an image load, store, or atomic
234 * operation using an image variable declared as an array,
235 * and if the index used to select an individual element is
236 * negative or greater than or equal to the size of the
237 * array, the results of the operation are undefined but may
238 * not lead to termination.
240 index
= si_get_bounded_indirect_index(ctx
, &image
->Indirect
,
241 image
->Register
.Index
,
243 index
= LLVMBuildSub(ctx
->ac
.builder
,
244 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
- 1, 0),
248 bool bindless
= false;
250 if (image
->Register
.File
!= TGSI_FILE_IMAGE
) {
251 /* Bindless descriptors are accessible from a different pair of
254 rsrc_ptr
= LLVMGetParam(ctx
->main_fn
,
255 ctx
->param_bindless_samplers_and_images
);
256 index
= lp_build_emit_fetch_src(bld_base
, image
,
257 TGSI_TYPE_UNSIGNED
, 0);
259 /* For simplicity, bindless image descriptors use fixed
260 * 16-dword slots for now.
262 index
= LLVMBuildMul(ctx
->ac
.builder
, index
,
263 LLVMConstInt(ctx
->i32
, 2, 0), "");
267 *rsrc
= si_load_image_desc(ctx
, rsrc_ptr
, index
,
268 target
== TGSI_TEXTURE_BUFFER
? AC_DESC_BUFFER
: AC_DESC_IMAGE
,
272 static void image_fetch_coords(
273 struct lp_build_tgsi_context
*bld_base
,
274 const struct tgsi_full_instruction
*inst
,
275 unsigned src
, LLVMValueRef desc
,
276 LLVMValueRef
*coords
)
278 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
279 LLVMBuilderRef builder
= ctx
->ac
.builder
;
280 unsigned target
= inst
->Memory
.Texture
;
281 unsigned num_coords
= tgsi_util_get_texture_coord_dim(target
);
285 if (target
== TGSI_TEXTURE_2D_MSAA
||
286 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
287 /* Need the sample index as well. */
291 for (chan
= 0; chan
< num_coords
; ++chan
) {
292 tmp
= lp_build_emit_fetch(bld_base
, inst
, src
, chan
);
293 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
297 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
298 /* 1D textures are allocated and used as 2D on GFX9. */
299 if (target
== TGSI_TEXTURE_1D
) {
300 coords
[1] = ctx
->i32_0
;
301 } else if (target
== TGSI_TEXTURE_1D_ARRAY
) {
302 coords
[2] = coords
[1];
303 coords
[1] = ctx
->i32_0
;
304 } else if (target
== TGSI_TEXTURE_2D
) {
305 /* The hw can't bind a slice of a 3D image as a 2D
306 * image, because it ignores BASE_ARRAY if the target
307 * is 3D. The workaround is to read BASE_ARRAY and set
308 * it as the 3rd address operand for all 2D images.
310 LLVMValueRef first_layer
, const5
, mask
;
312 const5
= LLVMConstInt(ctx
->i32
, 5, 0);
313 mask
= LLVMConstInt(ctx
->i32
, S_008F24_BASE_ARRAY(~0), 0);
314 first_layer
= LLVMBuildExtractElement(builder
, desc
, const5
, "");
315 first_layer
= LLVMBuildAnd(builder
, first_layer
, mask
, "");
317 coords
[2] = first_layer
;
322 static unsigned get_cache_policy(struct si_shader_context
*ctx
,
323 const struct tgsi_full_instruction
*inst
,
324 bool atomic
, bool may_store_unaligned
,
325 bool writeonly_memory
)
327 unsigned cache_policy
= 0;
330 /* SI has a TC L1 bug causing corruption of 8bit/16bit stores.
331 * All store opcodes not aligned to a dword are affected.
332 * The only way to get unaligned stores in radeonsi is through
334 ((may_store_unaligned
&& ctx
->screen
->info
.chip_class
== SI
) ||
335 /* If this is write-only, don't keep data in L1 to prevent
336 * evicting L1 cache lines that may be needed by other
339 inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
)))
340 cache_policy
|= ac_glc
;
342 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_STREAM_CACHE_POLICY
)
343 cache_policy
|= ac_slc
;
348 static LLVMValueRef
get_memory_ptr(struct si_shader_context
*ctx
,
349 const struct tgsi_full_instruction
*inst
,
350 LLVMTypeRef type
, int arg
)
352 LLVMBuilderRef builder
= ctx
->ac
.builder
;
353 LLVMValueRef offset
, ptr
;
356 offset
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, arg
, 0);
357 offset
= ac_to_integer(&ctx
->ac
, offset
);
360 ptr
= LLVMBuildGEP(builder
, ptr
, &offset
, 1, "");
361 addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
362 ptr
= LLVMBuildBitCast(builder
, ptr
, LLVMPointerType(type
, addr_space
), "");
367 static void load_emit_memory(
368 struct si_shader_context
*ctx
,
369 struct lp_build_emit_data
*emit_data
)
371 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
372 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
373 LLVMValueRef channels
[4], ptr
, derived_ptr
, index
;
376 ptr
= get_memory_ptr(ctx
, inst
, ctx
->f32
, 1);
378 for (chan
= 0; chan
< 4; ++chan
) {
379 if (!(writemask
& (1 << chan
))) {
380 channels
[chan
] = LLVMGetUndef(ctx
->f32
);
384 index
= LLVMConstInt(ctx
->i32
, chan
, 0);
385 derived_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ptr
, &index
, 1, "");
386 channels
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, derived_ptr
, "");
388 emit_data
->output
[emit_data
->chan
] = ac_build_gather_values(&ctx
->ac
, channels
, 4);
392 * Return true if the memory accessed by a LOAD or STORE instruction is
393 * read-only or write-only, respectively.
395 * \param shader_buffers_reverse_access_mask
396 * For LOAD, set this to (store | atomic) slot usage in the shader.
397 * For STORE, set this to (load | atomic) slot usage in the shader.
398 * \param images_reverse_access_mask Same as above, but for images.
399 * \param bindless_buffer_reverse_access_mask Same as above, but for bindless image buffers.
400 * \param bindless_image_reverse_access_mask Same as above, but for bindless images.
402 static bool is_oneway_access_only(const struct tgsi_full_instruction
*inst
,
403 const struct tgsi_shader_info
*info
,
404 unsigned shader_buffers_reverse_access_mask
,
405 unsigned images_reverse_access_mask
,
406 bool bindless_buffer_reverse_access_mask
,
407 bool bindless_image_reverse_access_mask
)
409 enum tgsi_file_type resource_file
;
410 unsigned resource_index
;
411 bool resource_indirect
;
413 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_STORE
) {
414 resource_file
= inst
->Dst
[0].Register
.File
;
415 resource_index
= inst
->Dst
[0].Register
.Index
;
416 resource_indirect
= inst
->Dst
[0].Register
.Indirect
;
418 resource_file
= inst
->Src
[0].Register
.File
;
419 resource_index
= inst
->Src
[0].Register
.Index
;
420 resource_indirect
= inst
->Src
[0].Register
.Indirect
;
423 assert(resource_file
== TGSI_FILE_BUFFER
||
424 resource_file
== TGSI_FILE_IMAGE
||
426 resource_file
== TGSI_FILE_INPUT
||
427 resource_file
== TGSI_FILE_OUTPUT
||
428 resource_file
== TGSI_FILE_CONSTANT
||
429 resource_file
== TGSI_FILE_TEMPORARY
||
430 resource_file
== TGSI_FILE_IMMEDIATE
);
432 assert(resource_file
!= TGSI_FILE_BUFFER
||
433 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
);
435 bool bindless
= resource_file
!= TGSI_FILE_BUFFER
&&
436 resource_file
!= TGSI_FILE_IMAGE
;
438 /* RESTRICT means NOALIAS.
439 * If there are no writes, we can assume the accessed memory is read-only.
440 * If there are no reads, we can assume the accessed memory is write-only.
442 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_RESTRICT
&& !bindless
) {
443 unsigned reverse_access_mask
;
445 if (resource_file
== TGSI_FILE_BUFFER
) {
446 reverse_access_mask
= shader_buffers_reverse_access_mask
;
447 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
448 reverse_access_mask
= info
->images_buffers
&
449 images_reverse_access_mask
;
451 reverse_access_mask
= ~info
->images_buffers
&
452 images_reverse_access_mask
;
455 if (resource_indirect
) {
456 if (!reverse_access_mask
)
459 if (!(reverse_access_mask
&
460 (1u << resource_index
)))
465 /* If there are no buffer writes (for both shader buffers & image
466 * buffers), it implies that buffer memory is read-only.
467 * If there are no buffer reads (for both shader buffers & image
468 * buffers), it implies that buffer memory is write-only.
470 * Same for the case when there are no writes/reads for non-buffer
473 if (resource_file
== TGSI_FILE_BUFFER
||
474 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
475 if (!shader_buffers_reverse_access_mask
&&
476 !(info
->images_buffers
& images_reverse_access_mask
) &&
477 !bindless_buffer_reverse_access_mask
)
480 if (!(~info
->images_buffers
& images_reverse_access_mask
) &&
481 !bindless_image_reverse_access_mask
)
487 static void load_emit(
488 const struct lp_build_tgsi_action
*action
,
489 struct lp_build_tgsi_context
*bld_base
,
490 struct lp_build_emit_data
*emit_data
)
492 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
493 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
494 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
495 bool can_speculate
= false;
496 LLVMValueRef vindex
= ctx
->i32_0
;
497 LLVMValueRef voffset
= ctx
->i32_0
;
498 struct ac_image_args args
= {};
500 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
) {
501 load_emit_memory(ctx
, emit_data
);
505 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
506 inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
) {
507 bool ubo
= inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
;
508 args
.resource
= shader_buffer_fetch_rsrc(ctx
, &inst
->Src
[0], ubo
);
509 voffset
= ac_to_integer(&ctx
->ac
, lp_build_emit_fetch(bld_base
, inst
, 1, 0));
511 unsigned target
= inst
->Memory
.Texture
;
513 image_fetch_rsrc(bld_base
, &inst
->Src
[0], false, target
, &args
.resource
);
514 image_fetch_coords(bld_base
, inst
, 1, args
.resource
, args
.coords
);
515 vindex
= args
.coords
[0]; /* for buffers only */
518 if (inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
) {
519 emit_data
->output
[emit_data
->chan
] =
520 ac_build_buffer_load(&ctx
->ac
, args
.resource
,
521 util_last_bit(inst
->Dst
[0].Register
.WriteMask
),
522 NULL
, voffset
, NULL
, 0, 0, 0, true, true);
526 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
527 ac_build_waitcnt(&ctx
->ac
, VM_CNT
);
529 can_speculate
= !(inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
) &&
530 is_oneway_access_only(inst
, info
,
531 info
->shader_buffers_store
|
532 info
->shader_buffers_atomic
,
535 info
->uses_bindless_buffer_store
|
536 info
->uses_bindless_buffer_atomic
,
537 info
->uses_bindless_image_store
|
538 info
->uses_bindless_image_atomic
);
539 args
.cache_policy
= get_cache_policy(ctx
, inst
, false, false, false);
541 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
542 /* Don't use SMEM for shader buffer loads, because LLVM doesn't
543 * select SMEM for SI.load.const with a non-constant offset, and
544 * constant offsets practically don't exist with shader buffers.
546 * Also, SI.load.const doesn't use inst_offset when it's lowered
547 * to VMEM, so we just end up with more VALU instructions in the end
550 * TODO: Remove this line once LLVM can select SMEM with a non-constant
551 * offset, and can derive inst_offset when VMEM is selected.
552 * After that, si_memory_barrier should invalidate sL1 for shader
555 emit_data
->output
[emit_data
->chan
] =
556 ac_build_buffer_load(&ctx
->ac
, args
.resource
,
557 util_last_bit(inst
->Dst
[0].Register
.WriteMask
),
558 NULL
, voffset
, NULL
, 0,
559 !!(args
.cache_policy
& ac_glc
),
560 !!(args
.cache_policy
& ac_slc
),
561 can_speculate
, false);
565 if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
566 unsigned num_channels
= util_last_bit(inst
->Dst
[0].Register
.WriteMask
);
567 LLVMValueRef result
=
568 ac_build_buffer_load_format(&ctx
->ac
,
573 !!(args
.cache_policy
& ac_glc
),
575 emit_data
->output
[emit_data
->chan
] =
576 ac_build_expand_to_vec4(&ctx
->ac
, result
, num_channels
);
578 args
.opcode
= ac_image_load
;
579 args
.dim
= ac_image_dim_from_tgsi_target(ctx
->screen
, inst
->Memory
.Texture
);
580 args
.attributes
= ac_get_load_intr_attribs(can_speculate
);
583 emit_data
->output
[emit_data
->chan
] =
584 ac_build_image_opcode(&ctx
->ac
, &args
);
588 static void store_emit_buffer(struct si_shader_context
*ctx
,
589 LLVMValueRef resource
,
592 LLVMValueRef voffset
,
593 unsigned cache_policy
,
594 bool writeonly_memory
)
596 LLVMBuilderRef builder
= ctx
->ac
.builder
;
597 LLVMValueRef base_data
= value
;
598 LLVMValueRef base_offset
= voffset
;
602 const char *intrinsic_name
;
603 LLVMValueRef data
, voff
;
605 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
607 /* Due to an LLVM limitation, split 3-element writes
608 * into a 2-element and a 1-element write. */
610 writemask
|= 1 << (start
+ 2);
616 intrinsic_name
= "llvm.amdgcn.buffer.store.v4f32";
617 } else if (count
== 2) {
618 LLVMValueRef values
[2] = {
619 LLVMBuildExtractElement(builder
, base_data
,
620 LLVMConstInt(ctx
->i32
, start
, 0), ""),
621 LLVMBuildExtractElement(builder
, base_data
,
622 LLVMConstInt(ctx
->i32
, start
+ 1, 0), ""),
625 data
= ac_build_gather_values(&ctx
->ac
, values
, 2);
626 intrinsic_name
= "llvm.amdgcn.buffer.store.v2f32";
629 data
= LLVMBuildExtractElement(
631 LLVMConstInt(ctx
->i32
, start
, 0), "");
632 intrinsic_name
= "llvm.amdgcn.buffer.store.f32";
639 LLVMConstInt(ctx
->i32
, start
* 4, 0), "");
642 LLVMValueRef args
[] = {
645 ctx
->i32_0
, /* vindex */
647 LLVMConstInt(ctx
->i1
, !!(cache_policy
& ac_glc
), 0),
648 LLVMConstInt(ctx
->i1
, !!(cache_policy
& ac_slc
), 0),
650 ac_build_intrinsic(&ctx
->ac
, intrinsic_name
, ctx
->voidt
, args
, 6,
651 ac_get_store_intr_attribs(writeonly_memory
));
655 static void store_emit_memory(
656 struct si_shader_context
*ctx
,
657 struct lp_build_emit_data
*emit_data
)
659 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
660 LLVMBuilderRef builder
= ctx
->ac
.builder
;
661 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
662 LLVMValueRef ptr
, derived_ptr
, data
, index
;
665 ptr
= get_memory_ptr(ctx
, inst
, ctx
->f32
, 0);
667 for (chan
= 0; chan
< 4; ++chan
) {
668 if (!(writemask
& (1 << chan
))) {
671 data
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, 1, chan
);
672 index
= LLVMConstInt(ctx
->i32
, chan
, 0);
673 derived_ptr
= LLVMBuildGEP(builder
, ptr
, &index
, 1, "");
674 LLVMBuildStore(builder
, data
, derived_ptr
);
678 static void store_emit(
679 const struct lp_build_tgsi_action
*action
,
680 struct lp_build_tgsi_context
*bld_base
,
681 struct lp_build_emit_data
*emit_data
)
683 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
684 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
685 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
686 struct tgsi_full_src_register resource_reg
=
687 tgsi_full_src_register_from_dst(&inst
->Dst
[0]);
688 unsigned target
= inst
->Memory
.Texture
;
690 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_MEMORY
) {
691 store_emit_memory(ctx
, emit_data
);
695 bool writeonly_memory
= is_oneway_access_only(inst
, info
,
696 info
->shader_buffers_load
|
697 info
->shader_buffers_atomic
,
700 info
->uses_bindless_buffer_load
|
701 info
->uses_bindless_buffer_atomic
,
702 info
->uses_bindless_image_load
|
703 info
->uses_bindless_image_atomic
);
704 LLVMValueRef chans
[4], value
;
705 LLVMValueRef vindex
= ctx
->i32_0
;
706 LLVMValueRef voffset
= ctx
->i32_0
;
707 struct ac_image_args args
= {};
709 for (unsigned chan
= 0; chan
< 4; ++chan
)
710 chans
[chan
] = lp_build_emit_fetch(bld_base
, inst
, 1, chan
);
712 value
= ac_build_gather_values(&ctx
->ac
, chans
, 4);
714 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
) {
715 args
.resource
= shader_buffer_fetch_rsrc(ctx
, &resource_reg
, false);
716 voffset
= ac_to_integer(&ctx
->ac
, lp_build_emit_fetch(bld_base
, inst
, 0, 0));
718 image_fetch_rsrc(bld_base
, &resource_reg
, true, target
, &args
.resource
);
719 image_fetch_coords(bld_base
, inst
, 0, args
.resource
, args
.coords
);
720 vindex
= args
.coords
[0]; /* for buffers only */
723 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
724 ac_build_waitcnt(&ctx
->ac
, VM_CNT
);
726 bool is_image
= inst
->Dst
[0].Register
.File
!= TGSI_FILE_BUFFER
;
727 args
.cache_policy
= get_cache_policy(ctx
, inst
,
729 is_image
, /* may_store_unaligned */
732 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
) {
733 store_emit_buffer(ctx
, args
.resource
, inst
->Dst
[0].Register
.WriteMask
,
734 value
, voffset
, args
.cache_policy
, writeonly_memory
);
738 if (target
== TGSI_TEXTURE_BUFFER
) {
739 LLVMValueRef buf_args
[6] = {
743 ctx
->i32_0
, /* voffset */
746 if (HAVE_LLVM
>= 0x0800) {
747 buf_args
[4] = ctx
->i32_0
; /* soffset */
748 buf_args
[5] = LLVMConstInt(ctx
->i1
, args
.cache_policy
, 0);
750 buf_args
[4] = LLVMConstInt(ctx
->i1
, !!(args
.cache_policy
& ac_glc
), 0);
751 buf_args
[5] = LLVMConstInt(ctx
->i1
, !!(args
.cache_policy
& ac_slc
), 0);
754 emit_data
->output
[emit_data
->chan
] = ac_build_intrinsic(
756 HAVE_LLVM
>= 0x0800 ? "llvm.amdgcn.struct.buffer.store.format.v4f32" :
757 "llvm.amdgcn.buffer.store.format.v4f32",
758 ctx
->voidt
, buf_args
, 6,
759 ac_get_store_intr_attribs(writeonly_memory
));
761 args
.opcode
= ac_image_store
;
762 args
.data
[0] = value
;
763 args
.dim
= ac_image_dim_from_tgsi_target(ctx
->screen
, inst
->Memory
.Texture
);
764 args
.attributes
= ac_get_store_intr_attribs(writeonly_memory
);
767 emit_data
->output
[emit_data
->chan
] =
768 ac_build_image_opcode(&ctx
->ac
, &args
);
772 static void atomic_emit_memory(struct si_shader_context
*ctx
,
773 struct lp_build_emit_data
*emit_data
) {
774 LLVMBuilderRef builder
= ctx
->ac
.builder
;
775 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
776 LLVMValueRef ptr
, result
, arg
;
778 ptr
= get_memory_ptr(ctx
, inst
, ctx
->i32
, 1);
780 arg
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, 2, 0);
781 arg
= ac_to_integer(&ctx
->ac
, arg
);
783 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
784 LLVMValueRef new_data
;
785 new_data
= lp_build_emit_fetch(&ctx
->bld_base
,
788 new_data
= ac_to_integer(&ctx
->ac
, new_data
);
790 result
= LLVMBuildAtomicCmpXchg(builder
, ptr
, arg
, new_data
,
791 LLVMAtomicOrderingSequentiallyConsistent
,
792 LLVMAtomicOrderingSequentiallyConsistent
,
795 result
= LLVMBuildExtractValue(builder
, result
, 0, "");
797 LLVMAtomicRMWBinOp op
;
799 switch(inst
->Instruction
.Opcode
) {
800 case TGSI_OPCODE_ATOMUADD
:
801 op
= LLVMAtomicRMWBinOpAdd
;
803 case TGSI_OPCODE_ATOMXCHG
:
804 op
= LLVMAtomicRMWBinOpXchg
;
806 case TGSI_OPCODE_ATOMAND
:
807 op
= LLVMAtomicRMWBinOpAnd
;
809 case TGSI_OPCODE_ATOMOR
:
810 op
= LLVMAtomicRMWBinOpOr
;
812 case TGSI_OPCODE_ATOMXOR
:
813 op
= LLVMAtomicRMWBinOpXor
;
815 case TGSI_OPCODE_ATOMUMIN
:
816 op
= LLVMAtomicRMWBinOpUMin
;
818 case TGSI_OPCODE_ATOMUMAX
:
819 op
= LLVMAtomicRMWBinOpUMax
;
821 case TGSI_OPCODE_ATOMIMIN
:
822 op
= LLVMAtomicRMWBinOpMin
;
824 case TGSI_OPCODE_ATOMIMAX
:
825 op
= LLVMAtomicRMWBinOpMax
;
828 unreachable("unknown atomic opcode");
831 result
= LLVMBuildAtomicRMW(builder
, op
, ptr
, arg
,
832 LLVMAtomicOrderingSequentiallyConsistent
,
835 emit_data
->output
[emit_data
->chan
] =
836 LLVMBuildBitCast(builder
, result
, ctx
->f32
, "");
839 static void atomic_emit(
840 const struct lp_build_tgsi_action
*action
,
841 struct lp_build_tgsi_context
*bld_base
,
842 struct lp_build_emit_data
*emit_data
)
844 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
845 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
846 struct ac_image_args args
= {};
847 unsigned num_data
= 0;
848 LLVMValueRef vindex
= ctx
->i32_0
;
849 LLVMValueRef voffset
= ctx
->i32_0
;
851 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
) {
852 atomic_emit_memory(ctx
, emit_data
);
856 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
857 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
858 * of arguments, which is reversed relative to TGSI (and GLSL)
860 args
.data
[num_data
++] =
861 ac_to_integer(&ctx
->ac
, lp_build_emit_fetch(bld_base
, inst
, 3, 0));
864 args
.data
[num_data
++] =
865 ac_to_integer(&ctx
->ac
, lp_build_emit_fetch(bld_base
, inst
, 2, 0));
866 args
.cache_policy
= get_cache_policy(ctx
, inst
, true, false, false);
868 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
869 args
.resource
= shader_buffer_fetch_rsrc(ctx
, &inst
->Src
[0], false);
870 voffset
= ac_to_integer(&ctx
->ac
, lp_build_emit_fetch(bld_base
, inst
, 1, 0));
872 image_fetch_rsrc(bld_base
, &inst
->Src
[0], true,
873 inst
->Memory
.Texture
, &args
.resource
);
874 image_fetch_coords(bld_base
, inst
, 1, args
.resource
, args
.coords
);
875 vindex
= args
.coords
[0]; /* for buffers only */
878 if (HAVE_LLVM
>= 0x0800 &&
879 inst
->Src
[0].Register
.File
!= TGSI_FILE_BUFFER
&&
880 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
881 LLVMValueRef buf_args
[7];
882 unsigned num_args
= 0;
884 buf_args
[num_args
++] = args
.data
[0];
885 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
886 buf_args
[num_args
++] = args
.data
[1];
888 buf_args
[num_args
++] = args
.resource
;
889 buf_args
[num_args
++] = vindex
;
890 buf_args
[num_args
++] = voffset
;
891 buf_args
[num_args
++] = ctx
->i32_0
; /* soffset */
892 buf_args
[num_args
++] = LLVMConstInt(ctx
->i32
, args
.cache_policy
& ac_slc
, 0);
894 char intrinsic_name
[64];
895 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
896 "llvm.amdgcn.struct.buffer.atomic.%s", action
->intr_name
);
897 emit_data
->output
[emit_data
->chan
] =
898 ac_to_float(&ctx
->ac
,
899 ac_build_intrinsic(&ctx
->ac
, intrinsic_name
,
900 ctx
->i32
, buf_args
, num_args
, 0));
904 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
905 (HAVE_LLVM
< 0x0800 &&
906 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
)) {
907 LLVMValueRef buf_args
[7];
908 unsigned num_args
= 0;
910 buf_args
[num_args
++] = args
.data
[0];
911 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
912 buf_args
[num_args
++] = args
.data
[1];
914 buf_args
[num_args
++] = args
.resource
;
915 buf_args
[num_args
++] = vindex
;
916 buf_args
[num_args
++] = voffset
;
917 buf_args
[num_args
++] = args
.cache_policy
& ac_slc
? ctx
->i1true
: ctx
->i1false
;
919 char intrinsic_name
[40];
920 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
921 "llvm.amdgcn.buffer.atomic.%s", action
->intr_name
);
922 emit_data
->output
[emit_data
->chan
] =
923 ac_to_float(&ctx
->ac
,
924 ac_build_intrinsic(&ctx
->ac
, intrinsic_name
,
925 ctx
->i32
, buf_args
, num_args
, 0));
927 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
928 args
.opcode
= ac_image_atomic_cmpswap
;
930 args
.opcode
= ac_image_atomic
;
931 switch (inst
->Instruction
.Opcode
) {
932 case TGSI_OPCODE_ATOMXCHG
: args
.atomic
= ac_atomic_swap
; break;
933 case TGSI_OPCODE_ATOMUADD
: args
.atomic
= ac_atomic_add
; break;
934 case TGSI_OPCODE_ATOMAND
: args
.atomic
= ac_atomic_and
; break;
935 case TGSI_OPCODE_ATOMOR
: args
.atomic
= ac_atomic_or
; break;
936 case TGSI_OPCODE_ATOMXOR
: args
.atomic
= ac_atomic_xor
; break;
937 case TGSI_OPCODE_ATOMUMIN
: args
.atomic
= ac_atomic_umin
; break;
938 case TGSI_OPCODE_ATOMUMAX
: args
.atomic
= ac_atomic_umax
; break;
939 case TGSI_OPCODE_ATOMIMIN
: args
.atomic
= ac_atomic_smin
; break;
940 case TGSI_OPCODE_ATOMIMAX
: args
.atomic
= ac_atomic_smax
; break;
941 default: unreachable("unhandled image atomic");
945 args
.dim
= ac_image_dim_from_tgsi_target(ctx
->screen
, inst
->Memory
.Texture
);
946 emit_data
->output
[emit_data
->chan
] =
947 ac_to_float(&ctx
->ac
, ac_build_image_opcode(&ctx
->ac
, &args
));
951 static LLVMValueRef
fix_resinfo(struct si_shader_context
*ctx
,
952 unsigned target
, LLVMValueRef out
)
954 LLVMBuilderRef builder
= ctx
->ac
.builder
;
956 /* 1D textures are allocated and used as 2D on GFX9. */
957 if (ctx
->screen
->info
.chip_class
>= GFX9
&&
958 (target
== TGSI_TEXTURE_1D_ARRAY
||
959 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
)) {
960 LLVMValueRef layers
=
961 LLVMBuildExtractElement(builder
, out
,
962 LLVMConstInt(ctx
->i32
, 2, 0), "");
963 out
= LLVMBuildInsertElement(builder
, out
, layers
,
967 /* Divide the number of layers by 6 to get the number of cubes. */
968 if (target
== TGSI_TEXTURE_CUBE_ARRAY
||
969 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
970 LLVMValueRef imm2
= LLVMConstInt(ctx
->i32
, 2, 0);
972 LLVMValueRef z
= LLVMBuildExtractElement(builder
, out
, imm2
, "");
973 z
= LLVMBuildSDiv(builder
, z
, LLVMConstInt(ctx
->i32
, 6, 0), "");
975 out
= LLVMBuildInsertElement(builder
, out
, z
, imm2
, "");
980 static void resq_emit(
981 const struct lp_build_tgsi_action
*action
,
982 struct lp_build_tgsi_context
*bld_base
,
983 struct lp_build_emit_data
*emit_data
)
985 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
986 LLVMBuilderRef builder
= ctx
->ac
.builder
;
987 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
988 const struct tgsi_full_src_register
*reg
=
989 &inst
->Src
[inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
? 1 : 0];
991 if (reg
->Register
.File
== TGSI_FILE_BUFFER
) {
992 LLVMValueRef rsrc
= shader_buffer_fetch_rsrc(ctx
, reg
, false);
994 emit_data
->output
[emit_data
->chan
] =
995 LLVMBuildExtractElement(builder
, rsrc
,
996 LLVMConstInt(ctx
->i32
, 2, 0), "");
1000 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
&&
1001 inst
->Texture
.Texture
== TGSI_TEXTURE_BUFFER
) {
1004 tex_fetch_ptrs(bld_base
, emit_data
, &rsrc
, NULL
, NULL
);
1005 /* Read the size from the buffer descriptor directly. */
1006 emit_data
->output
[emit_data
->chan
] =
1007 get_buffer_size(bld_base
, rsrc
);
1011 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_RESQ
&&
1012 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
1015 image_fetch_rsrc(bld_base
, reg
, false, inst
->Memory
.Texture
, &rsrc
);
1016 emit_data
->output
[emit_data
->chan
] =
1017 get_buffer_size(bld_base
, rsrc
);
1023 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
) {
1024 target
= inst
->Texture
.Texture
;
1026 if (inst
->Memory
.Texture
== TGSI_TEXTURE_3D
)
1027 target
= TGSI_TEXTURE_2D_ARRAY
;
1029 target
= inst
->Memory
.Texture
;
1032 struct ac_image_args args
= {};
1033 args
.opcode
= ac_image_get_resinfo
;
1034 args
.dim
= ac_texture_dim_from_tgsi_target(ctx
->screen
, target
);
1037 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
) {
1038 tex_fetch_ptrs(bld_base
, emit_data
, &args
.resource
, NULL
, NULL
);
1039 args
.lod
= lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_X
);
1041 image_fetch_rsrc(bld_base
, reg
, false, target
, &args
.resource
);
1042 args
.lod
= ctx
->i32_0
;
1045 emit_data
->output
[emit_data
->chan
] =
1046 fix_resinfo(ctx
, target
, ac_build_image_opcode(&ctx
->ac
, &args
));
1050 * Load an image view, fmask view. or sampler state descriptor.
1052 LLVMValueRef
si_load_sampler_desc(struct si_shader_context
*ctx
,
1053 LLVMValueRef list
, LLVMValueRef index
,
1054 enum ac_descriptor_type type
)
1056 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1060 /* The image is at [0:7]. */
1061 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 2, 0), "");
1063 case AC_DESC_BUFFER
:
1064 /* The buffer is in [4:7]. */
1065 index
= ac_build_imad(&ctx
->ac
, index
, LLVMConstInt(ctx
->i32
, 4, 0),
1067 list
= LLVMBuildPointerCast(builder
, list
,
1068 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
1071 /* The FMASK is at [8:15]. */
1072 index
= ac_build_imad(&ctx
->ac
, index
, LLVMConstInt(ctx
->i32
, 2, 0),
1075 case AC_DESC_SAMPLER
:
1076 /* The sampler state is at [12:15]. */
1077 index
= ac_build_imad(&ctx
->ac
, index
, LLVMConstInt(ctx
->i32
, 4, 0),
1078 LLVMConstInt(ctx
->i32
, 3, 0));
1079 list
= LLVMBuildPointerCast(builder
, list
,
1080 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
1084 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
1087 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
1090 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
1091 * filtering manually. The driver sets img7 to a mask clearing
1092 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
1093 * s_and_b32 samp0, samp0, img7
1096 * The ANISO_OVERRIDE sampler field enables this fix in TA.
1098 static LLVMValueRef
sici_fix_sampler_aniso(struct si_shader_context
*ctx
,
1099 LLVMValueRef res
, LLVMValueRef samp
)
1101 LLVMValueRef img7
, samp0
;
1103 if (ctx
->screen
->info
.chip_class
>= VI
)
1106 img7
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
1107 LLVMConstInt(ctx
->i32
, 7, 0), "");
1108 samp0
= LLVMBuildExtractElement(ctx
->ac
.builder
, samp
,
1110 samp0
= LLVMBuildAnd(ctx
->ac
.builder
, samp0
, img7
, "");
1111 return LLVMBuildInsertElement(ctx
->ac
.builder
, samp
, samp0
,
1115 static void tex_fetch_ptrs(struct lp_build_tgsi_context
*bld_base
,
1116 struct lp_build_emit_data
*emit_data
,
1117 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
,
1118 LLVMValueRef
*fmask_ptr
)
1120 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1121 LLVMValueRef list
= LLVMGetParam(ctx
->main_fn
, ctx
->param_samplers_and_images
);
1122 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1123 const struct tgsi_full_src_register
*reg
;
1124 unsigned target
= inst
->Texture
.Texture
;
1125 unsigned sampler_src
;
1128 sampler_src
= emit_data
->inst
->Instruction
.NumSrcRegs
- 1;
1129 reg
= &emit_data
->inst
->Src
[sampler_src
];
1131 if (reg
->Register
.Indirect
) {
1132 index
= si_get_bounded_indirect_index(ctx
,
1134 reg
->Register
.Index
,
1136 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
1137 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
/ 2, 0), "");
1139 index
= LLVMConstInt(ctx
->i32
,
1140 si_get_sampler_slot(reg
->Register
.Index
), 0);
1143 if (reg
->Register
.File
!= TGSI_FILE_SAMPLER
) {
1144 /* Bindless descriptors are accessible from a different pair of
1145 * user SGPR indices.
1147 list
= LLVMGetParam(ctx
->main_fn
,
1148 ctx
->param_bindless_samplers_and_images
);
1149 index
= lp_build_emit_fetch_src(bld_base
, reg
,
1150 TGSI_TYPE_UNSIGNED
, 0);
1152 /* Since bindless handle arithmetic can contain an unsigned integer
1153 * wraparound and si_load_sampler_desc assumes there isn't any,
1154 * use GEP without "inbounds" (inside ac_build_pointer_add)
1155 * to prevent incorrect code generation and hangs.
1157 index
= LLVMBuildMul(ctx
->ac
.builder
, index
, LLVMConstInt(ctx
->i32
, 2, 0), "");
1158 list
= ac_build_pointer_add(&ctx
->ac
, list
, index
);
1162 if (target
== TGSI_TEXTURE_BUFFER
)
1163 *res_ptr
= si_load_sampler_desc(ctx
, list
, index
, AC_DESC_BUFFER
);
1165 *res_ptr
= si_load_sampler_desc(ctx
, list
, index
, AC_DESC_IMAGE
);
1172 if (target
== TGSI_TEXTURE_2D_MSAA
||
1173 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1175 *fmask_ptr
= si_load_sampler_desc(ctx
, list
, index
,
1177 } else if (target
!= TGSI_TEXTURE_BUFFER
) {
1179 *samp_ptr
= si_load_sampler_desc(ctx
, list
, index
,
1181 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
1186 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
1187 * incorrectly forces nearest filtering if the texture format is integer.
1188 * The only effect it has on Gather4, which always returns 4 texels for
1189 * bilinear filtering, is that the final coordinates are off by 0.5 of
1192 * The workaround is to subtract 0.5 from the unnormalized coordinates,
1193 * or (0.5 / size) from the normalized coordinates.
1195 * However, cube textures with 8_8_8_8 data formats require a different
1196 * workaround of overriding the num format to USCALED/SSCALED. This would lose
1197 * precision in 32-bit data formats, so it needs to be applied dynamically at
1198 * runtime. In this case, return an i1 value that indicates whether the
1199 * descriptor was overridden (and hence a fixup of the sampler result is needed).
1202 si_lower_gather4_integer(struct si_shader_context
*ctx
,
1203 struct ac_image_args
*args
,
1205 enum tgsi_return_type return_type
)
1207 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1208 LLVMValueRef wa_8888
= NULL
;
1209 LLVMValueRef half_texel
[2];
1211 assert(return_type
== TGSI_RETURN_TYPE_SINT
||
1212 return_type
== TGSI_RETURN_TYPE_UINT
);
1214 if (target
== TGSI_TEXTURE_CUBE
||
1215 target
== TGSI_TEXTURE_CUBE_ARRAY
) {
1216 LLVMValueRef formats
;
1217 LLVMValueRef data_format
;
1218 LLVMValueRef wa_formats
;
1220 formats
= LLVMBuildExtractElement(builder
, args
->resource
, ctx
->i32_1
, "");
1222 data_format
= LLVMBuildLShr(builder
, formats
,
1223 LLVMConstInt(ctx
->i32
, 20, false), "");
1224 data_format
= LLVMBuildAnd(builder
, data_format
,
1225 LLVMConstInt(ctx
->i32
, (1u << 6) - 1, false), "");
1226 wa_8888
= LLVMBuildICmp(
1227 builder
, LLVMIntEQ
, data_format
,
1228 LLVMConstInt(ctx
->i32
, V_008F14_IMG_DATA_FORMAT_8_8_8_8
, false),
1231 uint32_t wa_num_format
=
1232 return_type
== TGSI_RETURN_TYPE_UINT
?
1233 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_USCALED
) :
1234 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_SSCALED
);
1235 wa_formats
= LLVMBuildAnd(builder
, formats
,
1236 LLVMConstInt(ctx
->i32
, C_008F14_NUM_FORMAT_GFX6
, false),
1238 wa_formats
= LLVMBuildOr(builder
, wa_formats
,
1239 LLVMConstInt(ctx
->i32
, wa_num_format
, false), "");
1241 formats
= LLVMBuildSelect(builder
, wa_8888
, wa_formats
, formats
, "");
1242 args
->resource
= LLVMBuildInsertElement(
1243 builder
, args
->resource
, formats
, ctx
->i32_1
, "");
1246 if (target
== TGSI_TEXTURE_RECT
||
1247 target
== TGSI_TEXTURE_SHADOWRECT
) {
1249 half_texel
[0] = half_texel
[1] = LLVMConstReal(ctx
->f32
, -0.5);
1251 struct ac_image_args resinfo
= {};
1252 struct lp_build_if_state if_ctx
;
1255 /* Skip the texture size query entirely if we don't need it. */
1256 lp_build_if(&if_ctx
, &ctx
->gallivm
, LLVMBuildNot(builder
, wa_8888
, ""));
1259 /* Query the texture size. */
1260 resinfo
.opcode
= ac_image_get_resinfo
;
1261 resinfo
.dim
= ac_texture_dim_from_tgsi_target(ctx
->screen
, target
);
1262 resinfo
.resource
= args
->resource
;
1263 resinfo
.sampler
= args
->sampler
;
1264 resinfo
.lod
= ctx
->ac
.i32_0
;
1265 resinfo
.dmask
= 0xf;
1267 LLVMValueRef texsize
=
1268 fix_resinfo(ctx
, target
,
1269 ac_build_image_opcode(&ctx
->ac
, &resinfo
));
1271 /* Compute -0.5 / size. */
1272 for (unsigned c
= 0; c
< 2; c
++) {
1274 LLVMBuildExtractElement(builder
, texsize
,
1275 LLVMConstInt(ctx
->i32
, c
, 0), "");
1276 half_texel
[c
] = LLVMBuildUIToFP(builder
, half_texel
[c
], ctx
->f32
, "");
1277 half_texel
[c
] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, half_texel
[c
]);
1278 half_texel
[c
] = LLVMBuildFMul(builder
, half_texel
[c
],
1279 LLVMConstReal(ctx
->f32
, -0.5), "");
1283 lp_build_endif(&if_ctx
);
1285 LLVMBasicBlockRef bb
[2] = { if_ctx
.true_block
, if_ctx
.entry_block
};
1287 for (unsigned c
= 0; c
< 2; c
++) {
1288 LLVMValueRef values
[2] = { half_texel
[c
], ctx
->ac
.f32_0
};
1289 half_texel
[c
] = ac_build_phi(&ctx
->ac
, ctx
->f32
, 2,
1295 for (unsigned c
= 0; c
< 2; c
++) {
1297 tmp
= ac_to_float(&ctx
->ac
, args
->coords
[c
]);
1298 tmp
= LLVMBuildFAdd(builder
, tmp
, half_texel
[c
], "");
1299 args
->coords
[c
] = ac_to_integer(&ctx
->ac
, tmp
);
1305 /* The second half of the cube texture 8_8_8_8 integer workaround: adjust the
1306 * result after the gather operation.
1309 si_fix_gather4_integer_result(struct si_shader_context
*ctx
,
1310 LLVMValueRef result
,
1311 enum tgsi_return_type return_type
,
1314 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1316 assert(return_type
== TGSI_RETURN_TYPE_SINT
||
1317 return_type
== TGSI_RETURN_TYPE_UINT
);
1319 for (unsigned chan
= 0; chan
< 4; ++chan
) {
1320 LLVMValueRef chanv
= LLVMConstInt(ctx
->i32
, chan
, false);
1322 LLVMValueRef wa_value
;
1324 value
= LLVMBuildExtractElement(builder
, result
, chanv
, "");
1326 if (return_type
== TGSI_RETURN_TYPE_UINT
)
1327 wa_value
= LLVMBuildFPToUI(builder
, value
, ctx
->i32
, "");
1329 wa_value
= LLVMBuildFPToSI(builder
, value
, ctx
->i32
, "");
1330 wa_value
= ac_to_float(&ctx
->ac
, wa_value
);
1331 value
= LLVMBuildSelect(builder
, wa
, wa_value
, value
, "");
1333 result
= LLVMBuildInsertElement(builder
, result
, value
, chanv
, "");
1339 static void build_tex_intrinsic(const struct lp_build_tgsi_action
*action
,
1340 struct lp_build_tgsi_context
*bld_base
,
1341 struct lp_build_emit_data
*emit_data
)
1343 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1344 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1345 unsigned opcode
= inst
->Instruction
.Opcode
;
1346 unsigned target
= inst
->Texture
.Texture
;
1347 struct ac_image_args args
= {};
1348 int ref_pos
= tgsi_util_get_shadow_ref_src_index(target
);
1350 bool has_offset
= inst
->Texture
.NumOffsets
> 0;
1351 LLVMValueRef fmask_ptr
= NULL
;
1353 tex_fetch_ptrs(bld_base
, emit_data
, &args
.resource
, &args
.sampler
, &fmask_ptr
);
1355 if (target
== TGSI_TEXTURE_BUFFER
) {
1356 LLVMValueRef vindex
= lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_X
);
1357 unsigned num_channels
=
1358 util_last_bit(inst
->Dst
[0].Register
.WriteMask
);
1359 LLVMValueRef result
=
1360 ac_build_buffer_load_format(&ctx
->ac
,
1364 num_channels
, false, true);
1365 emit_data
->output
[emit_data
->chan
] =
1366 ac_build_expand_to_vec4(&ctx
->ac
, result
, num_channels
);
1370 /* Fetch and project texture coordinates */
1371 args
.coords
[3] = lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_W
);
1372 for (chan
= 0; chan
< 3; chan
++) {
1373 args
.coords
[chan
] = lp_build_emit_fetch(bld_base
, inst
, 0, chan
);
1374 if (opcode
== TGSI_OPCODE_TXP
)
1375 args
.coords
[chan
] = ac_build_fdiv(&ctx
->ac
,
1376 args
.coords
[chan
], args
.coords
[3]);
1379 if (opcode
== TGSI_OPCODE_TXP
)
1380 args
.coords
[3] = ctx
->ac
.f32_1
;
1384 opcode
!= TGSI_OPCODE_TXF
&&
1385 opcode
!= TGSI_OPCODE_TXF_LZ
) {
1386 /* The offsets are six-bit signed integers packed like this:
1387 * X=[5:0], Y=[13:8], and Z=[21:16].
1389 LLVMValueRef offset
[3], pack
;
1391 assert(inst
->Texture
.NumOffsets
== 1);
1393 for (chan
= 0; chan
< 3; chan
++) {
1394 offset
[chan
] = lp_build_emit_fetch_texoffset(bld_base
, inst
, 0, chan
);
1395 offset
[chan
] = LLVMBuildAnd(ctx
->ac
.builder
, offset
[chan
],
1396 LLVMConstInt(ctx
->i32
, 0x3f, 0), "");
1398 offset
[chan
] = LLVMBuildShl(ctx
->ac
.builder
, offset
[chan
],
1399 LLVMConstInt(ctx
->i32
, chan
*8, 0), "");
1402 pack
= LLVMBuildOr(ctx
->ac
.builder
, offset
[0], offset
[1], "");
1403 pack
= LLVMBuildOr(ctx
->ac
.builder
, pack
, offset
[2], "");
1407 /* Pack LOD bias value */
1408 if (opcode
== TGSI_OPCODE_TXB
)
1409 args
.bias
= args
.coords
[3];
1410 if (opcode
== TGSI_OPCODE_TXB2
)
1411 args
.bias
= lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1413 /* Pack depth comparison value */
1414 if (tgsi_is_shadow_target(target
) && opcode
!= TGSI_OPCODE_LODQ
) {
1417 if (target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1418 z
= lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1420 assert(ref_pos
>= 0);
1421 z
= args
.coords
[ref_pos
];
1424 /* Section 8.23.1 (Depth Texture Comparison Mode) of the
1425 * OpenGL 4.5 spec says:
1427 * "If the texture’s internal format indicates a fixed-point
1428 * depth texture, then D_t and D_ref are clamped to the
1429 * range [0, 1]; otherwise no clamping is performed."
1431 * TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
1432 * so the depth comparison value isn't clamped for Z16 and
1433 * Z24 anymore. Do it manually here.
1435 if (ctx
->screen
->info
.chip_class
>= VI
) {
1436 LLVMValueRef upgraded
;
1437 LLVMValueRef clamped
;
1438 upgraded
= LLVMBuildExtractElement(ctx
->ac
.builder
, args
.sampler
,
1439 LLVMConstInt(ctx
->i32
, 3, false), "");
1440 upgraded
= LLVMBuildLShr(ctx
->ac
.builder
, upgraded
,
1441 LLVMConstInt(ctx
->i32
, 29, false), "");
1442 upgraded
= LLVMBuildTrunc(ctx
->ac
.builder
, upgraded
, ctx
->i1
, "");
1443 clamped
= ac_build_clamp(&ctx
->ac
, z
);
1444 z
= LLVMBuildSelect(ctx
->ac
.builder
, upgraded
, clamped
, z
, "");
1450 /* Pack user derivatives */
1451 if (opcode
== TGSI_OPCODE_TXD
) {
1452 int param
, num_src_deriv_channels
, num_dst_deriv_channels
;
1455 case TGSI_TEXTURE_3D
:
1456 num_src_deriv_channels
= 3;
1457 num_dst_deriv_channels
= 3;
1459 case TGSI_TEXTURE_2D
:
1460 case TGSI_TEXTURE_SHADOW2D
:
1461 case TGSI_TEXTURE_RECT
:
1462 case TGSI_TEXTURE_SHADOWRECT
:
1463 case TGSI_TEXTURE_2D_ARRAY
:
1464 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1465 num_src_deriv_channels
= 2;
1466 num_dst_deriv_channels
= 2;
1468 case TGSI_TEXTURE_CUBE
:
1469 case TGSI_TEXTURE_SHADOWCUBE
:
1470 case TGSI_TEXTURE_CUBE_ARRAY
:
1471 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
1472 /* Cube derivatives will be converted to 2D. */
1473 num_src_deriv_channels
= 3;
1474 num_dst_deriv_channels
= 3;
1476 case TGSI_TEXTURE_1D
:
1477 case TGSI_TEXTURE_SHADOW1D
:
1478 case TGSI_TEXTURE_1D_ARRAY
:
1479 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1480 num_src_deriv_channels
= 1;
1482 /* 1D textures are allocated and used as 2D on GFX9. */
1483 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
1484 num_dst_deriv_channels
= 2;
1486 num_dst_deriv_channels
= 1;
1490 unreachable("invalid target");
1493 for (param
= 0; param
< 2; param
++) {
1494 for (chan
= 0; chan
< num_src_deriv_channels
; chan
++)
1495 args
.derivs
[param
* num_dst_deriv_channels
+ chan
] =
1496 lp_build_emit_fetch(bld_base
, inst
, param
+1, chan
);
1498 /* Fill in the rest with zeros. */
1499 for (chan
= num_src_deriv_channels
;
1500 chan
< num_dst_deriv_channels
; chan
++)
1501 args
.derivs
[param
* num_dst_deriv_channels
+ chan
] =
1506 if (target
== TGSI_TEXTURE_CUBE
||
1507 target
== TGSI_TEXTURE_CUBE_ARRAY
||
1508 target
== TGSI_TEXTURE_SHADOWCUBE
||
1509 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1510 ac_prepare_cube_coords(&ctx
->ac
,
1511 opcode
== TGSI_OPCODE_TXD
,
1512 target
== TGSI_TEXTURE_CUBE_ARRAY
||
1513 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
,
1514 opcode
== TGSI_OPCODE_LODQ
,
1515 args
.coords
, args
.derivs
);
1516 } else if (tgsi_is_array_sampler(target
) &&
1517 opcode
!= TGSI_OPCODE_TXF
&&
1518 opcode
!= TGSI_OPCODE_TXF_LZ
&&
1519 ctx
->screen
->info
.chip_class
<= VI
) {
1520 unsigned array_coord
= target
== TGSI_TEXTURE_1D_ARRAY
? 1 : 2;
1521 args
.coords
[array_coord
] = ac_build_round(&ctx
->ac
, args
.coords
[array_coord
]);
1524 /* 1D textures are allocated and used as 2D on GFX9. */
1525 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
1526 LLVMValueRef filler
;
1528 /* Use 0.5, so that we don't sample the border color. */
1529 if (opcode
== TGSI_OPCODE_TXF
||
1530 opcode
== TGSI_OPCODE_TXF_LZ
)
1531 filler
= ctx
->i32_0
;
1533 filler
= LLVMConstReal(ctx
->f32
, 0.5);
1535 if (target
== TGSI_TEXTURE_1D
||
1536 target
== TGSI_TEXTURE_SHADOW1D
) {
1537 args
.coords
[1] = filler
;
1538 } else if (target
== TGSI_TEXTURE_1D_ARRAY
||
1539 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
) {
1540 args
.coords
[2] = args
.coords
[1];
1541 args
.coords
[1] = filler
;
1545 /* Pack LOD or sample index */
1546 if (opcode
== TGSI_OPCODE_TXL
)
1547 args
.lod
= args
.coords
[3];
1548 else if (opcode
== TGSI_OPCODE_TXL2
)
1549 args
.lod
= lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1550 else if (opcode
== TGSI_OPCODE_TXF
) {
1551 if (target
== TGSI_TEXTURE_2D_MSAA
) {
1552 /* No LOD, but move sample index into the right place. */
1553 args
.coords
[2] = args
.coords
[3];
1554 } else if (target
!= TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1555 args
.lod
= args
.coords
[3];
1559 if (target
== TGSI_TEXTURE_2D_MSAA
||
1560 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1561 ac_apply_fmask_to_sample(&ctx
->ac
, fmask_ptr
, args
.coords
,
1562 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
);
1565 if (opcode
== TGSI_OPCODE_TXF
||
1566 opcode
== TGSI_OPCODE_TXF_LZ
) {
1567 /* add tex offsets */
1568 if (inst
->Texture
.NumOffsets
) {
1569 const struct tgsi_texture_offset
*off
= inst
->TexOffsets
;
1571 assert(inst
->Texture
.NumOffsets
== 1);
1574 case TGSI_TEXTURE_3D
:
1576 LLVMBuildAdd(ctx
->ac
.builder
, args
.coords
[2],
1577 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleZ
], "");
1579 case TGSI_TEXTURE_2D
:
1580 case TGSI_TEXTURE_SHADOW2D
:
1581 case TGSI_TEXTURE_RECT
:
1582 case TGSI_TEXTURE_SHADOWRECT
:
1583 case TGSI_TEXTURE_2D_ARRAY
:
1584 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1586 LLVMBuildAdd(ctx
->ac
.builder
, args
.coords
[1],
1587 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleY
], "");
1589 case TGSI_TEXTURE_1D
:
1590 case TGSI_TEXTURE_SHADOW1D
:
1591 case TGSI_TEXTURE_1D_ARRAY
:
1592 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1594 LLVMBuildAdd(ctx
->ac
.builder
, args
.coords
[0],
1595 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleX
], "");
1597 /* texture offsets do not apply to other texture targets */
1602 if (opcode
== TGSI_OPCODE_TG4
) {
1603 unsigned gather_comp
= 0;
1605 /* DMASK was repurposed for GATHER4. 4 components are always
1606 * returned and DMASK works like a swizzle - it selects
1607 * the component to fetch. The only valid DMASK values are
1608 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1609 * (red,red,red,red) etc.) The ISA document doesn't mention
1613 /* Get the component index from src1.x for Gather4. */
1614 if (!tgsi_is_shadow_target(target
)) {
1615 LLVMValueRef comp_imm
;
1616 struct tgsi_src_register src1
= inst
->Src
[1].Register
;
1618 assert(src1
.File
== TGSI_FILE_IMMEDIATE
);
1620 comp_imm
= ctx
->imms
[src1
.Index
* TGSI_NUM_CHANNELS
+ src1
.SwizzleX
];
1621 gather_comp
= LLVMConstIntGetZExtValue(comp_imm
);
1622 gather_comp
= CLAMP(gather_comp
, 0, 3);
1625 args
.dmask
= 1 << gather_comp
;
1630 args
.dim
= ac_texture_dim_from_tgsi_target(ctx
->screen
, target
);
1631 args
.unorm
= target
== TGSI_TEXTURE_RECT
||
1632 target
== TGSI_TEXTURE_SHADOWRECT
;
1633 args
.opcode
= ac_image_sample
;
1636 case TGSI_OPCODE_TXF
:
1637 case TGSI_OPCODE_TXF_LZ
:
1638 args
.opcode
= opcode
== TGSI_OPCODE_TXF_LZ
||
1639 target
== TGSI_TEXTURE_2D_MSAA
||
1640 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
?
1641 ac_image_load
: ac_image_load_mip
;
1643 case TGSI_OPCODE_LODQ
:
1644 args
.opcode
= ac_image_get_lod
;
1646 case TGSI_OPCODE_TEX
:
1647 case TGSI_OPCODE_TEX2
:
1648 case TGSI_OPCODE_TXP
:
1649 if (ctx
->type
!= PIPE_SHADER_FRAGMENT
)
1650 args
.level_zero
= true;
1652 case TGSI_OPCODE_TEX_LZ
:
1653 args
.level_zero
= true;
1655 case TGSI_OPCODE_TXB
:
1656 case TGSI_OPCODE_TXB2
:
1657 assert(ctx
->type
== PIPE_SHADER_FRAGMENT
);
1659 case TGSI_OPCODE_TXL
:
1660 case TGSI_OPCODE_TXL2
:
1662 case TGSI_OPCODE_TXD
:
1664 case TGSI_OPCODE_TG4
:
1665 args
.opcode
= ac_image_gather4
;
1666 args
.level_zero
= true;
1673 /* The hardware needs special lowering for Gather4 with integer formats. */
1674 LLVMValueRef gather4_int_result_workaround
= NULL
;
1676 if (ctx
->screen
->info
.chip_class
<= VI
&&
1677 opcode
== TGSI_OPCODE_TG4
) {
1678 assert(inst
->Texture
.ReturnType
!= TGSI_RETURN_TYPE_UNKNOWN
);
1680 if (inst
->Texture
.ReturnType
== TGSI_RETURN_TYPE_SINT
||
1681 inst
->Texture
.ReturnType
== TGSI_RETURN_TYPE_UINT
) {
1682 gather4_int_result_workaround
=
1683 si_lower_gather4_integer(ctx
, &args
, target
,
1684 inst
->Texture
.ReturnType
);
1688 args
.attributes
= AC_FUNC_ATTR_READNONE
;
1689 LLVMValueRef result
= ac_build_image_opcode(&ctx
->ac
, &args
);
1691 if (gather4_int_result_workaround
) {
1692 result
= si_fix_gather4_integer_result(ctx
, result
,
1693 inst
->Texture
.ReturnType
,
1694 gather4_int_result_workaround
);
1697 emit_data
->output
[emit_data
->chan
] = result
;
1700 static void si_llvm_emit_txqs(
1701 const struct lp_build_tgsi_action
*action
,
1702 struct lp_build_tgsi_context
*bld_base
,
1703 struct lp_build_emit_data
*emit_data
)
1705 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1706 LLVMValueRef res
, samples
;
1707 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
;
1709 tex_fetch_ptrs(bld_base
, emit_data
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
1711 /* Read the samples from the descriptor directly. */
1712 res
= LLVMBuildBitCast(ctx
->ac
.builder
, res_ptr
, ctx
->v8i32
, "");
1713 samples
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
1714 LLVMConstInt(ctx
->i32
, 3, 0), "");
1715 samples
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
1716 LLVMConstInt(ctx
->i32
, 16, 0), "");
1717 samples
= LLVMBuildAnd(ctx
->ac
.builder
, samples
,
1718 LLVMConstInt(ctx
->i32
, 0xf, 0), "");
1719 samples
= LLVMBuildShl(ctx
->ac
.builder
, ctx
->i32_1
,
1722 emit_data
->output
[emit_data
->chan
] = samples
;
1725 static void si_llvm_emit_fbfetch(const struct lp_build_tgsi_action
*action
,
1726 struct lp_build_tgsi_context
*bld_base
,
1727 struct lp_build_emit_data
*emit_data
)
1729 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1730 struct ac_image_args args
= {};
1731 LLVMValueRef ptr
, image
, fmask
;
1733 /* Ignore src0, because KHR_blend_func_extended disallows multiple render
1737 /* Load the image descriptor. */
1738 STATIC_ASSERT(SI_PS_IMAGE_COLORBUF0
% 2 == 0);
1739 ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
1740 ptr
= LLVMBuildPointerCast(ctx
->ac
.builder
, ptr
,
1741 ac_array_in_const32_addr_space(ctx
->v8i32
), "");
1742 image
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
,
1743 LLVMConstInt(ctx
->i32
, SI_PS_IMAGE_COLORBUF0
/ 2, 0));
1747 args
.coords
[chan
++] = si_unpack_param(ctx
, SI_PARAM_POS_FIXED_PT
, 0, 16);
1749 if (!ctx
->shader
->key
.mono
.u
.ps
.fbfetch_is_1D
)
1750 args
.coords
[chan
++] = si_unpack_param(ctx
, SI_PARAM_POS_FIXED_PT
, 16, 16);
1752 /* Get the current render target layer index. */
1753 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
)
1754 args
.coords
[chan
++] = si_unpack_param(ctx
, SI_PARAM_ANCILLARY
, 16, 11);
1756 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_msaa
)
1757 args
.coords
[chan
++] = si_get_sample_id(ctx
);
1759 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_msaa
) {
1760 fmask
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
,
1761 LLVMConstInt(ctx
->i32
, SI_PS_IMAGE_COLORBUF0_FMASK
/ 2, 0));
1763 ac_apply_fmask_to_sample(&ctx
->ac
, fmask
, args
.coords
,
1764 ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
);
1767 args
.opcode
= ac_image_load
;
1768 args
.resource
= image
;
1770 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_msaa
)
1771 args
.dim
= ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
?
1772 ac_image_2darraymsaa
: ac_image_2dmsaa
;
1773 else if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_is_1D
)
1774 args
.dim
= ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
?
1775 ac_image_1darray
: ac_image_1d
;
1777 args
.dim
= ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
?
1778 ac_image_2darray
: ac_image_2d
;
1780 emit_data
->output
[emit_data
->chan
] =
1781 ac_build_image_opcode(&ctx
->ac
, &args
);
1785 * Setup actions for TGSI memory opcode, including texture opcodes.
1787 void si_shader_context_init_mem(struct si_shader_context
*ctx
)
1789 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
1791 bld_base
->op_actions
[TGSI_OPCODE_TEX
].emit
= build_tex_intrinsic
;
1792 bld_base
->op_actions
[TGSI_OPCODE_TEX_LZ
].emit
= build_tex_intrinsic
;
1793 bld_base
->op_actions
[TGSI_OPCODE_TEX2
].emit
= build_tex_intrinsic
;
1794 bld_base
->op_actions
[TGSI_OPCODE_TXB
].emit
= build_tex_intrinsic
;
1795 bld_base
->op_actions
[TGSI_OPCODE_TXB2
].emit
= build_tex_intrinsic
;
1796 bld_base
->op_actions
[TGSI_OPCODE_TXD
].emit
= build_tex_intrinsic
;
1797 bld_base
->op_actions
[TGSI_OPCODE_TXF
].emit
= build_tex_intrinsic
;
1798 bld_base
->op_actions
[TGSI_OPCODE_TXF_LZ
].emit
= build_tex_intrinsic
;
1799 bld_base
->op_actions
[TGSI_OPCODE_TXL
].emit
= build_tex_intrinsic
;
1800 bld_base
->op_actions
[TGSI_OPCODE_TXL2
].emit
= build_tex_intrinsic
;
1801 bld_base
->op_actions
[TGSI_OPCODE_TXP
].emit
= build_tex_intrinsic
;
1802 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].emit
= resq_emit
;
1803 bld_base
->op_actions
[TGSI_OPCODE_TG4
].emit
= build_tex_intrinsic
;
1804 bld_base
->op_actions
[TGSI_OPCODE_LODQ
].emit
= build_tex_intrinsic
;
1805 bld_base
->op_actions
[TGSI_OPCODE_TXQS
].emit
= si_llvm_emit_txqs
;
1807 bld_base
->op_actions
[TGSI_OPCODE_FBFETCH
].emit
= si_llvm_emit_fbfetch
;
1809 bld_base
->op_actions
[TGSI_OPCODE_LOAD
].emit
= load_emit
;
1810 bld_base
->op_actions
[TGSI_OPCODE_STORE
].emit
= store_emit
;
1811 bld_base
->op_actions
[TGSI_OPCODE_RESQ
].emit
= resq_emit
;
1813 bld_base
->op_actions
[TGSI_OPCODE_ATOMUADD
].emit
= atomic_emit
;
1814 bld_base
->op_actions
[TGSI_OPCODE_ATOMUADD
].intr_name
= "add";
1815 bld_base
->op_actions
[TGSI_OPCODE_ATOMXCHG
].emit
= atomic_emit
;
1816 bld_base
->op_actions
[TGSI_OPCODE_ATOMXCHG
].intr_name
= "swap";
1817 bld_base
->op_actions
[TGSI_OPCODE_ATOMCAS
].emit
= atomic_emit
;
1818 bld_base
->op_actions
[TGSI_OPCODE_ATOMCAS
].intr_name
= "cmpswap";
1819 bld_base
->op_actions
[TGSI_OPCODE_ATOMAND
].emit
= atomic_emit
;
1820 bld_base
->op_actions
[TGSI_OPCODE_ATOMAND
].intr_name
= "and";
1821 bld_base
->op_actions
[TGSI_OPCODE_ATOMOR
].emit
= atomic_emit
;
1822 bld_base
->op_actions
[TGSI_OPCODE_ATOMOR
].intr_name
= "or";
1823 bld_base
->op_actions
[TGSI_OPCODE_ATOMXOR
].emit
= atomic_emit
;
1824 bld_base
->op_actions
[TGSI_OPCODE_ATOMXOR
].intr_name
= "xor";
1825 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMIN
].emit
= atomic_emit
;
1826 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMIN
].intr_name
= "umin";
1827 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMAX
].emit
= atomic_emit
;
1828 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMAX
].intr_name
= "umax";
1829 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMIN
].emit
= atomic_emit
;
1830 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMIN
].intr_name
= "smin";
1831 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMAX
].emit
= atomic_emit
;
1832 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMAX
].intr_name
= "smax";