2 * Copyright 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "si_shader_internal.h"
27 #include "gallivm/lp_bld_arit.h"
28 #include "gallivm/lp_bld_gather.h"
29 #include "gallivm/lp_bld_intr.h"
30 #include "tgsi/tgsi_build.h"
31 #include "tgsi/tgsi_parse.h"
32 #include "tgsi/tgsi_util.h"
34 static void build_tex_intrinsic(const struct lp_build_tgsi_action
*action
,
35 struct lp_build_tgsi_context
*bld_base
,
36 struct lp_build_emit_data
*emit_data
);
38 static const struct lp_build_tgsi_action tex_action
;
41 * Given a v8i32 resource descriptor for a buffer, extract the size of the
42 * buffer in number of elements and return it as an i32.
44 static LLVMValueRef
get_buffer_size(
45 struct lp_build_tgsi_context
*bld_base
,
46 LLVMValueRef descriptor
)
48 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
49 LLVMBuilderRef builder
= ctx
->ac
.builder
;
51 LLVMBuildExtractElement(builder
, descriptor
,
52 LLVMConstInt(ctx
->i32
, 2, 0), "");
54 if (ctx
->screen
->b
.chip_class
== VI
) {
55 /* On VI, the descriptor contains the size in bytes,
56 * but TXQ must return the size in elements.
57 * The stride is always non-zero for resources using TXQ.
60 LLVMBuildExtractElement(builder
, descriptor
,
62 stride
= LLVMBuildLShr(builder
, stride
,
63 LLVMConstInt(ctx
->i32
, 16, 0), "");
64 stride
= LLVMBuildAnd(builder
, stride
,
65 LLVMConstInt(ctx
->i32
, 0x3FFF, 0), "");
67 size
= LLVMBuildUDiv(builder
, size
, stride
, "");
74 shader_buffer_fetch_rsrc(struct si_shader_context
*ctx
,
75 const struct tgsi_full_src_register
*reg
,
80 if (!reg
->Register
.Indirect
) {
81 index
= LLVMConstInt(ctx
->i32
, reg
->Register
.Index
, false);
83 index
= si_get_indirect_index(ctx
, ®
->Indirect
,
84 1, reg
->Register
.Index
);
88 return ctx
->abi
.load_ubo(&ctx
->abi
, index
);
90 return ctx
->abi
.load_ssbo(&ctx
->abi
, index
, false);
93 static bool tgsi_is_array_image(unsigned target
)
95 return target
== TGSI_TEXTURE_3D
||
96 target
== TGSI_TEXTURE_CUBE
||
97 target
== TGSI_TEXTURE_1D_ARRAY
||
98 target
== TGSI_TEXTURE_2D_ARRAY
||
99 target
== TGSI_TEXTURE_CUBE_ARRAY
||
100 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
;
104 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
106 * At least on Tonga, executing image stores on images with DCC enabled and
107 * non-trivial can eventually lead to lockups. This can occur when an
108 * application binds an image as read-only but then uses a shader that writes
109 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
110 * program termination) in this case, but it doesn't cost much to be a bit
111 * nicer: disabling DCC in the shader still leads to undefined results but
114 static LLVMValueRef
force_dcc_off(struct si_shader_context
*ctx
,
117 if (ctx
->screen
->b
.chip_class
<= CIK
) {
120 LLVMValueRef i32_6
= LLVMConstInt(ctx
->i32
, 6, 0);
121 LLVMValueRef i32_C
= LLVMConstInt(ctx
->i32
, C_008F28_COMPRESSION_EN
, 0);
124 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, rsrc
, i32_6
, "");
125 tmp
= LLVMBuildAnd(ctx
->ac
.builder
, tmp
, i32_C
, "");
126 return LLVMBuildInsertElement(ctx
->ac
.builder
, rsrc
, tmp
, i32_6
, "");
130 LLVMValueRef
si_load_image_desc(struct si_shader_context
*ctx
,
131 LLVMValueRef list
, LLVMValueRef index
,
132 enum ac_descriptor_type desc_type
, bool dcc_off
)
134 LLVMBuilderRef builder
= ctx
->ac
.builder
;
137 if (desc_type
== AC_DESC_BUFFER
) {
138 index
= LLVMBuildMul(builder
, index
,
139 LLVMConstInt(ctx
->i32
, 2, 0), "");
140 index
= LLVMBuildAdd(builder
, index
,
142 list
= LLVMBuildPointerCast(builder
, list
,
143 si_const_array(ctx
->v4i32
, 0), "");
145 assert(desc_type
== AC_DESC_IMAGE
);
148 rsrc
= ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
150 rsrc
= force_dcc_off(ctx
, rsrc
);
155 * Load the resource descriptor for \p image.
159 struct lp_build_tgsi_context
*bld_base
,
160 const struct tgsi_full_src_register
*image
,
161 bool is_store
, unsigned target
,
164 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
165 LLVMValueRef rsrc_ptr
= LLVMGetParam(ctx
->main_fn
,
166 ctx
->param_samplers_and_images
);
168 bool dcc_off
= is_store
;
170 if (!image
->Register
.Indirect
) {
171 const struct tgsi_shader_info
*info
= bld_base
->info
;
172 unsigned images_writemask
= info
->images_store
|
175 index
= LLVMConstInt(ctx
->i32
,
176 si_get_image_slot(image
->Register
.Index
), 0);
178 if (images_writemask
& (1 << image
->Register
.Index
))
181 /* From the GL_ARB_shader_image_load_store extension spec:
183 * If a shader performs an image load, store, or atomic
184 * operation using an image variable declared as an array,
185 * and if the index used to select an individual element is
186 * negative or greater than or equal to the size of the
187 * array, the results of the operation are undefined but may
188 * not lead to termination.
190 index
= si_get_bounded_indirect_index(ctx
, &image
->Indirect
,
191 image
->Register
.Index
,
193 index
= LLVMBuildSub(ctx
->ac
.builder
,
194 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
- 1, 0),
198 if (image
->Register
.File
!= TGSI_FILE_IMAGE
) {
199 /* Bindless descriptors are accessible from a different pair of
202 rsrc_ptr
= LLVMGetParam(ctx
->main_fn
,
203 ctx
->param_bindless_samplers_and_images
);
204 index
= lp_build_emit_fetch_src(bld_base
, image
,
205 TGSI_TYPE_UNSIGNED
, 0);
207 /* For simplicity, bindless image descriptors use fixed
208 * 16-dword slots for now.
210 index
= LLVMBuildMul(ctx
->ac
.builder
, index
,
211 LLVMConstInt(ctx
->i32
, 2, 0), "");
214 *rsrc
= si_load_image_desc(ctx
, rsrc_ptr
, index
,
215 target
== TGSI_TEXTURE_BUFFER
? AC_DESC_BUFFER
: AC_DESC_IMAGE
,
219 static LLVMValueRef
image_fetch_coords(
220 struct lp_build_tgsi_context
*bld_base
,
221 const struct tgsi_full_instruction
*inst
,
222 unsigned src
, LLVMValueRef desc
)
224 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
225 LLVMBuilderRef builder
= ctx
->ac
.builder
;
226 unsigned target
= inst
->Memory
.Texture
;
227 unsigned num_coords
= tgsi_util_get_texture_coord_dim(target
);
228 LLVMValueRef coords
[4];
232 for (chan
= 0; chan
< num_coords
; ++chan
) {
233 tmp
= lp_build_emit_fetch(bld_base
, inst
, src
, chan
);
234 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
238 if (ctx
->screen
->b
.chip_class
>= GFX9
) {
239 /* 1D textures are allocated and used as 2D on GFX9. */
240 if (target
== TGSI_TEXTURE_1D
) {
241 coords
[1] = ctx
->i32_0
;
243 } else if (target
== TGSI_TEXTURE_1D_ARRAY
) {
244 coords
[2] = coords
[1];
245 coords
[1] = ctx
->i32_0
;
247 } else if (target
== TGSI_TEXTURE_2D
) {
248 /* The hw can't bind a slice of a 3D image as a 2D
249 * image, because it ignores BASE_ARRAY if the target
250 * is 3D. The workaround is to read BASE_ARRAY and set
251 * it as the 3rd address operand for all 2D images.
253 LLVMValueRef first_layer
, const5
, mask
;
255 const5
= LLVMConstInt(ctx
->i32
, 5, 0);
256 mask
= LLVMConstInt(ctx
->i32
, S_008F24_BASE_ARRAY(~0), 0);
257 first_layer
= LLVMBuildExtractElement(builder
, desc
, const5
, "");
258 first_layer
= LLVMBuildAnd(builder
, first_layer
, mask
, "");
260 coords
[2] = first_layer
;
268 if (num_coords
== 3) {
269 /* LLVM has difficulties lowering 3-element vectors. */
270 coords
[3] = bld_base
->uint_bld
.undef
;
274 return lp_build_gather_values(&ctx
->gallivm
, coords
, num_coords
);
278 * Append the extra mode bits that are used by image load and store.
280 static void image_append_args(
281 struct si_shader_context
*ctx
,
282 struct lp_build_emit_data
* emit_data
,
287 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
288 LLVMValueRef i1false
= LLVMConstInt(ctx
->i1
, 0, 0);
289 LLVMValueRef i1true
= LLVMConstInt(ctx
->i1
, 1, 0);
290 LLVMValueRef r128
= i1false
;
291 LLVMValueRef da
= tgsi_is_array_image(target
) ? i1true
: i1false
;
294 inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
) ?
296 LLVMValueRef slc
= i1false
;
297 LLVMValueRef lwe
= i1false
;
299 if (atomic
|| (HAVE_LLVM
<= 0x0309)) {
300 emit_data
->args
[emit_data
->arg_count
++] = r128
;
301 emit_data
->args
[emit_data
->arg_count
++] = da
;
303 emit_data
->args
[emit_data
->arg_count
++] = glc
;
305 emit_data
->args
[emit_data
->arg_count
++] = slc
;
309 /* HAVE_LLVM >= 0x0400 */
310 emit_data
->args
[emit_data
->arg_count
++] = glc
;
311 emit_data
->args
[emit_data
->arg_count
++] = slc
;
312 emit_data
->args
[emit_data
->arg_count
++] = lwe
;
313 emit_data
->args
[emit_data
->arg_count
++] = da
;
317 * Append the resource and indexing arguments for buffer intrinsics.
319 * \param rsrc the v4i32 buffer resource
320 * \param index index into the buffer (stride-based)
321 * \param offset byte offset into the buffer
323 static void buffer_append_args(
324 struct si_shader_context
*ctx
,
325 struct lp_build_emit_data
*emit_data
,
332 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
333 LLVMValueRef i1false
= LLVMConstInt(ctx
->i1
, 0, 0);
334 LLVMValueRef i1true
= LLVMConstInt(ctx
->i1
, 1, 0);
336 emit_data
->args
[emit_data
->arg_count
++] = rsrc
;
337 emit_data
->args
[emit_data
->arg_count
++] = index
; /* vindex */
338 emit_data
->args
[emit_data
->arg_count
++] = offset
; /* voffset */
340 emit_data
->args
[emit_data
->arg_count
++] =
342 inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
) ?
343 i1true
: i1false
; /* glc */
345 emit_data
->args
[emit_data
->arg_count
++] = i1false
; /* slc */
348 static void load_fetch_args(
349 struct lp_build_tgsi_context
* bld_base
,
350 struct lp_build_emit_data
* emit_data
)
352 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
353 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
354 unsigned target
= inst
->Memory
.Texture
;
357 emit_data
->dst_type
= ctx
->v4f32
;
359 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
360 inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
) {
364 bool ubo
= inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
;
365 rsrc
= shader_buffer_fetch_rsrc(ctx
, &inst
->Src
[0], ubo
);
367 tmp
= lp_build_emit_fetch(bld_base
, inst
, 1, 0);
368 offset
= ac_to_integer(&ctx
->ac
, tmp
);
370 buffer_append_args(ctx
, emit_data
, rsrc
, ctx
->i32_0
,
371 offset
, false, false);
372 } else if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
||
373 tgsi_is_bindless_image_file(inst
->Src
[0].Register
.File
)) {
376 image_fetch_rsrc(bld_base
, &inst
->Src
[0], false, target
, &rsrc
);
377 coords
= image_fetch_coords(bld_base
, inst
, 1, rsrc
);
379 if (target
== TGSI_TEXTURE_BUFFER
) {
380 buffer_append_args(ctx
, emit_data
, rsrc
, coords
,
381 ctx
->i32_0
, false, false);
383 emit_data
->args
[0] = coords
;
384 emit_data
->args
[1] = rsrc
;
385 emit_data
->args
[2] = LLVMConstInt(ctx
->i32
, 15, 0); /* dmask */
386 emit_data
->arg_count
= 3;
388 image_append_args(ctx
, emit_data
, target
, false, false);
393 static unsigned get_load_intr_attribs(bool can_speculate
)
395 /* READNONE means writes can't affect it, while READONLY means that
396 * writes can affect it. */
397 return can_speculate
&& HAVE_LLVM
>= 0x0400 ?
398 LP_FUNC_ATTR_READNONE
:
399 LP_FUNC_ATTR_READONLY
;
402 static unsigned get_store_intr_attribs(bool writeonly_memory
)
404 return writeonly_memory
&& HAVE_LLVM
>= 0x0400 ?
405 LP_FUNC_ATTR_INACCESSIBLE_MEM_ONLY
:
406 LP_FUNC_ATTR_WRITEONLY
;
409 static void load_emit_buffer(struct si_shader_context
*ctx
,
410 struct lp_build_emit_data
*emit_data
,
411 bool can_speculate
, bool allow_smem
)
413 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
414 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
415 uint count
= util_last_bit(writemask
);
416 LLVMValueRef
*args
= emit_data
->args
;
418 /* Don't use SMEM for shader buffer loads, because LLVM doesn't
419 * select SMEM for SI.load.const with a non-constant offset, and
420 * constant offsets practically don't exist with shader buffers.
422 * Also, SI.load.const doesn't use inst_offset when it's lowered
423 * to VMEM, so we just end up with more VALU instructions in the end
426 * TODO: Remove this line once LLVM can select SMEM with a non-constant
427 * offset, and can derive inst_offset when VMEM is selected.
428 * After that, si_memory_barrier should invalidate sL1 for shader
432 assert(LLVMConstIntGetZExtValue(args
[1]) == 0); /* vindex */
433 emit_data
->output
[emit_data
->chan
] =
434 ac_build_buffer_load(&ctx
->ac
, args
[0], count
, NULL
,
436 LLVMConstIntGetZExtValue(args
[3]),
437 LLVMConstIntGetZExtValue(args
[4]),
438 can_speculate
, allow_smem
);
441 static LLVMValueRef
get_memory_ptr(struct si_shader_context
*ctx
,
442 const struct tgsi_full_instruction
*inst
,
443 LLVMTypeRef type
, int arg
)
445 LLVMBuilderRef builder
= ctx
->ac
.builder
;
446 LLVMValueRef offset
, ptr
;
449 offset
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, arg
, 0);
450 offset
= ac_to_integer(&ctx
->ac
, offset
);
452 ptr
= ctx
->shared_memory
;
453 ptr
= LLVMBuildGEP(builder
, ptr
, &offset
, 1, "");
454 addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
455 ptr
= LLVMBuildBitCast(builder
, ptr
, LLVMPointerType(type
, addr_space
), "");
460 static void load_emit_memory(
461 struct si_shader_context
*ctx
,
462 struct lp_build_emit_data
*emit_data
)
464 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
465 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
466 LLVMValueRef channels
[4], ptr
, derived_ptr
, index
;
469 ptr
= get_memory_ptr(ctx
, inst
, ctx
->f32
, 1);
471 for (chan
= 0; chan
< 4; ++chan
) {
472 if (!(writemask
& (1 << chan
))) {
473 channels
[chan
] = LLVMGetUndef(ctx
->f32
);
477 index
= LLVMConstInt(ctx
->i32
, chan
, 0);
478 derived_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ptr
, &index
, 1, "");
479 channels
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, derived_ptr
, "");
481 emit_data
->output
[emit_data
->chan
] = lp_build_gather_values(&ctx
->gallivm
, channels
, 4);
485 * Return true if the memory accessed by a LOAD or STORE instruction is
486 * read-only or write-only, respectively.
488 * \param shader_buffers_reverse_access_mask
489 * For LOAD, set this to (store | atomic) slot usage in the shader.
490 * For STORE, set this to (load | atomic) slot usage in the shader.
491 * \param images_reverse_access_mask Same as above, but for images.
493 static bool is_oneway_access_only(const struct tgsi_full_instruction
*inst
,
494 const struct tgsi_shader_info
*info
,
495 unsigned shader_buffers_reverse_access_mask
,
496 unsigned images_reverse_access_mask
)
498 /* RESTRICT means NOALIAS.
499 * If there are no writes, we can assume the accessed memory is read-only.
500 * If there are no reads, we can assume the accessed memory is write-only.
502 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_RESTRICT
) {
503 unsigned reverse_access_mask
;
505 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
506 reverse_access_mask
= shader_buffers_reverse_access_mask
;
507 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
508 reverse_access_mask
= info
->images_buffers
&
509 images_reverse_access_mask
;
511 reverse_access_mask
= ~info
->images_buffers
&
512 images_reverse_access_mask
;
515 if (inst
->Src
[0].Register
.Indirect
) {
516 if (!reverse_access_mask
)
519 if (!(reverse_access_mask
&
520 (1u << inst
->Src
[0].Register
.Index
)))
525 /* If there are no buffer writes (for both shader buffers & image
526 * buffers), it implies that buffer memory is read-only.
527 * If there are no buffer reads (for both shader buffers & image
528 * buffers), it implies that buffer memory is write-only.
530 * Same for the case when there are no writes/reads for non-buffer
533 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
534 (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
&&
535 (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
||
536 tgsi_is_bindless_image_file(inst
->Src
[0].Register
.File
)))) {
537 if (!shader_buffers_reverse_access_mask
&&
538 !(info
->images_buffers
& images_reverse_access_mask
))
541 if (!(~info
->images_buffers
& images_reverse_access_mask
))
547 static void load_emit(
548 const struct lp_build_tgsi_action
*action
,
549 struct lp_build_tgsi_context
*bld_base
,
550 struct lp_build_emit_data
*emit_data
)
552 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
553 LLVMBuilderRef builder
= ctx
->ac
.builder
;
554 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
555 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
556 char intrinsic_name
[64];
557 bool can_speculate
= false;
559 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
) {
560 load_emit_memory(ctx
, emit_data
);
564 if (inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
) {
565 load_emit_buffer(ctx
, emit_data
, true, true);
569 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
570 si_emit_waitcnt(ctx
, VM_CNT
);
572 can_speculate
= !(inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
) &&
573 is_oneway_access_only(inst
, info
,
574 info
->shader_buffers_store
|
575 info
->shader_buffers_atomic
,
577 info
->images_atomic
);
579 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
580 load_emit_buffer(ctx
, emit_data
, can_speculate
, false);
584 if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
585 emit_data
->output
[emit_data
->chan
] =
587 builder
, "llvm.amdgcn.buffer.load.format.v4f32", emit_data
->dst_type
,
588 emit_data
->args
, emit_data
->arg_count
,
589 get_load_intr_attribs(can_speculate
));
591 ac_get_image_intr_name("llvm.amdgcn.image.load",
592 emit_data
->dst_type
, /* vdata */
593 LLVMTypeOf(emit_data
->args
[0]), /* coords */
594 LLVMTypeOf(emit_data
->args
[1]), /* rsrc */
595 intrinsic_name
, sizeof(intrinsic_name
));
597 emit_data
->output
[emit_data
->chan
] =
599 builder
, intrinsic_name
, emit_data
->dst_type
,
600 emit_data
->args
, emit_data
->arg_count
,
601 get_load_intr_attribs(can_speculate
));
605 static void store_fetch_args(
606 struct lp_build_tgsi_context
* bld_base
,
607 struct lp_build_emit_data
* emit_data
)
609 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
610 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
611 struct tgsi_full_src_register memory
;
612 LLVMValueRef chans
[4];
617 emit_data
->dst_type
= ctx
->voidt
;
619 for (chan
= 0; chan
< 4; ++chan
) {
620 chans
[chan
] = lp_build_emit_fetch(bld_base
, inst
, 1, chan
);
622 data
= lp_build_gather_values(&ctx
->gallivm
, chans
, 4);
624 emit_data
->args
[emit_data
->arg_count
++] = data
;
626 memory
= tgsi_full_src_register_from_dst(&inst
->Dst
[0]);
628 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
) {
632 rsrc
= shader_buffer_fetch_rsrc(ctx
, &memory
, false);
634 tmp
= lp_build_emit_fetch(bld_base
, inst
, 0, 0);
635 offset
= ac_to_integer(&ctx
->ac
, tmp
);
637 buffer_append_args(ctx
, emit_data
, rsrc
, ctx
->i32_0
,
638 offset
, false, false);
639 } else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_IMAGE
||
640 tgsi_is_bindless_image_file(inst
->Dst
[0].Register
.File
)) {
641 unsigned target
= inst
->Memory
.Texture
;
644 /* 8bit/16bit TC L1 write corruption bug on SI.
645 * All store opcodes not aligned to a dword are affected.
647 * The only way to get unaligned stores in radeonsi is through
650 bool force_glc
= ctx
->screen
->b
.chip_class
== SI
;
652 image_fetch_rsrc(bld_base
, &memory
, true, target
, &rsrc
);
653 coords
= image_fetch_coords(bld_base
, inst
, 0, rsrc
);
655 if (target
== TGSI_TEXTURE_BUFFER
) {
656 buffer_append_args(ctx
, emit_data
, rsrc
, coords
,
657 ctx
->i32_0
, false, force_glc
);
659 emit_data
->args
[1] = coords
;
660 emit_data
->args
[2] = rsrc
;
661 emit_data
->args
[3] = LLVMConstInt(ctx
->i32
, 15, 0); /* dmask */
662 emit_data
->arg_count
= 4;
664 image_append_args(ctx
, emit_data
, target
, false, force_glc
);
669 static void store_emit_buffer(
670 struct si_shader_context
*ctx
,
671 struct lp_build_emit_data
*emit_data
,
672 bool writeonly_memory
)
674 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
675 LLVMBuilderRef builder
= ctx
->ac
.builder
;
676 LLVMValueRef base_data
= emit_data
->args
[0];
677 LLVMValueRef base_offset
= emit_data
->args
[3];
678 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
682 const char *intrinsic_name
;
687 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
689 /* Due to an LLVM limitation, split 3-element writes
690 * into a 2-element and a 1-element write. */
692 writemask
|= 1 << (start
+ 2);
698 intrinsic_name
= "llvm.amdgcn.buffer.store.v4f32";
699 } else if (count
== 2) {
700 LLVMTypeRef v2f32
= LLVMVectorType(ctx
->f32
, 2);
702 tmp
= LLVMBuildExtractElement(
704 LLVMConstInt(ctx
->i32
, start
, 0), "");
705 data
= LLVMBuildInsertElement(
706 builder
, LLVMGetUndef(v2f32
), tmp
,
709 tmp
= LLVMBuildExtractElement(
711 LLVMConstInt(ctx
->i32
, start
+ 1, 0), "");
712 data
= LLVMBuildInsertElement(
713 builder
, data
, tmp
, ctx
->i32_1
, "");
715 intrinsic_name
= "llvm.amdgcn.buffer.store.v2f32";
718 data
= LLVMBuildExtractElement(
720 LLVMConstInt(ctx
->i32
, start
, 0), "");
721 intrinsic_name
= "llvm.amdgcn.buffer.store.f32";
724 offset
= base_offset
;
726 offset
= LLVMBuildAdd(
728 LLVMConstInt(ctx
->i32
, start
* 4, 0), "");
731 emit_data
->args
[0] = data
;
732 emit_data
->args
[3] = offset
;
735 builder
, intrinsic_name
, emit_data
->dst_type
,
736 emit_data
->args
, emit_data
->arg_count
,
737 get_store_intr_attribs(writeonly_memory
));
741 static void store_emit_memory(
742 struct si_shader_context
*ctx
,
743 struct lp_build_emit_data
*emit_data
)
745 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
746 LLVMBuilderRef builder
= ctx
->ac
.builder
;
747 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
748 LLVMValueRef ptr
, derived_ptr
, data
, index
;
751 ptr
= get_memory_ptr(ctx
, inst
, ctx
->f32
, 0);
753 for (chan
= 0; chan
< 4; ++chan
) {
754 if (!(writemask
& (1 << chan
))) {
757 data
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, 1, chan
);
758 index
= LLVMConstInt(ctx
->i32
, chan
, 0);
759 derived_ptr
= LLVMBuildGEP(builder
, ptr
, &index
, 1, "");
760 LLVMBuildStore(builder
, data
, derived_ptr
);
764 static void store_emit(
765 const struct lp_build_tgsi_action
*action
,
766 struct lp_build_tgsi_context
*bld_base
,
767 struct lp_build_emit_data
*emit_data
)
769 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
770 LLVMBuilderRef builder
= ctx
->ac
.builder
;
771 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
772 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
773 unsigned target
= inst
->Memory
.Texture
;
774 char intrinsic_name
[64];
775 bool writeonly_memory
= false;
777 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_MEMORY
) {
778 store_emit_memory(ctx
, emit_data
);
782 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
783 si_emit_waitcnt(ctx
, VM_CNT
);
785 writeonly_memory
= is_oneway_access_only(inst
, info
,
786 info
->shader_buffers_load
|
787 info
->shader_buffers_atomic
,
789 info
->images_atomic
);
791 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
) {
792 store_emit_buffer(ctx
, emit_data
, writeonly_memory
);
796 if (target
== TGSI_TEXTURE_BUFFER
) {
797 emit_data
->output
[emit_data
->chan
] = lp_build_intrinsic(
798 builder
, "llvm.amdgcn.buffer.store.format.v4f32",
799 emit_data
->dst_type
, emit_data
->args
,
800 emit_data
->arg_count
,
801 get_store_intr_attribs(writeonly_memory
));
803 ac_get_image_intr_name("llvm.amdgcn.image.store",
804 LLVMTypeOf(emit_data
->args
[0]), /* vdata */
805 LLVMTypeOf(emit_data
->args
[1]), /* coords */
806 LLVMTypeOf(emit_data
->args
[2]), /* rsrc */
807 intrinsic_name
, sizeof(intrinsic_name
));
809 emit_data
->output
[emit_data
->chan
] =
811 builder
, intrinsic_name
, emit_data
->dst_type
,
812 emit_data
->args
, emit_data
->arg_count
,
813 get_store_intr_attribs(writeonly_memory
));
817 static void atomic_fetch_args(
818 struct lp_build_tgsi_context
* bld_base
,
819 struct lp_build_emit_data
* emit_data
)
821 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
822 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
823 LLVMValueRef data1
, data2
;
827 emit_data
->dst_type
= ctx
->f32
;
829 tmp
= lp_build_emit_fetch(bld_base
, inst
, 2, 0);
830 data1
= ac_to_integer(&ctx
->ac
, tmp
);
832 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
833 tmp
= lp_build_emit_fetch(bld_base
, inst
, 3, 0);
834 data2
= ac_to_integer(&ctx
->ac
, tmp
);
837 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
838 * of arguments, which is reversed relative to TGSI (and GLSL)
840 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
841 emit_data
->args
[emit_data
->arg_count
++] = data2
;
842 emit_data
->args
[emit_data
->arg_count
++] = data1
;
844 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
847 rsrc
= shader_buffer_fetch_rsrc(ctx
, &inst
->Src
[0], false);
849 tmp
= lp_build_emit_fetch(bld_base
, inst
, 1, 0);
850 offset
= ac_to_integer(&ctx
->ac
, tmp
);
852 buffer_append_args(ctx
, emit_data
, rsrc
, ctx
->i32_0
,
853 offset
, true, false);
854 } else if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
||
855 tgsi_is_bindless_image_file(inst
->Src
[0].Register
.File
)) {
856 unsigned target
= inst
->Memory
.Texture
;
859 image_fetch_rsrc(bld_base
, &inst
->Src
[0], true, target
, &rsrc
);
860 coords
= image_fetch_coords(bld_base
, inst
, 1, rsrc
);
862 if (target
== TGSI_TEXTURE_BUFFER
) {
863 buffer_append_args(ctx
, emit_data
, rsrc
, coords
,
864 ctx
->i32_0
, true, false);
866 emit_data
->args
[emit_data
->arg_count
++] = coords
;
867 emit_data
->args
[emit_data
->arg_count
++] = rsrc
;
869 image_append_args(ctx
, emit_data
, target
, true, false);
874 static void atomic_emit_memory(struct si_shader_context
*ctx
,
875 struct lp_build_emit_data
*emit_data
) {
876 LLVMBuilderRef builder
= ctx
->ac
.builder
;
877 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
878 LLVMValueRef ptr
, result
, arg
;
880 ptr
= get_memory_ptr(ctx
, inst
, ctx
->i32
, 1);
882 arg
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, 2, 0);
883 arg
= ac_to_integer(&ctx
->ac
, arg
);
885 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
886 LLVMValueRef new_data
;
887 new_data
= lp_build_emit_fetch(&ctx
->bld_base
,
890 new_data
= ac_to_integer(&ctx
->ac
, new_data
);
892 result
= LLVMBuildAtomicCmpXchg(builder
, ptr
, arg
, new_data
,
893 LLVMAtomicOrderingSequentiallyConsistent
,
894 LLVMAtomicOrderingSequentiallyConsistent
,
897 result
= LLVMBuildExtractValue(builder
, result
, 0, "");
899 LLVMAtomicRMWBinOp op
;
901 switch(inst
->Instruction
.Opcode
) {
902 case TGSI_OPCODE_ATOMUADD
:
903 op
= LLVMAtomicRMWBinOpAdd
;
905 case TGSI_OPCODE_ATOMXCHG
:
906 op
= LLVMAtomicRMWBinOpXchg
;
908 case TGSI_OPCODE_ATOMAND
:
909 op
= LLVMAtomicRMWBinOpAnd
;
911 case TGSI_OPCODE_ATOMOR
:
912 op
= LLVMAtomicRMWBinOpOr
;
914 case TGSI_OPCODE_ATOMXOR
:
915 op
= LLVMAtomicRMWBinOpXor
;
917 case TGSI_OPCODE_ATOMUMIN
:
918 op
= LLVMAtomicRMWBinOpUMin
;
920 case TGSI_OPCODE_ATOMUMAX
:
921 op
= LLVMAtomicRMWBinOpUMax
;
923 case TGSI_OPCODE_ATOMIMIN
:
924 op
= LLVMAtomicRMWBinOpMin
;
926 case TGSI_OPCODE_ATOMIMAX
:
927 op
= LLVMAtomicRMWBinOpMax
;
930 unreachable("unknown atomic opcode");
933 result
= LLVMBuildAtomicRMW(builder
, op
, ptr
, arg
,
934 LLVMAtomicOrderingSequentiallyConsistent
,
937 emit_data
->output
[emit_data
->chan
] = LLVMBuildBitCast(builder
, result
, emit_data
->dst_type
, "");
940 static void atomic_emit(
941 const struct lp_build_tgsi_action
*action
,
942 struct lp_build_tgsi_context
*bld_base
,
943 struct lp_build_emit_data
*emit_data
)
945 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
946 LLVMBuilderRef builder
= ctx
->ac
.builder
;
947 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
948 char intrinsic_name
[40];
951 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
) {
952 atomic_emit_memory(ctx
, emit_data
);
956 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
957 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
958 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
959 "llvm.amdgcn.buffer.atomic.%s", action
->intr_name
);
964 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
965 coords
= emit_data
->args
[2];
967 coords
= emit_data
->args
[1];
969 ac_build_type_name_for_intr(LLVMTypeOf(coords
), coords_type
, sizeof(coords_type
));
970 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
971 "llvm.amdgcn.image.atomic.%s.%s",
972 action
->intr_name
, coords_type
);
975 tmp
= lp_build_intrinsic(
976 builder
, intrinsic_name
, ctx
->i32
,
977 emit_data
->args
, emit_data
->arg_count
, 0);
978 emit_data
->output
[emit_data
->chan
] = ac_to_float(&ctx
->ac
, tmp
);
981 static void set_tex_fetch_args(struct si_shader_context
*ctx
,
982 struct lp_build_emit_data
*emit_data
,
984 LLVMValueRef res_ptr
, LLVMValueRef samp_ptr
,
985 LLVMValueRef
*param
, unsigned count
,
988 struct ac_image_args args
= {};
990 /* Pad to power of two vector */
991 while (count
< util_next_power_of_two(count
))
992 param
[count
++] = LLVMGetUndef(ctx
->i32
);
995 args
.addr
= lp_build_gather_values(&ctx
->gallivm
, param
, count
);
997 args
.addr
= param
[0];
999 args
.resource
= res_ptr
;
1000 args
.sampler
= samp_ptr
;
1002 args
.unorm
= target
== TGSI_TEXTURE_RECT
||
1003 target
== TGSI_TEXTURE_SHADOWRECT
;
1004 args
.da
= tgsi_is_array_sampler(target
);
1006 /* Ugly, but we seem to have no other choice right now. */
1007 STATIC_ASSERT(sizeof(args
) <= sizeof(emit_data
->args
));
1008 memcpy(emit_data
->args
, &args
, sizeof(args
));
1011 static LLVMValueRef
fix_resinfo(struct si_shader_context
*ctx
,
1012 unsigned target
, LLVMValueRef out
)
1014 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1016 /* 1D textures are allocated and used as 2D on GFX9. */
1017 if (ctx
->screen
->b
.chip_class
>= GFX9
&&
1018 (target
== TGSI_TEXTURE_1D_ARRAY
||
1019 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
)) {
1020 LLVMValueRef layers
=
1021 LLVMBuildExtractElement(builder
, out
,
1022 LLVMConstInt(ctx
->i32
, 2, 0), "");
1023 out
= LLVMBuildInsertElement(builder
, out
, layers
,
1027 /* Divide the number of layers by 6 to get the number of cubes. */
1028 if (target
== TGSI_TEXTURE_CUBE_ARRAY
||
1029 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1030 LLVMValueRef imm2
= LLVMConstInt(ctx
->i32
, 2, 0);
1032 LLVMValueRef z
= LLVMBuildExtractElement(builder
, out
, imm2
, "");
1033 z
= LLVMBuildSDiv(builder
, z
, LLVMConstInt(ctx
->i32
, 6, 0), "");
1035 out
= LLVMBuildInsertElement(builder
, out
, z
, imm2
, "");
1040 static void resq_fetch_args(
1041 struct lp_build_tgsi_context
* bld_base
,
1042 struct lp_build_emit_data
* emit_data
)
1044 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1045 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1046 const struct tgsi_full_src_register
*reg
= &inst
->Src
[0];
1048 emit_data
->dst_type
= ctx
->v4i32
;
1050 if (reg
->Register
.File
== TGSI_FILE_BUFFER
) {
1051 emit_data
->args
[0] = shader_buffer_fetch_rsrc(ctx
, reg
, false);
1052 emit_data
->arg_count
= 1;
1053 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
1054 image_fetch_rsrc(bld_base
, reg
, false, inst
->Memory
.Texture
,
1055 &emit_data
->args
[0]);
1056 emit_data
->arg_count
= 1;
1058 LLVMValueRef res_ptr
;
1059 unsigned image_target
;
1061 if (inst
->Memory
.Texture
== TGSI_TEXTURE_3D
)
1062 image_target
= TGSI_TEXTURE_2D_ARRAY
;
1064 image_target
= inst
->Memory
.Texture
;
1066 image_fetch_rsrc(bld_base
, reg
, false, inst
->Memory
.Texture
,
1068 set_tex_fetch_args(ctx
, emit_data
, image_target
,
1069 res_ptr
, NULL
, &ctx
->i32_0
, 1,
1074 static void resq_emit(
1075 const struct lp_build_tgsi_action
*action
,
1076 struct lp_build_tgsi_context
*bld_base
,
1077 struct lp_build_emit_data
*emit_data
)
1079 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1080 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1081 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1084 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
1085 out
= LLVMBuildExtractElement(builder
, emit_data
->args
[0],
1086 LLVMConstInt(ctx
->i32
, 2, 0), "");
1087 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
1088 out
= get_buffer_size(bld_base
, emit_data
->args
[0]);
1090 struct ac_image_args args
;
1092 memcpy(&args
, emit_data
->args
, sizeof(args
)); /* ugly */
1093 args
.opcode
= ac_image_get_resinfo
;
1094 out
= ac_build_image_opcode(&ctx
->ac
, &args
);
1096 out
= fix_resinfo(ctx
, inst
->Memory
.Texture
, out
);
1099 emit_data
->output
[emit_data
->chan
] = out
;
1103 * Load an image view, fmask view. or sampler state descriptor.
1105 LLVMValueRef
si_load_sampler_desc(struct si_shader_context
*ctx
,
1106 LLVMValueRef list
, LLVMValueRef index
,
1107 enum ac_descriptor_type type
)
1109 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1113 /* The image is at [0:7]. */
1114 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 2, 0), "");
1116 case AC_DESC_BUFFER
:
1117 /* The buffer is in [4:7]. */
1118 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 4, 0), "");
1119 index
= LLVMBuildAdd(builder
, index
, ctx
->i32_1
, "");
1120 list
= LLVMBuildPointerCast(builder
, list
,
1121 si_const_array(ctx
->v4i32
, 0), "");
1124 /* The FMASK is at [8:15]. */
1125 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 2, 0), "");
1126 index
= LLVMBuildAdd(builder
, index
, ctx
->i32_1
, "");
1128 case AC_DESC_SAMPLER
:
1129 /* The sampler state is at [12:15]. */
1130 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 4, 0), "");
1131 index
= LLVMBuildAdd(builder
, index
, LLVMConstInt(ctx
->i32
, 3, 0), "");
1132 list
= LLVMBuildPointerCast(builder
, list
,
1133 si_const_array(ctx
->v4i32
, 0), "");
1137 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
1140 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
1143 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
1144 * filtering manually. The driver sets img7 to a mask clearing
1145 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
1146 * s_and_b32 samp0, samp0, img7
1149 * The ANISO_OVERRIDE sampler field enables this fix in TA.
1151 static LLVMValueRef
sici_fix_sampler_aniso(struct si_shader_context
*ctx
,
1152 LLVMValueRef res
, LLVMValueRef samp
)
1154 LLVMValueRef img7
, samp0
;
1156 if (ctx
->screen
->b
.chip_class
>= VI
)
1159 img7
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
1160 LLVMConstInt(ctx
->i32
, 7, 0), "");
1161 samp0
= LLVMBuildExtractElement(ctx
->ac
.builder
, samp
,
1163 samp0
= LLVMBuildAnd(ctx
->ac
.builder
, samp0
, img7
, "");
1164 return LLVMBuildInsertElement(ctx
->ac
.builder
, samp
, samp0
,
1168 static void tex_fetch_ptrs(
1169 struct lp_build_tgsi_context
*bld_base
,
1170 struct lp_build_emit_data
*emit_data
,
1171 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
, LLVMValueRef
*fmask_ptr
)
1173 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1174 LLVMValueRef list
= LLVMGetParam(ctx
->main_fn
, ctx
->param_samplers_and_images
);
1175 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1176 const struct tgsi_full_src_register
*reg
;
1177 unsigned target
= inst
->Texture
.Texture
;
1178 unsigned sampler_src
;
1181 sampler_src
= emit_data
->inst
->Instruction
.NumSrcRegs
- 1;
1182 reg
= &emit_data
->inst
->Src
[sampler_src
];
1184 if (reg
->Register
.Indirect
) {
1185 index
= si_get_bounded_indirect_index(ctx
,
1187 reg
->Register
.Index
,
1189 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
1190 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
/ 2, 0), "");
1192 index
= LLVMConstInt(ctx
->i32
,
1193 si_get_sampler_slot(reg
->Register
.Index
), 0);
1196 if (reg
->Register
.File
!= TGSI_FILE_SAMPLER
) {
1197 /* Bindless descriptors are accessible from a different pair of
1198 * user SGPR indices.
1200 list
= LLVMGetParam(ctx
->main_fn
,
1201 ctx
->param_bindless_samplers_and_images
);
1202 index
= lp_build_emit_fetch_src(bld_base
, reg
,
1203 TGSI_TYPE_UNSIGNED
, 0);
1206 if (target
== TGSI_TEXTURE_BUFFER
)
1207 *res_ptr
= si_load_sampler_desc(ctx
, list
, index
, AC_DESC_BUFFER
);
1209 *res_ptr
= si_load_sampler_desc(ctx
, list
, index
, AC_DESC_IMAGE
);
1216 if (target
== TGSI_TEXTURE_2D_MSAA
||
1217 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1219 *fmask_ptr
= si_load_sampler_desc(ctx
, list
, index
,
1221 } else if (target
!= TGSI_TEXTURE_BUFFER
) {
1223 *samp_ptr
= si_load_sampler_desc(ctx
, list
, index
,
1225 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
1230 static void txq_fetch_args(
1231 struct lp_build_tgsi_context
*bld_base
,
1232 struct lp_build_emit_data
*emit_data
)
1234 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1235 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1236 unsigned target
= inst
->Texture
.Texture
;
1237 LLVMValueRef res_ptr
;
1238 LLVMValueRef address
;
1240 tex_fetch_ptrs(bld_base
, emit_data
, &res_ptr
, NULL
, NULL
);
1242 if (target
== TGSI_TEXTURE_BUFFER
) {
1243 /* Read the size from the buffer descriptor directly. */
1244 emit_data
->args
[0] = get_buffer_size(bld_base
, res_ptr
);
1248 /* Textures - set the mip level. */
1249 address
= lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_X
);
1251 set_tex_fetch_args(ctx
, emit_data
, target
, res_ptr
,
1252 NULL
, &address
, 1, 0xf);
1255 static void txq_emit(const struct lp_build_tgsi_action
*action
,
1256 struct lp_build_tgsi_context
*bld_base
,
1257 struct lp_build_emit_data
*emit_data
)
1259 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1260 struct ac_image_args args
;
1261 unsigned target
= emit_data
->inst
->Texture
.Texture
;
1263 if (target
== TGSI_TEXTURE_BUFFER
) {
1264 /* Just return the buffer size. */
1265 emit_data
->output
[emit_data
->chan
] = emit_data
->args
[0];
1269 memcpy(&args
, emit_data
->args
, sizeof(args
)); /* ugly */
1271 args
.opcode
= ac_image_get_resinfo
;
1272 LLVMValueRef result
= ac_build_image_opcode(&ctx
->ac
, &args
);
1274 emit_data
->output
[emit_data
->chan
] = fix_resinfo(ctx
, target
, result
);
1277 static void tex_fetch_args(
1278 struct lp_build_tgsi_context
*bld_base
,
1279 struct lp_build_emit_data
*emit_data
)
1281 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1282 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1283 unsigned opcode
= inst
->Instruction
.Opcode
;
1284 unsigned target
= inst
->Texture
.Texture
;
1285 LLVMValueRef coords
[5], derivs
[6];
1286 LLVMValueRef address
[16];
1287 unsigned num_coords
= tgsi_util_get_texture_coord_dim(target
);
1288 int ref_pos
= tgsi_util_get_shadow_ref_src_index(target
);
1291 unsigned num_deriv_channels
= 0;
1292 bool has_offset
= inst
->Texture
.NumOffsets
> 0;
1293 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
;
1294 unsigned dmask
= 0xf;
1296 tex_fetch_ptrs(bld_base
, emit_data
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
1298 if (target
== TGSI_TEXTURE_BUFFER
) {
1299 emit_data
->dst_type
= ctx
->v4f32
;
1300 emit_data
->args
[0] = res_ptr
;
1301 emit_data
->args
[1] = ctx
->i32_0
;
1302 emit_data
->args
[2] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_X
);
1303 emit_data
->arg_count
= 3;
1307 /* Fetch and project texture coordinates */
1308 coords
[3] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_W
);
1309 for (chan
= 0; chan
< 3; chan
++) {
1310 coords
[chan
] = lp_build_emit_fetch(bld_base
,
1313 if (opcode
== TGSI_OPCODE_TXP
)
1314 coords
[chan
] = lp_build_emit_llvm_binary(bld_base
,
1320 if (opcode
== TGSI_OPCODE_TXP
)
1321 coords
[3] = ctx
->ac
.f32_1
;
1325 opcode
!= TGSI_OPCODE_TXF
&&
1326 opcode
!= TGSI_OPCODE_TXF_LZ
) {
1327 /* The offsets are six-bit signed integers packed like this:
1328 * X=[5:0], Y=[13:8], and Z=[21:16].
1330 LLVMValueRef offset
[3], pack
;
1332 assert(inst
->Texture
.NumOffsets
== 1);
1334 for (chan
= 0; chan
< 3; chan
++) {
1335 offset
[chan
] = lp_build_emit_fetch_texoffset(bld_base
,
1336 emit_data
->inst
, 0, chan
);
1337 offset
[chan
] = LLVMBuildAnd(ctx
->ac
.builder
, offset
[chan
],
1338 LLVMConstInt(ctx
->i32
, 0x3f, 0), "");
1340 offset
[chan
] = LLVMBuildShl(ctx
->ac
.builder
, offset
[chan
],
1341 LLVMConstInt(ctx
->i32
, chan
*8, 0), "");
1344 pack
= LLVMBuildOr(ctx
->ac
.builder
, offset
[0], offset
[1], "");
1345 pack
= LLVMBuildOr(ctx
->ac
.builder
, pack
, offset
[2], "");
1346 address
[count
++] = pack
;
1349 /* Pack LOD bias value */
1350 if (opcode
== TGSI_OPCODE_TXB
)
1351 address
[count
++] = coords
[3];
1352 if (opcode
== TGSI_OPCODE_TXB2
)
1353 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1355 /* Pack depth comparison value */
1356 if (tgsi_is_shadow_target(target
) && opcode
!= TGSI_OPCODE_LODQ
) {
1359 if (target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1360 z
= lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1362 assert(ref_pos
>= 0);
1363 z
= coords
[ref_pos
];
1366 /* Section 8.23.1 (Depth Texture Comparison Mode) of the
1367 * OpenGL 4.5 spec says:
1369 * "If the texture’s internal format indicates a fixed-point
1370 * depth texture, then D_t and D_ref are clamped to the
1371 * range [0, 1]; otherwise no clamping is performed."
1373 * TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
1374 * so the depth comparison value isn't clamped for Z16 and
1375 * Z24 anymore. Do it manually here.
1377 if (ctx
->screen
->b
.chip_class
>= VI
) {
1378 LLVMValueRef upgraded
;
1379 LLVMValueRef clamped
;
1380 upgraded
= LLVMBuildExtractElement(ctx
->ac
.builder
, samp_ptr
,
1381 LLVMConstInt(ctx
->i32
, 3, false), "");
1382 upgraded
= LLVMBuildLShr(ctx
->ac
.builder
, upgraded
,
1383 LLVMConstInt(ctx
->i32
, 29, false), "");
1384 upgraded
= LLVMBuildTrunc(ctx
->ac
.builder
, upgraded
, ctx
->i1
, "");
1385 clamped
= ac_build_clamp(&ctx
->ac
, z
);
1386 z
= LLVMBuildSelect(ctx
->ac
.builder
, upgraded
, clamped
, z
, "");
1389 address
[count
++] = z
;
1392 /* Pack user derivatives */
1393 if (opcode
== TGSI_OPCODE_TXD
) {
1394 int param
, num_src_deriv_channels
, num_dst_deriv_channels
;
1397 case TGSI_TEXTURE_3D
:
1398 num_src_deriv_channels
= 3;
1399 num_dst_deriv_channels
= 3;
1400 num_deriv_channels
= 3;
1402 case TGSI_TEXTURE_2D
:
1403 case TGSI_TEXTURE_SHADOW2D
:
1404 case TGSI_TEXTURE_RECT
:
1405 case TGSI_TEXTURE_SHADOWRECT
:
1406 case TGSI_TEXTURE_2D_ARRAY
:
1407 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1408 num_src_deriv_channels
= 2;
1409 num_dst_deriv_channels
= 2;
1410 num_deriv_channels
= 2;
1412 case TGSI_TEXTURE_CUBE
:
1413 case TGSI_TEXTURE_SHADOWCUBE
:
1414 case TGSI_TEXTURE_CUBE_ARRAY
:
1415 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
1416 /* Cube derivatives will be converted to 2D. */
1417 num_src_deriv_channels
= 3;
1418 num_dst_deriv_channels
= 3;
1419 num_deriv_channels
= 2;
1421 case TGSI_TEXTURE_1D
:
1422 case TGSI_TEXTURE_SHADOW1D
:
1423 case TGSI_TEXTURE_1D_ARRAY
:
1424 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1425 num_src_deriv_channels
= 1;
1427 /* 1D textures are allocated and used as 2D on GFX9. */
1428 if (ctx
->screen
->b
.chip_class
>= GFX9
) {
1429 num_dst_deriv_channels
= 2;
1430 num_deriv_channels
= 2;
1432 num_dst_deriv_channels
= 1;
1433 num_deriv_channels
= 1;
1437 unreachable("invalid target");
1440 for (param
= 0; param
< 2; param
++) {
1441 for (chan
= 0; chan
< num_src_deriv_channels
; chan
++)
1442 derivs
[param
* num_dst_deriv_channels
+ chan
] =
1443 lp_build_emit_fetch(bld_base
, inst
, param
+1, chan
);
1445 /* Fill in the rest with zeros. */
1446 for (chan
= num_src_deriv_channels
;
1447 chan
< num_dst_deriv_channels
; chan
++)
1448 derivs
[param
* num_dst_deriv_channels
+ chan
] =
1453 if (target
== TGSI_TEXTURE_CUBE
||
1454 target
== TGSI_TEXTURE_CUBE_ARRAY
||
1455 target
== TGSI_TEXTURE_SHADOWCUBE
||
1456 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1457 ac_prepare_cube_coords(&ctx
->ac
,
1458 opcode
== TGSI_OPCODE_TXD
,
1459 target
== TGSI_TEXTURE_CUBE_ARRAY
||
1460 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
,
1461 opcode
== TGSI_OPCODE_LODQ
,
1463 } else if (tgsi_is_array_sampler(target
) &&
1464 opcode
!= TGSI_OPCODE_TXF
&&
1465 opcode
!= TGSI_OPCODE_TXF_LZ
&&
1466 ctx
->screen
->b
.chip_class
<= VI
) {
1467 unsigned array_coord
= target
== TGSI_TEXTURE_1D_ARRAY
? 1 : 2;
1468 coords
[array_coord
] =
1469 ac_build_intrinsic(&ctx
->ac
, "llvm.rint.f32", ctx
->f32
,
1470 &coords
[array_coord
], 1, 0);
1473 if (opcode
== TGSI_OPCODE_TXD
)
1474 for (int i
= 0; i
< num_deriv_channels
* 2; i
++)
1475 address
[count
++] = derivs
[i
];
1477 /* Pack texture coordinates */
1478 address
[count
++] = coords
[0];
1480 address
[count
++] = coords
[1];
1482 address
[count
++] = coords
[2];
1484 /* 1D textures are allocated and used as 2D on GFX9. */
1485 if (ctx
->screen
->b
.chip_class
>= GFX9
) {
1486 LLVMValueRef filler
;
1488 /* Use 0.5, so that we don't sample the border color. */
1489 if (opcode
== TGSI_OPCODE_TXF
||
1490 opcode
== TGSI_OPCODE_TXF_LZ
)
1491 filler
= ctx
->i32_0
;
1493 filler
= LLVMConstReal(ctx
->f32
, 0.5);
1495 if (target
== TGSI_TEXTURE_1D
||
1496 target
== TGSI_TEXTURE_SHADOW1D
) {
1497 address
[count
++] = filler
;
1498 } else if (target
== TGSI_TEXTURE_1D_ARRAY
||
1499 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
) {
1500 address
[count
] = address
[count
- 1];
1501 address
[count
- 1] = filler
;
1506 /* Pack LOD or sample index */
1507 if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXF
)
1508 address
[count
++] = coords
[3];
1509 else if (opcode
== TGSI_OPCODE_TXL2
)
1510 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1513 assert(!"Cannot handle more than 16 texture address parameters");
1517 for (chan
= 0; chan
< count
; chan
++)
1518 address
[chan
] = ac_to_integer(&ctx
->ac
, address
[chan
]);
1520 /* Adjust the sample index according to FMASK.
1522 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1523 * which is the identity mapping. Each nibble says which physical sample
1524 * should be fetched to get that sample.
1526 * For example, 0x11111100 means there are only 2 samples stored and
1527 * the second sample covers 3/4 of the pixel. When reading samples 0
1528 * and 1, return physical sample 0 (determined by the first two 0s
1529 * in FMASK), otherwise return physical sample 1.
1531 * The sample index should be adjusted as follows:
1532 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1534 if (target
== TGSI_TEXTURE_2D_MSAA
||
1535 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1536 struct lp_build_emit_data txf_emit_data
= *emit_data
;
1537 LLVMValueRef txf_address
[4];
1538 /* We only need .xy for non-arrays, and .xyz for arrays. */
1539 unsigned txf_count
= target
== TGSI_TEXTURE_2D_MSAA
? 2 : 3;
1540 struct tgsi_full_instruction inst
= {};
1542 memcpy(txf_address
, address
, sizeof(txf_address
));
1544 /* Read FMASK using TXF_LZ. */
1545 inst
.Instruction
.Opcode
= TGSI_OPCODE_TXF_LZ
;
1546 inst
.Texture
.Texture
= target
;
1547 txf_emit_data
.inst
= &inst
;
1548 txf_emit_data
.chan
= 0;
1549 set_tex_fetch_args(ctx
, &txf_emit_data
,
1550 target
, fmask_ptr
, NULL
,
1551 txf_address
, txf_count
, 0xf);
1552 build_tex_intrinsic(&tex_action
, bld_base
, &txf_emit_data
);
1554 /* Initialize some constants. */
1555 LLVMValueRef four
= LLVMConstInt(ctx
->i32
, 4, 0);
1556 LLVMValueRef F
= LLVMConstInt(ctx
->i32
, 0xF, 0);
1558 /* Apply the formula. */
1559 LLVMValueRef fmask
=
1560 LLVMBuildExtractElement(ctx
->ac
.builder
,
1561 txf_emit_data
.output
[0],
1564 unsigned sample_chan
= txf_count
; /* the sample index is last */
1566 LLVMValueRef sample_index4
=
1567 LLVMBuildMul(ctx
->ac
.builder
, address
[sample_chan
], four
, "");
1569 LLVMValueRef shifted_fmask
=
1570 LLVMBuildLShr(ctx
->ac
.builder
, fmask
, sample_index4
, "");
1572 LLVMValueRef final_sample
=
1573 LLVMBuildAnd(ctx
->ac
.builder
, shifted_fmask
, F
, "");
1575 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1576 * resource descriptor is 0 (invalid),
1578 LLVMValueRef fmask_desc
=
1579 LLVMBuildBitCast(ctx
->ac
.builder
, fmask_ptr
,
1582 LLVMValueRef fmask_word1
=
1583 LLVMBuildExtractElement(ctx
->ac
.builder
, fmask_desc
,
1586 LLVMValueRef word1_is_nonzero
=
1587 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntNE
,
1588 fmask_word1
, ctx
->i32_0
, "");
1590 /* Replace the MSAA sample index. */
1591 address
[sample_chan
] =
1592 LLVMBuildSelect(ctx
->ac
.builder
, word1_is_nonzero
,
1593 final_sample
, address
[sample_chan
], "");
1596 if (opcode
== TGSI_OPCODE_TXF
||
1597 opcode
== TGSI_OPCODE_TXF_LZ
) {
1598 /* add tex offsets */
1599 if (inst
->Texture
.NumOffsets
) {
1600 struct lp_build_context
*uint_bld
= &bld_base
->uint_bld
;
1601 const struct tgsi_texture_offset
*off
= inst
->TexOffsets
;
1603 assert(inst
->Texture
.NumOffsets
== 1);
1606 case TGSI_TEXTURE_3D
:
1607 address
[2] = lp_build_add(uint_bld
, address
[2],
1608 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleZ
]);
1610 case TGSI_TEXTURE_2D
:
1611 case TGSI_TEXTURE_SHADOW2D
:
1612 case TGSI_TEXTURE_RECT
:
1613 case TGSI_TEXTURE_SHADOWRECT
:
1614 case TGSI_TEXTURE_2D_ARRAY
:
1615 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1617 lp_build_add(uint_bld
, address
[1],
1618 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleY
]);
1620 case TGSI_TEXTURE_1D
:
1621 case TGSI_TEXTURE_SHADOW1D
:
1622 case TGSI_TEXTURE_1D_ARRAY
:
1623 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1625 lp_build_add(uint_bld
, address
[0],
1626 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleX
]);
1628 /* texture offsets do not apply to other texture targets */
1633 if (opcode
== TGSI_OPCODE_TG4
) {
1634 unsigned gather_comp
= 0;
1636 /* DMASK was repurposed for GATHER4. 4 components are always
1637 * returned and DMASK works like a swizzle - it selects
1638 * the component to fetch. The only valid DMASK values are
1639 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1640 * (red,red,red,red) etc.) The ISA document doesn't mention
1644 /* Get the component index from src1.x for Gather4. */
1645 if (!tgsi_is_shadow_target(target
)) {
1646 LLVMValueRef comp_imm
;
1647 struct tgsi_src_register src1
= inst
->Src
[1].Register
;
1649 assert(src1
.File
== TGSI_FILE_IMMEDIATE
);
1651 comp_imm
= ctx
->imms
[src1
.Index
* TGSI_NUM_CHANNELS
+ src1
.SwizzleX
];
1652 gather_comp
= LLVMConstIntGetZExtValue(comp_imm
);
1653 gather_comp
= CLAMP(gather_comp
, 0, 3);
1656 dmask
= 1 << gather_comp
;
1659 set_tex_fetch_args(ctx
, emit_data
, target
, res_ptr
,
1660 samp_ptr
, address
, count
, dmask
);
1663 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
1664 * incorrectly forces nearest filtering if the texture format is integer.
1665 * The only effect it has on Gather4, which always returns 4 texels for
1666 * bilinear filtering, is that the final coordinates are off by 0.5 of
1669 * The workaround is to subtract 0.5 from the unnormalized coordinates,
1670 * or (0.5 / size) from the normalized coordinates.
1672 * However, cube textures with 8_8_8_8 data formats require a different
1673 * workaround of overriding the num format to USCALED/SSCALED. This would lose
1674 * precision in 32-bit data formats, so it needs to be applied dynamically at
1675 * runtime. In this case, return an i1 value that indicates whether the
1676 * descriptor was overridden (and hence a fixup of the sampler result is needed).
1679 si_lower_gather4_integer(struct si_shader_context
*ctx
,
1680 struct ac_image_args
*args
,
1682 enum tgsi_return_type return_type
)
1684 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1685 LLVMValueRef wa_8888
= NULL
;
1686 LLVMValueRef coord
= args
->addr
;
1687 LLVMValueRef half_texel
[2];
1688 /* Texture coordinates start after:
1689 * {offset, bias, z-compare, derivatives}
1690 * Only the offset and z-compare can occur here.
1692 unsigned coord_vgpr_index
= (int)args
->offset
+ (int)args
->compare
;
1695 assert(return_type
== TGSI_RETURN_TYPE_SINT
||
1696 return_type
== TGSI_RETURN_TYPE_UINT
);
1698 if (target
== TGSI_TEXTURE_CUBE
||
1699 target
== TGSI_TEXTURE_CUBE_ARRAY
) {
1700 LLVMValueRef formats
;
1701 LLVMValueRef data_format
;
1702 LLVMValueRef wa_formats
;
1704 formats
= LLVMBuildExtractElement(builder
, args
->resource
, ctx
->i32_1
, "");
1706 data_format
= LLVMBuildLShr(builder
, formats
,
1707 LLVMConstInt(ctx
->i32
, 20, false), "");
1708 data_format
= LLVMBuildAnd(builder
, data_format
,
1709 LLVMConstInt(ctx
->i32
, (1u << 6) - 1, false), "");
1710 wa_8888
= LLVMBuildICmp(
1711 builder
, LLVMIntEQ
, data_format
,
1712 LLVMConstInt(ctx
->i32
, V_008F14_IMG_DATA_FORMAT_8_8_8_8
, false),
1715 uint32_t wa_num_format
=
1716 return_type
== TGSI_RETURN_TYPE_UINT
?
1717 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_USCALED
) :
1718 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_SSCALED
);
1719 wa_formats
= LLVMBuildAnd(builder
, formats
,
1720 LLVMConstInt(ctx
->i32
, C_008F14_NUM_FORMAT_GFX6
, false),
1722 wa_formats
= LLVMBuildOr(builder
, wa_formats
,
1723 LLVMConstInt(ctx
->i32
, wa_num_format
, false), "");
1725 formats
= LLVMBuildSelect(builder
, wa_8888
, wa_formats
, formats
, "");
1726 args
->resource
= LLVMBuildInsertElement(
1727 builder
, args
->resource
, formats
, ctx
->i32_1
, "");
1730 if (target
== TGSI_TEXTURE_RECT
||
1731 target
== TGSI_TEXTURE_SHADOWRECT
) {
1733 half_texel
[0] = half_texel
[1] = LLVMConstReal(ctx
->f32
, -0.5);
1735 struct tgsi_full_instruction txq_inst
= {};
1736 struct lp_build_emit_data txq_emit_data
= {};
1737 struct lp_build_if_state if_ctx
;
1740 /* Skip the texture size query entirely if we don't need it. */
1741 lp_build_if(&if_ctx
, &ctx
->gallivm
, LLVMBuildNot(builder
, wa_8888
, ""));
1744 /* Query the texture size. */
1745 txq_inst
.Texture
.Texture
= target
;
1746 txq_emit_data
.inst
= &txq_inst
;
1747 txq_emit_data
.dst_type
= ctx
->v4i32
;
1748 set_tex_fetch_args(ctx
, &txq_emit_data
, target
,
1749 args
->resource
, NULL
, &ctx
->i32_0
,
1751 txq_emit(NULL
, &ctx
->bld_base
, &txq_emit_data
);
1753 /* Compute -0.5 / size. */
1754 for (c
= 0; c
< 2; c
++) {
1756 LLVMBuildExtractElement(builder
, txq_emit_data
.output
[0],
1757 LLVMConstInt(ctx
->i32
, c
, 0), "");
1758 half_texel
[c
] = LLVMBuildUIToFP(builder
, half_texel
[c
], ctx
->f32
, "");
1760 lp_build_emit_llvm_unary(&ctx
->bld_base
,
1761 TGSI_OPCODE_RCP
, half_texel
[c
]);
1762 half_texel
[c
] = LLVMBuildFMul(builder
, half_texel
[c
],
1763 LLVMConstReal(ctx
->f32
, -0.5), "");
1767 lp_build_endif(&if_ctx
);
1769 LLVMBasicBlockRef bb
[2] = { if_ctx
.true_block
, if_ctx
.entry_block
};
1771 for (c
= 0; c
< 2; c
++) {
1772 LLVMValueRef values
[2] = { half_texel
[c
], ctx
->ac
.f32_0
};
1773 half_texel
[c
] = ac_build_phi(&ctx
->ac
, ctx
->f32
, 2,
1779 for (c
= 0; c
< 2; c
++) {
1781 LLVMValueRef index
= LLVMConstInt(ctx
->i32
, coord_vgpr_index
+ c
, 0);
1783 tmp
= LLVMBuildExtractElement(builder
, coord
, index
, "");
1784 tmp
= ac_to_float(&ctx
->ac
, tmp
);
1785 tmp
= LLVMBuildFAdd(builder
, tmp
, half_texel
[c
], "");
1786 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
1787 coord
= LLVMBuildInsertElement(builder
, coord
, tmp
, index
, "");
1795 /* The second half of the cube texture 8_8_8_8 integer workaround: adjust the
1796 * result after the gather operation.
1799 si_fix_gather4_integer_result(struct si_shader_context
*ctx
,
1800 LLVMValueRef result
,
1801 enum tgsi_return_type return_type
,
1804 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1806 assert(return_type
== TGSI_RETURN_TYPE_SINT
||
1807 return_type
== TGSI_RETURN_TYPE_UINT
);
1809 for (unsigned chan
= 0; chan
< 4; ++chan
) {
1810 LLVMValueRef chanv
= LLVMConstInt(ctx
->i32
, chan
, false);
1812 LLVMValueRef wa_value
;
1814 value
= LLVMBuildExtractElement(builder
, result
, chanv
, "");
1816 if (return_type
== TGSI_RETURN_TYPE_UINT
)
1817 wa_value
= LLVMBuildFPToUI(builder
, value
, ctx
->i32
, "");
1819 wa_value
= LLVMBuildFPToSI(builder
, value
, ctx
->i32
, "");
1820 wa_value
= ac_to_float(&ctx
->ac
, wa_value
);
1821 value
= LLVMBuildSelect(builder
, wa
, wa_value
, value
, "");
1823 result
= LLVMBuildInsertElement(builder
, result
, value
, chanv
, "");
1829 static void build_tex_intrinsic(const struct lp_build_tgsi_action
*action
,
1830 struct lp_build_tgsi_context
*bld_base
,
1831 struct lp_build_emit_data
*emit_data
)
1833 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1834 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1835 struct ac_image_args args
;
1836 unsigned opcode
= inst
->Instruction
.Opcode
;
1837 unsigned target
= inst
->Texture
.Texture
;
1839 if (target
== TGSI_TEXTURE_BUFFER
) {
1840 emit_data
->output
[emit_data
->chan
] =
1841 ac_build_buffer_load_format(&ctx
->ac
,
1849 memcpy(&args
, emit_data
->args
, sizeof(args
)); /* ugly */
1851 args
.opcode
= ac_image_sample
;
1852 args
.compare
= tgsi_is_shadow_target(target
);
1853 args
.offset
= inst
->Texture
.NumOffsets
> 0;
1856 case TGSI_OPCODE_TXF
:
1857 case TGSI_OPCODE_TXF_LZ
:
1858 args
.opcode
= opcode
== TGSI_OPCODE_TXF_LZ
||
1859 target
== TGSI_TEXTURE_2D_MSAA
||
1860 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
?
1861 ac_image_load
: ac_image_load_mip
;
1862 args
.compare
= false;
1863 args
.offset
= false;
1865 case TGSI_OPCODE_LODQ
:
1866 args
.opcode
= ac_image_get_lod
;
1867 args
.compare
= false;
1868 args
.offset
= false;
1870 case TGSI_OPCODE_TEX
:
1871 case TGSI_OPCODE_TEX2
:
1872 case TGSI_OPCODE_TXP
:
1873 if (ctx
->type
!= PIPE_SHADER_FRAGMENT
)
1874 args
.level_zero
= true;
1876 case TGSI_OPCODE_TEX_LZ
:
1877 args
.level_zero
= true;
1879 case TGSI_OPCODE_TXB
:
1880 case TGSI_OPCODE_TXB2
:
1881 assert(ctx
->type
== PIPE_SHADER_FRAGMENT
);
1884 case TGSI_OPCODE_TXL
:
1885 case TGSI_OPCODE_TXL2
:
1888 case TGSI_OPCODE_TXD
:
1891 case TGSI_OPCODE_TG4
:
1892 args
.opcode
= ac_image_gather4
;
1893 args
.level_zero
= true;
1900 /* The hardware needs special lowering for Gather4 with integer formats. */
1901 LLVMValueRef gather4_int_result_workaround
= NULL
;
1903 if (ctx
->screen
->b
.chip_class
<= VI
&&
1904 opcode
== TGSI_OPCODE_TG4
) {
1905 assert(inst
->Texture
.ReturnType
!= TGSI_RETURN_TYPE_UNKNOWN
);
1907 if (inst
->Texture
.ReturnType
== TGSI_RETURN_TYPE_SINT
||
1908 inst
->Texture
.ReturnType
== TGSI_RETURN_TYPE_UINT
) {
1909 gather4_int_result_workaround
=
1910 si_lower_gather4_integer(ctx
, &args
, target
,
1911 inst
->Texture
.ReturnType
);
1915 LLVMValueRef result
=
1916 ac_build_image_opcode(&ctx
->ac
, &args
);
1918 if (gather4_int_result_workaround
) {
1919 result
= si_fix_gather4_integer_result(ctx
, result
,
1920 inst
->Texture
.ReturnType
,
1921 gather4_int_result_workaround
);
1924 emit_data
->output
[emit_data
->chan
] = result
;
1927 static void si_llvm_emit_txqs(
1928 const struct lp_build_tgsi_action
*action
,
1929 struct lp_build_tgsi_context
*bld_base
,
1930 struct lp_build_emit_data
*emit_data
)
1932 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1933 LLVMValueRef res
, samples
;
1934 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
;
1936 tex_fetch_ptrs(bld_base
, emit_data
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
1939 /* Read the samples from the descriptor directly. */
1940 res
= LLVMBuildBitCast(ctx
->ac
.builder
, res_ptr
, ctx
->v8i32
, "");
1941 samples
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
1942 LLVMConstInt(ctx
->i32
, 3, 0), "");
1943 samples
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
1944 LLVMConstInt(ctx
->i32
, 16, 0), "");
1945 samples
= LLVMBuildAnd(ctx
->ac
.builder
, samples
,
1946 LLVMConstInt(ctx
->i32
, 0xf, 0), "");
1947 samples
= LLVMBuildShl(ctx
->ac
.builder
, ctx
->i32_1
,
1950 emit_data
->output
[emit_data
->chan
] = samples
;
1953 static const struct lp_build_tgsi_action tex_action
= {
1954 .fetch_args
= tex_fetch_args
,
1955 .emit
= build_tex_intrinsic
,
1959 * Setup actions for TGSI memory opcode, including texture opcodes.
1961 void si_shader_context_init_mem(struct si_shader_context
*ctx
)
1963 struct lp_build_tgsi_context
*bld_base
;
1964 struct lp_build_tgsi_action tmpl
= {};
1966 bld_base
= &ctx
->bld_base
;
1968 bld_base
->op_actions
[TGSI_OPCODE_TEX
] = tex_action
;
1969 bld_base
->op_actions
[TGSI_OPCODE_TEX_LZ
] = tex_action
;
1970 bld_base
->op_actions
[TGSI_OPCODE_TEX2
] = tex_action
;
1971 bld_base
->op_actions
[TGSI_OPCODE_TXB
] = tex_action
;
1972 bld_base
->op_actions
[TGSI_OPCODE_TXB2
] = tex_action
;
1973 bld_base
->op_actions
[TGSI_OPCODE_TXD
] = tex_action
;
1974 bld_base
->op_actions
[TGSI_OPCODE_TXF
] = tex_action
;
1975 bld_base
->op_actions
[TGSI_OPCODE_TXF_LZ
] = tex_action
;
1976 bld_base
->op_actions
[TGSI_OPCODE_TXL
] = tex_action
;
1977 bld_base
->op_actions
[TGSI_OPCODE_TXL2
] = tex_action
;
1978 bld_base
->op_actions
[TGSI_OPCODE_TXP
] = tex_action
;
1979 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].fetch_args
= txq_fetch_args
;
1980 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].emit
= txq_emit
;
1981 bld_base
->op_actions
[TGSI_OPCODE_TG4
] = tex_action
;
1982 bld_base
->op_actions
[TGSI_OPCODE_LODQ
] = tex_action
;
1983 bld_base
->op_actions
[TGSI_OPCODE_TXQS
].emit
= si_llvm_emit_txqs
;
1985 bld_base
->op_actions
[TGSI_OPCODE_LOAD
].fetch_args
= load_fetch_args
;
1986 bld_base
->op_actions
[TGSI_OPCODE_LOAD
].emit
= load_emit
;
1987 bld_base
->op_actions
[TGSI_OPCODE_STORE
].fetch_args
= store_fetch_args
;
1988 bld_base
->op_actions
[TGSI_OPCODE_STORE
].emit
= store_emit
;
1989 bld_base
->op_actions
[TGSI_OPCODE_RESQ
].fetch_args
= resq_fetch_args
;
1990 bld_base
->op_actions
[TGSI_OPCODE_RESQ
].emit
= resq_emit
;
1992 tmpl
.fetch_args
= atomic_fetch_args
;
1993 tmpl
.emit
= atomic_emit
;
1994 bld_base
->op_actions
[TGSI_OPCODE_ATOMUADD
] = tmpl
;
1995 bld_base
->op_actions
[TGSI_OPCODE_ATOMUADD
].intr_name
= "add";
1996 bld_base
->op_actions
[TGSI_OPCODE_ATOMXCHG
] = tmpl
;
1997 bld_base
->op_actions
[TGSI_OPCODE_ATOMXCHG
].intr_name
= "swap";
1998 bld_base
->op_actions
[TGSI_OPCODE_ATOMCAS
] = tmpl
;
1999 bld_base
->op_actions
[TGSI_OPCODE_ATOMCAS
].intr_name
= "cmpswap";
2000 bld_base
->op_actions
[TGSI_OPCODE_ATOMAND
] = tmpl
;
2001 bld_base
->op_actions
[TGSI_OPCODE_ATOMAND
].intr_name
= "and";
2002 bld_base
->op_actions
[TGSI_OPCODE_ATOMOR
] = tmpl
;
2003 bld_base
->op_actions
[TGSI_OPCODE_ATOMOR
].intr_name
= "or";
2004 bld_base
->op_actions
[TGSI_OPCODE_ATOMXOR
] = tmpl
;
2005 bld_base
->op_actions
[TGSI_OPCODE_ATOMXOR
].intr_name
= "xor";
2006 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMIN
] = tmpl
;
2007 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMIN
].intr_name
= "umin";
2008 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMAX
] = tmpl
;
2009 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMAX
].intr_name
= "umax";
2010 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMIN
] = tmpl
;
2011 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMIN
].intr_name
= "smin";
2012 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMAX
] = tmpl
;
2013 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMAX
].intr_name
= "smax";