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broadcom/vc5: Align 1D texture miplevels to 64b.
authorEric Anholt <eric@anholt.net>
Mon, 20 Nov 2017 18:14:38 +0000 (10:14 -0800)
committerEric Anholt <eric@anholt.net>
Mon, 20 Nov 2017 21:54:45 +0000 (13:54 -0800)
Fixes tex-miplevel-selection GL2:texture() 1D

src/gallium/drivers/vc5/vc5_resource.c patch | blob | history

diff --git a/src/gallium/drivers/vc5/vc5_resource.c b/src/gallium/drivers/vc5/vc5_resource.c
index dad238f89fbaed6e26c65a0cf284878428a66bd8..768f8d41f08ae7151c2d149492f7c0865144718d 100644 (file)
--- a/src/gallium/drivers/vc5/vc5_resource.c
+++ b/src/gallium/drivers/vc5/vc5_resource.c
@@ -442,6 +442,8 @@ vc5_setup_slices(struct vc5_resource *rsc)
 
                 if (!rsc->tiled) {
                         slice->tiling = VC5_TILING_RASTER;
+                        if (prsc->target == PIPE_TEXTURE_1D)
+                                level_width = align(level_width, 64 / rsc->cpp);
                 } else {
                         if ((i != 0 || !uif_top) &&
                             (level_width <= utile_w ||