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radeonsi: cache flush/invalidation for missing PIPE_BARRIER_*_BUFFER bits (v2)
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37 #include "util/u_resource.h"
38
39 /* Initialize an external atom (owned by ../radeon). */
40 static void
41 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
42 struct r600_atom **list_elem)
43 {
44 atom->id = list_elem - sctx->atoms.array + 1;
45 *list_elem = atom;
46 }
47
48 /* Initialize an atom owned by radeonsi. */
49 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
50 struct r600_atom **list_elem,
51 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
52 {
53 atom->emit = (void*)emit_func;
54 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
55 *list_elem = atom;
56 }
57
58 unsigned si_array_mode(unsigned mode)
59 {
60 switch (mode) {
61 case RADEON_SURF_MODE_LINEAR_ALIGNED:
62 return V_009910_ARRAY_LINEAR_ALIGNED;
63 case RADEON_SURF_MODE_1D:
64 return V_009910_ARRAY_1D_TILED_THIN1;
65 case RADEON_SURF_MODE_2D:
66 return V_009910_ARRAY_2D_TILED_THIN1;
67 default:
68 case RADEON_SURF_MODE_LINEAR:
69 return V_009910_ARRAY_LINEAR_GENERAL;
70 }
71 }
72
73 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
74 {
75 if (sscreen->b.chip_class >= CIK &&
76 sscreen->b.info.cik_macrotile_mode_array_valid) {
77 unsigned index, tileb;
78
79 tileb = 8 * 8 * tex->surface.bpe;
80 tileb = MIN2(tex->surface.tile_split, tileb);
81
82 for (index = 0; tileb > 64; index++) {
83 tileb >>= 1;
84 }
85 assert(index < 16);
86
87 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
88 }
89
90 if (sscreen->b.chip_class == SI &&
91 sscreen->b.info.si_tile_mode_array_valid) {
92 /* Don't use stencil_tiling_index, because num_banks is always
93 * read from the depth mode. */
94 unsigned tile_mode_index = tex->surface.tiling_index[0];
95 assert(tile_mode_index < 32);
96
97 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
98 }
99
100 /* The old way. */
101 switch (sscreen->b.info.r600_num_banks) {
102 case 2:
103 return V_02803C_ADDR_SURF_2_BANK;
104 case 4:
105 return V_02803C_ADDR_SURF_4_BANK;
106 case 8:
107 default:
108 return V_02803C_ADDR_SURF_8_BANK;
109 case 16:
110 return V_02803C_ADDR_SURF_16_BANK;
111 }
112 }
113
114 unsigned cik_tile_split(unsigned tile_split)
115 {
116 switch (tile_split) {
117 case 64:
118 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
119 break;
120 case 128:
121 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
122 break;
123 case 256:
124 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
125 break;
126 case 512:
127 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
128 break;
129 default:
130 case 1024:
131 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
132 break;
133 case 2048:
134 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
135 break;
136 case 4096:
137 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
138 break;
139 }
140 return tile_split;
141 }
142
143 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
144 {
145 switch (macro_tile_aspect) {
146 default:
147 case 1:
148 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
149 break;
150 case 2:
151 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
152 break;
153 case 4:
154 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
155 break;
156 case 8:
157 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
158 break;
159 }
160 return macro_tile_aspect;
161 }
162
163 unsigned cik_bank_wh(unsigned bankwh)
164 {
165 switch (bankwh) {
166 default:
167 case 1:
168 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
169 break;
170 case 2:
171 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
172 break;
173 case 4:
174 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
175 break;
176 case 8:
177 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
178 break;
179 }
180 return bankwh;
181 }
182
183 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
184 {
185 if (sscreen->b.info.si_tile_mode_array_valid) {
186 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
187
188 return G_009910_PIPE_CONFIG(gb_tile_mode);
189 }
190
191 /* This is probably broken for a lot of chips, but it's only used
192 * if the kernel cannot return the tile mode array for CIK. */
193 switch (sscreen->b.info.num_tile_pipes) {
194 case 16:
195 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
196 case 8:
197 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
198 case 4:
199 default:
200 if (sscreen->b.info.num_render_backends == 4)
201 return V_02803C_X_ADDR_SURF_P4_16X16;
202 else
203 return V_02803C_X_ADDR_SURF_P4_8X16;
204 case 2:
205 return V_02803C_ADDR_SURF_P2;
206 }
207 }
208
209 static unsigned si_map_swizzle(unsigned swizzle)
210 {
211 switch (swizzle) {
212 case UTIL_FORMAT_SWIZZLE_Y:
213 return V_008F0C_SQ_SEL_Y;
214 case UTIL_FORMAT_SWIZZLE_Z:
215 return V_008F0C_SQ_SEL_Z;
216 case UTIL_FORMAT_SWIZZLE_W:
217 return V_008F0C_SQ_SEL_W;
218 case UTIL_FORMAT_SWIZZLE_0:
219 return V_008F0C_SQ_SEL_0;
220 case UTIL_FORMAT_SWIZZLE_1:
221 return V_008F0C_SQ_SEL_1;
222 default: /* UTIL_FORMAT_SWIZZLE_X */
223 return V_008F0C_SQ_SEL_X;
224 }
225 }
226
227 static uint32_t S_FIXED(float value, uint32_t frac_bits)
228 {
229 return value * (1 << frac_bits);
230 }
231
232 /* 12.4 fixed-point */
233 static unsigned si_pack_float_12p4(float x)
234 {
235 return x <= 0 ? 0 :
236 x >= 4096 ? 0xffff : x * 16;
237 }
238
239 /*
240 * Inferred framebuffer and blender state.
241 *
242 * One of the reasons CB_TARGET_MASK must be derived from the framebuffer state
243 * is that:
244 * - The blend state mask is 0xf most of the time.
245 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
246 * so COLOR1 is enabled pretty much all the time.
247 * So CB_TARGET_MASK is the only register that can disable COLOR1.
248 *
249 * Another reason is to avoid a hang with dual source blending.
250 */
251 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
252 {
253 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
254 struct si_state_blend *blend = sctx->queued.named.blend;
255 uint32_t cb_target_mask = 0, i;
256
257 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
258 if (sctx->framebuffer.state.cbufs[i])
259 cb_target_mask |= 0xf << (4*i);
260
261 if (blend)
262 cb_target_mask &= blend->cb_target_mask;
263
264 /* Avoid a hang that happens when dual source blending is enabled
265 * but there is not enough color outputs. This is undefined behavior,
266 * so disable color writes completely.
267 *
268 * Reproducible with Unigine Heaven 4.0 and drirc missing.
269 */
270 if (blend && blend->dual_src_blend &&
271 sctx->ps_shader.cso &&
272 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
273 cb_target_mask = 0;
274
275 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
276
277 /* STONEY-specific register settings. */
278 if (sctx->b.family == CHIP_STONEY) {
279 unsigned spi_shader_col_format =
280 sctx->ps_shader.cso ?
281 sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0;
282 unsigned sx_ps_downconvert = 0;
283 unsigned sx_blend_opt_epsilon = 0;
284 unsigned sx_blend_opt_control = 0;
285
286 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
287 struct r600_surface *surf =
288 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
289 unsigned format, swap, spi_format, colormask;
290 bool has_alpha, has_rgb;
291
292 if (!surf)
293 continue;
294
295 format = G_028C70_FORMAT(surf->cb_color_info);
296 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
297 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
298 colormask = (cb_target_mask >> (i * 4)) & 0xf;
299
300 /* Set if RGB and A are present. */
301 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
302
303 if (format == V_028C70_COLOR_8 ||
304 format == V_028C70_COLOR_16 ||
305 format == V_028C70_COLOR_32)
306 has_rgb = !has_alpha;
307 else
308 has_rgb = true;
309
310 /* Check the colormask and export format. */
311 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
312 has_rgb = false;
313 if (!(colormask & PIPE_MASK_A))
314 has_alpha = false;
315
316 if (spi_format == V_028714_SPI_SHADER_ZERO) {
317 has_rgb = false;
318 has_alpha = false;
319 }
320
321 /* Disable value checking for disabled channels. */
322 if (!has_rgb)
323 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
324 if (!has_alpha)
325 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
326
327 /* Enable down-conversion for 32bpp and smaller formats. */
328 switch (format) {
329 case V_028C70_COLOR_8:
330 case V_028C70_COLOR_8_8:
331 case V_028C70_COLOR_8_8_8_8:
332 /* For 1 and 2-channel formats, use the superset thereof. */
333 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
334 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
335 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
336 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
337 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
338 }
339 break;
340
341 case V_028C70_COLOR_5_6_5:
342 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
343 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
344 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
345 }
346 break;
347
348 case V_028C70_COLOR_1_5_5_5:
349 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
350 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
351 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
352 }
353 break;
354
355 case V_028C70_COLOR_4_4_4_4:
356 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
357 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
358 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
359 }
360 break;
361
362 case V_028C70_COLOR_32:
363 if (swap == V_0280A0_SWAP_STD &&
364 spi_format == V_028714_SPI_SHADER_32_R)
365 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
366 else if (swap == V_0280A0_SWAP_ALT_REV &&
367 spi_format == V_028714_SPI_SHADER_32_AR)
368 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
369 break;
370
371 case V_028C70_COLOR_16:
372 case V_028C70_COLOR_16_16:
373 /* For 1-channel formats, use the superset thereof. */
374 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
375 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
376 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
377 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
378 if (swap == V_0280A0_SWAP_STD ||
379 swap == V_0280A0_SWAP_STD_REV)
380 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
381 else
382 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
383 }
384 break;
385
386 case V_028C70_COLOR_10_11_11:
387 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
388 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
389 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
390 }
391 break;
392
393 case V_028C70_COLOR_2_10_10_10:
394 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
395 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
396 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
397 }
398 break;
399 }
400 }
401
402 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
403 sx_ps_downconvert = 0;
404 sx_blend_opt_epsilon = 0;
405 sx_blend_opt_control = 0;
406 }
407
408 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
409 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
410 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
411 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
412 }
413 }
414
415 /*
416 * Blender functions
417 */
418
419 static uint32_t si_translate_blend_function(int blend_func)
420 {
421 switch (blend_func) {
422 case PIPE_BLEND_ADD:
423 return V_028780_COMB_DST_PLUS_SRC;
424 case PIPE_BLEND_SUBTRACT:
425 return V_028780_COMB_SRC_MINUS_DST;
426 case PIPE_BLEND_REVERSE_SUBTRACT:
427 return V_028780_COMB_DST_MINUS_SRC;
428 case PIPE_BLEND_MIN:
429 return V_028780_COMB_MIN_DST_SRC;
430 case PIPE_BLEND_MAX:
431 return V_028780_COMB_MAX_DST_SRC;
432 default:
433 R600_ERR("Unknown blend function %d\n", blend_func);
434 assert(0);
435 break;
436 }
437 return 0;
438 }
439
440 static uint32_t si_translate_blend_factor(int blend_fact)
441 {
442 switch (blend_fact) {
443 case PIPE_BLENDFACTOR_ONE:
444 return V_028780_BLEND_ONE;
445 case PIPE_BLENDFACTOR_SRC_COLOR:
446 return V_028780_BLEND_SRC_COLOR;
447 case PIPE_BLENDFACTOR_SRC_ALPHA:
448 return V_028780_BLEND_SRC_ALPHA;
449 case PIPE_BLENDFACTOR_DST_ALPHA:
450 return V_028780_BLEND_DST_ALPHA;
451 case PIPE_BLENDFACTOR_DST_COLOR:
452 return V_028780_BLEND_DST_COLOR;
453 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
454 return V_028780_BLEND_SRC_ALPHA_SATURATE;
455 case PIPE_BLENDFACTOR_CONST_COLOR:
456 return V_028780_BLEND_CONSTANT_COLOR;
457 case PIPE_BLENDFACTOR_CONST_ALPHA:
458 return V_028780_BLEND_CONSTANT_ALPHA;
459 case PIPE_BLENDFACTOR_ZERO:
460 return V_028780_BLEND_ZERO;
461 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
462 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
463 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
464 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
465 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
466 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
467 case PIPE_BLENDFACTOR_INV_DST_COLOR:
468 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
469 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
470 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
471 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
472 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
473 case PIPE_BLENDFACTOR_SRC1_COLOR:
474 return V_028780_BLEND_SRC1_COLOR;
475 case PIPE_BLENDFACTOR_SRC1_ALPHA:
476 return V_028780_BLEND_SRC1_ALPHA;
477 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
478 return V_028780_BLEND_INV_SRC1_COLOR;
479 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
480 return V_028780_BLEND_INV_SRC1_ALPHA;
481 default:
482 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
483 assert(0);
484 break;
485 }
486 return 0;
487 }
488
489 static uint32_t si_translate_blend_opt_function(int blend_func)
490 {
491 switch (blend_func) {
492 case PIPE_BLEND_ADD:
493 return V_028760_OPT_COMB_ADD;
494 case PIPE_BLEND_SUBTRACT:
495 return V_028760_OPT_COMB_SUBTRACT;
496 case PIPE_BLEND_REVERSE_SUBTRACT:
497 return V_028760_OPT_COMB_REVSUBTRACT;
498 case PIPE_BLEND_MIN:
499 return V_028760_OPT_COMB_MIN;
500 case PIPE_BLEND_MAX:
501 return V_028760_OPT_COMB_MAX;
502 default:
503 return V_028760_OPT_COMB_BLEND_DISABLED;
504 }
505 }
506
507 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
508 {
509 switch (blend_fact) {
510 case PIPE_BLENDFACTOR_ZERO:
511 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
512 case PIPE_BLENDFACTOR_ONE:
513 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
514 case PIPE_BLENDFACTOR_SRC_COLOR:
515 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
516 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
517 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
518 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
519 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
520 case PIPE_BLENDFACTOR_SRC_ALPHA:
521 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
522 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
523 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
524 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
525 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
526 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
527 default:
528 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
529 }
530 }
531
532 /**
533 * Get rid of DST in the blend factors by commuting the operands:
534 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
535 */
536 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
537 unsigned *dst_factor, unsigned expected_dst,
538 unsigned replacement_src)
539 {
540 if (*src_factor == expected_dst &&
541 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
542 *src_factor = PIPE_BLENDFACTOR_ZERO;
543 *dst_factor = replacement_src;
544
545 /* Commuting the operands requires reversing subtractions. */
546 if (*func == PIPE_BLEND_SUBTRACT)
547 *func = PIPE_BLEND_REVERSE_SUBTRACT;
548 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
549 *func = PIPE_BLEND_SUBTRACT;
550 }
551 }
552
553 static bool si_blend_factor_uses_dst(unsigned factor)
554 {
555 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
556 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
557 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
558 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
559 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
560 }
561
562 static void *si_create_blend_state_mode(struct pipe_context *ctx,
563 const struct pipe_blend_state *state,
564 unsigned mode)
565 {
566 struct si_context *sctx = (struct si_context*)ctx;
567 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
568 struct si_pm4_state *pm4 = &blend->pm4;
569 uint32_t sx_mrt_blend_opt[8] = {0};
570 uint32_t color_control = 0;
571
572 if (!blend)
573 return NULL;
574
575 blend->alpha_to_coverage = state->alpha_to_coverage;
576 blend->alpha_to_one = state->alpha_to_one;
577 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
578
579 if (state->logicop_enable) {
580 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
581 } else {
582 color_control |= S_028808_ROP3(0xcc);
583 }
584
585 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
586 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
587 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
588 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
589 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
590 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
591
592 if (state->alpha_to_coverage)
593 blend->need_src_alpha_4bit |= 0xf;
594
595 blend->cb_target_mask = 0;
596 for (int i = 0; i < 8; i++) {
597 /* state->rt entries > 0 only written if independent blending */
598 const int j = state->independent_blend_enable ? i : 0;
599
600 unsigned eqRGB = state->rt[j].rgb_func;
601 unsigned srcRGB = state->rt[j].rgb_src_factor;
602 unsigned dstRGB = state->rt[j].rgb_dst_factor;
603 unsigned eqA = state->rt[j].alpha_func;
604 unsigned srcA = state->rt[j].alpha_src_factor;
605 unsigned dstA = state->rt[j].alpha_dst_factor;
606
607 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
608 unsigned blend_cntl = 0;
609
610 sx_mrt_blend_opt[i] =
611 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
612 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
613
614 if (!state->rt[j].colormask)
615 continue;
616
617 /* cb_render_state will disable unused ones */
618 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
619
620 if (!state->rt[j].blend_enable) {
621 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
622 continue;
623 }
624
625 /* Blending optimizations for Stoney.
626 * These transformations don't change the behavior.
627 *
628 * First, get rid of DST in the blend factors:
629 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
630 */
631 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
632 PIPE_BLENDFACTOR_DST_COLOR,
633 PIPE_BLENDFACTOR_SRC_COLOR);
634 si_blend_remove_dst(&eqA, &srcA, &dstA,
635 PIPE_BLENDFACTOR_DST_COLOR,
636 PIPE_BLENDFACTOR_SRC_COLOR);
637 si_blend_remove_dst(&eqA, &srcA, &dstA,
638 PIPE_BLENDFACTOR_DST_ALPHA,
639 PIPE_BLENDFACTOR_SRC_ALPHA);
640
641 /* Look up the ideal settings from tables. */
642 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
643 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
644 srcA_opt = si_translate_blend_opt_factor(srcA, true);
645 dstA_opt = si_translate_blend_opt_factor(dstA, true);
646
647 /* Handle interdependencies. */
648 if (si_blend_factor_uses_dst(srcRGB))
649 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
650 if (si_blend_factor_uses_dst(srcA))
651 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
652
653 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
654 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
655 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
656 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
657 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
658
659 /* Set the final value. */
660 sx_mrt_blend_opt[i] =
661 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
662 S_028760_COLOR_DST_OPT(dstRGB_opt) |
663 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
664 S_028760_ALPHA_SRC_OPT(srcA_opt) |
665 S_028760_ALPHA_DST_OPT(dstA_opt) |
666 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
667
668 /* Set blend state. */
669 blend_cntl |= S_028780_ENABLE(1);
670 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
671 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
672 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
673
674 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
675 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
676 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
677 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
678 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
679 }
680 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
681
682 blend->blend_enable_4bit |= 0xf << (i * 4);
683
684 /* This is only important for formats without alpha. */
685 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
686 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
687 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
688 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
689 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
690 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
691 blend->need_src_alpha_4bit |= 0xf << (i * 4);
692 }
693
694 if (blend->cb_target_mask) {
695 color_control |= S_028808_MODE(mode);
696 } else {
697 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
698 }
699
700 if (sctx->b.family == CHIP_STONEY) {
701 for (int i = 0; i < 8; i++)
702 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
703 sx_mrt_blend_opt[i]);
704
705 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
706 if (blend->dual_src_blend || state->logicop_enable ||
707 mode == V_028808_CB_RESOLVE)
708 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
709 }
710
711 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
712 return blend;
713 }
714
715 static void *si_create_blend_state(struct pipe_context *ctx,
716 const struct pipe_blend_state *state)
717 {
718 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
719 }
720
721 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
722 {
723 struct si_context *sctx = (struct si_context *)ctx;
724 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
725 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
726 }
727
728 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
729 {
730 struct si_context *sctx = (struct si_context *)ctx;
731 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
732 }
733
734 static void si_set_blend_color(struct pipe_context *ctx,
735 const struct pipe_blend_color *state)
736 {
737 struct si_context *sctx = (struct si_context *)ctx;
738
739 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
740 return;
741
742 sctx->blend_color.state = *state;
743 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
744 }
745
746 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
747 {
748 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
749
750 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
751 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
752 }
753
754 /*
755 * Clipping, scissors and viewport
756 */
757
758 static void si_set_clip_state(struct pipe_context *ctx,
759 const struct pipe_clip_state *state)
760 {
761 struct si_context *sctx = (struct si_context *)ctx;
762 struct pipe_constant_buffer cb;
763
764 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
765 return;
766
767 sctx->clip_state.state = *state;
768 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
769
770 cb.buffer = NULL;
771 cb.user_buffer = state->ucp;
772 cb.buffer_offset = 0;
773 cb.buffer_size = 4*4*8;
774 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
775 pipe_resource_reference(&cb.buffer, NULL);
776 }
777
778 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
779 {
780 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
781
782 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
783 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
784 }
785
786 #define SIX_BITS 0x3F
787
788 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
789 {
790 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
791 struct tgsi_shader_info *info = si_get_vs_info(sctx);
792 unsigned window_space =
793 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
794 unsigned clipdist_mask =
795 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
796
797 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
798 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
799 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
800 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
801 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
802 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
803 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
804 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
805 info->writes_edgeflag ||
806 info->writes_layer ||
807 info->writes_viewport_index) |
808 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
809 (sctx->queued.named.rasterizer->clip_plane_enable &
810 clipdist_mask));
811 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
812 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
813 (clipdist_mask ? 0 :
814 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
815 S_028810_CLIP_DISABLE(window_space));
816
817 /* reuse needs to be set off if we write oViewport */
818 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
819 S_028AB4_REUSE_OFF(info->writes_viewport_index));
820 }
821
822 static void si_set_scissor_states(struct pipe_context *ctx,
823 unsigned start_slot,
824 unsigned num_scissors,
825 const struct pipe_scissor_state *state)
826 {
827 struct si_context *sctx = (struct si_context *)ctx;
828 int i;
829
830 for (i = 0; i < num_scissors; i++)
831 sctx->scissors.states[start_slot + i] = state[i];
832
833 sctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
834 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
835 }
836
837 static void si_emit_scissors(struct si_context *sctx, struct r600_atom *atom)
838 {
839 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
840 struct pipe_scissor_state *states = sctx->scissors.states;
841 unsigned mask = sctx->scissors.dirty_mask;
842
843 /* The simple case: Only 1 viewport is active. */
844 if (mask & 1 &&
845 !si_get_vs_info(sctx)->writes_viewport_index) {
846 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
847 radeon_emit(cs, S_028250_TL_X(states[0].minx) |
848 S_028250_TL_Y(states[0].miny) |
849 S_028250_WINDOW_OFFSET_DISABLE(1));
850 radeon_emit(cs, S_028254_BR_X(states[0].maxx) |
851 S_028254_BR_Y(states[0].maxy));
852 sctx->scissors.dirty_mask &= ~1; /* clear one bit */
853 return;
854 }
855
856 while (mask) {
857 int start, count, i;
858
859 u_bit_scan_consecutive_range(&mask, &start, &count);
860
861 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
862 start * 4 * 2, count * 2);
863 for (i = start; i < start+count; i++) {
864 radeon_emit(cs, S_028250_TL_X(states[i].minx) |
865 S_028250_TL_Y(states[i].miny) |
866 S_028250_WINDOW_OFFSET_DISABLE(1));
867 radeon_emit(cs, S_028254_BR_X(states[i].maxx) |
868 S_028254_BR_Y(states[i].maxy));
869 }
870 }
871 sctx->scissors.dirty_mask = 0;
872 }
873
874 static void si_set_viewport_states(struct pipe_context *ctx,
875 unsigned start_slot,
876 unsigned num_viewports,
877 const struct pipe_viewport_state *state)
878 {
879 struct si_context *sctx = (struct si_context *)ctx;
880 int i;
881
882 for (i = 0; i < num_viewports; i++)
883 sctx->viewports.states[start_slot + i] = state[i];
884
885 sctx->viewports.dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
886 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
887 }
888
889 static void si_emit_viewports(struct si_context *sctx, struct r600_atom *atom)
890 {
891 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
892 struct pipe_viewport_state *states = sctx->viewports.states;
893 unsigned mask = sctx->viewports.dirty_mask;
894
895 /* The simple case: Only 1 viewport is active. */
896 if (mask & 1 &&
897 !si_get_vs_info(sctx)->writes_viewport_index) {
898 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
899 radeon_emit(cs, fui(states[0].scale[0]));
900 radeon_emit(cs, fui(states[0].translate[0]));
901 radeon_emit(cs, fui(states[0].scale[1]));
902 radeon_emit(cs, fui(states[0].translate[1]));
903 radeon_emit(cs, fui(states[0].scale[2]));
904 radeon_emit(cs, fui(states[0].translate[2]));
905 sctx->viewports.dirty_mask &= ~1; /* clear one bit */
906 return;
907 }
908
909 while (mask) {
910 int start, count, i;
911
912 u_bit_scan_consecutive_range(&mask, &start, &count);
913
914 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
915 start * 4 * 6, count * 6);
916 for (i = start; i < start+count; i++) {
917 radeon_emit(cs, fui(states[i].scale[0]));
918 radeon_emit(cs, fui(states[i].translate[0]));
919 radeon_emit(cs, fui(states[i].scale[1]));
920 radeon_emit(cs, fui(states[i].translate[1]));
921 radeon_emit(cs, fui(states[i].scale[2]));
922 radeon_emit(cs, fui(states[i].translate[2]));
923 }
924 }
925 sctx->viewports.dirty_mask = 0;
926 }
927
928 /*
929 * inferred state between framebuffer and rasterizer
930 */
931 static void si_update_poly_offset_state(struct si_context *sctx)
932 {
933 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
934
935 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
936 return;
937
938 switch (sctx->framebuffer.state.zsbuf->texture->format) {
939 case PIPE_FORMAT_Z16_UNORM:
940 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
941 break;
942 default: /* 24-bit */
943 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
944 break;
945 case PIPE_FORMAT_Z32_FLOAT:
946 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
947 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
948 break;
949 }
950 }
951
952 /*
953 * Rasterizer
954 */
955
956 static uint32_t si_translate_fill(uint32_t func)
957 {
958 switch(func) {
959 case PIPE_POLYGON_MODE_FILL:
960 return V_028814_X_DRAW_TRIANGLES;
961 case PIPE_POLYGON_MODE_LINE:
962 return V_028814_X_DRAW_LINES;
963 case PIPE_POLYGON_MODE_POINT:
964 return V_028814_X_DRAW_POINTS;
965 default:
966 assert(0);
967 return V_028814_X_DRAW_POINTS;
968 }
969 }
970
971 static void *si_create_rs_state(struct pipe_context *ctx,
972 const struct pipe_rasterizer_state *state)
973 {
974 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
975 struct si_pm4_state *pm4 = &rs->pm4;
976 unsigned tmp, i;
977 float psize_min, psize_max;
978
979 if (!rs) {
980 return NULL;
981 }
982
983 rs->two_side = state->light_twoside;
984 rs->multisample_enable = state->multisample;
985 rs->force_persample_interp = state->force_persample_interp;
986 rs->clip_plane_enable = state->clip_plane_enable;
987 rs->line_stipple_enable = state->line_stipple_enable;
988 rs->poly_stipple_enable = state->poly_stipple_enable;
989 rs->line_smooth = state->line_smooth;
990 rs->poly_smooth = state->poly_smooth;
991 rs->uses_poly_offset = state->offset_point || state->offset_line ||
992 state->offset_tri;
993 rs->clamp_fragment_color = state->clamp_fragment_color;
994 rs->flatshade = state->flatshade;
995 rs->sprite_coord_enable = state->sprite_coord_enable;
996 rs->rasterizer_discard = state->rasterizer_discard;
997 rs->pa_sc_line_stipple = state->line_stipple_enable ?
998 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
999 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
1000 rs->pa_cl_clip_cntl =
1001 S_028810_PS_UCP_MODE(3) |
1002 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
1003 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
1004 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
1005 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
1006 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1007
1008 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
1009 S_0286D4_FLAT_SHADE_ENA(1) |
1010 S_0286D4_PNT_SPRITE_ENA(1) |
1011 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1012 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1013 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1014 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1015 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
1016
1017 /* point size 12.4 fixed point */
1018 tmp = (unsigned)(state->point_size * 8.0);
1019 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
1020
1021 if (state->point_size_per_vertex) {
1022 psize_min = util_get_min_point_size(state);
1023 psize_max = 8192;
1024 } else {
1025 /* Force the point size to be as if the vertex output was disabled. */
1026 psize_min = state->point_size;
1027 psize_max = state->point_size;
1028 }
1029 /* Divide by two, because 0.5 = 1 pixel. */
1030 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
1031 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
1032 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
1033
1034 tmp = (unsigned)state->line_width * 8;
1035 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
1036 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
1037 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
1038 S_028A48_MSAA_ENABLE(state->multisample ||
1039 state->poly_smooth ||
1040 state->line_smooth) |
1041 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
1042
1043 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
1044 S_028BE4_PIX_CENTER(state->half_pixel_center) |
1045 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
1046
1047 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
1048 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
1049 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
1050 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
1051 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
1052 S_028814_FACE(!state->front_ccw) |
1053 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
1054 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
1055 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
1056 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
1057 state->fill_back != PIPE_POLYGON_MODE_FILL) |
1058 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
1059 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
1060 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
1061 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
1062
1063 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
1064 for (i = 0; i < 3; i++) {
1065 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
1066 float offset_units = state->offset_units;
1067 float offset_scale = state->offset_scale * 16.0f;
1068
1069 switch (i) {
1070 case 0: /* 16-bit zbuffer */
1071 offset_units *= 4.0f;
1072 break;
1073 case 1: /* 24-bit zbuffer */
1074 offset_units *= 2.0f;
1075 break;
1076 case 2: /* 32-bit zbuffer */
1077 offset_units *= 1.0f;
1078 break;
1079 }
1080
1081 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1082 fui(offset_scale));
1083 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1084 fui(offset_units));
1085 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1086 fui(offset_scale));
1087 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1088 fui(offset_units));
1089 }
1090
1091 return rs;
1092 }
1093
1094 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1095 {
1096 struct si_context *sctx = (struct si_context *)ctx;
1097 struct si_state_rasterizer *old_rs =
1098 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
1099 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1100
1101 if (!state)
1102 return;
1103
1104 if (sctx->framebuffer.nr_samples > 1 &&
1105 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
1106 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1107
1108 si_pm4_bind_state(sctx, rasterizer, rs);
1109 si_update_poly_offset_state(sctx);
1110
1111 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1112 }
1113
1114 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1115 {
1116 struct si_context *sctx = (struct si_context *)ctx;
1117
1118 if (sctx->queued.named.rasterizer == state)
1119 si_pm4_bind_state(sctx, poly_offset, NULL);
1120 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
1121 }
1122
1123 /*
1124 * infeered state between dsa and stencil ref
1125 */
1126 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
1127 {
1128 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1129 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1130 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1131
1132 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1133 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1134 S_028430_STENCILMASK(dsa->valuemask[0]) |
1135 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1136 S_028430_STENCILOPVAL(1));
1137 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1138 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1139 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1140 S_028434_STENCILOPVAL_BF(1));
1141 }
1142
1143 static void si_set_stencil_ref(struct pipe_context *ctx,
1144 const struct pipe_stencil_ref *state)
1145 {
1146 struct si_context *sctx = (struct si_context *)ctx;
1147
1148 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1149 return;
1150
1151 sctx->stencil_ref.state = *state;
1152 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1153 }
1154
1155
1156 /*
1157 * DSA
1158 */
1159
1160 static uint32_t si_translate_stencil_op(int s_op)
1161 {
1162 switch (s_op) {
1163 case PIPE_STENCIL_OP_KEEP:
1164 return V_02842C_STENCIL_KEEP;
1165 case PIPE_STENCIL_OP_ZERO:
1166 return V_02842C_STENCIL_ZERO;
1167 case PIPE_STENCIL_OP_REPLACE:
1168 return V_02842C_STENCIL_REPLACE_TEST;
1169 case PIPE_STENCIL_OP_INCR:
1170 return V_02842C_STENCIL_ADD_CLAMP;
1171 case PIPE_STENCIL_OP_DECR:
1172 return V_02842C_STENCIL_SUB_CLAMP;
1173 case PIPE_STENCIL_OP_INCR_WRAP:
1174 return V_02842C_STENCIL_ADD_WRAP;
1175 case PIPE_STENCIL_OP_DECR_WRAP:
1176 return V_02842C_STENCIL_SUB_WRAP;
1177 case PIPE_STENCIL_OP_INVERT:
1178 return V_02842C_STENCIL_INVERT;
1179 default:
1180 R600_ERR("Unknown stencil op %d", s_op);
1181 assert(0);
1182 break;
1183 }
1184 return 0;
1185 }
1186
1187 static void *si_create_dsa_state(struct pipe_context *ctx,
1188 const struct pipe_depth_stencil_alpha_state *state)
1189 {
1190 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1191 struct si_pm4_state *pm4 = &dsa->pm4;
1192 unsigned db_depth_control;
1193 uint32_t db_stencil_control = 0;
1194
1195 if (!dsa) {
1196 return NULL;
1197 }
1198
1199 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1200 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1201 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1202 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1203
1204 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1205 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1206 S_028800_ZFUNC(state->depth.func) |
1207 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1208
1209 /* stencil */
1210 if (state->stencil[0].enabled) {
1211 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1212 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1213 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1214 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1215 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1216
1217 if (state->stencil[1].enabled) {
1218 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1219 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1220 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1221 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1222 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1223 }
1224 }
1225
1226 /* alpha */
1227 if (state->alpha.enabled) {
1228 dsa->alpha_func = state->alpha.func;
1229
1230 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1231 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1232 } else {
1233 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1234 }
1235
1236 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1237 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1238 if (state->depth.bounds_test) {
1239 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1240 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1241 }
1242
1243 return dsa;
1244 }
1245
1246 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1247 {
1248 struct si_context *sctx = (struct si_context *)ctx;
1249 struct si_state_dsa *dsa = state;
1250
1251 if (!state)
1252 return;
1253
1254 si_pm4_bind_state(sctx, dsa, dsa);
1255
1256 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1257 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1258 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1259 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1260 }
1261 }
1262
1263 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1264 {
1265 struct si_context *sctx = (struct si_context *)ctx;
1266 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1267 }
1268
1269 static void *si_create_db_flush_dsa(struct si_context *sctx)
1270 {
1271 struct pipe_depth_stencil_alpha_state dsa = {};
1272
1273 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1274 }
1275
1276 /* DB RENDER STATE */
1277
1278 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1279 {
1280 struct si_context *sctx = (struct si_context*)ctx;
1281
1282 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1283 }
1284
1285 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1286 {
1287 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1288 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1289 unsigned db_shader_control;
1290
1291 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1292
1293 /* DB_RENDER_CONTROL */
1294 if (sctx->dbcb_depth_copy_enabled ||
1295 sctx->dbcb_stencil_copy_enabled) {
1296 radeon_emit(cs,
1297 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1298 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1299 S_028000_COPY_CENTROID(1) |
1300 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1301 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1302 radeon_emit(cs,
1303 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1304 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1305 } else {
1306 radeon_emit(cs,
1307 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1308 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1309 }
1310
1311 /* DB_COUNT_CONTROL (occlusion queries) */
1312 if (sctx->b.num_occlusion_queries > 0) {
1313 if (sctx->b.chip_class >= CIK) {
1314 radeon_emit(cs,
1315 S_028004_PERFECT_ZPASS_COUNTS(1) |
1316 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1317 S_028004_ZPASS_ENABLE(1) |
1318 S_028004_SLICE_EVEN_ENABLE(1) |
1319 S_028004_SLICE_ODD_ENABLE(1));
1320 } else {
1321 radeon_emit(cs,
1322 S_028004_PERFECT_ZPASS_COUNTS(1) |
1323 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1324 }
1325 } else {
1326 /* Disable occlusion queries. */
1327 if (sctx->b.chip_class >= CIK) {
1328 radeon_emit(cs, 0);
1329 } else {
1330 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1331 }
1332 }
1333
1334 /* DB_RENDER_OVERRIDE2 */
1335 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1336 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1337 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear));
1338
1339 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1340 sctx->ps_db_shader_control;
1341
1342 /* Bug workaround for smoothing (overrasterization) on SI. */
1343 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1344 db_shader_control &= C_02880C_Z_ORDER;
1345 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1346 }
1347
1348 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1349 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1350 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1351
1352 if (sctx->b.family == CHIP_STONEY &&
1353 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1354 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1355
1356 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1357 db_shader_control);
1358 }
1359
1360 /*
1361 * format translation
1362 */
1363 static uint32_t si_translate_colorformat(enum pipe_format format)
1364 {
1365 const struct util_format_description *desc = util_format_description(format);
1366
1367 #define HAS_SIZE(x,y,z,w) \
1368 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1369 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1370
1371 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1372 return V_028C70_COLOR_10_11_11;
1373
1374 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1375 return V_028C70_COLOR_INVALID;
1376
1377 switch (desc->nr_channels) {
1378 case 1:
1379 switch (desc->channel[0].size) {
1380 case 8:
1381 return V_028C70_COLOR_8;
1382 case 16:
1383 return V_028C70_COLOR_16;
1384 case 32:
1385 return V_028C70_COLOR_32;
1386 }
1387 break;
1388 case 2:
1389 if (desc->channel[0].size == desc->channel[1].size) {
1390 switch (desc->channel[0].size) {
1391 case 8:
1392 return V_028C70_COLOR_8_8;
1393 case 16:
1394 return V_028C70_COLOR_16_16;
1395 case 32:
1396 return V_028C70_COLOR_32_32;
1397 }
1398 } else if (HAS_SIZE(8,24,0,0)) {
1399 return V_028C70_COLOR_24_8;
1400 } else if (HAS_SIZE(24,8,0,0)) {
1401 return V_028C70_COLOR_8_24;
1402 }
1403 break;
1404 case 3:
1405 if (HAS_SIZE(5,6,5,0)) {
1406 return V_028C70_COLOR_5_6_5;
1407 } else if (HAS_SIZE(32,8,24,0)) {
1408 return V_028C70_COLOR_X24_8_32_FLOAT;
1409 }
1410 break;
1411 case 4:
1412 if (desc->channel[0].size == desc->channel[1].size &&
1413 desc->channel[0].size == desc->channel[2].size &&
1414 desc->channel[0].size == desc->channel[3].size) {
1415 switch (desc->channel[0].size) {
1416 case 4:
1417 return V_028C70_COLOR_4_4_4_4;
1418 case 8:
1419 return V_028C70_COLOR_8_8_8_8;
1420 case 16:
1421 return V_028C70_COLOR_16_16_16_16;
1422 case 32:
1423 return V_028C70_COLOR_32_32_32_32;
1424 }
1425 } else if (HAS_SIZE(5,5,5,1)) {
1426 return V_028C70_COLOR_1_5_5_5;
1427 } else if (HAS_SIZE(10,10,10,2)) {
1428 return V_028C70_COLOR_2_10_10_10;
1429 }
1430 break;
1431 }
1432 return V_028C70_COLOR_INVALID;
1433 }
1434
1435 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1436 {
1437 if (SI_BIG_ENDIAN) {
1438 switch(colorformat) {
1439 /* 8-bit buffers. */
1440 case V_028C70_COLOR_8:
1441 return V_028C70_ENDIAN_NONE;
1442
1443 /* 16-bit buffers. */
1444 case V_028C70_COLOR_5_6_5:
1445 case V_028C70_COLOR_1_5_5_5:
1446 case V_028C70_COLOR_4_4_4_4:
1447 case V_028C70_COLOR_16:
1448 case V_028C70_COLOR_8_8:
1449 return V_028C70_ENDIAN_8IN16;
1450
1451 /* 32-bit buffers. */
1452 case V_028C70_COLOR_8_8_8_8:
1453 case V_028C70_COLOR_2_10_10_10:
1454 case V_028C70_COLOR_8_24:
1455 case V_028C70_COLOR_24_8:
1456 case V_028C70_COLOR_16_16:
1457 return V_028C70_ENDIAN_8IN32;
1458
1459 /* 64-bit buffers. */
1460 case V_028C70_COLOR_16_16_16_16:
1461 return V_028C70_ENDIAN_8IN16;
1462
1463 case V_028C70_COLOR_32_32:
1464 return V_028C70_ENDIAN_8IN32;
1465
1466 /* 128-bit buffers. */
1467 case V_028C70_COLOR_32_32_32_32:
1468 return V_028C70_ENDIAN_8IN32;
1469 default:
1470 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1471 }
1472 } else {
1473 return V_028C70_ENDIAN_NONE;
1474 }
1475 }
1476
1477 static uint32_t si_translate_dbformat(enum pipe_format format)
1478 {
1479 switch (format) {
1480 case PIPE_FORMAT_Z16_UNORM:
1481 return V_028040_Z_16;
1482 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1483 case PIPE_FORMAT_X8Z24_UNORM:
1484 case PIPE_FORMAT_Z24X8_UNORM:
1485 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1486 return V_028040_Z_24; /* deprecated on SI */
1487 case PIPE_FORMAT_Z32_FLOAT:
1488 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1489 return V_028040_Z_32_FLOAT;
1490 default:
1491 return V_028040_Z_INVALID;
1492 }
1493 }
1494
1495 /*
1496 * Texture translation
1497 */
1498
1499 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1500 enum pipe_format format,
1501 const struct util_format_description *desc,
1502 int first_non_void)
1503 {
1504 struct si_screen *sscreen = (struct si_screen*)screen;
1505 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1506 sscreen->b.info.drm_minor >= 31) ||
1507 sscreen->b.info.drm_major == 3;
1508 boolean uniform = TRUE;
1509 int i;
1510
1511 /* Colorspace (return non-RGB formats directly). */
1512 switch (desc->colorspace) {
1513 /* Depth stencil formats */
1514 case UTIL_FORMAT_COLORSPACE_ZS:
1515 switch (format) {
1516 case PIPE_FORMAT_Z16_UNORM:
1517 return V_008F14_IMG_DATA_FORMAT_16;
1518 case PIPE_FORMAT_X24S8_UINT:
1519 case PIPE_FORMAT_Z24X8_UNORM:
1520 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1521 return V_008F14_IMG_DATA_FORMAT_8_24;
1522 case PIPE_FORMAT_X8Z24_UNORM:
1523 case PIPE_FORMAT_S8X24_UINT:
1524 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1525 return V_008F14_IMG_DATA_FORMAT_24_8;
1526 case PIPE_FORMAT_S8_UINT:
1527 return V_008F14_IMG_DATA_FORMAT_8;
1528 case PIPE_FORMAT_Z32_FLOAT:
1529 return V_008F14_IMG_DATA_FORMAT_32;
1530 case PIPE_FORMAT_X32_S8X24_UINT:
1531 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1532 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1533 default:
1534 goto out_unknown;
1535 }
1536
1537 case UTIL_FORMAT_COLORSPACE_YUV:
1538 goto out_unknown; /* TODO */
1539
1540 case UTIL_FORMAT_COLORSPACE_SRGB:
1541 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1542 goto out_unknown;
1543 break;
1544
1545 default:
1546 break;
1547 }
1548
1549 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1550 if (!enable_compressed_formats)
1551 goto out_unknown;
1552
1553 switch (format) {
1554 case PIPE_FORMAT_RGTC1_SNORM:
1555 case PIPE_FORMAT_LATC1_SNORM:
1556 case PIPE_FORMAT_RGTC1_UNORM:
1557 case PIPE_FORMAT_LATC1_UNORM:
1558 return V_008F14_IMG_DATA_FORMAT_BC4;
1559 case PIPE_FORMAT_RGTC2_SNORM:
1560 case PIPE_FORMAT_LATC2_SNORM:
1561 case PIPE_FORMAT_RGTC2_UNORM:
1562 case PIPE_FORMAT_LATC2_UNORM:
1563 return V_008F14_IMG_DATA_FORMAT_BC5;
1564 default:
1565 goto out_unknown;
1566 }
1567 }
1568
1569 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1570 sscreen->b.family >= CHIP_STONEY) {
1571 switch (format) {
1572 case PIPE_FORMAT_ETC1_RGB8:
1573 case PIPE_FORMAT_ETC2_RGB8:
1574 case PIPE_FORMAT_ETC2_SRGB8:
1575 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1576 case PIPE_FORMAT_ETC2_RGB8A1:
1577 case PIPE_FORMAT_ETC2_SRGB8A1:
1578 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1579 case PIPE_FORMAT_ETC2_RGBA8:
1580 case PIPE_FORMAT_ETC2_SRGBA8:
1581 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1582 case PIPE_FORMAT_ETC2_R11_UNORM:
1583 case PIPE_FORMAT_ETC2_R11_SNORM:
1584 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1585 case PIPE_FORMAT_ETC2_RG11_UNORM:
1586 case PIPE_FORMAT_ETC2_RG11_SNORM:
1587 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1588 default:
1589 goto out_unknown;
1590 }
1591 }
1592
1593 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1594 if (!enable_compressed_formats)
1595 goto out_unknown;
1596
1597 switch (format) {
1598 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1599 case PIPE_FORMAT_BPTC_SRGBA:
1600 return V_008F14_IMG_DATA_FORMAT_BC7;
1601 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1602 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1603 return V_008F14_IMG_DATA_FORMAT_BC6;
1604 default:
1605 goto out_unknown;
1606 }
1607 }
1608
1609 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1610 switch (format) {
1611 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1612 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1613 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1614 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1615 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1616 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1617 default:
1618 goto out_unknown;
1619 }
1620 }
1621
1622 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1623 if (!enable_compressed_formats)
1624 goto out_unknown;
1625
1626 if (!util_format_s3tc_enabled) {
1627 goto out_unknown;
1628 }
1629
1630 switch (format) {
1631 case PIPE_FORMAT_DXT1_RGB:
1632 case PIPE_FORMAT_DXT1_RGBA:
1633 case PIPE_FORMAT_DXT1_SRGB:
1634 case PIPE_FORMAT_DXT1_SRGBA:
1635 return V_008F14_IMG_DATA_FORMAT_BC1;
1636 case PIPE_FORMAT_DXT3_RGBA:
1637 case PIPE_FORMAT_DXT3_SRGBA:
1638 return V_008F14_IMG_DATA_FORMAT_BC2;
1639 case PIPE_FORMAT_DXT5_RGBA:
1640 case PIPE_FORMAT_DXT5_SRGBA:
1641 return V_008F14_IMG_DATA_FORMAT_BC3;
1642 default:
1643 goto out_unknown;
1644 }
1645 }
1646
1647 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1648 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1649 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1650 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1651 }
1652
1653 /* R8G8Bx_SNORM - TODO CxV8U8 */
1654
1655 /* See whether the components are of the same size. */
1656 for (i = 1; i < desc->nr_channels; i++) {
1657 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1658 }
1659
1660 /* Non-uniform formats. */
1661 if (!uniform) {
1662 switch(desc->nr_channels) {
1663 case 3:
1664 if (desc->channel[0].size == 5 &&
1665 desc->channel[1].size == 6 &&
1666 desc->channel[2].size == 5) {
1667 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1668 }
1669 goto out_unknown;
1670 case 4:
1671 if (desc->channel[0].size == 5 &&
1672 desc->channel[1].size == 5 &&
1673 desc->channel[2].size == 5 &&
1674 desc->channel[3].size == 1) {
1675 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1676 }
1677 if (desc->channel[0].size == 10 &&
1678 desc->channel[1].size == 10 &&
1679 desc->channel[2].size == 10 &&
1680 desc->channel[3].size == 2) {
1681 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1682 }
1683 goto out_unknown;
1684 }
1685 goto out_unknown;
1686 }
1687
1688 if (first_non_void < 0 || first_non_void > 3)
1689 goto out_unknown;
1690
1691 /* uniform formats */
1692 switch (desc->channel[first_non_void].size) {
1693 case 4:
1694 switch (desc->nr_channels) {
1695 #if 0 /* Not supported for render targets */
1696 case 2:
1697 return V_008F14_IMG_DATA_FORMAT_4_4;
1698 #endif
1699 case 4:
1700 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1701 }
1702 break;
1703 case 8:
1704 switch (desc->nr_channels) {
1705 case 1:
1706 return V_008F14_IMG_DATA_FORMAT_8;
1707 case 2:
1708 return V_008F14_IMG_DATA_FORMAT_8_8;
1709 case 4:
1710 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1711 }
1712 break;
1713 case 16:
1714 switch (desc->nr_channels) {
1715 case 1:
1716 return V_008F14_IMG_DATA_FORMAT_16;
1717 case 2:
1718 return V_008F14_IMG_DATA_FORMAT_16_16;
1719 case 4:
1720 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1721 }
1722 break;
1723 case 32:
1724 switch (desc->nr_channels) {
1725 case 1:
1726 return V_008F14_IMG_DATA_FORMAT_32;
1727 case 2:
1728 return V_008F14_IMG_DATA_FORMAT_32_32;
1729 #if 0 /* Not supported for render targets */
1730 case 3:
1731 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1732 #endif
1733 case 4:
1734 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1735 }
1736 }
1737
1738 out_unknown:
1739 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1740 return ~0;
1741 }
1742
1743 static unsigned si_tex_wrap(unsigned wrap)
1744 {
1745 switch (wrap) {
1746 default:
1747 case PIPE_TEX_WRAP_REPEAT:
1748 return V_008F30_SQ_TEX_WRAP;
1749 case PIPE_TEX_WRAP_CLAMP:
1750 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1751 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1752 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1753 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1754 return V_008F30_SQ_TEX_CLAMP_BORDER;
1755 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1756 return V_008F30_SQ_TEX_MIRROR;
1757 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1758 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1759 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1760 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1761 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1762 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1763 }
1764 }
1765
1766 static unsigned si_tex_filter(unsigned filter)
1767 {
1768 switch (filter) {
1769 default:
1770 case PIPE_TEX_FILTER_NEAREST:
1771 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1772 case PIPE_TEX_FILTER_LINEAR:
1773 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1774 }
1775 }
1776
1777 static unsigned si_tex_mipfilter(unsigned filter)
1778 {
1779 switch (filter) {
1780 case PIPE_TEX_MIPFILTER_NEAREST:
1781 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1782 case PIPE_TEX_MIPFILTER_LINEAR:
1783 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1784 default:
1785 case PIPE_TEX_MIPFILTER_NONE:
1786 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1787 }
1788 }
1789
1790 static unsigned si_tex_compare(unsigned compare)
1791 {
1792 switch (compare) {
1793 default:
1794 case PIPE_FUNC_NEVER:
1795 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1796 case PIPE_FUNC_LESS:
1797 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1798 case PIPE_FUNC_EQUAL:
1799 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1800 case PIPE_FUNC_LEQUAL:
1801 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1802 case PIPE_FUNC_GREATER:
1803 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1804 case PIPE_FUNC_NOTEQUAL:
1805 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1806 case PIPE_FUNC_GEQUAL:
1807 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1808 case PIPE_FUNC_ALWAYS:
1809 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1810 }
1811 }
1812
1813 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1814 unsigned nr_samples)
1815 {
1816 if (view_target == PIPE_TEXTURE_CUBE ||
1817 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1818 res_target = view_target;
1819
1820 switch (res_target) {
1821 default:
1822 case PIPE_TEXTURE_1D:
1823 return V_008F1C_SQ_RSRC_IMG_1D;
1824 case PIPE_TEXTURE_1D_ARRAY:
1825 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1826 case PIPE_TEXTURE_2D:
1827 case PIPE_TEXTURE_RECT:
1828 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1829 V_008F1C_SQ_RSRC_IMG_2D;
1830 case PIPE_TEXTURE_2D_ARRAY:
1831 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1832 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1833 case PIPE_TEXTURE_3D:
1834 return V_008F1C_SQ_RSRC_IMG_3D;
1835 case PIPE_TEXTURE_CUBE:
1836 case PIPE_TEXTURE_CUBE_ARRAY:
1837 return V_008F1C_SQ_RSRC_IMG_CUBE;
1838 }
1839 }
1840
1841 /*
1842 * Format support testing
1843 */
1844
1845 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1846 {
1847 return si_translate_texformat(screen, format, util_format_description(format),
1848 util_format_get_first_non_void_channel(format)) != ~0U;
1849 }
1850
1851 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1852 const struct util_format_description *desc,
1853 int first_non_void)
1854 {
1855 unsigned type = desc->channel[first_non_void].type;
1856 int i;
1857
1858 if (type == UTIL_FORMAT_TYPE_FIXED)
1859 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1860
1861 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1862 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1863
1864 if (desc->nr_channels == 4 &&
1865 desc->channel[0].size == 10 &&
1866 desc->channel[1].size == 10 &&
1867 desc->channel[2].size == 10 &&
1868 desc->channel[3].size == 2)
1869 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1870
1871 /* See whether the components are of the same size. */
1872 for (i = 0; i < desc->nr_channels; i++) {
1873 if (desc->channel[first_non_void].size != desc->channel[i].size)
1874 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1875 }
1876
1877 switch (desc->channel[first_non_void].size) {
1878 case 8:
1879 switch (desc->nr_channels) {
1880 case 1:
1881 return V_008F0C_BUF_DATA_FORMAT_8;
1882 case 2:
1883 return V_008F0C_BUF_DATA_FORMAT_8_8;
1884 case 3:
1885 case 4:
1886 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1887 }
1888 break;
1889 case 16:
1890 switch (desc->nr_channels) {
1891 case 1:
1892 return V_008F0C_BUF_DATA_FORMAT_16;
1893 case 2:
1894 return V_008F0C_BUF_DATA_FORMAT_16_16;
1895 case 3:
1896 case 4:
1897 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1898 }
1899 break;
1900 case 32:
1901 /* From the Southern Islands ISA documentation about MTBUF:
1902 * 'Memory reads of data in memory that is 32 or 64 bits do not
1903 * undergo any format conversion.'
1904 */
1905 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1906 !desc->channel[first_non_void].pure_integer)
1907 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1908
1909 switch (desc->nr_channels) {
1910 case 1:
1911 return V_008F0C_BUF_DATA_FORMAT_32;
1912 case 2:
1913 return V_008F0C_BUF_DATA_FORMAT_32_32;
1914 case 3:
1915 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1916 case 4:
1917 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1918 }
1919 break;
1920 }
1921
1922 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1923 }
1924
1925 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1926 const struct util_format_description *desc,
1927 int first_non_void)
1928 {
1929 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1930 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1931
1932 switch (desc->channel[first_non_void].type) {
1933 case UTIL_FORMAT_TYPE_SIGNED:
1934 if (desc->channel[first_non_void].normalized)
1935 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1936 else if (desc->channel[first_non_void].pure_integer)
1937 return V_008F0C_BUF_NUM_FORMAT_SINT;
1938 else
1939 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1940 break;
1941 case UTIL_FORMAT_TYPE_UNSIGNED:
1942 if (desc->channel[first_non_void].normalized)
1943 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1944 else if (desc->channel[first_non_void].pure_integer)
1945 return V_008F0C_BUF_NUM_FORMAT_UINT;
1946 else
1947 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1948 break;
1949 case UTIL_FORMAT_TYPE_FLOAT:
1950 default:
1951 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1952 }
1953 }
1954
1955 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1956 {
1957 const struct util_format_description *desc;
1958 int first_non_void;
1959 unsigned data_format;
1960
1961 desc = util_format_description(format);
1962 first_non_void = util_format_get_first_non_void_channel(format);
1963 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1964 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1965 }
1966
1967 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1968 {
1969 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1970 r600_translate_colorswap(format) != ~0U;
1971 }
1972
1973 static bool si_is_zs_format_supported(enum pipe_format format)
1974 {
1975 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1976 }
1977
1978 boolean si_is_format_supported(struct pipe_screen *screen,
1979 enum pipe_format format,
1980 enum pipe_texture_target target,
1981 unsigned sample_count,
1982 unsigned usage)
1983 {
1984 unsigned retval = 0;
1985
1986 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1987 R600_ERR("r600: unsupported texture type %d\n", target);
1988 return FALSE;
1989 }
1990
1991 if (!util_format_is_supported(format, usage))
1992 return FALSE;
1993
1994 if (sample_count > 1) {
1995 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1996 return FALSE;
1997
1998 switch (sample_count) {
1999 case 2:
2000 case 4:
2001 case 8:
2002 break;
2003 default:
2004 return FALSE;
2005 }
2006 }
2007
2008 if (usage & PIPE_BIND_SAMPLER_VIEW) {
2009 if (target == PIPE_BUFFER) {
2010 if (si_is_vertex_format_supported(screen, format))
2011 retval |= PIPE_BIND_SAMPLER_VIEW;
2012 } else {
2013 if (si_is_sampler_format_supported(screen, format))
2014 retval |= PIPE_BIND_SAMPLER_VIEW;
2015 }
2016 }
2017
2018 if ((usage & (PIPE_BIND_RENDER_TARGET |
2019 PIPE_BIND_DISPLAY_TARGET |
2020 PIPE_BIND_SCANOUT |
2021 PIPE_BIND_SHARED |
2022 PIPE_BIND_BLENDABLE)) &&
2023 si_is_colorbuffer_format_supported(format)) {
2024 retval |= usage &
2025 (PIPE_BIND_RENDER_TARGET |
2026 PIPE_BIND_DISPLAY_TARGET |
2027 PIPE_BIND_SCANOUT |
2028 PIPE_BIND_SHARED);
2029 if (!util_format_is_pure_integer(format) &&
2030 !util_format_is_depth_or_stencil(format))
2031 retval |= usage & PIPE_BIND_BLENDABLE;
2032 }
2033
2034 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2035 si_is_zs_format_supported(format)) {
2036 retval |= PIPE_BIND_DEPTH_STENCIL;
2037 }
2038
2039 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
2040 si_is_vertex_format_supported(screen, format)) {
2041 retval |= PIPE_BIND_VERTEX_BUFFER;
2042 }
2043
2044 if (usage & PIPE_BIND_TRANSFER_READ)
2045 retval |= PIPE_BIND_TRANSFER_READ;
2046 if (usage & PIPE_BIND_TRANSFER_WRITE)
2047 retval |= PIPE_BIND_TRANSFER_WRITE;
2048
2049 return retval == usage;
2050 }
2051
2052 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
2053 {
2054 unsigned tile_mode_index = 0;
2055
2056 if (stencil) {
2057 tile_mode_index = rtex->surface.stencil_tiling_index[level];
2058 } else {
2059 tile_mode_index = rtex->surface.tiling_index[level];
2060 }
2061 return tile_mode_index;
2062 }
2063
2064 /*
2065 * framebuffer handling
2066 */
2067
2068 static void si_choose_spi_color_formats(struct r600_surface *surf,
2069 unsigned format, unsigned swap,
2070 unsigned ntype, bool is_depth)
2071 {
2072 /* Alpha is needed for alpha-to-coverage.
2073 * Blending may be with or without alpha.
2074 */
2075 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2076 unsigned alpha = 0; /* exports alpha, but may not support blending */
2077 unsigned blend = 0; /* supports blending, but may not export alpha */
2078 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2079
2080 /* Choose the SPI color formats. These are required values for Stoney/RB+.
2081 * Other chips have multiple choices, though they are not necessarily better.
2082 */
2083 switch (format) {
2084 case V_028C70_COLOR_5_6_5:
2085 case V_028C70_COLOR_1_5_5_5:
2086 case V_028C70_COLOR_5_5_5_1:
2087 case V_028C70_COLOR_4_4_4_4:
2088 case V_028C70_COLOR_10_11_11:
2089 case V_028C70_COLOR_11_11_10:
2090 case V_028C70_COLOR_8:
2091 case V_028C70_COLOR_8_8:
2092 case V_028C70_COLOR_8_8_8_8:
2093 case V_028C70_COLOR_10_10_10_2:
2094 case V_028C70_COLOR_2_10_10_10:
2095 if (ntype == V_028C70_NUMBER_UINT)
2096 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2097 else if (ntype == V_028C70_NUMBER_SINT)
2098 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2099 else
2100 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2101 break;
2102
2103 case V_028C70_COLOR_16:
2104 case V_028C70_COLOR_16_16:
2105 case V_028C70_COLOR_16_16_16_16:
2106 if (ntype == V_028C70_NUMBER_UNORM ||
2107 ntype == V_028C70_NUMBER_SNORM) {
2108 /* UNORM16 and SNORM16 don't support blending */
2109 if (ntype == V_028C70_NUMBER_UNORM)
2110 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2111 else
2112 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2113
2114 /* Use 32 bits per channel for blending. */
2115 if (format == V_028C70_COLOR_16) {
2116 if (swap == V_028C70_SWAP_STD) { /* R */
2117 blend = V_028714_SPI_SHADER_32_R;
2118 blend_alpha = V_028714_SPI_SHADER_32_AR;
2119 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2120 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2121 else
2122 assert(0);
2123 } else if (format == V_028C70_COLOR_16_16) {
2124 if (swap == V_028C70_SWAP_STD) { /* RG */
2125 blend = V_028714_SPI_SHADER_32_GR;
2126 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2127 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2128 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2129 else
2130 assert(0);
2131 } else /* 16_16_16_16 */
2132 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2133 } else if (ntype == V_028C70_NUMBER_UINT)
2134 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2135 else if (ntype == V_028C70_NUMBER_SINT)
2136 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2137 else if (ntype == V_028C70_NUMBER_FLOAT)
2138 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2139 else
2140 assert(0);
2141 break;
2142
2143 case V_028C70_COLOR_32:
2144 if (swap == V_028C70_SWAP_STD) { /* R */
2145 blend = normal = V_028714_SPI_SHADER_32_R;
2146 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2147 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2148 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2149 else
2150 assert(0);
2151 break;
2152
2153 case V_028C70_COLOR_32_32:
2154 if (swap == V_028C70_SWAP_STD) { /* RG */
2155 blend = normal = V_028714_SPI_SHADER_32_GR;
2156 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2157 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2158 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2159 else
2160 assert(0);
2161 break;
2162
2163 case V_028C70_COLOR_32_32_32_32:
2164 case V_028C70_COLOR_8_24:
2165 case V_028C70_COLOR_24_8:
2166 case V_028C70_COLOR_X24_8_32_FLOAT:
2167 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2168 break;
2169
2170 default:
2171 assert(0);
2172 return;
2173 }
2174
2175 /* The DB->CB copy needs 32_ABGR. */
2176 if (is_depth)
2177 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2178
2179 surf->spi_shader_col_format = normal;
2180 surf->spi_shader_col_format_alpha = alpha;
2181 surf->spi_shader_col_format_blend = blend;
2182 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2183 }
2184
2185 static void si_initialize_color_surface(struct si_context *sctx,
2186 struct r600_surface *surf)
2187 {
2188 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2189 unsigned level = surf->base.u.tex.level;
2190 uint64_t offset = rtex->surface.level[level].offset;
2191 unsigned pitch, slice;
2192 unsigned color_info, color_attrib, color_pitch, color_view;
2193 unsigned tile_mode_index;
2194 unsigned format, swap, ntype, endian;
2195 const struct util_format_description *desc;
2196 int i;
2197 unsigned blend_clamp = 0, blend_bypass = 0;
2198
2199 /* Layered rendering doesn't work with LINEAR_GENERAL.
2200 * (LINEAR_ALIGNED and others work) */
2201 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
2202 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
2203 offset += rtex->surface.level[level].slice_size *
2204 surf->base.u.tex.first_layer;
2205 color_view = 0;
2206 } else {
2207 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2208 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2209 }
2210
2211 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
2212 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
2213 if (slice) {
2214 slice = slice - 1;
2215 }
2216
2217 tile_mode_index = si_tile_mode_index(rtex, level, false);
2218
2219 desc = util_format_description(surf->base.format);
2220 for (i = 0; i < 4; i++) {
2221 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2222 break;
2223 }
2224 }
2225 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2226 ntype = V_028C70_NUMBER_FLOAT;
2227 } else {
2228 ntype = V_028C70_NUMBER_UNORM;
2229 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2230 ntype = V_028C70_NUMBER_SRGB;
2231 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2232 if (desc->channel[i].pure_integer) {
2233 ntype = V_028C70_NUMBER_SINT;
2234 } else {
2235 assert(desc->channel[i].normalized);
2236 ntype = V_028C70_NUMBER_SNORM;
2237 }
2238 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2239 if (desc->channel[i].pure_integer) {
2240 ntype = V_028C70_NUMBER_UINT;
2241 } else {
2242 assert(desc->channel[i].normalized);
2243 ntype = V_028C70_NUMBER_UNORM;
2244 }
2245 }
2246 }
2247
2248 format = si_translate_colorformat(surf->base.format);
2249 if (format == V_028C70_COLOR_INVALID) {
2250 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2251 }
2252 assert(format != V_028C70_COLOR_INVALID);
2253 swap = r600_translate_colorswap(surf->base.format);
2254 endian = si_colorformat_endian_swap(format);
2255
2256 /* blend clamp should be set for all NORM/SRGB types */
2257 if (ntype == V_028C70_NUMBER_UNORM ||
2258 ntype == V_028C70_NUMBER_SNORM ||
2259 ntype == V_028C70_NUMBER_SRGB)
2260 blend_clamp = 1;
2261
2262 /* set blend bypass according to docs if SINT/UINT or
2263 8/24 COLOR variants */
2264 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2265 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2266 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2267 blend_clamp = 0;
2268 blend_bypass = 1;
2269 }
2270
2271 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2272 (format == V_028C70_COLOR_8 ||
2273 format == V_028C70_COLOR_8_8 ||
2274 format == V_028C70_COLOR_8_8_8_8))
2275 surf->color_is_int8 = true;
2276
2277 color_info = S_028C70_FORMAT(format) |
2278 S_028C70_COMP_SWAP(swap) |
2279 S_028C70_BLEND_CLAMP(blend_clamp) |
2280 S_028C70_BLEND_BYPASS(blend_bypass) |
2281 S_028C70_NUMBER_TYPE(ntype) |
2282 S_028C70_ENDIAN(endian);
2283
2284 color_pitch = S_028C64_TILE_MAX(pitch);
2285
2286 /* Intensity is implemented as Red, so treat it that way. */
2287 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
2288 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1 ||
2289 util_format_is_intensity(surf->base.format));
2290
2291 if (rtex->resource.b.b.nr_samples > 1) {
2292 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2293
2294 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2295 S_028C74_NUM_FRAGMENTS(log_samples);
2296
2297 if (rtex->fmask.size) {
2298 color_info |= S_028C70_COMPRESSION(1);
2299 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2300
2301 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
2302
2303 if (sctx->b.chip_class == SI) {
2304 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2305 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2306 }
2307 if (sctx->b.chip_class >= CIK) {
2308 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch_in_pixels / 8 - 1);
2309 }
2310 }
2311 }
2312
2313 offset += rtex->resource.gpu_address;
2314
2315 surf->cb_color_base = offset >> 8;
2316 surf->cb_color_pitch = color_pitch;
2317 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
2318 surf->cb_color_view = color_view;
2319 surf->cb_color_info = color_info;
2320 surf->cb_color_attrib = color_attrib;
2321
2322 if (sctx->b.chip_class >= VI && rtex->dcc_offset) {
2323 unsigned max_uncompressed_block_size = 2;
2324
2325 if (rtex->surface.nsamples > 1) {
2326 if (rtex->surface.bpe == 1)
2327 max_uncompressed_block_size = 0;
2328 else if (rtex->surface.bpe == 2)
2329 max_uncompressed_block_size = 1;
2330 }
2331
2332 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2333 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2334 surf->cb_dcc_base = (rtex->resource.gpu_address +
2335 rtex->dcc_offset +
2336 rtex->surface.level[level].dcc_offset) >> 8;
2337 }
2338
2339 if (rtex->fmask.size) {
2340 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
2341 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
2342 } else {
2343 /* This must be set for fast clear to work without FMASK. */
2344 surf->cb_color_fmask = surf->cb_color_base;
2345 surf->cb_color_fmask_slice = surf->cb_color_slice;
2346 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2347
2348 if (sctx->b.chip_class == SI) {
2349 unsigned bankh = util_logbase2(rtex->surface.bankh);
2350 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2351 }
2352
2353 if (sctx->b.chip_class >= CIK) {
2354 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
2355 }
2356 }
2357
2358 /* Determine pixel shader export format */
2359 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2360
2361 surf->color_initialized = true;
2362 }
2363
2364 static void si_init_depth_surface(struct si_context *sctx,
2365 struct r600_surface *surf)
2366 {
2367 struct si_screen *sscreen = sctx->screen;
2368 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2369 unsigned level = surf->base.u.tex.level;
2370 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2371 unsigned format, tile_mode_index, array_mode;
2372 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
2373 uint32_t z_info, s_info, db_depth_info;
2374 uint64_t z_offs, s_offs;
2375 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
2376
2377 switch (sctx->framebuffer.state.zsbuf->texture->format) {
2378 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2379 case PIPE_FORMAT_X8Z24_UNORM:
2380 case PIPE_FORMAT_Z24X8_UNORM:
2381 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2382 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2383 break;
2384 case PIPE_FORMAT_Z32_FLOAT:
2385 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2386 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2387 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2388 break;
2389 case PIPE_FORMAT_Z16_UNORM:
2390 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2391 break;
2392 default:
2393 assert(0);
2394 }
2395
2396 format = si_translate_dbformat(rtex->resource.b.b.format);
2397
2398 if (format == V_028040_Z_INVALID) {
2399 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2400 }
2401 assert(format != V_028040_Z_INVALID);
2402
2403 s_offs = z_offs = rtex->resource.gpu_address;
2404 z_offs += rtex->surface.level[level].offset;
2405 s_offs += rtex->surface.stencil_level[level].offset;
2406
2407 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2408
2409 z_info = S_028040_FORMAT(format);
2410 if (rtex->resource.b.b.nr_samples > 1) {
2411 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2412 }
2413
2414 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2415 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2416 else
2417 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2418
2419 if (sctx->b.chip_class >= CIK) {
2420 switch (rtex->surface.level[level].mode) {
2421 case RADEON_SURF_MODE_2D:
2422 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
2423 break;
2424 case RADEON_SURF_MODE_1D:
2425 case RADEON_SURF_MODE_LINEAR_ALIGNED:
2426 case RADEON_SURF_MODE_LINEAR:
2427 default:
2428 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
2429 break;
2430 }
2431 tile_split = rtex->surface.tile_split;
2432 stile_split = rtex->surface.stencil_tile_split;
2433 macro_aspect = rtex->surface.mtilea;
2434 bankw = rtex->surface.bankw;
2435 bankh = rtex->surface.bankh;
2436 tile_split = cik_tile_split(tile_split);
2437 stile_split = cik_tile_split(stile_split);
2438 macro_aspect = cik_macro_tile_aspect(macro_aspect);
2439 bankw = cik_bank_wh(bankw);
2440 bankh = cik_bank_wh(bankh);
2441 nbanks = si_num_banks(sscreen, rtex);
2442 tile_mode_index = si_tile_mode_index(rtex, level, false);
2443 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
2444
2445 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
2446 S_02803C_PIPE_CONFIG(pipe_config) |
2447 S_02803C_BANK_WIDTH(bankw) |
2448 S_02803C_BANK_HEIGHT(bankh) |
2449 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
2450 S_02803C_NUM_BANKS(nbanks);
2451 z_info |= S_028040_TILE_SPLIT(tile_split);
2452 s_info |= S_028044_TILE_SPLIT(stile_split);
2453 } else {
2454 tile_mode_index = si_tile_mode_index(rtex, level, false);
2455 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2456 tile_mode_index = si_tile_mode_index(rtex, level, true);
2457 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2458 }
2459
2460 /* HiZ aka depth buffer htile */
2461 /* use htile only for first level */
2462 if (rtex->htile_buffer && !level) {
2463 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2464 S_028040_ALLOW_EXPCLEAR(1);
2465
2466 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2467 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2468 else
2469 /* Use all of the htile_buffer for depth if there's no stencil. */
2470 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2471
2472 uint64_t va = rtex->htile_buffer->gpu_address;
2473 db_htile_data_base = va >> 8;
2474 db_htile_surface = S_028ABC_FULL_CACHE(1);
2475 } else {
2476 db_htile_data_base = 0;
2477 db_htile_surface = 0;
2478 }
2479
2480 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2481
2482 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2483 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2484 surf->db_htile_data_base = db_htile_data_base;
2485 surf->db_depth_info = db_depth_info;
2486 surf->db_z_info = z_info;
2487 surf->db_stencil_info = s_info;
2488 surf->db_depth_base = z_offs >> 8;
2489 surf->db_stencil_base = s_offs >> 8;
2490 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2491 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2492 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2493 levelinfo->nblk_y) / 64 - 1);
2494 surf->db_htile_surface = db_htile_surface;
2495 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2496
2497 surf->depth_initialized = true;
2498 }
2499
2500 static void si_set_framebuffer_state(struct pipe_context *ctx,
2501 const struct pipe_framebuffer_state *state)
2502 {
2503 struct si_context *sctx = (struct si_context *)ctx;
2504 struct pipe_constant_buffer constbuf = {0};
2505 struct r600_surface *surf = NULL;
2506 struct r600_texture *rtex;
2507 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2508 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2509 int i;
2510
2511 /* Only flush TC when changing the framebuffer state, because
2512 * the only client not using TC that can change textures is
2513 * the framebuffer.
2514 *
2515 * Flush all CB and DB caches here because all buffers can be used
2516 * for write by both TC (with shader image stores) and CB/DB.
2517 */
2518 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2519 SI_CONTEXT_INV_GLOBAL_L2 |
2520 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
2521
2522 /* Take the maximum of the old and new count. If the new count is lower,
2523 * dirtying is needed to disable the unbound colorbuffers.
2524 */
2525 sctx->framebuffer.dirty_cbufs |=
2526 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2527 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2528
2529 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2530
2531 sctx->framebuffer.spi_shader_col_format = 0;
2532 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2533 sctx->framebuffer.spi_shader_col_format_blend = 0;
2534 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2535 sctx->framebuffer.color_is_int8 = 0;
2536
2537 sctx->framebuffer.compressed_cb_mask = 0;
2538 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2539 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2540 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2541 util_format_is_pure_integer(state->cbufs[0]->format);
2542
2543 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2544 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2545
2546 for (i = 0; i < state->nr_cbufs; i++) {
2547 if (!state->cbufs[i])
2548 continue;
2549
2550 surf = (struct r600_surface*)state->cbufs[i];
2551 rtex = (struct r600_texture*)surf->base.texture;
2552
2553 if (!surf->color_initialized) {
2554 si_initialize_color_surface(sctx, surf);
2555 }
2556
2557 sctx->framebuffer.spi_shader_col_format |=
2558 surf->spi_shader_col_format << (i * 4);
2559 sctx->framebuffer.spi_shader_col_format_alpha |=
2560 surf->spi_shader_col_format_alpha << (i * 4);
2561 sctx->framebuffer.spi_shader_col_format_blend |=
2562 surf->spi_shader_col_format_blend << (i * 4);
2563 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2564 surf->spi_shader_col_format_blend_alpha << (i * 4);
2565
2566 if (surf->color_is_int8)
2567 sctx->framebuffer.color_is_int8 |= 1 << i;
2568
2569 if (rtex->fmask.size && rtex->cmask.size) {
2570 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2571 }
2572 r600_context_add_resource_size(ctx, surf->base.texture);
2573 }
2574 /* Set the second SPI format for possible dual-src blending. */
2575 if (i == 1 && surf) {
2576 sctx->framebuffer.spi_shader_col_format |=
2577 surf->spi_shader_col_format << (i * 4);
2578 sctx->framebuffer.spi_shader_col_format_alpha |=
2579 surf->spi_shader_col_format_alpha << (i * 4);
2580 sctx->framebuffer.spi_shader_col_format_blend |=
2581 surf->spi_shader_col_format_blend << (i * 4);
2582 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2583 surf->spi_shader_col_format_blend_alpha << (i * 4);
2584 }
2585
2586 if (state->zsbuf) {
2587 surf = (struct r600_surface*)state->zsbuf;
2588
2589 if (!surf->depth_initialized) {
2590 si_init_depth_surface(sctx, surf);
2591 }
2592 r600_context_add_resource_size(ctx, surf->base.texture);
2593 }
2594
2595 si_update_poly_offset_state(sctx);
2596 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2597 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2598
2599 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2600 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2601 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2602
2603 /* Set sample locations as fragment shader constants. */
2604 switch (sctx->framebuffer.nr_samples) {
2605 case 1:
2606 constbuf.user_buffer = sctx->b.sample_locations_1x;
2607 break;
2608 case 2:
2609 constbuf.user_buffer = sctx->b.sample_locations_2x;
2610 break;
2611 case 4:
2612 constbuf.user_buffer = sctx->b.sample_locations_4x;
2613 break;
2614 case 8:
2615 constbuf.user_buffer = sctx->b.sample_locations_8x;
2616 break;
2617 case 16:
2618 constbuf.user_buffer = sctx->b.sample_locations_16x;
2619 break;
2620 default:
2621 assert(0);
2622 }
2623 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2624 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2625 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2626
2627 /* Smoothing (only possible with nr_samples == 1) uses the same
2628 * sample locations as the MSAA it simulates.
2629 *
2630 * Therefore, don't update the sample locations when
2631 * transitioning from no AA to smoothing-equivalent AA, and
2632 * vice versa.
2633 */
2634 if ((sctx->framebuffer.nr_samples != 1 ||
2635 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2636 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2637 old_nr_samples != 1))
2638 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2639 }
2640 }
2641
2642 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2643 {
2644 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2645 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2646 unsigned i, nr_cbufs = state->nr_cbufs;
2647 struct r600_texture *tex = NULL;
2648 struct r600_surface *cb = NULL;
2649
2650 /* Colorbuffers. */
2651 for (i = 0; i < nr_cbufs; i++) {
2652 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2653 continue;
2654
2655 cb = (struct r600_surface*)state->cbufs[i];
2656 if (!cb) {
2657 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2658 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2659 continue;
2660 }
2661
2662 tex = (struct r600_texture *)cb->base.texture;
2663 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2664 &tex->resource, RADEON_USAGE_READWRITE,
2665 tex->surface.nsamples > 1 ?
2666 RADEON_PRIO_COLOR_BUFFER_MSAA :
2667 RADEON_PRIO_COLOR_BUFFER);
2668
2669 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2670 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2671 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2672 RADEON_PRIO_CMASK);
2673 }
2674
2675 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2676 sctx->b.chip_class >= VI ? 14 : 13);
2677 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2678 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2679 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2680 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2681 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2682 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2683 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2684 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2685 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2686 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2687 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2688 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2689 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2690
2691 if (sctx->b.chip_class >= VI)
2692 radeon_emit(cs, cb->cb_dcc_base); /* R_028C94_CB_COLOR0_DCC_BASE */
2693 }
2694 /* set CB_COLOR1_INFO for possible dual-src blending */
2695 if (i == 1 && state->cbufs[0] &&
2696 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2697 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2698 cb->cb_color_info | tex->cb_color_info);
2699 i++;
2700 }
2701 for (; i < 8 ; i++)
2702 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2703 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2704
2705 /* ZS buffer. */
2706 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2707 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2708 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2709
2710 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2711 &rtex->resource, RADEON_USAGE_READWRITE,
2712 zb->base.texture->nr_samples > 1 ?
2713 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2714 RADEON_PRIO_DEPTH_BUFFER);
2715
2716 if (zb->db_htile_data_base) {
2717 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2718 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2719 RADEON_PRIO_HTILE);
2720 }
2721
2722 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2723 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2724
2725 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2726 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2727 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2728 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2729 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2730 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2731 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2732 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2733 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2734 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2735 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2736
2737 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2738 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2739 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2740
2741 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2742 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2743 zb->pa_su_poly_offset_db_fmt_cntl);
2744 } else if (sctx->framebuffer.dirty_zsbuf) {
2745 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2746 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2747 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2748 }
2749
2750 /* Framebuffer dimensions. */
2751 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2752 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2753 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2754
2755 sctx->framebuffer.dirty_cbufs = 0;
2756 sctx->framebuffer.dirty_zsbuf = false;
2757 }
2758
2759 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2760 struct r600_atom *atom)
2761 {
2762 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2763 unsigned nr_samples = sctx->framebuffer.nr_samples;
2764
2765 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2766 SI_NUM_SMOOTH_AA_SAMPLES);
2767 }
2768
2769 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2770 {
2771 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2772
2773 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2774 sctx->ps_iter_samples,
2775 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2776 }
2777
2778
2779 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2780 {
2781 struct si_context *sctx = (struct si_context *)ctx;
2782
2783 if (sctx->ps_iter_samples == min_samples)
2784 return;
2785
2786 sctx->ps_iter_samples = min_samples;
2787
2788 if (sctx->framebuffer.nr_samples > 1)
2789 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2790 }
2791
2792 /*
2793 * Samplers
2794 */
2795
2796 /**
2797 * Build the sampler view descriptor for a buffer texture.
2798 * @param state 256-bit descriptor; only the high 128 bits are filled in
2799 */
2800 void
2801 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2802 enum pipe_format format,
2803 unsigned first_element, unsigned last_element,
2804 uint32_t *state)
2805 {
2806 const struct util_format_description *desc;
2807 int first_non_void;
2808 uint64_t va;
2809 unsigned stride;
2810 unsigned num_records;
2811 unsigned num_format, data_format;
2812
2813 desc = util_format_description(format);
2814 first_non_void = util_format_get_first_non_void_channel(format);
2815 stride = desc->block.bits / 8;
2816 va = buf->gpu_address + first_element * stride;
2817 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2818 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2819
2820 num_records = last_element + 1 - first_element;
2821 num_records = MIN2(num_records, buf->b.b.width0 / stride);
2822
2823 if (screen->b.chip_class >= VI)
2824 num_records *= stride;
2825
2826 state[4] = va;
2827 state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2828 S_008F04_STRIDE(stride);
2829 state[6] = num_records;
2830 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2831 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2832 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2833 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2834 S_008F0C_NUM_FORMAT(num_format) |
2835 S_008F0C_DATA_FORMAT(data_format);
2836 }
2837
2838 /**
2839 * Build the sampler view descriptor for a texture.
2840 */
2841 void
2842 si_make_texture_descriptor(struct si_screen *screen,
2843 struct r600_texture *tex,
2844 bool sampler,
2845 enum pipe_texture_target target,
2846 enum pipe_format pipe_format,
2847 const unsigned char state_swizzle[4],
2848 unsigned base_level, unsigned first_level, unsigned last_level,
2849 unsigned first_layer, unsigned last_layer,
2850 unsigned width, unsigned height, unsigned depth,
2851 uint32_t *state,
2852 uint32_t *fmask_state)
2853 {
2854 struct pipe_resource *res = &tex->resource.b.b;
2855 const struct radeon_surf_level *surflevel = tex->surface.level;
2856 const struct util_format_description *desc;
2857 unsigned char swizzle[4];
2858 int first_non_void;
2859 unsigned num_format, data_format, type;
2860 uint32_t pitch;
2861 uint64_t va;
2862
2863 /* Texturing with separate depth and stencil. */
2864 if (tex->is_depth && !tex->is_flushing_texture) {
2865 switch (pipe_format) {
2866 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2867 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2868 break;
2869 case PIPE_FORMAT_X8Z24_UNORM:
2870 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2871 /* Z24 is always stored like this. */
2872 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2873 break;
2874 case PIPE_FORMAT_X24S8_UINT:
2875 case PIPE_FORMAT_S8X24_UINT:
2876 case PIPE_FORMAT_X32_S8X24_UINT:
2877 pipe_format = PIPE_FORMAT_S8_UINT;
2878 surflevel = tex->surface.stencil_level;
2879 break;
2880 default:;
2881 }
2882 }
2883
2884 desc = util_format_description(pipe_format);
2885
2886 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2887 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2888 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2889
2890 switch (pipe_format) {
2891 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2892 case PIPE_FORMAT_X24S8_UINT:
2893 case PIPE_FORMAT_X32_S8X24_UINT:
2894 case PIPE_FORMAT_X8Z24_UNORM:
2895 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2896 break;
2897 default:
2898 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2899 }
2900 } else {
2901 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2902 }
2903
2904 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2905
2906 switch (pipe_format) {
2907 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2908 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2909 break;
2910 default:
2911 if (first_non_void < 0) {
2912 if (util_format_is_compressed(pipe_format)) {
2913 switch (pipe_format) {
2914 case PIPE_FORMAT_DXT1_SRGB:
2915 case PIPE_FORMAT_DXT1_SRGBA:
2916 case PIPE_FORMAT_DXT3_SRGBA:
2917 case PIPE_FORMAT_DXT5_SRGBA:
2918 case PIPE_FORMAT_BPTC_SRGBA:
2919 case PIPE_FORMAT_ETC2_SRGB8:
2920 case PIPE_FORMAT_ETC2_SRGB8A1:
2921 case PIPE_FORMAT_ETC2_SRGBA8:
2922 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2923 break;
2924 case PIPE_FORMAT_RGTC1_SNORM:
2925 case PIPE_FORMAT_LATC1_SNORM:
2926 case PIPE_FORMAT_RGTC2_SNORM:
2927 case PIPE_FORMAT_LATC2_SNORM:
2928 case PIPE_FORMAT_ETC2_R11_SNORM:
2929 case PIPE_FORMAT_ETC2_RG11_SNORM:
2930 /* implies float, so use SNORM/UNORM to determine
2931 whether data is signed or not */
2932 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2933 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2934 break;
2935 default:
2936 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2937 break;
2938 }
2939 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2940 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2941 } else {
2942 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2943 }
2944 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2945 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2946 } else {
2947 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2948
2949 switch (desc->channel[first_non_void].type) {
2950 case UTIL_FORMAT_TYPE_FLOAT:
2951 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2952 break;
2953 case UTIL_FORMAT_TYPE_SIGNED:
2954 if (desc->channel[first_non_void].normalized)
2955 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2956 else if (desc->channel[first_non_void].pure_integer)
2957 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2958 else
2959 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2960 break;
2961 case UTIL_FORMAT_TYPE_UNSIGNED:
2962 if (desc->channel[first_non_void].normalized)
2963 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2964 else if (desc->channel[first_non_void].pure_integer)
2965 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2966 else
2967 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2968 }
2969 }
2970 }
2971
2972 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2973 if (data_format == ~0) {
2974 data_format = 0;
2975 }
2976
2977 if (!sampler &&
2978 (res->target == PIPE_TEXTURE_CUBE ||
2979 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2980 res->target == PIPE_TEXTURE_3D)) {
2981 /* For the purpose of shader images, treat cube maps and 3D
2982 * textures as 2D arrays. For 3D textures, the address
2983 * calculations for mipmaps are different, so we rely on the
2984 * caller to effectively disable mipmaps.
2985 */
2986 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2987
2988 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2989 } else {
2990 type = si_tex_dim(res->target, target, res->nr_samples);
2991 }
2992
2993 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2994 height = 1;
2995 depth = res->array_size;
2996 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2997 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2998 if (sampler || res->target != PIPE_TEXTURE_3D)
2999 depth = res->array_size;
3000 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3001 depth = res->array_size / 6;
3002
3003 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
3004 va = tex->resource.gpu_address + surflevel[base_level].offset;
3005
3006 state[0] = va >> 8;
3007 state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
3008 S_008F14_DATA_FORMAT(data_format) |
3009 S_008F14_NUM_FORMAT(num_format));
3010 state[2] = (S_008F18_WIDTH(width - 1) |
3011 S_008F18_HEIGHT(height - 1));
3012 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3013 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3014 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3015 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3016 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3017 0 : first_level) |
3018 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3019 util_logbase2(res->nr_samples) :
3020 last_level) |
3021 S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level, false)) |
3022 S_008F1C_POW2_PAD(res->last_level > 0) |
3023 S_008F1C_TYPE(type));
3024 state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
3025 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
3026 S_008F24_LAST_ARRAY(last_layer));
3027
3028 if (tex->dcc_offset) {
3029 unsigned swap = r600_translate_colorswap(pipe_format);
3030
3031 state[6] = S_008F28_COMPRESSION_EN(1) | S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3032 state[7] = (tex->resource.gpu_address +
3033 tex->dcc_offset +
3034 surflevel[base_level].dcc_offset) >> 8;
3035 } else {
3036 state[6] = 0;
3037 state[7] = 0;
3038 }
3039
3040 /* Initialize the sampler view for FMASK. */
3041 if (tex->fmask.size) {
3042 uint32_t fmask_format;
3043
3044 va = tex->resource.gpu_address + tex->fmask.offset;
3045
3046 switch (res->nr_samples) {
3047 case 2:
3048 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3049 break;
3050 case 4:
3051 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3052 break;
3053 case 8:
3054 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3055 break;
3056 default:
3057 assert(0);
3058 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
3059 }
3060
3061 fmask_state[0] = va >> 8;
3062 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3063 S_008F14_DATA_FORMAT(fmask_format) |
3064 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
3065 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3066 S_008F18_HEIGHT(height - 1);
3067 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3068 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3069 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3070 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3071 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
3072 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
3073 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
3074 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
3075 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
3076 S_008F24_LAST_ARRAY(last_layer);
3077 fmask_state[6] = 0;
3078 fmask_state[7] = 0;
3079 }
3080 }
3081
3082 /**
3083 * Create a sampler view.
3084 *
3085 * @param ctx context
3086 * @param texture texture
3087 * @param state sampler view template
3088 * @param width0 width0 override (for compressed textures as int)
3089 * @param height0 height0 override (for compressed textures as int)
3090 * @param force_level set the base address to the level (for compressed textures)
3091 */
3092 struct pipe_sampler_view *
3093 si_create_sampler_view_custom(struct pipe_context *ctx,
3094 struct pipe_resource *texture,
3095 const struct pipe_sampler_view *state,
3096 unsigned width0, unsigned height0,
3097 unsigned force_level)
3098 {
3099 struct si_context *sctx = (struct si_context*)ctx;
3100 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3101 struct r600_texture *tmp = (struct r600_texture*)texture;
3102 unsigned base_level, first_level, last_level;
3103 unsigned char state_swizzle[4];
3104 unsigned height, depth, width;
3105 unsigned last_layer = state->u.tex.last_layer;
3106
3107 if (!view)
3108 return NULL;
3109
3110 /* initialize base object */
3111 view->base = *state;
3112 view->base.texture = NULL;
3113 view->base.reference.count = 1;
3114 view->base.context = ctx;
3115
3116 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
3117 if (!texture) {
3118 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
3119 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
3120 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
3121 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
3122 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
3123 return &view->base;
3124 }
3125
3126 pipe_resource_reference(&view->base.texture, texture);
3127
3128 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3129 state->format == PIPE_FORMAT_S8X24_UINT ||
3130 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3131 state->format == PIPE_FORMAT_S8_UINT)
3132 view->is_stencil_sampler = true;
3133
3134 /* Buffer resource. */
3135 if (texture->target == PIPE_BUFFER) {
3136 si_make_buffer_descriptor(sctx->screen,
3137 (struct r600_resource *)texture,
3138 state->format,
3139 state->u.buf.first_element,
3140 state->u.buf.last_element,
3141 view->state);
3142
3143 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
3144 return &view->base;
3145 }
3146
3147 state_swizzle[0] = state->swizzle_r;
3148 state_swizzle[1] = state->swizzle_g;
3149 state_swizzle[2] = state->swizzle_b;
3150 state_swizzle[3] = state->swizzle_a;
3151
3152 base_level = 0;
3153 first_level = state->u.tex.first_level;
3154 last_level = state->u.tex.last_level;
3155 width = width0;
3156 height = height0;
3157 depth = texture->depth0;
3158
3159 if (force_level) {
3160 assert(force_level == first_level &&
3161 force_level == last_level);
3162 base_level = force_level;
3163 first_level = 0;
3164 last_level = 0;
3165 width = u_minify(width, force_level);
3166 height = u_minify(height, force_level);
3167 depth = u_minify(depth, force_level);
3168 }
3169
3170 /* This is not needed if state trackers set last_layer correctly. */
3171 if (state->target == PIPE_TEXTURE_1D ||
3172 state->target == PIPE_TEXTURE_2D ||
3173 state->target == PIPE_TEXTURE_RECT ||
3174 state->target == PIPE_TEXTURE_CUBE)
3175 last_layer = state->u.tex.first_layer;
3176
3177 si_make_texture_descriptor(sctx->screen, tmp, true, state->target,
3178 state->format, state_swizzle,
3179 base_level, first_level, last_level,
3180 state->u.tex.first_layer, last_layer,
3181 width, height, depth,
3182 view->state, view->fmask_state);
3183
3184 return &view->base;
3185 }
3186
3187 static struct pipe_sampler_view *
3188 si_create_sampler_view(struct pipe_context *ctx,
3189 struct pipe_resource *texture,
3190 const struct pipe_sampler_view *state)
3191 {
3192 return si_create_sampler_view_custom(ctx, texture, state,
3193 texture ? texture->width0 : 0,
3194 texture ? texture->height0 : 0, 0);
3195 }
3196
3197 static void si_sampler_view_destroy(struct pipe_context *ctx,
3198 struct pipe_sampler_view *state)
3199 {
3200 struct si_sampler_view *view = (struct si_sampler_view *)state;
3201
3202 if (state->texture && state->texture->target == PIPE_BUFFER)
3203 LIST_DELINIT(&view->list);
3204
3205 pipe_resource_reference(&state->texture, NULL);
3206 FREE(view);
3207 }
3208
3209 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3210 {
3211 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3212 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3213 (linear_filter &&
3214 (wrap == PIPE_TEX_WRAP_CLAMP ||
3215 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3216 }
3217
3218 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3219 {
3220 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3221 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3222
3223 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3224 state->border_color.ui[2] || state->border_color.ui[3]) &&
3225 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3226 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3227 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3228 }
3229
3230 static void *si_create_sampler_state(struct pipe_context *ctx,
3231 const struct pipe_sampler_state *state)
3232 {
3233 struct si_context *sctx = (struct si_context *)ctx;
3234 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3235 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
3236 unsigned border_color_type, border_color_index = 0;
3237
3238 if (!rstate) {
3239 return NULL;
3240 }
3241
3242 if (!sampler_state_needs_border_color(state))
3243 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3244 else if (state->border_color.f[0] == 0 &&
3245 state->border_color.f[1] == 0 &&
3246 state->border_color.f[2] == 0 &&
3247 state->border_color.f[3] == 0)
3248 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3249 else if (state->border_color.f[0] == 0 &&
3250 state->border_color.f[1] == 0 &&
3251 state->border_color.f[2] == 0 &&
3252 state->border_color.f[3] == 1)
3253 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3254 else if (state->border_color.f[0] == 1 &&
3255 state->border_color.f[1] == 1 &&
3256 state->border_color.f[2] == 1 &&
3257 state->border_color.f[3] == 1)
3258 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3259 else {
3260 int i;
3261
3262 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3263
3264 /* Check if the border has been uploaded already. */
3265 for (i = 0; i < sctx->border_color_count; i++)
3266 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3267 sizeof(state->border_color)) == 0)
3268 break;
3269
3270 if (i >= SI_MAX_BORDER_COLORS) {
3271 /* Getting 4096 unique border colors is very unlikely. */
3272 fprintf(stderr, "radeonsi: The border color table is full. "
3273 "Any new border colors will be just black. "
3274 "Please file a bug.\n");
3275 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3276 } else {
3277 if (i == sctx->border_color_count) {
3278 /* Upload a new border color. */
3279 memcpy(&sctx->border_color_table[i], &state->border_color,
3280 sizeof(state->border_color));
3281 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3282 &state->border_color,
3283 sizeof(state->border_color));
3284 sctx->border_color_count++;
3285 }
3286
3287 border_color_index = i;
3288 }
3289 }
3290
3291 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3292 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3293 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3294 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
3295 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3296 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3297 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
3298 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3299 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
3300 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3301 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
3302 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
3303 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
3304 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3305 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3306 return rstate;
3307 }
3308
3309 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3310 {
3311 struct si_context *sctx = (struct si_context *)ctx;
3312
3313 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3314 return;
3315
3316 sctx->sample_mask.sample_mask = sample_mask;
3317 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3318 }
3319
3320 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3321 {
3322 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3323 unsigned mask = sctx->sample_mask.sample_mask;
3324
3325 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3326 radeon_emit(cs, mask | (mask << 16));
3327 radeon_emit(cs, mask | (mask << 16));
3328 }
3329
3330 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3331 {
3332 free(state);
3333 }
3334
3335 /*
3336 * Vertex elements & buffers
3337 */
3338
3339 static void *si_create_vertex_elements(struct pipe_context *ctx,
3340 unsigned count,
3341 const struct pipe_vertex_element *elements)
3342 {
3343 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3344 int i;
3345
3346 assert(count < SI_MAX_ATTRIBS);
3347 if (!v)
3348 return NULL;
3349
3350 v->count = count;
3351 for (i = 0; i < count; ++i) {
3352 const struct util_format_description *desc;
3353 unsigned data_format, num_format;
3354 int first_non_void;
3355
3356 desc = util_format_description(elements[i].src_format);
3357 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3358 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3359 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3360
3361 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3362 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3363 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3364 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3365 S_008F0C_NUM_FORMAT(num_format) |
3366 S_008F0C_DATA_FORMAT(data_format);
3367 v->format_size[i] = desc->block.bits / 8;
3368 }
3369 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3370
3371 return v;
3372 }
3373
3374 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3375 {
3376 struct si_context *sctx = (struct si_context *)ctx;
3377 struct si_vertex_element *v = (struct si_vertex_element*)state;
3378
3379 sctx->vertex_elements = v;
3380 sctx->vertex_buffers_dirty = true;
3381 }
3382
3383 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3384 {
3385 struct si_context *sctx = (struct si_context *)ctx;
3386
3387 if (sctx->vertex_elements == state)
3388 sctx->vertex_elements = NULL;
3389 FREE(state);
3390 }
3391
3392 static void si_set_vertex_buffers(struct pipe_context *ctx,
3393 unsigned start_slot, unsigned count,
3394 const struct pipe_vertex_buffer *buffers)
3395 {
3396 struct si_context *sctx = (struct si_context *)ctx;
3397 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3398 int i;
3399
3400 assert(start_slot + count <= Elements(sctx->vertex_buffer));
3401
3402 if (buffers) {
3403 for (i = 0; i < count; i++) {
3404 const struct pipe_vertex_buffer *src = buffers + i;
3405 struct pipe_vertex_buffer *dsti = dst + i;
3406
3407 pipe_resource_reference(&dsti->buffer, src->buffer);
3408 dsti->buffer_offset = src->buffer_offset;
3409 dsti->stride = src->stride;
3410 r600_context_add_resource_size(ctx, src->buffer);
3411 }
3412 } else {
3413 for (i = 0; i < count; i++) {
3414 pipe_resource_reference(&dst[i].buffer, NULL);
3415 }
3416 }
3417 sctx->vertex_buffers_dirty = true;
3418 }
3419
3420 static void si_set_index_buffer(struct pipe_context *ctx,
3421 const struct pipe_index_buffer *ib)
3422 {
3423 struct si_context *sctx = (struct si_context *)ctx;
3424
3425 if (ib) {
3426 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
3427 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3428 r600_context_add_resource_size(ctx, ib->buffer);
3429 } else {
3430 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3431 }
3432 }
3433
3434 /*
3435 * Misc
3436 */
3437 static void si_set_polygon_stipple(struct pipe_context *ctx,
3438 const struct pipe_poly_stipple *state)
3439 {
3440 struct si_context *sctx = (struct si_context *)ctx;
3441 struct pipe_resource *tex;
3442 struct pipe_sampler_view *view;
3443 bool is_zero = true;
3444 bool is_one = true;
3445 int i;
3446
3447 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
3448 * the resource is NULL/invalid. Take advantage of this fact and skip
3449 * texture allocation if the stipple pattern is constant.
3450 *
3451 * This is an optimization for the common case when stippling isn't
3452 * used but set_polygon_stipple is still called by st/mesa.
3453 */
3454 for (i = 0; i < Elements(state->stipple); i++) {
3455 is_zero = is_zero && state->stipple[i] == 0;
3456 is_one = is_one && state->stipple[i] == 0xffffffff;
3457 }
3458
3459 if (is_zero || is_one) {
3460 struct pipe_sampler_view templ = {{0}};
3461
3462 templ.swizzle_r = PIPE_SWIZZLE_ZERO;
3463 templ.swizzle_g = PIPE_SWIZZLE_ZERO;
3464 templ.swizzle_b = PIPE_SWIZZLE_ZERO;
3465 /* The pattern should be inverted in the texture. */
3466 templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO;
3467
3468 view = ctx->create_sampler_view(ctx, NULL, &templ);
3469 } else {
3470 /* Create a new texture. */
3471 tex = util_pstipple_create_stipple_texture(ctx, state->stipple);
3472 if (!tex)
3473 return;
3474
3475 view = util_pstipple_create_sampler_view(ctx, tex);
3476 pipe_resource_reference(&tex, NULL);
3477 }
3478
3479 ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT,
3480 SI_POLY_STIPPLE_SAMPLER, 1, &view);
3481 pipe_sampler_view_reference(&view, NULL);
3482
3483 /* Bind the sampler state if needed. */
3484 if (!sctx->pstipple_sampler_state) {
3485 sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx);
3486 ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT,
3487 SI_POLY_STIPPLE_SAMPLER, 1,
3488 &sctx->pstipple_sampler_state);
3489 }
3490 }
3491
3492 static void si_set_tess_state(struct pipe_context *ctx,
3493 const float default_outer_level[4],
3494 const float default_inner_level[2])
3495 {
3496 struct si_context *sctx = (struct si_context *)ctx;
3497 struct pipe_constant_buffer cb;
3498 float array[8];
3499
3500 memcpy(array, default_outer_level, sizeof(float) * 4);
3501 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3502
3503 cb.buffer = NULL;
3504 cb.user_buffer = NULL;
3505 cb.buffer_size = sizeof(array);
3506
3507 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3508 (void*)array, sizeof(array),
3509 &cb.buffer_offset);
3510
3511 ctx->set_constant_buffer(ctx, PIPE_SHADER_TESS_CTRL,
3512 SI_DRIVER_STATE_CONST_BUF, &cb);
3513 pipe_resource_reference(&cb.buffer, NULL);
3514 }
3515
3516 static void si_texture_barrier(struct pipe_context *ctx)
3517 {
3518 struct si_context *sctx = (struct si_context *)ctx;
3519
3520 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3521 SI_CONTEXT_INV_GLOBAL_L2 |
3522 SI_CONTEXT_FLUSH_AND_INV_CB;
3523 }
3524
3525 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3526 {
3527 struct si_context *sctx = (struct si_context *)ctx;
3528
3529 /* Subsequent commands must wait for all shader invocations to
3530 * complete. */
3531 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
3532
3533 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3534 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3535 SI_CONTEXT_INV_VMEM_L1;
3536
3537 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3538 PIPE_BARRIER_SHADER_BUFFER |
3539 PIPE_BARRIER_TEXTURE |
3540 PIPE_BARRIER_IMAGE |
3541 PIPE_BARRIER_STREAMOUT_BUFFER)) {
3542 /* As far as I can tell, L1 contents are written back to L2
3543 * automatically at end of shader, but the contents of other
3544 * L1 caches might still be stale. */
3545 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3546 }
3547
3548 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3549 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3550
3551 /* Indices are read through TC L2 since VI. */
3552 if (sctx->screen->b.chip_class <= CIK)
3553 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3554 }
3555
3556 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3557 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3558
3559 if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
3560 PIPE_BARRIER_FRAMEBUFFER |
3561 PIPE_BARRIER_INDIRECT_BUFFER)) {
3562 /* Not sure if INV_GLOBAL_L2 is the best thing here.
3563 *
3564 * We need to make sure that TC L1 & L2 are written back to
3565 * memory, because neither CPU accesses nor CB fetches consider
3566 * TC, but there's no need to invalidate any TC cache lines. */
3567 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3568 }
3569 }
3570
3571 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3572 {
3573 struct pipe_blend_state blend;
3574
3575 memset(&blend, 0, sizeof(blend));
3576 blend.independent_blend_enable = true;
3577 blend.rt[0].colormask = 0xf;
3578 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3579 }
3580
3581 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3582 bool include_draw_vbo)
3583 {
3584 si_need_cs_space((struct si_context*)ctx);
3585 }
3586
3587 static void si_init_config(struct si_context *sctx);
3588
3589 void si_init_state_functions(struct si_context *sctx)
3590 {
3591 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3592 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3593 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3594
3595 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3596 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3597 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3598 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3599 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3600 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3601 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3602 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3603 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3604 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3605 si_init_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors, si_emit_scissors);
3606 si_init_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports, si_emit_viewports);
3607 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3608
3609 sctx->b.b.create_blend_state = si_create_blend_state;
3610 sctx->b.b.bind_blend_state = si_bind_blend_state;
3611 sctx->b.b.delete_blend_state = si_delete_blend_state;
3612 sctx->b.b.set_blend_color = si_set_blend_color;
3613
3614 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3615 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3616 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3617
3618 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3619 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3620 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3621
3622 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3623 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3624 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3625 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3626 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3627
3628 sctx->b.b.set_clip_state = si_set_clip_state;
3629 sctx->b.b.set_scissor_states = si_set_scissor_states;
3630 sctx->b.b.set_viewport_states = si_set_viewport_states;
3631 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3632
3633 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3634 sctx->b.b.get_sample_position = cayman_get_sample_position;
3635
3636 sctx->b.b.create_sampler_state = si_create_sampler_state;
3637 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3638
3639 sctx->b.b.create_sampler_view = si_create_sampler_view;
3640 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3641
3642 sctx->b.b.set_sample_mask = si_set_sample_mask;
3643
3644 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3645 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3646 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3647 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3648 sctx->b.b.set_index_buffer = si_set_index_buffer;
3649
3650 sctx->b.b.texture_barrier = si_texture_barrier;
3651 sctx->b.b.memory_barrier = si_memory_barrier;
3652 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3653 sctx->b.b.set_min_samples = si_set_min_samples;
3654 sctx->b.b.set_tess_state = si_set_tess_state;
3655
3656 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3657 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3658
3659 sctx->b.b.draw_vbo = si_draw_vbo;
3660
3661 if (sctx->b.chip_class >= CIK) {
3662 sctx->b.dma_copy = cik_sdma_copy;
3663 } else {
3664 sctx->b.dma_copy = si_dma_copy;
3665 }
3666
3667 si_init_config(sctx);
3668 }
3669
3670 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3671 struct r600_texture *rtex,
3672 struct radeon_bo_metadata *md)
3673 {
3674 struct si_screen *sscreen = (struct si_screen*)rscreen;
3675 struct pipe_resource *res = &rtex->resource.b.b;
3676 static const unsigned char swizzle[] = {
3677 PIPE_SWIZZLE_RED,
3678 PIPE_SWIZZLE_GREEN,
3679 PIPE_SWIZZLE_BLUE,
3680 PIPE_SWIZZLE_ALPHA
3681 };
3682 uint32_t desc[8], i;
3683 bool is_array = util_resource_is_array_texture(res);
3684
3685 /* DRM 2.x.x doesn't support this. */
3686 if (rscreen->info.drm_major != 3)
3687 return;
3688
3689 assert(rtex->fmask.size == 0);
3690
3691 /* Metadata image format format version 1:
3692 * [0] = 1 (metadata format identifier)
3693 * [1] = (VENDOR_ID << 16) | PCI_ID
3694 * [2:9] = image descriptor for the whole resource
3695 * [2] is always 0, because the base address is cleared
3696 * [9] is the DCC offset bits [39:8] from the beginning of
3697 * the buffer
3698 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3699 */
3700
3701 md->metadata[0] = 1; /* metadata image format version 1 */
3702
3703 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3704 md->metadata[1] = (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3705
3706 si_make_texture_descriptor(sscreen, rtex, true,
3707 res->target, res->format,
3708 swizzle, 0, 0, res->last_level, 0,
3709 is_array ? res->array_size - 1 : 0,
3710 res->width0, res->height0, res->depth0,
3711 desc, NULL);
3712
3713 /* Clear the base address and set the relative DCC offset. */
3714 desc[0] = 0;
3715 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3716 desc[7] = rtex->dcc_offset >> 8;
3717
3718 /* Dwords [2:9] contain the image descriptor. */
3719 memcpy(&md->metadata[2], desc, sizeof(desc));
3720
3721 /* Dwords [10:..] contain the mipmap level offsets. */
3722 for (i = 0; i <= res->last_level; i++)
3723 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3724
3725 md->size_metadata = (11 + res->last_level) * 4;
3726 }
3727
3728 void si_init_screen_state_functions(struct si_screen *sscreen)
3729 {
3730 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3731 }
3732
3733 static void
3734 si_write_harvested_raster_configs(struct si_context *sctx,
3735 struct si_pm4_state *pm4,
3736 unsigned raster_config,
3737 unsigned raster_config_1)
3738 {
3739 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3740 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3741 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3742 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3743 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3744 unsigned rb_per_se = num_rb / num_se;
3745 unsigned se_mask[4];
3746 unsigned se;
3747
3748 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3749 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3750 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3751 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3752
3753 assert(num_se == 1 || num_se == 2 || num_se == 4);
3754 assert(sh_per_se == 1 || sh_per_se == 2);
3755 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3756
3757 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3758 * fields are for, so I'm leaving them as their default
3759 * values. */
3760
3761 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3762 (!se_mask[2] && !se_mask[3]))) {
3763 raster_config_1 &= C_028354_SE_PAIR_MAP;
3764
3765 if (!se_mask[0] && !se_mask[1]) {
3766 raster_config_1 |=
3767 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3768 } else {
3769 raster_config_1 |=
3770 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3771 }
3772 }
3773
3774 for (se = 0; se < num_se; se++) {
3775 unsigned raster_config_se = raster_config;
3776 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3777 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3778 int idx = (se / 2) * 2;
3779
3780 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3781 raster_config_se &= C_028350_SE_MAP;
3782
3783 if (!se_mask[idx]) {
3784 raster_config_se |=
3785 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3786 } else {
3787 raster_config_se |=
3788 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3789 }
3790 }
3791
3792 pkr0_mask &= rb_mask;
3793 pkr1_mask &= rb_mask;
3794 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3795 raster_config_se &= C_028350_PKR_MAP;
3796
3797 if (!pkr0_mask) {
3798 raster_config_se |=
3799 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3800 } else {
3801 raster_config_se |=
3802 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3803 }
3804 }
3805
3806 if (rb_per_se >= 2) {
3807 unsigned rb0_mask = 1 << (se * rb_per_se);
3808 unsigned rb1_mask = rb0_mask << 1;
3809
3810 rb0_mask &= rb_mask;
3811 rb1_mask &= rb_mask;
3812 if (!rb0_mask || !rb1_mask) {
3813 raster_config_se &= C_028350_RB_MAP_PKR0;
3814
3815 if (!rb0_mask) {
3816 raster_config_se |=
3817 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3818 } else {
3819 raster_config_se |=
3820 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3821 }
3822 }
3823
3824 if (rb_per_se > 2) {
3825 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3826 rb1_mask = rb0_mask << 1;
3827 rb0_mask &= rb_mask;
3828 rb1_mask &= rb_mask;
3829 if (!rb0_mask || !rb1_mask) {
3830 raster_config_se &= C_028350_RB_MAP_PKR1;
3831
3832 if (!rb0_mask) {
3833 raster_config_se |=
3834 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3835 } else {
3836 raster_config_se |=
3837 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3838 }
3839 }
3840 }
3841 }
3842
3843 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3844 if (sctx->b.chip_class < CIK)
3845 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3846 SE_INDEX(se) | SH_BROADCAST_WRITES |
3847 INSTANCE_BROADCAST_WRITES);
3848 else
3849 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3850 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3851 S_030800_INSTANCE_BROADCAST_WRITES(1));
3852 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3853 if (sctx->b.chip_class >= CIK)
3854 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3855 }
3856
3857 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3858 if (sctx->b.chip_class < CIK)
3859 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3860 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3861 INSTANCE_BROADCAST_WRITES);
3862 else
3863 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3864 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3865 S_030800_INSTANCE_BROADCAST_WRITES(1));
3866 }
3867
3868 static void si_init_config(struct si_context *sctx)
3869 {
3870 struct si_screen *sscreen = sctx->screen;
3871 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3872 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3873 unsigned raster_config, raster_config_1;
3874 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3875 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3876 int i;
3877
3878 if (!pm4)
3879 return;
3880
3881 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3882 si_pm4_cmd_add(pm4, 0x80000000);
3883 si_pm4_cmd_add(pm4, 0x80000000);
3884 si_pm4_cmd_end(pm4, false);
3885
3886 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3887 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3888
3889 /* FIXME calculate these values somehow ??? */
3890 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3891 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3892 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3893
3894 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3895 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3896
3897 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3898 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3899 if (sctx->b.chip_class < CIK)
3900 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3901 S_008A14_CLIP_VTX_REORDER_ENA(1));
3902
3903 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3904 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3905
3906 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3907
3908 for (i = 0; i < 16; i++) {
3909 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3910 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3911 }
3912
3913 switch (sctx->screen->b.family) {
3914 case CHIP_TAHITI:
3915 case CHIP_PITCAIRN:
3916 raster_config = 0x2a00126a;
3917 raster_config_1 = 0x00000000;
3918 break;
3919 case CHIP_VERDE:
3920 raster_config = 0x0000124a;
3921 raster_config_1 = 0x00000000;
3922 break;
3923 case CHIP_OLAND:
3924 raster_config = 0x00000082;
3925 raster_config_1 = 0x00000000;
3926 break;
3927 case CHIP_HAINAN:
3928 raster_config = 0x00000000;
3929 raster_config_1 = 0x00000000;
3930 break;
3931 case CHIP_BONAIRE:
3932 raster_config = 0x16000012;
3933 raster_config_1 = 0x00000000;
3934 break;
3935 case CHIP_HAWAII:
3936 raster_config = 0x3a00161a;
3937 raster_config_1 = 0x0000002e;
3938 break;
3939 case CHIP_FIJI:
3940 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3941 /* old kernels with old tiling config */
3942 raster_config = 0x16000012;
3943 raster_config_1 = 0x0000002a;
3944 } else {
3945 raster_config = 0x3a00161a;
3946 raster_config_1 = 0x0000002e;
3947 }
3948 break;
3949 case CHIP_TONGA:
3950 raster_config = 0x16000012;
3951 raster_config_1 = 0x0000002a;
3952 break;
3953 case CHIP_ICELAND:
3954 raster_config = 0x00000002;
3955 raster_config_1 = 0x00000000;
3956 break;
3957 case CHIP_CARRIZO:
3958 raster_config = 0x00000002;
3959 raster_config_1 = 0x00000000;
3960 break;
3961 case CHIP_KAVERI:
3962 /* KV should be 0x00000002, but that causes problems with radeon */
3963 raster_config = 0x00000000; /* 0x00000002 */
3964 raster_config_1 = 0x00000000;
3965 break;
3966 case CHIP_KABINI:
3967 case CHIP_MULLINS:
3968 case CHIP_STONEY:
3969 raster_config = 0x00000000;
3970 raster_config_1 = 0x00000000;
3971 break;
3972 default:
3973 fprintf(stderr,
3974 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3975 raster_config = 0x00000000;
3976 raster_config_1 = 0x00000000;
3977 break;
3978 }
3979
3980 /* Always use the default config when all backends are enabled
3981 * (or when we failed to determine the enabled backends).
3982 */
3983 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3984 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3985 raster_config);
3986 if (sctx->b.chip_class >= CIK)
3987 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3988 raster_config_1);
3989 } else {
3990 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3991 }
3992
3993 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3994 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3995 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3996 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3997 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3998 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3999 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4000
4001 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4002 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
4003 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4004 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4005 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4006 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
4007 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
4008 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
4009 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
4010 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4011 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4012 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4013 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
4014 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
4015 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
4016
4017 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4018 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4019 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4020
4021 if (sctx->b.chip_class >= CIK) {
4022 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4023 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4024 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4025
4026 if (sscreen->b.info.num_good_compute_units /
4027 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
4028 /* Too few available compute units per SH. Disallowing
4029 * VS to run on CU0 could hurt us more than late VS
4030 * allocation would help.
4031 *
4032 * LATE_ALLOC_VS = 2 is the highest safe number.
4033 */
4034 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4035 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4036 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4037 } else {
4038 /* Set LATE_ALLOC_VS == 31. It should be less than
4039 * the number of scratch waves. Limitations:
4040 * - VS can't execute on CU0.
4041 * - If HS writes outputs to LDS, LS can't execute on CU0.
4042 */
4043 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffe));
4044 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4045 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4046 }
4047
4048 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4049 }
4050
4051 if (sctx->b.chip_class >= VI) {
4052 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4053 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4054 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4055 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4056 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4057 }
4058
4059 if (sctx->b.family == CHIP_STONEY)
4060 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4061
4062 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4063 if (sctx->b.chip_class >= CIK)
4064 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4065 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4066 RADEON_PRIO_BORDER_COLORS);
4067
4068 si_pm4_upload_indirect_buffer(sctx, pm4);
4069 sctx->init_config = pm4;
4070 }