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radeonsi: Fix handling of TGSI_SEMANTIC_PSIZE
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "radeonsi_pipe.h"
32 #include "radeonsi_shader.h"
33 #include "si_state.h"
34 #include "sid.h"
35
36 /*
37 * Shaders
38 */
39
40 static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
41 {
42 struct r600_context *rctx = (struct r600_context *)ctx;
43 struct si_pm4_state *pm4;
44 unsigned num_sgprs, num_user_sgprs;
45 unsigned nparams, i, vgpr_comp_cnt;
46 uint64_t va;
47
48 si_pm4_delete_state(rctx, vs, shader->pm4);
49 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
50
51 si_pm4_inval_shader_cache(pm4);
52
53 /* Certain attributes (position, psize, etc.) don't count as params.
54 * VS is required to export at least one param and r600_shader_from_tgsi()
55 * takes care of adding a dummy export.
56 */
57 for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
58 switch (shader->shader.output[i].name) {
59 case TGSI_SEMANTIC_POSITION:
60 case TGSI_SEMANTIC_PSIZE:
61 break;
62 default:
63 nparams++;
64 }
65 }
66 if (nparams < 1)
67 nparams = 1;
68
69 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
70 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
71
72 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
73 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
74 S_02870C_POS1_EXPORT_FORMAT(shader->shader.vs_out_misc_write ?
75 V_02870C_SPI_SHADER_4COMP :
76 V_02870C_SPI_SHADER_NONE) |
77 S_02870C_POS2_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
78 S_02870C_POS3_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE));
79
80 va = r600_resource_va(ctx->screen, (void *)shader->bo);
81 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
82 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
83 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
84
85 num_user_sgprs = SI_VS_NUM_USER_SGPR;
86 num_sgprs = shader->num_sgprs;
87 if (num_user_sgprs > num_sgprs)
88 num_sgprs = num_user_sgprs;
89 /* Last 2 reserved SGPRs are used for VCC */
90 num_sgprs += 2;
91 assert(num_sgprs <= 104);
92
93 vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
94
95 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
96 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
97 S_00B128_SGPRS((num_sgprs - 1) / 8) |
98 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt));
99 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
100 S_00B12C_USER_SGPR(num_user_sgprs));
101
102 si_pm4_bind_state(rctx, vs, shader->pm4);
103 }
104
105 static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
106 {
107 struct r600_context *rctx = (struct r600_context *)ctx;
108 struct si_pm4_state *pm4;
109 unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
110 unsigned num_sgprs, num_user_sgprs;
111 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
112 unsigned fragcoord_interp_mode = 0;
113 unsigned spi_baryc_cntl, spi_ps_input_ena, spi_shader_z_format;
114 uint64_t va;
115
116 si_pm4_delete_state(rctx, ps, shader->pm4);
117 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
118
119 si_pm4_inval_shader_cache(pm4);
120
121 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
122 for (i = 0; i < shader->shader.ninput; i++) {
123 switch (shader->shader.input[i].name) {
124 case TGSI_SEMANTIC_POSITION:
125 if (shader->shader.input[i].centroid) {
126 /* fragcoord_interp_mode will be written to
127 * SPI_BARYC_CNTL.POS_FLOAT_LOCATION
128 * Possible vaules:
129 * 0 -> Position = pixel center (default)
130 * 1 -> Position = pixel centroid
131 * 2 -> Position = iterated sample number XXX:
132 * What does this mean?
133 */
134 fragcoord_interp_mode = 1;
135 }
136 /* Fall through */
137 case TGSI_SEMANTIC_FACE:
138 continue;
139 }
140
141 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
142 have_linear = TRUE;
143 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
144 have_perspective = TRUE;
145 if (shader->shader.input[i].centroid)
146 have_centroid = TRUE;
147 }
148
149 for (i = 0; i < shader->shader.noutput; i++) {
150 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION)
151 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
152 if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
153 db_shader_control |= S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
154 }
155 if (shader->shader.uses_kill || shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
156 db_shader_control |= S_02880C_KILL_ENABLE(1);
157
158 exports_ps = 0;
159 num_cout = 0;
160 for (i = 0; i < shader->shader.noutput; i++) {
161 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION ||
162 shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
163 exports_ps |= 1;
164 else if (shader->shader.output[i].name == TGSI_SEMANTIC_COLOR) {
165 if (shader->shader.fs_write_all)
166 num_cout = shader->shader.nr_cbufs;
167 else
168 num_cout++;
169 }
170 }
171 if (!exports_ps) {
172 /* always at least export 1 component per pixel */
173 exports_ps = 2;
174 }
175
176 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.ninterp);
177
178 spi_baryc_cntl = 0;
179 if (have_perspective)
180 spi_baryc_cntl |= have_centroid ?
181 S_0286E0_PERSP_CENTROID_CNTL(1) : S_0286E0_PERSP_CENTER_CNTL(1);
182 if (have_linear)
183 spi_baryc_cntl |= have_centroid ?
184 S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1);
185 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(fragcoord_interp_mode);
186
187 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
188 spi_ps_input_ena = shader->spi_ps_input_ena;
189 /* we need to enable at least one of them, otherwise we hang the GPU */
190 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
191 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
192 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
193 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
194 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
195 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
196 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
197 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
198
199 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
200 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
201 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
202
203 if (G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(db_shader_control))
204 spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
205 else if (G_02880C_Z_EXPORT_ENABLE(db_shader_control))
206 spi_shader_z_format = V_028710_SPI_SHADER_32_R;
207 else
208 spi_shader_z_format = 0;
209 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, spi_shader_z_format);
210 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
211 shader->spi_shader_col_format);
212
213 va = r600_resource_va(ctx->screen, (void *)shader->bo);
214 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
215 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
216 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
217
218 num_user_sgprs = SI_PS_NUM_USER_SGPR;
219 num_sgprs = shader->num_sgprs;
220 if (num_user_sgprs > num_sgprs)
221 num_sgprs = num_user_sgprs;
222 /* Last 2 reserved SGPRs are used for VCC */
223 num_sgprs += 2;
224 assert(num_sgprs <= 104);
225
226 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
227 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
228 S_00B028_SGPRS((num_sgprs - 1) / 8));
229 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
230 S_00B02C_USER_SGPR(num_user_sgprs));
231
232 si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
233
234 shader->sprite_coord_enable = rctx->sprite_coord_enable;
235 si_pm4_bind_state(rctx, ps, shader->pm4);
236 }
237
238 /*
239 * Drawing
240 */
241
242 static unsigned si_conv_pipe_prim(unsigned pprim)
243 {
244 static const unsigned prim_conv[] = {
245 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
246 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
247 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
248 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
249 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
250 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
251 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
252 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
253 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
254 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
255 [PIPE_PRIM_LINES_ADJACENCY] = ~0,
256 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = ~0,
257 [PIPE_PRIM_TRIANGLES_ADJACENCY] = ~0,
258 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = ~0
259 };
260 unsigned result = prim_conv[pprim];
261 if (result == ~0) {
262 R600_ERR("unsupported primitive type %d\n", pprim);
263 }
264 return result;
265 }
266
267 static bool si_update_draw_info_state(struct r600_context *rctx,
268 const struct pipe_draw_info *info)
269 {
270 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
271 struct si_shader *vs = &rctx->vs_shader->current->shader;
272 unsigned prim = si_conv_pipe_prim(info->mode);
273 unsigned ls_mask = 0;
274
275 if (pm4 == NULL)
276 return false;
277
278 if (prim == ~0) {
279 FREE(pm4);
280 return false;
281 }
282
283 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
284 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
285 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
286 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET,
287 info->indexed ? info->index_bias : info->start);
288 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
289 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
290 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_START_INSTANCE * 4,
291 info->start_instance);
292
293 if (prim == V_008958_DI_PT_LINELIST)
294 ls_mask = 1;
295 else if (prim == V_008958_DI_PT_LINESTRIP)
296 ls_mask = 2;
297 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
298 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
299 rctx->pa_sc_line_stipple);
300
301 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
302 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
303 S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
304 } else {
305 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl);
306 }
307 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
308 S_02881C_USE_VTX_POINT_SIZE(vs->vs_out_point_size) |
309 S_02881C_VS_OUT_MISC_VEC_ENA(vs->vs_out_misc_write)
310 /*| (rctx->rasterizer->clip_plane_enable &
311 rctx->vs_shader->shader.clip_dist_write)*/);
312 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL, rctx->pa_cl_clip_cntl
313 /*| (rctx->vs_shader->shader.clip_dist_write ||
314 rctx->vs_shader->shader.vs_prohibit_ucps ?
315 0 : rctx->rasterizer->clip_plane_enable & 0x3F)*/);
316
317 si_pm4_set_state(rctx, draw_info, pm4);
318 return true;
319 }
320
321 static void si_update_spi_map(struct r600_context *rctx)
322 {
323 struct si_shader *ps = &rctx->ps_shader->current->shader;
324 struct si_shader *vs = &rctx->vs_shader->current->shader;
325 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
326 unsigned i, j, tmp;
327
328 for (i = 0; i < ps->ninput; i++) {
329 unsigned name = ps->input[i].name;
330 unsigned param_offset = ps->input[i].param_offset;
331
332 if (name == TGSI_SEMANTIC_POSITION)
333 /* Read from preloaded VGPRs, not parameters */
334 continue;
335
336 bcolor:
337 tmp = 0;
338
339 if (ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
340 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
341 rctx->ps_shader->current->key.ps.flatshade)) {
342 tmp |= S_028644_FLAT_SHADE(1);
343 }
344
345 if (name == TGSI_SEMANTIC_GENERIC &&
346 rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
347 tmp |= S_028644_PT_SPRITE_TEX(1);
348 }
349
350 for (j = 0; j < vs->noutput; j++) {
351 if (name == vs->output[j].name &&
352 ps->input[i].sid == vs->output[j].sid) {
353 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
354 break;
355 }
356 }
357
358 if (j == vs->noutput) {
359 /* No corresponding output found, load defaults into input */
360 tmp |= S_028644_OFFSET(0x20);
361 }
362
363 si_pm4_set_reg(pm4,
364 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
365 tmp);
366
367 if (name == TGSI_SEMANTIC_COLOR &&
368 rctx->ps_shader->current->key.ps.color_two_side) {
369 name = TGSI_SEMANTIC_BCOLOR;
370 param_offset++;
371 goto bcolor;
372 }
373 }
374
375 si_pm4_set_state(rctx, spi, pm4);
376 }
377
378 static void si_update_derived_state(struct r600_context *rctx)
379 {
380 struct pipe_context * ctx = (struct pipe_context*)rctx;
381 unsigned vs_dirty = 0, ps_dirty = 0;
382
383 if (!rctx->blitter->running) {
384 /* Flush depth textures which need to be flushed. */
385 if (rctx->vs_samplers.depth_texture_mask) {
386 si_flush_depth_textures(rctx, &rctx->vs_samplers);
387 }
388 if (rctx->ps_samplers.depth_texture_mask) {
389 si_flush_depth_textures(rctx, &rctx->ps_samplers);
390 }
391 }
392
393 si_shader_select(ctx, rctx->vs_shader, &vs_dirty);
394
395 if (!rctx->vs_shader->current->pm4) {
396 si_pipe_shader_vs(ctx, rctx->vs_shader->current);
397 vs_dirty = 0;
398 }
399
400 if (vs_dirty) {
401 si_pm4_bind_state(rctx, vs, rctx->vs_shader->current->pm4);
402 }
403
404
405 si_shader_select(ctx, rctx->ps_shader, &ps_dirty);
406
407 if (!rctx->ps_shader->current->pm4) {
408 si_pipe_shader_ps(ctx, rctx->ps_shader->current);
409 ps_dirty = 0;
410 }
411 if (!rctx->ps_shader->current->bo) {
412 if (!rctx->dummy_pixel_shader->pm4)
413 si_pipe_shader_ps(ctx, rctx->dummy_pixel_shader);
414 else
415 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
416
417 ps_dirty = 0;
418 }
419
420 if (ps_dirty) {
421 si_pm4_bind_state(rctx, ps, rctx->ps_shader->current->pm4);
422 }
423
424 if (si_pm4_state_changed(rctx, ps) || si_pm4_state_changed(rctx, vs)) {
425 /* XXX: Emitting the PS state even when only the VS changed
426 * fixes random failures with piglit glsl-max-varyings.
427 * Not sure why...
428 */
429 rctx->emitted.named.ps = NULL;
430 si_update_spi_map(rctx);
431 }
432 }
433
434 static void si_vertex_buffer_update(struct r600_context *rctx)
435 {
436 struct pipe_context *ctx = &rctx->context;
437 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
438 bool bound[PIPE_MAX_ATTRIBS] = {};
439 unsigned i, count;
440 uint64_t va;
441
442 si_pm4_inval_texture_cache(pm4);
443
444 /* bind vertex buffer once */
445 count = rctx->vertex_elements->count;
446 assert(count <= 256 / 4);
447
448 si_pm4_sh_data_begin(pm4);
449 for (i = 0 ; i < count; i++) {
450 struct pipe_vertex_element *ve = &rctx->vertex_elements->elements[i];
451 struct pipe_vertex_buffer *vb;
452 struct si_resource *rbuffer;
453 unsigned offset;
454
455 if (ve->vertex_buffer_index >= rctx->nr_vertex_buffers)
456 continue;
457
458 vb = &rctx->vertex_buffer[ve->vertex_buffer_index];
459 rbuffer = (struct si_resource*)vb->buffer;
460 if (rbuffer == NULL)
461 continue;
462
463 offset = 0;
464 offset += vb->buffer_offset;
465 offset += ve->src_offset;
466
467 va = r600_resource_va(ctx->screen, (void*)rbuffer);
468 va += offset;
469
470 /* Fill in T# buffer resource description */
471 si_pm4_sh_data_add(pm4, va & 0xFFFFFFFF);
472 si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
473 S_008F04_STRIDE(vb->stride)));
474 if (vb->stride)
475 /* Round up by rounding down and adding 1 */
476 si_pm4_sh_data_add(pm4,
477 (vb->buffer->width0 - offset -
478 util_format_get_blocksize(ve->src_format)) /
479 vb->stride + 1);
480 else
481 si_pm4_sh_data_add(pm4, vb->buffer->width0 - offset);
482 si_pm4_sh_data_add(pm4, rctx->vertex_elements->rsrc_word3[i]);
483
484 if (!bound[ve->vertex_buffer_index]) {
485 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
486 bound[ve->vertex_buffer_index] = true;
487 }
488 }
489 si_pm4_sh_data_end(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, SI_SGPR_VERTEX_BUFFER);
490 si_pm4_set_state(rctx, vertex_buffers, pm4);
491 }
492
493 static void si_state_draw(struct r600_context *rctx,
494 const struct pipe_draw_info *info,
495 const struct pipe_index_buffer *ib)
496 {
497 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
498
499 /* queries need some special values
500 * (this is non-zero if any query is active) */
501 if (rctx->num_cs_dw_queries_suspend) {
502 struct si_state_dsa *dsa = rctx->queued.named.dsa;
503
504 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
505 S_028004_PERFECT_ZPASS_COUNTS(1));
506 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
507 dsa->db_render_override |
508 S_02800C_NOOP_CULL_DISABLE(1));
509 }
510
511 /* draw packet */
512 si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
513 if (ib->index_size == 4) {
514 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (R600_BIG_ENDIAN ?
515 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
516 } else {
517 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (R600_BIG_ENDIAN ?
518 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
519 }
520 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
521
522 si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
523 si_pm4_cmd_add(pm4, info->instance_count);
524 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
525
526 if (info->indexed) {
527 uint32_t max_size = (ib->buffer->width0 - ib->offset) /
528 rctx->index_buffer.index_size;
529 uint64_t va;
530 va = r600_resource_va(&rctx->screen->screen, ib->buffer);
531 va += ib->offset;
532
533 si_pm4_add_bo(pm4, (struct si_resource *)ib->buffer, RADEON_USAGE_READ);
534 si_cmd_draw_index_2(pm4, max_size, va, info->count,
535 V_0287F0_DI_SRC_SEL_DMA,
536 rctx->predicate_drawing);
537 } else {
538 uint32_t initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
539 initiator |= S_0287F0_USE_OPAQUE(!!info->count_from_stream_output);
540 si_cmd_draw_index_auto(pm4, info->count, initiator, rctx->predicate_drawing);
541 }
542 si_pm4_set_state(rctx, draw, pm4);
543 }
544
545 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
546 {
547 struct r600_context *rctx = (struct r600_context *)ctx;
548 struct pipe_index_buffer ib = {};
549 uint32_t cp_coher_cntl;
550
551 if (!info->count && (info->indexed || !info->count_from_stream_output))
552 return;
553
554 if (!rctx->ps_shader || !rctx->vs_shader)
555 return;
556
557 si_update_derived_state(rctx);
558 si_vertex_buffer_update(rctx);
559
560 if (info->indexed) {
561 /* Initialize the index buffer struct. */
562 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
563 ib.user_buffer = rctx->index_buffer.user_buffer;
564 ib.index_size = rctx->index_buffer.index_size;
565 ib.offset = rctx->index_buffer.offset + info->start * ib.index_size;
566
567 /* Translate or upload, if needed. */
568 r600_translate_index_buffer(rctx, &ib, info->count);
569
570 if (ib.user_buffer && !ib.buffer) {
571 r600_upload_index_buffer(rctx, &ib, info->count);
572 }
573
574 } else if (info->count_from_stream_output) {
575 r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info->count_from_stream_output);
576 }
577
578 rctx->vs_shader_so_strides = rctx->vs_shader->current->so_strides;
579
580 if (!si_update_draw_info_state(rctx, info))
581 return;
582
583 si_state_draw(rctx, info, &ib);
584
585 cp_coher_cntl = si_pm4_sync_flags(rctx);
586 if (cp_coher_cntl) {
587 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
588 si_cmd_surface_sync(pm4, cp_coher_cntl);
589 si_pm4_set_state(rctx, sync, pm4);
590 }
591
592 /* Emit states. */
593 rctx->pm4_dirty_cdwords += si_pm4_dirty_dw(rctx);
594
595 si_need_cs_space(rctx, 0, TRUE);
596
597 si_pm4_emit_dirty(rctx);
598 rctx->pm4_dirty_cdwords = 0;
599
600 #if R600_TRACE_CS
601 if (rctx->screen->trace_bo) {
602 r600_trace_emit(rctx);
603 }
604 #endif
605
606 #if 0
607 /* Enable stream out if needed. */
608 if (rctx->streamout_start) {
609 r600_context_streamout_begin(rctx);
610 rctx->streamout_start = FALSE;
611 }
612 #endif
613
614 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY;
615
616 /* Set the depth buffer as dirty. */
617 if (rctx->framebuffer.zsbuf) {
618 struct pipe_surface *surf = rctx->framebuffer.zsbuf;
619 struct r600_resource_texture *rtex = (struct r600_resource_texture *)surf->texture;
620
621 rtex->dirty_db_mask |= 1 << surf->u.tex.level;
622 }
623
624 pipe_resource_reference(&ib.buffer, NULL);
625 }