projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi/gfx10: don't initialize VGPRs not used by NGG passthrough
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR key for the shader cache.
45 */
46 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
47 unsigned char ir_sha1_cache_key[20])
48 {
49 struct blob blob = {};
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->nir_binary) {
54 ir_binary = sel->nir_binary;
55 ir_size = sel->nir_size;
56 } else {
57 assert(sel->nir);
58
59 blob_init(&blob);
60 nir_serialize(&blob, sel->nir, true);
61 ir_binary = blob.data;
62 ir_size = blob.size;
63 }
64
65 /* These settings affect the compilation, but they are not derived
66 * from the input shader IR.
67 */
68 unsigned shader_variant_flags = 0;
69
70 if (ngg)
71 shader_variant_flags |= 1 << 0;
72 if (sel->nir)
73 shader_variant_flags |= 1 << 1;
74 if (si_get_wave_size(sel->screen, sel->type, ngg, es) == 32)
75 shader_variant_flags |= 1 << 2;
76 if (sel->force_correct_derivs_after_kill)
77 shader_variant_flags |= 1 << 3;
78
79 struct mesa_sha1 ctx;
80 _mesa_sha1_init(&ctx);
81 _mesa_sha1_update(&ctx, &shader_variant_flags, 4);
82 _mesa_sha1_update(&ctx, ir_binary, ir_size);
83 if (sel->type == PIPE_SHADER_VERTEX ||
84 sel->type == PIPE_SHADER_TESS_EVAL ||
85 sel->type == PIPE_SHADER_GEOMETRY)
86 _mesa_sha1_update(&ctx, &sel->so, sizeof(sel->so));
87 _mesa_sha1_final(&ctx, ir_sha1_cache_key);
88
89 if (ir_binary == blob.data)
90 blob_finish(&blob);
91 }
92
93 /** Copy "data" to "ptr" and return the next dword following copied data. */
94 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
95 {
96 /* data may be NULL if size == 0 */
97 if (size)
98 memcpy(ptr, data, size);
99 ptr += DIV_ROUND_UP(size, 4);
100 return ptr;
101 }
102
103 /** Read data from "ptr". Return the next dword following the data. */
104 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
105 {
106 memcpy(data, ptr, size);
107 ptr += DIV_ROUND_UP(size, 4);
108 return ptr;
109 }
110
111 /**
112 * Write the size as uint followed by the data. Return the next dword
113 * following the copied data.
114 */
115 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
116 {
117 *ptr++ = size;
118 return write_data(ptr, data, size);
119 }
120
121 /**
122 * Read the size as uint followed by the data. Return both via parameters.
123 * Return the next dword following the data.
124 */
125 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
126 {
127 *size = *ptr++;
128 assert(*data == NULL);
129 if (!*size)
130 return ptr;
131 *data = malloc(*size);
132 return read_data(ptr, *data, *size);
133 }
134
135 /**
136 * Return the shader binary in a buffer. The first 4 bytes contain its size
137 * as integer.
138 */
139 static void *si_get_shader_binary(struct si_shader *shader)
140 {
141 /* There is always a size of data followed by the data itself. */
142 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
143 strlen(shader->binary.llvm_ir_string) + 1 : 0;
144
145 /* Refuse to allocate overly large buffers and guard against integer
146 * overflow. */
147 if (shader->binary.elf_size > UINT_MAX / 4 ||
148 llvm_ir_size > UINT_MAX / 4)
149 return NULL;
150
151 unsigned size =
152 4 + /* total size */
153 4 + /* CRC32 of the data below */
154 align(sizeof(shader->config), 4) +
155 align(sizeof(shader->info), 4) +
156 4 + align(shader->binary.elf_size, 4) +
157 4 + align(llvm_ir_size, 4);
158 void *buffer = CALLOC(1, size);
159 uint32_t *ptr = (uint32_t*)buffer;
160
161 if (!buffer)
162 return NULL;
163
164 *ptr++ = size;
165 ptr++; /* CRC32 is calculated at the end. */
166
167 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
168 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
169 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
170 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
171 assert((char *)ptr - (char *)buffer == size);
172
173 /* Compute CRC32. */
174 ptr = (uint32_t*)buffer;
175 ptr++;
176 *ptr = util_hash_crc32(ptr + 1, size - 8);
177
178 return buffer;
179 }
180
181 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
182 {
183 uint32_t *ptr = (uint32_t*)binary;
184 uint32_t size = *ptr++;
185 uint32_t crc32 = *ptr++;
186 unsigned chunk_size;
187 unsigned elf_size;
188
189 if (util_hash_crc32(ptr, size - 8) != crc32) {
190 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
191 return false;
192 }
193
194 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
195 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
196 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
197 &elf_size);
198 shader->binary.elf_size = elf_size;
199 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
200
201 return true;
202 }
203
204 /**
205 * Insert a shader into the cache. It's assumed the shader is not in the cache.
206 * Use si_shader_cache_load_shader before calling this.
207 */
208 void si_shader_cache_insert_shader(struct si_screen *sscreen,
209 unsigned char ir_sha1_cache_key[20],
210 struct si_shader *shader,
211 bool insert_into_disk_cache)
212 {
213 void *hw_binary;
214 struct hash_entry *entry;
215 uint8_t key[CACHE_KEY_SIZE];
216
217 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
218 if (entry)
219 return; /* already added */
220
221 hw_binary = si_get_shader_binary(shader);
222 if (!hw_binary)
223 return;
224
225 if (_mesa_hash_table_insert(sscreen->shader_cache,
226 mem_dup(ir_sha1_cache_key, 20),
227 hw_binary) == NULL) {
228 FREE(hw_binary);
229 return;
230 }
231
232 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
233 disk_cache_compute_key(sscreen->disk_shader_cache,
234 ir_sha1_cache_key, 20, key);
235 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
236 *((uint32_t *) hw_binary), NULL);
237 }
238 }
239
240 bool si_shader_cache_load_shader(struct si_screen *sscreen,
241 unsigned char ir_sha1_cache_key[20],
242 struct si_shader *shader)
243 {
244 struct hash_entry *entry =
245 _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
246 if (!entry) {
247 if (sscreen->disk_shader_cache) {
248 unsigned char sha1[CACHE_KEY_SIZE];
249
250 disk_cache_compute_key(sscreen->disk_shader_cache,
251 ir_sha1_cache_key, 20, sha1);
252
253 size_t binary_size;
254 uint8_t *buffer =
255 disk_cache_get(sscreen->disk_shader_cache,
256 sha1, &binary_size);
257 if (!buffer)
258 return false;
259
260 if (binary_size < sizeof(uint32_t) ||
261 *((uint32_t*)buffer) != binary_size) {
262 /* Something has gone wrong discard the item
263 * from the cache and rebuild/link from
264 * source.
265 */
266 assert(!"Invalid radeonsi shader disk cache "
267 "item!");
268
269 disk_cache_remove(sscreen->disk_shader_cache,
270 sha1);
271 free(buffer);
272
273 return false;
274 }
275
276 if (!si_load_shader_binary(shader, buffer)) {
277 free(buffer);
278 return false;
279 }
280 free(buffer);
281
282 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
283 shader, false);
284 } else {
285 return false;
286 }
287 } else {
288 if (!si_load_shader_binary(shader, entry->data))
289 return false;
290 }
291 p_atomic_inc(&sscreen->num_shader_cache_hits);
292 return true;
293 }
294
295 static uint32_t si_shader_cache_key_hash(const void *key)
296 {
297 /* Take the first dword of SHA1. */
298 return *(uint32_t*)key;
299 }
300
301 static bool si_shader_cache_key_equals(const void *a, const void *b)
302 {
303 /* Compare SHA1s. */
304 return memcmp(a, b, 20) == 0;
305 }
306
307 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
308 {
309 FREE((void*)entry->key);
310 FREE(entry->data);
311 }
312
313 bool si_init_shader_cache(struct si_screen *sscreen)
314 {
315 (void) simple_mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
316 sscreen->shader_cache =
317 _mesa_hash_table_create(NULL,
318 si_shader_cache_key_hash,
319 si_shader_cache_key_equals);
320
321 return sscreen->shader_cache != NULL;
322 }
323
324 void si_destroy_shader_cache(struct si_screen *sscreen)
325 {
326 if (sscreen->shader_cache)
327 _mesa_hash_table_destroy(sscreen->shader_cache,
328 si_destroy_shader_cache_entry);
329 simple_mtx_destroy(&sscreen->shader_cache_mutex);
330 }
331
332 /* SHADER STATES */
333
334 static void si_set_tesseval_regs(struct si_screen *sscreen,
335 const struct si_shader_selector *tes,
336 struct si_pm4_state *pm4)
337 {
338 const struct si_shader_info *info = &tes->info;
339 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
340 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
341 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
342 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
343 unsigned type, partitioning, topology, distribution_mode;
344
345 switch (tes_prim_mode) {
346 case PIPE_PRIM_LINES:
347 type = V_028B6C_TESS_ISOLINE;
348 break;
349 case PIPE_PRIM_TRIANGLES:
350 type = V_028B6C_TESS_TRIANGLE;
351 break;
352 case PIPE_PRIM_QUADS:
353 type = V_028B6C_TESS_QUAD;
354 break;
355 default:
356 assert(0);
357 return;
358 }
359
360 switch (tes_spacing) {
361 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
362 partitioning = V_028B6C_PART_FRAC_ODD;
363 break;
364 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
365 partitioning = V_028B6C_PART_FRAC_EVEN;
366 break;
367 case PIPE_TESS_SPACING_EQUAL:
368 partitioning = V_028B6C_PART_INTEGER;
369 break;
370 default:
371 assert(0);
372 return;
373 }
374
375 if (tes_point_mode)
376 topology = V_028B6C_OUTPUT_POINT;
377 else if (tes_prim_mode == PIPE_PRIM_LINES)
378 topology = V_028B6C_OUTPUT_LINE;
379 else if (tes_vertex_order_cw)
380 /* for some reason, this must be the other way around */
381 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
382 else
383 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
384
385 if (sscreen->info.has_distributed_tess) {
386 if (sscreen->info.family == CHIP_FIJI ||
387 sscreen->info.family >= CHIP_POLARIS10)
388 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
389 else
390 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
391 } else
392 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
393
394 assert(pm4->shader);
395 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
396 S_028B6C_PARTITIONING(partitioning) |
397 S_028B6C_TOPOLOGY(topology) |
398 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
399 }
400
401 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
402 * whether the "fractional odd" tessellation spacing is used.
403 *
404 * Possible VGT configurations and which state should set the register:
405 *
406 * Reg set in | VGT shader configuration | Value
407 * ------------------------------------------------------
408 * VS as VS | VS | 30
409 * VS as ES | ES -> GS -> VS | 30
410 * TES as VS | LS -> HS -> VS | 14 or 30
411 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
412 *
413 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
414 */
415 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
416 struct si_shader_selector *sel,
417 struct si_shader *shader,
418 struct si_pm4_state *pm4)
419 {
420 unsigned type = sel->type;
421
422 if (sscreen->info.family < CHIP_POLARIS10 ||
423 sscreen->info.chip_class >= GFX10)
424 return;
425
426 /* VS as VS, or VS as ES: */
427 if ((type == PIPE_SHADER_VERTEX &&
428 (!shader ||
429 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
430 /* TES as VS, or TES as ES: */
431 type == PIPE_SHADER_TESS_EVAL) {
432 unsigned vtx_reuse_depth = 30;
433
434 if (type == PIPE_SHADER_TESS_EVAL &&
435 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
436 PIPE_TESS_SPACING_FRACTIONAL_ODD)
437 vtx_reuse_depth = 14;
438
439 assert(pm4->shader);
440 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
441 }
442 }
443
444 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
445 {
446 if (shader->pm4)
447 si_pm4_clear_state(shader->pm4);
448 else
449 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
450
451 if (shader->pm4) {
452 shader->pm4->shader = shader;
453 return shader->pm4;
454 } else {
455 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
456 return NULL;
457 }
458 }
459
460 static unsigned si_get_num_vs_user_sgprs(struct si_shader *shader,
461 unsigned num_always_on_user_sgprs)
462 {
463 struct si_shader_selector *vs = shader->previous_stage_sel ?
464 shader->previous_stage_sel : shader->selector;
465 unsigned num_vbos_in_user_sgprs = vs->num_vbos_in_user_sgprs;
466
467 /* 1 SGPR is reserved for the vertex buffer pointer. */
468 assert(num_always_on_user_sgprs <= SI_SGPR_VS_VB_DESCRIPTOR_FIRST - 1);
469
470 if (num_vbos_in_user_sgprs)
471 return SI_SGPR_VS_VB_DESCRIPTOR_FIRST + num_vbos_in_user_sgprs * 4;
472
473 /* Add the pointer to VBO descriptors. */
474 return num_always_on_user_sgprs + 1;
475 }
476
477 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
478 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen,
479 struct si_shader *shader, bool legacy_vs_prim_id)
480 {
481 assert(shader->selector->type == PIPE_SHADER_VERTEX ||
482 (shader->previous_stage_sel &&
483 shader->previous_stage_sel->type == PIPE_SHADER_VERTEX));
484
485 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
486 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
487 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
488 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or InstanceID)
489 */
490 bool is_ls = shader->selector->type == PIPE_SHADER_TESS_CTRL || shader->key.as_ls;
491
492 if (sscreen->info.chip_class >= GFX10 && shader->info.uses_instanceid)
493 return 3;
494 else if ((is_ls && shader->info.uses_instanceid) || legacy_vs_prim_id)
495 return 2;
496 else if (is_ls || shader->info.uses_instanceid)
497 return 1;
498 else
499 return 0;
500 }
501
502 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
503 {
504 struct si_pm4_state *pm4;
505 uint64_t va;
506
507 assert(sscreen->info.chip_class <= GFX8);
508
509 pm4 = si_get_shader_pm4_state(shader);
510 if (!pm4)
511 return;
512
513 va = shader->bo->gpu_address;
514 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
515
516 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
517 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
518
519 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
520 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
521 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen, shader, false)) |
522 S_00B528_DX10_CLAMP(1) |
523 S_00B528_FLOAT_MODE(shader->config.float_mode);
524 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR)) |
525 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
526 }
527
528 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
529 {
530 struct si_pm4_state *pm4;
531 uint64_t va;
532
533 pm4 = si_get_shader_pm4_state(shader);
534 if (!pm4)
535 return;
536
537 va = shader->bo->gpu_address;
538 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
539
540 if (sscreen->info.chip_class >= GFX9) {
541 if (sscreen->info.chip_class >= GFX10) {
542 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
543 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
544 } else {
545 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
546 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
547 }
548
549 unsigned num_user_sgprs =
550 si_get_num_vs_user_sgprs(shader, GFX9_TCS_NUM_USER_SGPR);
551
552 shader->config.rsrc2 =
553 S_00B42C_USER_SGPR(num_user_sgprs) |
554 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
555
556 if (sscreen->info.chip_class >= GFX10)
557 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
558 else
559 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
560 } else {
561 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
562 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
563
564 shader->config.rsrc2 =
565 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
566 S_00B42C_OC_LDS_EN(1) |
567 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
568 }
569
570 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
571 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
572 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
573 (sscreen->info.chip_class <= GFX9 ?
574 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
575 S_00B428_DX10_CLAMP(1) |
576 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
577 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
578 S_00B428_FLOAT_MODE(shader->config.float_mode) |
579 S_00B428_LS_VGPR_COMP_CNT(sscreen->info.chip_class >= GFX9 ?
580 si_get_vs_vgpr_comp_cnt(sscreen, shader, false) : 0));
581
582 if (sscreen->info.chip_class <= GFX8) {
583 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
584 shader->config.rsrc2);
585 }
586 }
587
588 static void si_emit_shader_es(struct si_context *sctx)
589 {
590 struct si_shader *shader = sctx->queued.named.es->shader;
591 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
592
593 if (!shader)
594 return;
595
596 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
597 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
598 shader->selector->esgs_itemsize / 4);
599
600 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
601 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
602 SI_TRACKED_VGT_TF_PARAM,
603 shader->vgt_tf_param);
604
605 if (shader->vgt_vertex_reuse_block_cntl)
606 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
607 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
608 shader->vgt_vertex_reuse_block_cntl);
609
610 if (initial_cdw != sctx->gfx_cs->current.cdw)
611 sctx->context_roll = true;
612 }
613
614 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
615 {
616 struct si_pm4_state *pm4;
617 unsigned num_user_sgprs;
618 unsigned vgpr_comp_cnt;
619 uint64_t va;
620 unsigned oc_lds_en;
621
622 assert(sscreen->info.chip_class <= GFX8);
623
624 pm4 = si_get_shader_pm4_state(shader);
625 if (!pm4)
626 return;
627
628 pm4->atom.emit = si_emit_shader_es;
629 va = shader->bo->gpu_address;
630 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
631
632 if (shader->selector->type == PIPE_SHADER_VERTEX) {
633 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
634 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
635 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
636 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
637 num_user_sgprs = SI_TES_NUM_USER_SGPR;
638 } else
639 unreachable("invalid shader selector type");
640
641 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
642
643 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
644 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
645 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
646 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
647 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
648 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
649 S_00B328_DX10_CLAMP(1) |
650 S_00B328_FLOAT_MODE(shader->config.float_mode));
651 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
652 S_00B32C_USER_SGPR(num_user_sgprs) |
653 S_00B32C_OC_LDS_EN(oc_lds_en) |
654 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
655
656 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
657 si_set_tesseval_regs(sscreen, shader->selector, pm4);
658
659 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
660 }
661
662 void gfx9_get_gs_info(struct si_shader_selector *es,
663 struct si_shader_selector *gs,
664 struct gfx9_gs_info *out)
665 {
666 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
667 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
668 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
669 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
670
671 /* All these are in dwords: */
672 /* We can't allow using the whole LDS, because GS waves compete with
673 * other shader stages for LDS space. */
674 const unsigned max_lds_size = 8 * 1024;
675 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
676 unsigned esgs_lds_size;
677
678 /* All these are per subgroup: */
679 const unsigned max_out_prims = 32 * 1024;
680 const unsigned max_es_verts = 255;
681 const unsigned ideal_gs_prims = 64;
682 unsigned max_gs_prims, gs_prims;
683 unsigned min_es_verts, es_verts, worst_case_es_verts;
684
685 if (uses_adjacency || gs_num_invocations > 1)
686 max_gs_prims = 127 / gs_num_invocations;
687 else
688 max_gs_prims = 255;
689
690 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
691 * Make sure we don't go over the maximum value.
692 */
693 if (gs->gs_max_out_vertices > 0) {
694 max_gs_prims = MIN2(max_gs_prims,
695 max_out_prims /
696 (gs->gs_max_out_vertices * gs_num_invocations));
697 }
698 assert(max_gs_prims > 0);
699
700 /* If the primitive has adjacency, halve the number of vertices
701 * that will be reused in multiple primitives.
702 */
703 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
704
705 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
706 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
707
708 /* Compute ESGS LDS size based on the worst case number of ES vertices
709 * needed to create the target number of GS prims per subgroup.
710 */
711 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
712
713 /* If total LDS usage is too big, refactor partitions based on ratio
714 * of ESGS item sizes.
715 */
716 if (esgs_lds_size > max_lds_size) {
717 /* Our target GS Prims Per Subgroup was too large. Calculate
718 * the maximum number of GS Prims Per Subgroup that will fit
719 * into LDS, capped by the maximum that the hardware can support.
720 */
721 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
722 max_gs_prims);
723 assert(gs_prims > 0);
724 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
725 max_es_verts);
726
727 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
728 assert(esgs_lds_size <= max_lds_size);
729 }
730
731 /* Now calculate remaining ESGS information. */
732 if (esgs_lds_size)
733 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
734 else
735 es_verts = max_es_verts;
736
737 /* Vertices for adjacency primitives are not always reused, so restore
738 * it for ES_VERTS_PER_SUBGRP.
739 */
740 min_es_verts = gs->gs_input_verts_per_prim;
741
742 /* For normal primitives, the VGT only checks if they are past the ES
743 * verts per subgroup after allocating a full GS primitive and if they
744 * are, kick off a new subgroup. But if those additional ES verts are
745 * unique (e.g. not reused) we need to make sure there is enough LDS
746 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
747 */
748 es_verts -= min_es_verts - 1;
749
750 out->es_verts_per_subgroup = es_verts;
751 out->gs_prims_per_subgroup = gs_prims;
752 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
753 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
754 gs->gs_max_out_vertices;
755 out->esgs_ring_size = 4 * esgs_lds_size;
756
757 assert(out->max_prims_per_subgroup <= max_out_prims);
758 }
759
760 static void si_emit_shader_gs(struct si_context *sctx)
761 {
762 struct si_shader *shader = sctx->queued.named.gs->shader;
763 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
764
765 if (!shader)
766 return;
767
768 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
769 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
770 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
771 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
772 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
773 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
774 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
775
776 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
777 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
778 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
779 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
780
781 /* R_028B38_VGT_GS_MAX_VERT_OUT */
782 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
783 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
784 shader->ctx_reg.gs.vgt_gs_max_vert_out);
785
786 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
787 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
788 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
789 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
790 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
791 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
792 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
793 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
794
795 /* R_028B90_VGT_GS_INSTANCE_CNT */
796 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
797 SI_TRACKED_VGT_GS_INSTANCE_CNT,
798 shader->ctx_reg.gs.vgt_gs_instance_cnt);
799
800 if (sctx->chip_class >= GFX9) {
801 /* R_028A44_VGT_GS_ONCHIP_CNTL */
802 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
803 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
804 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
805 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
806 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
807 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
808 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
809 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
810 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
811 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
812 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
813
814 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
815 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
816 SI_TRACKED_VGT_TF_PARAM,
817 shader->vgt_tf_param);
818 if (shader->vgt_vertex_reuse_block_cntl)
819 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
820 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
821 shader->vgt_vertex_reuse_block_cntl);
822 }
823
824 if (initial_cdw != sctx->gfx_cs->current.cdw)
825 sctx->context_roll = true;
826 }
827
828 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
829 {
830 struct si_shader_selector *sel = shader->selector;
831 const ubyte *num_components = sel->info.num_stream_output_components;
832 unsigned gs_num_invocations = sel->gs_num_invocations;
833 struct si_pm4_state *pm4;
834 uint64_t va;
835 unsigned max_stream = sel->max_gs_stream;
836 unsigned offset;
837
838 pm4 = si_get_shader_pm4_state(shader);
839 if (!pm4)
840 return;
841
842 pm4->atom.emit = si_emit_shader_gs;
843
844 offset = num_components[0] * sel->gs_max_out_vertices;
845 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
846
847 if (max_stream >= 1)
848 offset += num_components[1] * sel->gs_max_out_vertices;
849 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
850
851 if (max_stream >= 2)
852 offset += num_components[2] * sel->gs_max_out_vertices;
853 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
854
855 if (max_stream >= 3)
856 offset += num_components[3] * sel->gs_max_out_vertices;
857 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
858
859 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
860 assert(offset < (1 << 15));
861
862 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
863
864 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
865 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
866 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
867 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
868
869 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
870 S_028B90_ENABLE(gs_num_invocations > 0);
871
872 va = shader->bo->gpu_address;
873 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
874
875 if (sscreen->info.chip_class >= GFX9) {
876 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
877 unsigned es_type = shader->key.part.gs.es->type;
878 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
879
880 if (es_type == PIPE_SHADER_VERTEX) {
881 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
882 } else if (es_type == PIPE_SHADER_TESS_EVAL)
883 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
884 else
885 unreachable("invalid shader selector type");
886
887 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
888 * VGPR[0:4] are always loaded.
889 */
890 if (sel->info.uses_invocationid)
891 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
892 else if (sel->info.uses_primid)
893 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
894 else if (input_prim >= PIPE_PRIM_TRIANGLES)
895 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
896 else
897 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
898
899 unsigned num_user_sgprs;
900 if (es_type == PIPE_SHADER_VERTEX)
901 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
902 else
903 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
904
905 if (sscreen->info.chip_class >= GFX10) {
906 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
907 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
908 } else {
909 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
910 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
911 }
912
913 uint32_t rsrc1 =
914 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
915 S_00B228_DX10_CLAMP(1) |
916 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
917 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
918 S_00B228_FLOAT_MODE(shader->config.float_mode) |
919 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
920 uint32_t rsrc2 =
921 S_00B22C_USER_SGPR(num_user_sgprs) |
922 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
923 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
924 S_00B22C_LDS_SIZE(shader->config.lds_size) |
925 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
926
927 if (sscreen->info.chip_class >= GFX10) {
928 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
929 } else {
930 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
931 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
932 }
933
934 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
935 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
936
937 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
938 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
939 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
940 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
941 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
942 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
943 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
944 shader->key.part.gs.es->esgs_itemsize / 4;
945
946 if (es_type == PIPE_SHADER_TESS_EVAL)
947 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
948
949 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
950 NULL, pm4);
951 } else {
952 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
953 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
954
955 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
956 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
957 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
958 S_00B228_DX10_CLAMP(1) |
959 S_00B228_FLOAT_MODE(shader->config.float_mode));
960 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
961 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
962 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
963 }
964 }
965
966 /* Common tail code for NGG primitive shaders. */
967 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
968 struct si_shader *shader,
969 unsigned initial_cdw)
970 {
971 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
972 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
973 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
974 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
975 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
976 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
977 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
978 SI_TRACKED_VGT_PRIMITIVEID_EN,
979 shader->ctx_reg.ngg.vgt_primitiveid_en);
980 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
981 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
982 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
983 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
984 SI_TRACKED_VGT_GS_INSTANCE_CNT,
985 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
986 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
987 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
988 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
989 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
990 SI_TRACKED_SPI_VS_OUT_CONFIG,
991 shader->ctx_reg.ngg.spi_vs_out_config);
992 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
993 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
994 shader->ctx_reg.ngg.spi_shader_idx_format,
995 shader->ctx_reg.ngg.spi_shader_pos_format);
996 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
997 SI_TRACKED_PA_CL_VTE_CNTL,
998 shader->ctx_reg.ngg.pa_cl_vte_cntl);
999 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
1000 SI_TRACKED_PA_CL_NGG_CNTL,
1001 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
1002
1003 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1004 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1005 shader->pa_cl_vs_out_cntl,
1006 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1007
1008 if (initial_cdw != sctx->gfx_cs->current.cdw)
1009 sctx->context_roll = true;
1010 }
1011
1012 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
1013 {
1014 struct si_shader *shader = sctx->queued.named.gs->shader;
1015 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1016
1017 if (!shader)
1018 return;
1019
1020 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1021 }
1022
1023 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1024 {
1025 struct si_shader *shader = sctx->queued.named.gs->shader;
1026 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1027
1028 if (!shader)
1029 return;
1030
1031 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1032 SI_TRACKED_VGT_TF_PARAM,
1033 shader->vgt_tf_param);
1034
1035 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1036 }
1037
1038 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1039 {
1040 struct si_shader *shader = sctx->queued.named.gs->shader;
1041 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1042
1043 if (!shader)
1044 return;
1045
1046 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1047 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1048 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1049
1050 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1051 }
1052
1053 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1054 {
1055 struct si_shader *shader = sctx->queued.named.gs->shader;
1056 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1057
1058 if (!shader)
1059 return;
1060
1061 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1062 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1063 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1064 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1065 SI_TRACKED_VGT_TF_PARAM,
1066 shader->vgt_tf_param);
1067
1068 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1069 }
1070
1071 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1072 {
1073 if (gs->type == PIPE_SHADER_GEOMETRY)
1074 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1075
1076 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1077 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1078 return PIPE_PRIM_POINTS;
1079 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1080 return PIPE_PRIM_LINES;
1081 return PIPE_PRIM_TRIANGLES;
1082 }
1083
1084 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1085 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1086 }
1087
1088 static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel, bool ngg)
1089 {
1090 bool misc_vec_ena =
1091 sel->info.writes_psize || (sel->info.writes_edgeflag && !ngg) ||
1092 sel->info.writes_layer || sel->info.writes_viewport_index;
1093 return S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
1094 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag && !ngg) |
1095 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
1096 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
1097 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1098 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
1099 }
1100
1101 /**
1102 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1103 * in NGG mode.
1104 */
1105 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1106 {
1107 const struct si_shader_selector *gs_sel = shader->selector;
1108 const struct si_shader_info *gs_info = &gs_sel->info;
1109 enum pipe_shader_type gs_type = shader->selector->type;
1110 const struct si_shader_selector *es_sel =
1111 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1112 const struct si_shader_info *es_info = &es_sel->info;
1113 enum pipe_shader_type es_type = es_sel->type;
1114 unsigned num_user_sgprs;
1115 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1116 uint64_t va;
1117 unsigned window_space =
1118 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1119 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1120 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1121 unsigned input_prim = si_get_input_prim(gs_sel);
1122 bool break_wave_at_eoi = false;
1123 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1124 if (!pm4)
1125 return;
1126
1127 if (es_type == PIPE_SHADER_TESS_EVAL) {
1128 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1129 : gfx10_emit_shader_ngg_tess_nogs;
1130 } else {
1131 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1132 : gfx10_emit_shader_ngg_notess_nogs;
1133 }
1134
1135 va = shader->bo->gpu_address;
1136 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1137
1138 if (es_type == PIPE_SHADER_VERTEX) {
1139 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
1140
1141 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1142 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1143 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1144 } else {
1145 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
1146 }
1147 } else {
1148 assert(es_type == PIPE_SHADER_TESS_EVAL);
1149 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1150 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1151
1152 if (es_enable_prim_id || gs_info->uses_primid)
1153 break_wave_at_eoi = true;
1154 }
1155
1156 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1157 * VGPR[0:4] are always loaded.
1158 *
1159 * Vertex shaders always need to load VGPR3, because they need to
1160 * pass edge flags for decomposed primitives (such as quads) to the PA
1161 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1162 */
1163 if (gs_info->uses_invocationid ||
1164 (gs_type == PIPE_SHADER_VERTEX && !gfx10_is_ngg_passthrough(shader)))
1165 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1166 else if ((gs_type == PIPE_SHADER_GEOMETRY && gs_info->uses_primid) ||
1167 (gs_type == PIPE_SHADER_VERTEX && shader->key.mono.u.vs_export_prim_id))
1168 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1169 else if (input_prim >= PIPE_PRIM_TRIANGLES && !gfx10_is_ngg_passthrough(shader))
1170 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1171 else
1172 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1173
1174 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1175 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1176 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1177 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1178 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1179 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1180 S_00B228_DX10_CLAMP(1) |
1181 S_00B228_MEM_ORDERED(1) |
1182 S_00B228_WGP_MODE(1) |
1183 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1184 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1185 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1186 S_00B22C_USER_SGPR(num_user_sgprs) |
1187 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1188 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1189 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1190 S_00B22C_LDS_SIZE(shader->config.lds_size));
1191
1192 nparams = MAX2(shader->info.nr_param_exports, 1);
1193 shader->ctx_reg.ngg.spi_vs_out_config =
1194 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1195 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1196
1197 shader->ctx_reg.ngg.spi_shader_idx_format =
1198 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1199 shader->ctx_reg.ngg.spi_shader_pos_format =
1200 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1201 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1202 V_02870C_SPI_SHADER_4COMP :
1203 V_02870C_SPI_SHADER_NONE) |
1204 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1205 V_02870C_SPI_SHADER_4COMP :
1206 V_02870C_SPI_SHADER_NONE) |
1207 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1208 V_02870C_SPI_SHADER_4COMP :
1209 V_02870C_SPI_SHADER_NONE);
1210
1211 shader->ctx_reg.ngg.vgt_primitiveid_en =
1212 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1213 S_028A84_NGG_DISABLE_PROVOK_REUSE(shader->key.mono.u.vs_export_prim_id ||
1214 gs_sel->info.writes_primid);
1215
1216 if (gs_type == PIPE_SHADER_GEOMETRY) {
1217 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1218 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1219 } else {
1220 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1221 }
1222
1223 if (es_type == PIPE_SHADER_TESS_EVAL)
1224 si_set_tesseval_regs(sscreen, es_sel, pm4);
1225
1226 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1227 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1228 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1229 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1230 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1231 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1232 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1233 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1234 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1235 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1236 S_028B90_CNT(gs_num_invocations) |
1237 S_028B90_ENABLE(gs_num_invocations > 1) |
1238 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1239 shader->ngg.max_vert_out_per_gs_instance);
1240
1241 /* Always output hw-generated edge flags and pass them via the prim
1242 * export to prevent drawing lines on internal edges of decomposed
1243 * primitives (such as quads) with polygon mode = lines. Only VS needs
1244 * this.
1245 */
1246 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1247 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1248 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(gs_sel, true);
1249
1250 shader->ge_cntl =
1251 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1252 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
1253 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1254
1255 /* Bug workaround for a possible hang with non-tessellation cases.
1256 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1257 *
1258 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1259 */
1260 if ((sscreen->info.family == CHIP_NAVI10 ||
1261 sscreen->info.family == CHIP_NAVI12 ||
1262 sscreen->info.family == CHIP_NAVI14) &&
1263 (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
1264 shader->ngg.hw_max_esverts != 256) {
1265 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1266
1267 if (shader->ngg.hw_max_esverts > 5) {
1268 shader->ge_cntl |=
1269 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1270 }
1271 }
1272
1273 if (window_space) {
1274 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1275 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1276 } else {
1277 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1278 S_028818_VTX_W0_FMT(1) |
1279 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1280 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1281 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1282 }
1283 }
1284
1285 static void si_emit_shader_vs(struct si_context *sctx)
1286 {
1287 struct si_shader *shader = sctx->queued.named.vs->shader;
1288 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1289
1290 if (!shader)
1291 return;
1292
1293 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1294 SI_TRACKED_VGT_GS_MODE,
1295 shader->ctx_reg.vs.vgt_gs_mode);
1296 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1297 SI_TRACKED_VGT_PRIMITIVEID_EN,
1298 shader->ctx_reg.vs.vgt_primitiveid_en);
1299
1300 if (sctx->chip_class <= GFX8) {
1301 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1302 SI_TRACKED_VGT_REUSE_OFF,
1303 shader->ctx_reg.vs.vgt_reuse_off);
1304 }
1305
1306 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1307 SI_TRACKED_SPI_VS_OUT_CONFIG,
1308 shader->ctx_reg.vs.spi_vs_out_config);
1309
1310 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1311 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1312 shader->ctx_reg.vs.spi_shader_pos_format);
1313
1314 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1315 SI_TRACKED_PA_CL_VTE_CNTL,
1316 shader->ctx_reg.vs.pa_cl_vte_cntl);
1317
1318 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1319 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1320 SI_TRACKED_VGT_TF_PARAM,
1321 shader->vgt_tf_param);
1322
1323 if (shader->vgt_vertex_reuse_block_cntl)
1324 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1325 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1326 shader->vgt_vertex_reuse_block_cntl);
1327
1328 /* Required programming for tessellation. (legacy pipeline only) */
1329 if (sctx->chip_class == GFX10 &&
1330 shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1331 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1332 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1333 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1334 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1335 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1336 }
1337
1338 if (sctx->chip_class >= GFX10) {
1339 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1340 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1341 shader->pa_cl_vs_out_cntl,
1342 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1343 }
1344
1345 if (initial_cdw != sctx->gfx_cs->current.cdw)
1346 sctx->context_roll = true;
1347 }
1348
1349 /**
1350 * Compute the state for \p shader, which will run as a vertex shader on the
1351 * hardware.
1352 *
1353 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1354 * is the copy shader.
1355 */
1356 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1357 struct si_shader_selector *gs)
1358 {
1359 const struct si_shader_info *info = &shader->selector->info;
1360 struct si_pm4_state *pm4;
1361 unsigned num_user_sgprs, vgpr_comp_cnt;
1362 uint64_t va;
1363 unsigned nparams, oc_lds_en;
1364 unsigned window_space =
1365 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1366 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1367
1368 pm4 = si_get_shader_pm4_state(shader);
1369 if (!pm4)
1370 return;
1371
1372 pm4->atom.emit = si_emit_shader_vs;
1373
1374 /* We always write VGT_GS_MODE in the VS state, because every switch
1375 * between different shader pipelines involving a different GS or no
1376 * GS at all involves a switch of the VS (different GS use different
1377 * copy shaders). On the other hand, when the API switches from a GS to
1378 * no GS and then back to the same GS used originally, the GS state is
1379 * not sent again.
1380 */
1381 if (!gs) {
1382 unsigned mode = V_028A40_GS_OFF;
1383
1384 /* PrimID needs GS scenario A. */
1385 if (enable_prim_id)
1386 mode = V_028A40_GS_SCENARIO_A;
1387
1388 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1389 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1390 } else {
1391 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1392 sscreen->info.chip_class);
1393 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1394 }
1395
1396 if (sscreen->info.chip_class <= GFX8) {
1397 /* Reuse needs to be set off if we write oViewport. */
1398 shader->ctx_reg.vs.vgt_reuse_off =
1399 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1400 }
1401
1402 va = shader->bo->gpu_address;
1403 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1404
1405 if (gs) {
1406 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1407 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1408 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1409 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
1410
1411 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1412 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1413 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1414 } else {
1415 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
1416 }
1417 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1418 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1419 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1420 } else
1421 unreachable("invalid shader selector type");
1422
1423 /* VS is required to export at least one param. */
1424 nparams = MAX2(shader->info.nr_param_exports, 1);
1425 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1426
1427 if (sscreen->info.chip_class >= GFX10) {
1428 shader->ctx_reg.vs.spi_vs_out_config |=
1429 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1430 }
1431
1432 shader->ctx_reg.vs.spi_shader_pos_format =
1433 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1434 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1435 V_02870C_SPI_SHADER_4COMP :
1436 V_02870C_SPI_SHADER_NONE) |
1437 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1438 V_02870C_SPI_SHADER_4COMP :
1439 V_02870C_SPI_SHADER_NONE) |
1440 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1441 V_02870C_SPI_SHADER_4COMP :
1442 V_02870C_SPI_SHADER_NONE);
1443 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, false);
1444
1445 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1446
1447 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1448 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1449
1450 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1451 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1452 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1453 S_00B128_DX10_CLAMP(1) |
1454 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1455 S_00B128_FLOAT_MODE(shader->config.float_mode);
1456 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1457 S_00B12C_OC_LDS_EN(oc_lds_en) |
1458 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1459
1460 if (sscreen->info.chip_class >= GFX10)
1461 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
1462 else if (sscreen->info.chip_class == GFX9)
1463 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
1464
1465 if (sscreen->info.chip_class <= GFX9)
1466 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1467
1468 if (!sscreen->use_ngg_streamout) {
1469 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1470 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1471 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1472 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1473 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1474 }
1475
1476 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1477 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1478
1479 if (window_space)
1480 shader->ctx_reg.vs.pa_cl_vte_cntl =
1481 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1482 else
1483 shader->ctx_reg.vs.pa_cl_vte_cntl =
1484 S_028818_VTX_W0_FMT(1) |
1485 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1486 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1487 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1488
1489 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1490 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1491
1492 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1493 }
1494
1495 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1496 {
1497 struct si_shader_info *info = &ps->selector->info;
1498 unsigned num_colors = !!(info->colors_read & 0x0f) +
1499 !!(info->colors_read & 0xf0);
1500 unsigned num_interp = ps->selector->info.num_inputs +
1501 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1502
1503 assert(num_interp <= 32);
1504 return MIN2(num_interp, 32);
1505 }
1506
1507 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1508 {
1509 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1510 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1511
1512 /* If the i-th target format is set, all previous target formats must
1513 * be non-zero to avoid hangs.
1514 */
1515 for (i = 0; i < num_targets; i++)
1516 if (!(value & (0xf << (i * 4))))
1517 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1518
1519 return value;
1520 }
1521
1522 static void si_emit_shader_ps(struct si_context *sctx)
1523 {
1524 struct si_shader *shader = sctx->queued.named.ps->shader;
1525 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1526
1527 if (!shader)
1528 return;
1529
1530 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1531 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1532 SI_TRACKED_SPI_PS_INPUT_ENA,
1533 shader->ctx_reg.ps.spi_ps_input_ena,
1534 shader->ctx_reg.ps.spi_ps_input_addr);
1535
1536 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1537 SI_TRACKED_SPI_BARYC_CNTL,
1538 shader->ctx_reg.ps.spi_baryc_cntl);
1539 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1540 SI_TRACKED_SPI_PS_IN_CONTROL,
1541 shader->ctx_reg.ps.spi_ps_in_control);
1542
1543 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1544 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1545 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1546 shader->ctx_reg.ps.spi_shader_z_format,
1547 shader->ctx_reg.ps.spi_shader_col_format);
1548
1549 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1550 SI_TRACKED_CB_SHADER_MASK,
1551 shader->ctx_reg.ps.cb_shader_mask);
1552
1553 if (initial_cdw != sctx->gfx_cs->current.cdw)
1554 sctx->context_roll = true;
1555 }
1556
1557 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1558 {
1559 struct si_shader_info *info = &shader->selector->info;
1560 struct si_pm4_state *pm4;
1561 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1562 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1563 uint64_t va;
1564 unsigned input_ena = shader->config.spi_ps_input_ena;
1565
1566 /* we need to enable at least one of them, otherwise we hang the GPU */
1567 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1568 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1569 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1570 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1571 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1572 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1573 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1574 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1575 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1576 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1577 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1578 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1579 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1580 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1581
1582 /* Validate interpolation optimization flags (read as implications). */
1583 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1584 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1585 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1586 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1587 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1588 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1589 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1590 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1591 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1592 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1593 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1594 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1595 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1596 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1597 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1598 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1599 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1600 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1601
1602 /* Validate cases when the optimizations are off (read as implications). */
1603 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1604 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1605 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1606 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1607 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1608 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1609
1610 pm4 = si_get_shader_pm4_state(shader);
1611 if (!pm4)
1612 return;
1613
1614 pm4->atom.emit = si_emit_shader_ps;
1615
1616 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1617 * Possible vaules:
1618 * 0 -> Position = pixel center
1619 * 1 -> Position = pixel centroid
1620 * 2 -> Position = at sample position
1621 *
1622 * From GLSL 4.5 specification, section 7.1:
1623 * "The variable gl_FragCoord is available as an input variable from
1624 * within fragment shaders and it holds the window relative coordinates
1625 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1626 * value can be for any location within the pixel, or one of the
1627 * fragment samples. The use of centroid does not further restrict
1628 * this value to be inside the current primitive."
1629 *
1630 * Meaning that centroid has no effect and we can return anything within
1631 * the pixel. Thus, return the value at sample position, because that's
1632 * the most accurate one shaders can get.
1633 */
1634 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1635
1636 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1637 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1638 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1639
1640 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1641 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1642
1643 /* Ensure that some export memory is always allocated, for two reasons:
1644 *
1645 * 1) Correctness: The hardware ignores the EXEC mask if no export
1646 * memory is allocated, so KILL and alpha test do not work correctly
1647 * without this.
1648 * 2) Performance: Every shader needs at least a NULL export, even when
1649 * it writes no color/depth output. The NULL export instruction
1650 * stalls without this setting.
1651 *
1652 * Don't add this to CB_SHADER_MASK.
1653 *
1654 * GFX10 supports pixel shaders without exports by setting both
1655 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1656 * instructions if any are present.
1657 */
1658 if ((sscreen->info.chip_class <= GFX9 ||
1659 info->uses_kill ||
1660 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1661 !spi_shader_col_format &&
1662 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1663 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1664
1665 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1666 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1667
1668 /* Set interpolation controls. */
1669 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1670 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1671
1672 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1673 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1674 shader->ctx_reg.ps.spi_shader_z_format =
1675 ac_get_spi_shader_z_format(info->writes_z,
1676 info->writes_stencil,
1677 info->writes_samplemask);
1678 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1679 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1680
1681 va = shader->bo->gpu_address;
1682 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1683 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1684 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1685
1686 uint32_t rsrc1 =
1687 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1688 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1689 S_00B028_DX10_CLAMP(1) |
1690 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1691 S_00B028_FLOAT_MODE(shader->config.float_mode);
1692
1693 if (sscreen->info.chip_class < GFX10) {
1694 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1695 }
1696
1697 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1698 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1699 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1700 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1701 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1702 }
1703
1704 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1705 struct si_shader *shader)
1706 {
1707 switch (shader->selector->type) {
1708 case PIPE_SHADER_VERTEX:
1709 if (shader->key.as_ls)
1710 si_shader_ls(sscreen, shader);
1711 else if (shader->key.as_es)
1712 si_shader_es(sscreen, shader);
1713 else if (shader->key.as_ngg)
1714 gfx10_shader_ngg(sscreen, shader);
1715 else
1716 si_shader_vs(sscreen, shader, NULL);
1717 break;
1718 case PIPE_SHADER_TESS_CTRL:
1719 si_shader_hs(sscreen, shader);
1720 break;
1721 case PIPE_SHADER_TESS_EVAL:
1722 if (shader->key.as_es)
1723 si_shader_es(sscreen, shader);
1724 else if (shader->key.as_ngg)
1725 gfx10_shader_ngg(sscreen, shader);
1726 else
1727 si_shader_vs(sscreen, shader, NULL);
1728 break;
1729 case PIPE_SHADER_GEOMETRY:
1730 if (shader->key.as_ngg)
1731 gfx10_shader_ngg(sscreen, shader);
1732 else
1733 si_shader_gs(sscreen, shader);
1734 break;
1735 case PIPE_SHADER_FRAGMENT:
1736 si_shader_ps(sscreen, shader);
1737 break;
1738 default:
1739 assert(0);
1740 }
1741 }
1742
1743 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1744 {
1745 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1746 return sctx->queued.named.dsa->alpha_func;
1747 }
1748
1749 void si_shader_selector_key_vs(struct si_context *sctx,
1750 struct si_shader_selector *vs,
1751 struct si_shader_key *key,
1752 struct si_vs_prolog_bits *prolog_key)
1753 {
1754 if (!sctx->vertex_elements ||
1755 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
1756 return;
1757
1758 struct si_vertex_elements *elts = sctx->vertex_elements;
1759
1760 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1761 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1762 prolog_key->unpack_instance_id_from_vertex_id =
1763 sctx->prim_discard_cs_instancing;
1764
1765 /* Prefer a monolithic shader to allow scheduling divisions around
1766 * VBO loads. */
1767 if (prolog_key->instance_divisor_is_fetched)
1768 key->opt.prefer_mono = 1;
1769
1770 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1771 unsigned count_mask = (1 << count) - 1;
1772 unsigned fix = elts->fix_fetch_always & count_mask;
1773 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1774
1775 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1776 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1777 while (mask) {
1778 unsigned i = u_bit_scan(&mask);
1779 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1780 unsigned vbidx = elts->vertex_buffer_index[i];
1781 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1782 unsigned align_mask = (1 << log_hw_load_size) - 1;
1783 if (vb->buffer_offset & align_mask ||
1784 vb->stride & align_mask) {
1785 fix |= 1 << i;
1786 opencode |= 1 << i;
1787 }
1788 }
1789 }
1790
1791 while (fix) {
1792 unsigned i = u_bit_scan(&fix);
1793 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1794 }
1795 key->mono.vs_fetch_opencode = opencode;
1796 }
1797
1798 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1799 struct si_shader_selector *vs,
1800 struct si_shader_key *key)
1801 {
1802 struct si_shader_selector *ps = sctx->ps_shader.cso;
1803
1804 key->opt.clip_disable =
1805 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1806 (vs->info.clipdist_writemask ||
1807 vs->info.writes_clipvertex) &&
1808 !vs->info.culldist_writemask;
1809
1810 /* Find out if PS is disabled. */
1811 bool ps_disabled = true;
1812 if (ps) {
1813 bool ps_modifies_zs = ps->info.uses_kill ||
1814 ps->info.writes_z ||
1815 ps->info.writes_stencil ||
1816 ps->info.writes_samplemask ||
1817 sctx->queued.named.blend->alpha_to_coverage ||
1818 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1819 unsigned ps_colormask = si_get_total_colormask(sctx);
1820
1821 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1822 (!ps_colormask &&
1823 !ps_modifies_zs &&
1824 !ps->info.writes_memory);
1825 }
1826
1827 /* Find out which VS outputs aren't used by the PS. */
1828 uint64_t outputs_written = vs->outputs_written_before_ps;
1829 uint64_t inputs_read = 0;
1830
1831 /* Ignore outputs that are not passed from VS to PS. */
1832 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1833 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1834 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1835
1836 if (!ps_disabled) {
1837 inputs_read = ps->inputs_read;
1838 }
1839
1840 uint64_t linked = outputs_written & inputs_read;
1841
1842 key->opt.kill_outputs = ~linked & outputs_written;
1843 }
1844
1845 /* Compute the key for the hw shader variant */
1846 static inline void si_shader_selector_key(struct pipe_context *ctx,
1847 struct si_shader_selector *sel,
1848 union si_vgt_stages_key stages_key,
1849 struct si_shader_key *key)
1850 {
1851 struct si_context *sctx = (struct si_context *)ctx;
1852
1853 memset(key, 0, sizeof(*key));
1854
1855 switch (sel->type) {
1856 case PIPE_SHADER_VERTEX:
1857 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1858
1859 if (sctx->tes_shader.cso)
1860 key->as_ls = 1;
1861 else if (sctx->gs_shader.cso) {
1862 key->as_es = 1;
1863 key->as_ngg = stages_key.u.ngg;
1864 } else {
1865 key->as_ngg = stages_key.u.ngg;
1866 si_shader_selector_key_hw_vs(sctx, sel, key);
1867
1868 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1869 key->mono.u.vs_export_prim_id = 1;
1870 }
1871 break;
1872 case PIPE_SHADER_TESS_CTRL:
1873 if (sctx->chip_class >= GFX9) {
1874 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1875 key, &key->part.tcs.ls_prolog);
1876 key->part.tcs.ls = sctx->vs_shader.cso;
1877
1878 /* When the LS VGPR fix is needed, monolithic shaders
1879 * can:
1880 * - avoid initializing EXEC in both the LS prolog
1881 * and the LS main part when !vs_needs_prolog
1882 * - remove the fixup for unused input VGPRs
1883 */
1884 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1885
1886 /* The LS output / HS input layout can be communicated
1887 * directly instead of via user SGPRs for merged LS-HS.
1888 * The LS VGPR fix prefers this too.
1889 */
1890 key->opt.prefer_mono = 1;
1891 }
1892
1893 key->part.tcs.epilog.prim_mode =
1894 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1895 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1896 sel->info.tessfactors_are_def_in_all_invocs;
1897 key->part.tcs.epilog.tes_reads_tess_factors =
1898 sctx->tes_shader.cso->info.reads_tess_factors;
1899
1900 if (sel == sctx->fixed_func_tcs_shader.cso)
1901 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1902 break;
1903 case PIPE_SHADER_TESS_EVAL:
1904 key->as_ngg = stages_key.u.ngg;
1905
1906 if (sctx->gs_shader.cso)
1907 key->as_es = 1;
1908 else {
1909 si_shader_selector_key_hw_vs(sctx, sel, key);
1910
1911 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1912 key->mono.u.vs_export_prim_id = 1;
1913 }
1914 break;
1915 case PIPE_SHADER_GEOMETRY:
1916 if (sctx->chip_class >= GFX9) {
1917 if (sctx->tes_shader.cso) {
1918 key->part.gs.es = sctx->tes_shader.cso;
1919 } else {
1920 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1921 key, &key->part.gs.vs_prolog);
1922 key->part.gs.es = sctx->vs_shader.cso;
1923 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1924 }
1925
1926 key->as_ngg = stages_key.u.ngg;
1927
1928 /* Merged ES-GS can have unbalanced wave usage.
1929 *
1930 * ES threads are per-vertex, while GS threads are
1931 * per-primitive. So without any amplification, there
1932 * are fewer GS threads than ES threads, which can result
1933 * in empty (no-op) GS waves. With too much amplification,
1934 * there are more GS threads than ES threads, which
1935 * can result in empty (no-op) ES waves.
1936 *
1937 * Non-monolithic shaders are implemented by setting EXEC
1938 * at the beginning of shader parts, and don't jump to
1939 * the end if EXEC is 0.
1940 *
1941 * Monolithic shaders use conditional blocks, so they can
1942 * jump and skip empty waves of ES or GS. So set this to
1943 * always use optimized variants, which are monolithic.
1944 */
1945 key->opt.prefer_mono = 1;
1946 }
1947 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1948 break;
1949 case PIPE_SHADER_FRAGMENT: {
1950 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1951 struct si_state_blend *blend = sctx->queued.named.blend;
1952
1953 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1954 sel->info.colors_written == 0x1)
1955 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1956
1957 /* Select the shader color format based on whether
1958 * blending or alpha are needed.
1959 */
1960 key->part.ps.epilog.spi_shader_col_format =
1961 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1962 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1963 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1964 sctx->framebuffer.spi_shader_col_format_blend) |
1965 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1966 sctx->framebuffer.spi_shader_col_format_alpha) |
1967 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1968 sctx->framebuffer.spi_shader_col_format);
1969 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1970
1971 /* The output for dual source blending should have
1972 * the same format as the first output.
1973 */
1974 if (blend->dual_src_blend) {
1975 key->part.ps.epilog.spi_shader_col_format |=
1976 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1977 }
1978
1979 /* If alpha-to-coverage is enabled, we have to export alpha
1980 * even if there is no color buffer.
1981 */
1982 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1983 blend->alpha_to_coverage)
1984 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1985
1986 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1987 * to the range supported by the type if a channel has less
1988 * than 16 bits and the export format is 16_ABGR.
1989 */
1990 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1991 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1992 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1993 }
1994
1995 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1996 if (!key->part.ps.epilog.last_cbuf) {
1997 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1998 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1999 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
2000 }
2001
2002 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
2003 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
2004
2005 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
2006 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
2007
2008 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
2009 rs->multisample_enable;
2010
2011 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
2012 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
2013 (is_line && rs->line_smooth)) &&
2014 sctx->framebuffer.nr_samples <= 1;
2015 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
2016
2017 if (sctx->ps_iter_samples > 1 &&
2018 sel->info.reads_samplemask) {
2019 key->part.ps.prolog.samplemask_log_ps_iter =
2020 util_logbase2(sctx->ps_iter_samples);
2021 }
2022
2023 if (rs->force_persample_interp &&
2024 rs->multisample_enable &&
2025 sctx->framebuffer.nr_samples > 1 &&
2026 sctx->ps_iter_samples > 1) {
2027 key->part.ps.prolog.force_persp_sample_interp =
2028 sel->info.uses_persp_center ||
2029 sel->info.uses_persp_centroid;
2030
2031 key->part.ps.prolog.force_linear_sample_interp =
2032 sel->info.uses_linear_center ||
2033 sel->info.uses_linear_centroid;
2034 } else if (rs->multisample_enable &&
2035 sctx->framebuffer.nr_samples > 1) {
2036 key->part.ps.prolog.bc_optimize_for_persp =
2037 sel->info.uses_persp_center &&
2038 sel->info.uses_persp_centroid;
2039 key->part.ps.prolog.bc_optimize_for_linear =
2040 sel->info.uses_linear_center &&
2041 sel->info.uses_linear_centroid;
2042 } else {
2043 /* Make sure SPI doesn't compute more than 1 pair
2044 * of (i,j), which is the optimization here. */
2045 key->part.ps.prolog.force_persp_center_interp =
2046 sel->info.uses_persp_center +
2047 sel->info.uses_persp_centroid +
2048 sel->info.uses_persp_sample > 1;
2049
2050 key->part.ps.prolog.force_linear_center_interp =
2051 sel->info.uses_linear_center +
2052 sel->info.uses_linear_centroid +
2053 sel->info.uses_linear_sample > 1;
2054
2055 if (sel->info.uses_persp_opcode_interp_sample ||
2056 sel->info.uses_linear_opcode_interp_sample)
2057 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2058 }
2059
2060 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2061
2062 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2063 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2064 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2065 struct pipe_resource *tex = cb0->texture;
2066
2067 /* 1D textures are allocated and used as 2D on GFX9. */
2068 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2069 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2070 (tex->target == PIPE_TEXTURE_1D ||
2071 tex->target == PIPE_TEXTURE_1D_ARRAY);
2072 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2073 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2074 tex->target == PIPE_TEXTURE_CUBE ||
2075 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2076 tex->target == PIPE_TEXTURE_3D;
2077 }
2078 break;
2079 }
2080 default:
2081 assert(0);
2082 }
2083
2084 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2085 memset(&key->opt, 0, sizeof(key->opt));
2086 }
2087
2088 static void si_build_shader_variant(struct si_shader *shader,
2089 int thread_index,
2090 bool low_priority)
2091 {
2092 struct si_shader_selector *sel = shader->selector;
2093 struct si_screen *sscreen = sel->screen;
2094 struct ac_llvm_compiler *compiler;
2095 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2096
2097 if (thread_index >= 0) {
2098 if (low_priority) {
2099 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2100 compiler = &sscreen->compiler_lowp[thread_index];
2101 } else {
2102 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2103 compiler = &sscreen->compiler[thread_index];
2104 }
2105 if (!debug->async)
2106 debug = NULL;
2107 } else {
2108 assert(!low_priority);
2109 compiler = shader->compiler_ctx_state.compiler;
2110 }
2111
2112 if (!compiler->passes)
2113 si_init_compiler(sscreen, compiler);
2114
2115 if (unlikely(!si_create_shader_variant(sscreen, compiler, shader, debug))) {
2116 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2117 sel->type);
2118 shader->compilation_failed = true;
2119 return;
2120 }
2121
2122 if (shader->compiler_ctx_state.is_debug_context) {
2123 FILE *f = open_memstream(&shader->shader_log,
2124 &shader->shader_log_size);
2125 if (f) {
2126 si_shader_dump(sscreen, shader, NULL, f, false);
2127 fclose(f);
2128 }
2129 }
2130
2131 si_shader_init_pm4_state(sscreen, shader);
2132 }
2133
2134 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2135 {
2136 struct si_shader *shader = (struct si_shader *)job;
2137
2138 assert(thread_index >= 0);
2139
2140 si_build_shader_variant(shader, thread_index, true);
2141 }
2142
2143 static const struct si_shader_key zeroed;
2144
2145 static bool si_check_missing_main_part(struct si_screen *sscreen,
2146 struct si_shader_selector *sel,
2147 struct si_compiler_ctx_state *compiler_state,
2148 struct si_shader_key *key)
2149 {
2150 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2151
2152 if (!*mainp) {
2153 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2154
2155 if (!main_part)
2156 return false;
2157
2158 /* We can leave the fence as permanently signaled because the
2159 * main part becomes visible globally only after it has been
2160 * compiled. */
2161 util_queue_fence_init(&main_part->ready);
2162
2163 main_part->selector = sel;
2164 main_part->key.as_es = key->as_es;
2165 main_part->key.as_ls = key->as_ls;
2166 main_part->key.as_ngg = key->as_ngg;
2167 main_part->is_monolithic = false;
2168
2169 if (si_compile_shader(sscreen, compiler_state->compiler,
2170 main_part, &compiler_state->debug) != 0) {
2171 FREE(main_part);
2172 return false;
2173 }
2174 *mainp = main_part;
2175 }
2176 return true;
2177 }
2178
2179 /**
2180 * Select a shader variant according to the shader key.
2181 *
2182 * \param optimized_or_none If the key describes an optimized shader variant and
2183 * the compilation isn't finished, don't select any
2184 * shader and return an error.
2185 */
2186 int si_shader_select_with_key(struct si_screen *sscreen,
2187 struct si_shader_ctx_state *state,
2188 struct si_compiler_ctx_state *compiler_state,
2189 struct si_shader_key *key,
2190 int thread_index,
2191 bool optimized_or_none)
2192 {
2193 struct si_shader_selector *sel = state->cso;
2194 struct si_shader_selector *previous_stage_sel = NULL;
2195 struct si_shader *current = state->current;
2196 struct si_shader *iter, *shader = NULL;
2197
2198 again:
2199 /* Check if we don't need to change anything.
2200 * This path is also used for most shaders that don't need multiple
2201 * variants, it will cost just a computation of the key and this
2202 * test. */
2203 if (likely(current &&
2204 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2205 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2206 if (current->is_optimized) {
2207 if (optimized_or_none)
2208 return -1;
2209
2210 memset(&key->opt, 0, sizeof(key->opt));
2211 goto current_not_ready;
2212 }
2213
2214 util_queue_fence_wait(&current->ready);
2215 }
2216
2217 return current->compilation_failed ? -1 : 0;
2218 }
2219 current_not_ready:
2220
2221 /* This must be done before the mutex is locked, because async GS
2222 * compilation calls this function too, and therefore must enter
2223 * the mutex first.
2224 *
2225 * Only wait if we are in a draw call. Don't wait if we are
2226 * in a compiler thread.
2227 */
2228 if (thread_index < 0)
2229 util_queue_fence_wait(&sel->ready);
2230
2231 simple_mtx_lock(&sel->mutex);
2232
2233 /* Find the shader variant. */
2234 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2235 /* Don't check the "current" shader. We checked it above. */
2236 if (current != iter &&
2237 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2238 simple_mtx_unlock(&sel->mutex);
2239
2240 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2241 /* If it's an optimized shader and its compilation has
2242 * been started but isn't done, use the unoptimized
2243 * shader so as not to cause a stall due to compilation.
2244 */
2245 if (iter->is_optimized) {
2246 if (optimized_or_none)
2247 return -1;
2248 memset(&key->opt, 0, sizeof(key->opt));
2249 goto again;
2250 }
2251
2252 util_queue_fence_wait(&iter->ready);
2253 }
2254
2255 if (iter->compilation_failed) {
2256 return -1; /* skip the draw call */
2257 }
2258
2259 state->current = iter;
2260 return 0;
2261 }
2262 }
2263
2264 /* Build a new shader. */
2265 shader = CALLOC_STRUCT(si_shader);
2266 if (!shader) {
2267 simple_mtx_unlock(&sel->mutex);
2268 return -ENOMEM;
2269 }
2270
2271 util_queue_fence_init(&shader->ready);
2272
2273 shader->selector = sel;
2274 shader->key = *key;
2275 shader->compiler_ctx_state = *compiler_state;
2276
2277 /* If this is a merged shader, get the first shader's selector. */
2278 if (sscreen->info.chip_class >= GFX9) {
2279 if (sel->type == PIPE_SHADER_TESS_CTRL)
2280 previous_stage_sel = key->part.tcs.ls;
2281 else if (sel->type == PIPE_SHADER_GEOMETRY)
2282 previous_stage_sel = key->part.gs.es;
2283
2284 /* We need to wait for the previous shader. */
2285 if (previous_stage_sel && thread_index < 0)
2286 util_queue_fence_wait(&previous_stage_sel->ready);
2287 }
2288
2289 bool is_pure_monolithic =
2290 sscreen->use_monolithic_shaders ||
2291 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2292
2293 /* Compile the main shader part if it doesn't exist. This can happen
2294 * if the initial guess was wrong.
2295 *
2296 * The prim discard CS doesn't need the main shader part.
2297 */
2298 if (!is_pure_monolithic &&
2299 !key->opt.vs_as_prim_discard_cs) {
2300 bool ok = true;
2301
2302 /* Make sure the main shader part is present. This is needed
2303 * for shaders that can be compiled as VS, LS, or ES, and only
2304 * one of them is compiled at creation.
2305 *
2306 * It is also needed for GS, which can be compiled as non-NGG
2307 * and NGG.
2308 *
2309 * For merged shaders, check that the starting shader's main
2310 * part is present.
2311 */
2312 if (previous_stage_sel) {
2313 struct si_shader_key shader1_key = zeroed;
2314
2315 if (sel->type == PIPE_SHADER_TESS_CTRL) {
2316 shader1_key.as_ls = 1;
2317 } else if (sel->type == PIPE_SHADER_GEOMETRY) {
2318 shader1_key.as_es = 1;
2319 shader1_key.as_ngg = key->as_ngg; /* for Wave32 vs Wave64 */
2320 } else {
2321 assert(0);
2322 }
2323
2324 simple_mtx_lock(&previous_stage_sel->mutex);
2325 ok = si_check_missing_main_part(sscreen,
2326 previous_stage_sel,
2327 compiler_state, &shader1_key);
2328 simple_mtx_unlock(&previous_stage_sel->mutex);
2329 }
2330
2331 if (ok) {
2332 ok = si_check_missing_main_part(sscreen, sel,
2333 compiler_state, key);
2334 }
2335
2336 if (!ok) {
2337 FREE(shader);
2338 simple_mtx_unlock(&sel->mutex);
2339 return -ENOMEM; /* skip the draw call */
2340 }
2341 }
2342
2343 /* Keep the reference to the 1st shader of merged shaders, so that
2344 * Gallium can't destroy it before we destroy the 2nd shader.
2345 *
2346 * Set sctx = NULL, because it's unused if we're not releasing
2347 * the shader, and we don't have any sctx here.
2348 */
2349 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2350 previous_stage_sel);
2351
2352 /* Monolithic-only shaders don't make a distinction between optimized
2353 * and unoptimized. */
2354 shader->is_monolithic =
2355 is_pure_monolithic ||
2356 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2357
2358 /* The prim discard CS is always optimized. */
2359 shader->is_optimized =
2360 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2361 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2362
2363 /* If it's an optimized shader, compile it asynchronously. */
2364 if (shader->is_optimized && thread_index < 0) {
2365 /* Compile it asynchronously. */
2366 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2367 shader, &shader->ready,
2368 si_build_shader_variant_low_priority, NULL,
2369 0);
2370
2371 /* Add only after the ready fence was reset, to guard against a
2372 * race with si_bind_XX_shader. */
2373 if (!sel->last_variant) {
2374 sel->first_variant = shader;
2375 sel->last_variant = shader;
2376 } else {
2377 sel->last_variant->next_variant = shader;
2378 sel->last_variant = shader;
2379 }
2380
2381 /* Use the default (unoptimized) shader for now. */
2382 memset(&key->opt, 0, sizeof(key->opt));
2383 simple_mtx_unlock(&sel->mutex);
2384
2385 if (sscreen->options.sync_compile)
2386 util_queue_fence_wait(&shader->ready);
2387
2388 if (optimized_or_none)
2389 return -1;
2390 goto again;
2391 }
2392
2393 /* Reset the fence before adding to the variant list. */
2394 util_queue_fence_reset(&shader->ready);
2395
2396 if (!sel->last_variant) {
2397 sel->first_variant = shader;
2398 sel->last_variant = shader;
2399 } else {
2400 sel->last_variant->next_variant = shader;
2401 sel->last_variant = shader;
2402 }
2403
2404 simple_mtx_unlock(&sel->mutex);
2405
2406 assert(!shader->is_optimized);
2407 si_build_shader_variant(shader, thread_index, false);
2408
2409 util_queue_fence_signal(&shader->ready);
2410
2411 if (!shader->compilation_failed)
2412 state->current = shader;
2413
2414 return shader->compilation_failed ? -1 : 0;
2415 }
2416
2417 static int si_shader_select(struct pipe_context *ctx,
2418 struct si_shader_ctx_state *state,
2419 union si_vgt_stages_key stages_key,
2420 struct si_compiler_ctx_state *compiler_state)
2421 {
2422 struct si_context *sctx = (struct si_context *)ctx;
2423 struct si_shader_key key;
2424
2425 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2426 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2427 &key, -1, false);
2428 }
2429
2430 static void si_parse_next_shader_property(const struct si_shader_info *info,
2431 bool streamout,
2432 struct si_shader_key *key)
2433 {
2434 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2435
2436 switch (info->processor) {
2437 case PIPE_SHADER_VERTEX:
2438 switch (next_shader) {
2439 case PIPE_SHADER_GEOMETRY:
2440 key->as_es = 1;
2441 break;
2442 case PIPE_SHADER_TESS_CTRL:
2443 case PIPE_SHADER_TESS_EVAL:
2444 key->as_ls = 1;
2445 break;
2446 default:
2447 /* If POSITION isn't written, it can only be a HW VS
2448 * if streamout is used. If streamout isn't used,
2449 * assume that it's a HW LS. (the next shader is TCS)
2450 * This heuristic is needed for separate shader objects.
2451 */
2452 if (!info->writes_position && !streamout)
2453 key->as_ls = 1;
2454 }
2455 break;
2456
2457 case PIPE_SHADER_TESS_EVAL:
2458 if (next_shader == PIPE_SHADER_GEOMETRY ||
2459 !info->writes_position)
2460 key->as_es = 1;
2461 break;
2462 }
2463 }
2464
2465 /**
2466 * Compile the main shader part or the monolithic shader as part of
2467 * si_shader_selector initialization. Since it can be done asynchronously,
2468 * there is no way to report compile failures to applications.
2469 */
2470 static void si_init_shader_selector_async(void *job, int thread_index)
2471 {
2472 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2473 struct si_screen *sscreen = sel->screen;
2474 struct ac_llvm_compiler *compiler;
2475 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2476
2477 assert(!debug->debug_message || debug->async);
2478 assert(thread_index >= 0);
2479 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2480 compiler = &sscreen->compiler[thread_index];
2481
2482 if (!compiler->passes)
2483 si_init_compiler(sscreen, compiler);
2484
2485 /* Serialize NIR to save memory. Monolithic shader variants
2486 * have to deserialize NIR before compilation.
2487 */
2488 if (sel->nir) {
2489 struct blob blob;
2490 size_t size;
2491
2492 blob_init(&blob);
2493 /* true = remove optional debugging data to increase
2494 * the likehood of getting more shader cache hits.
2495 * It also drops variable names, so we'll save more memory.
2496 */
2497 nir_serialize(&blob, sel->nir, true);
2498 blob_finish_get_buffer(&blob, &sel->nir_binary, &size);
2499 sel->nir_size = size;
2500 }
2501
2502 /* Compile the main shader part for use with a prolog and/or epilog.
2503 * If this fails, the driver will try to compile a monolithic shader
2504 * on demand.
2505 */
2506 if (!sscreen->use_monolithic_shaders) {
2507 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2508 unsigned char ir_sha1_cache_key[20];
2509
2510 if (!shader) {
2511 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2512 return;
2513 }
2514
2515 /* We can leave the fence signaled because use of the default
2516 * main part is guarded by the selector's ready fence. */
2517 util_queue_fence_init(&shader->ready);
2518
2519 shader->selector = sel;
2520 shader->is_monolithic = false;
2521 si_parse_next_shader_property(&sel->info,
2522 sel->so.num_outputs != 0,
2523 &shader->key);
2524
2525 if (sscreen->use_ngg &&
2526 (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
2527 ((sel->type == PIPE_SHADER_VERTEX && !shader->key.as_ls) ||
2528 sel->type == PIPE_SHADER_TESS_EVAL ||
2529 sel->type == PIPE_SHADER_GEOMETRY))
2530 shader->key.as_ngg = 1;
2531
2532 if (sel->nir) {
2533 si_get_ir_cache_key(sel, shader->key.as_ngg,
2534 shader->key.as_es, ir_sha1_cache_key);
2535 }
2536
2537 /* Try to load the shader from the shader cache. */
2538 simple_mtx_lock(&sscreen->shader_cache_mutex);
2539
2540 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
2541 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2542 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2543 } else {
2544 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2545
2546 /* Compile the shader if it hasn't been loaded from the cache. */
2547 if (si_compile_shader(sscreen, compiler, shader,
2548 debug) != 0) {
2549 FREE(shader);
2550 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2551 return;
2552 }
2553
2554 simple_mtx_lock(&sscreen->shader_cache_mutex);
2555 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
2556 shader, true);
2557 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2558 }
2559
2560 *si_get_main_shader_part(sel, &shader->key) = shader;
2561
2562 /* Unset "outputs_written" flags for outputs converted to
2563 * DEFAULT_VAL, so that later inter-shader optimizations don't
2564 * try to eliminate outputs that don't exist in the final
2565 * shader.
2566 *
2567 * This is only done if non-monolithic shaders are enabled.
2568 */
2569 if ((sel->type == PIPE_SHADER_VERTEX ||
2570 sel->type == PIPE_SHADER_TESS_EVAL) &&
2571 !shader->key.as_ls &&
2572 !shader->key.as_es) {
2573 unsigned i;
2574
2575 for (i = 0; i < sel->info.num_outputs; i++) {
2576 unsigned offset = shader->info.vs_output_param_offset[i];
2577
2578 if (offset <= AC_EXP_PARAM_OFFSET_31)
2579 continue;
2580
2581 unsigned name = sel->info.output_semantic_name[i];
2582 unsigned index = sel->info.output_semantic_index[i];
2583 unsigned id;
2584
2585 switch (name) {
2586 case TGSI_SEMANTIC_GENERIC:
2587 /* don't process indices the function can't handle */
2588 if (index >= SI_MAX_IO_GENERIC)
2589 break;
2590 /* fall through */
2591 default:
2592 id = si_shader_io_get_unique_index(name, index, true);
2593 sel->outputs_written_before_ps &= ~(1ull << id);
2594 break;
2595 case TGSI_SEMANTIC_POSITION: /* ignore these */
2596 case TGSI_SEMANTIC_PSIZE:
2597 case TGSI_SEMANTIC_CLIPVERTEX:
2598 case TGSI_SEMANTIC_EDGEFLAG:
2599 break;
2600 }
2601 }
2602 }
2603 }
2604
2605 /* The GS copy shader is always pre-compiled. */
2606 if (sel->type == PIPE_SHADER_GEOMETRY &&
2607 (!sscreen->use_ngg ||
2608 !sscreen->use_ngg_streamout || /* also for PRIMITIVES_GENERATED */
2609 sel->tess_turns_off_ngg)) {
2610 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2611 if (!sel->gs_copy_shader) {
2612 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2613 return;
2614 }
2615
2616 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2617 }
2618
2619 /* Free NIR. We only keep serialized NIR after this point. */
2620 if (sel->nir) {
2621 ralloc_free(sel->nir);
2622 sel->nir = NULL;
2623 }
2624 }
2625
2626 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2627 struct util_queue_fence *ready_fence,
2628 struct si_compiler_ctx_state *compiler_ctx_state,
2629 void *job, util_queue_execute_func execute)
2630 {
2631 util_queue_fence_init(ready_fence);
2632
2633 struct util_async_debug_callback async_debug;
2634 bool debug =
2635 (sctx->debug.debug_message && !sctx->debug.async) ||
2636 sctx->is_debug ||
2637 si_can_dump_shader(sctx->screen, processor);
2638
2639 if (debug) {
2640 u_async_debug_init(&async_debug);
2641 compiler_ctx_state->debug = async_debug.base;
2642 }
2643
2644 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2645 ready_fence, execute, NULL, 0);
2646
2647 if (debug) {
2648 util_queue_fence_wait(ready_fence);
2649 u_async_debug_drain(&async_debug, &sctx->debug);
2650 u_async_debug_cleanup(&async_debug);
2651 }
2652
2653 if (sctx->screen->options.sync_compile)
2654 util_queue_fence_wait(ready_fence);
2655 }
2656
2657 /* Return descriptor slot usage masks from the given shader info. */
2658 void si_get_active_slot_masks(const struct si_shader_info *info,
2659 uint32_t *const_and_shader_buffers,
2660 uint64_t *samplers_and_images)
2661 {
2662 unsigned start, num_shaderbufs, num_constbufs, num_images, num_msaa_images, num_samplers;
2663
2664 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2665 num_constbufs = util_last_bit(info->const_buffers_declared);
2666 /* two 8-byte images share one 16-byte slot */
2667 num_images = align(util_last_bit(info->images_declared), 2);
2668 num_msaa_images = align(util_last_bit(info->msaa_images_declared), 2);
2669 num_samplers = util_last_bit(info->samplers_declared);
2670
2671 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2672 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2673 *const_and_shader_buffers =
2674 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2675
2676 /* The layout is:
2677 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2678 * - image[last] ... image[0] go to [31-last .. 31]
2679 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2680 *
2681 * FMASKs for images are placed separately, because MSAA images are rare,
2682 * and so we can benefit from a better cache hit rate if we keep image
2683 * descriptors together.
2684 */
2685 if (num_msaa_images)
2686 num_images = SI_NUM_IMAGES + num_msaa_images; /* add FMASK descriptors */
2687
2688 start = si_get_image_slot(num_images - 1) / 2;
2689 *samplers_and_images =
2690 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2691 }
2692
2693 static void *si_create_shader_selector(struct pipe_context *ctx,
2694 const struct pipe_shader_state *state)
2695 {
2696 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2697 struct si_context *sctx = (struct si_context*)ctx;
2698 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2699 int i;
2700
2701 if (!sel)
2702 return NULL;
2703
2704 pipe_reference_init(&sel->reference, 1);
2705 sel->screen = sscreen;
2706 sel->compiler_ctx_state.debug = sctx->debug;
2707 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2708
2709 sel->so = state->stream_output;
2710
2711 if (state->type == PIPE_SHADER_IR_TGSI) {
2712 sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
2713 } else {
2714 assert(state->type == PIPE_SHADER_IR_NIR);
2715 sel->nir = state->ir.nir;
2716 }
2717
2718 si_nir_scan_shader(sel->nir, &sel->info);
2719 si_nir_adjust_driver_locations(sel->nir);
2720
2721 sel->type = sel->info.processor;
2722 p_atomic_inc(&sscreen->num_shaders_created);
2723 si_get_active_slot_masks(&sel->info,
2724 &sel->active_const_and_shader_buffers,
2725 &sel->active_samplers_and_images);
2726
2727 /* Record which streamout buffers are enabled. */
2728 for (i = 0; i < sel->so.num_outputs; i++) {
2729 sel->enabled_streamout_buffer_mask |=
2730 (1 << sel->so.output[i].output_buffer) <<
2731 (sel->so.output[i].stream * 4);
2732 }
2733
2734 sel->num_vs_inputs = sel->type == PIPE_SHADER_VERTEX &&
2735 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] ?
2736 sel->info.num_inputs : 0;
2737 sel->num_vbos_in_user_sgprs =
2738 MIN2(sel->num_vs_inputs, sscreen->num_vbos_in_user_sgprs);
2739
2740 /* The prolog is a no-op if there are no inputs. */
2741 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2742 sel->info.num_inputs &&
2743 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
2744
2745 sel->force_correct_derivs_after_kill =
2746 sel->type == PIPE_SHADER_FRAGMENT &&
2747 sel->info.uses_derivatives &&
2748 sel->info.uses_kill &&
2749 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2750
2751 sel->prim_discard_cs_allowed =
2752 sel->type == PIPE_SHADER_VERTEX &&
2753 !sel->info.uses_bindless_images &&
2754 !sel->info.uses_bindless_samplers &&
2755 !sel->info.writes_memory &&
2756 !sel->info.writes_viewport_index &&
2757 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2758 !sel->so.num_outputs;
2759
2760 switch (sel->type) {
2761 case PIPE_SHADER_GEOMETRY:
2762 sel->gs_output_prim =
2763 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2764
2765 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2766 sel->rast_prim = sel->gs_output_prim;
2767 if (util_rast_prim_is_triangles(sel->rast_prim))
2768 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2769
2770 sel->gs_max_out_vertices =
2771 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2772 sel->gs_num_invocations =
2773 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2774 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2775 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2776 sel->gs_max_out_vertices;
2777
2778 sel->max_gs_stream = 0;
2779 for (i = 0; i < sel->so.num_outputs; i++)
2780 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2781 sel->so.output[i].stream);
2782
2783 sel->gs_input_verts_per_prim =
2784 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2785
2786 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2787 sel->tess_turns_off_ngg =
2788 sscreen->info.chip_class == GFX10 &&
2789 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2790 break;
2791
2792 case PIPE_SHADER_TESS_CTRL:
2793 /* Always reserve space for these. */
2794 sel->patch_outputs_written |=
2795 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2796 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2797 /* fall through */
2798 case PIPE_SHADER_VERTEX:
2799 case PIPE_SHADER_TESS_EVAL:
2800 for (i = 0; i < sel->info.num_outputs; i++) {
2801 unsigned name = sel->info.output_semantic_name[i];
2802 unsigned index = sel->info.output_semantic_index[i];
2803
2804 switch (name) {
2805 case TGSI_SEMANTIC_TESSINNER:
2806 case TGSI_SEMANTIC_TESSOUTER:
2807 case TGSI_SEMANTIC_PATCH:
2808 sel->patch_outputs_written |=
2809 1ull << si_shader_io_get_unique_index_patch(name, index);
2810 break;
2811
2812 case TGSI_SEMANTIC_GENERIC:
2813 /* don't process indices the function can't handle */
2814 if (index >= SI_MAX_IO_GENERIC)
2815 break;
2816 /* fall through */
2817 default:
2818 sel->outputs_written |=
2819 1ull << si_shader_io_get_unique_index(name, index, false);
2820 sel->outputs_written_before_ps |=
2821 1ull << si_shader_io_get_unique_index(name, index, true);
2822 break;
2823 case TGSI_SEMANTIC_EDGEFLAG:
2824 break;
2825 }
2826 }
2827 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2828 sel->lshs_vertex_stride = sel->esgs_itemsize;
2829
2830 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2831 * will start on a different bank. (except for the maximum 32*16).
2832 */
2833 if (sel->lshs_vertex_stride < 32*16)
2834 sel->lshs_vertex_stride += 4;
2835
2836 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2837 * conflicts, i.e. each vertex will start at a different bank.
2838 */
2839 if (sctx->chip_class >= GFX9)
2840 sel->esgs_itemsize += 4;
2841
2842 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2843
2844 /* Only for TES: */
2845 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2846 sel->rast_prim = PIPE_PRIM_POINTS;
2847 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2848 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2849 else
2850 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2851 break;
2852
2853 case PIPE_SHADER_FRAGMENT:
2854 for (i = 0; i < sel->info.num_inputs; i++) {
2855 unsigned name = sel->info.input_semantic_name[i];
2856 unsigned index = sel->info.input_semantic_index[i];
2857
2858 switch (name) {
2859 case TGSI_SEMANTIC_GENERIC:
2860 /* don't process indices the function can't handle */
2861 if (index >= SI_MAX_IO_GENERIC)
2862 break;
2863 /* fall through */
2864 default:
2865 sel->inputs_read |=
2866 1ull << si_shader_io_get_unique_index(name, index, true);
2867 break;
2868 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2869 break;
2870 }
2871 }
2872
2873 for (i = 0; i < 8; i++)
2874 if (sel->info.colors_written & (1 << i))
2875 sel->colors_written_4bit |= 0xf << (4 * i);
2876
2877 for (i = 0; i < sel->info.num_inputs; i++) {
2878 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2879 int index = sel->info.input_semantic_index[i];
2880 sel->color_attr_index[index] = i;
2881 }
2882 }
2883 break;
2884 default:;
2885 }
2886
2887 /* PA_CL_VS_OUT_CNTL */
2888 if (sctx->chip_class <= GFX9)
2889 sel->pa_cl_vs_out_cntl = si_get_vs_out_cntl(sel, false);
2890
2891 sel->clipdist_mask = sel->info.writes_clipvertex ?
2892 SIX_BITS : sel->info.clipdist_writemask;
2893 sel->culldist_mask = sel->info.culldist_writemask <<
2894 sel->info.num_written_clipdistance;
2895
2896 /* DB_SHADER_CONTROL */
2897 sel->db_shader_control =
2898 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2899 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2900 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2901 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2902
2903 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2904 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2905 sel->db_shader_control |=
2906 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2907 break;
2908 case TGSI_FS_DEPTH_LAYOUT_LESS:
2909 sel->db_shader_control |=
2910 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2911 break;
2912 }
2913
2914 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2915 *
2916 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2917 * --|-----------|------------|------------|--------------------|-------------------|-------------
2918 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2919 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2920 * 2 | false | true | n/a | LateZ | 1 | 0
2921 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2922 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2923 *
2924 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2925 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2926 *
2927 * Don't use ReZ without profiling !!!
2928 *
2929 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2930 * shaders.
2931 */
2932 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2933 /* Cases 3, 4. */
2934 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2935 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2936 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2937 } else if (sel->info.writes_memory) {
2938 /* Case 2. */
2939 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2940 S_02880C_EXEC_ON_HIER_FAIL(1);
2941 } else {
2942 /* Case 1. */
2943 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2944 }
2945
2946 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
2947 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2948
2949 (void) simple_mtx_init(&sel->mutex, mtx_plain);
2950
2951 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2952 &sel->compiler_ctx_state, sel,
2953 si_init_shader_selector_async);
2954 return sel;
2955 }
2956
2957 static void si_update_streamout_state(struct si_context *sctx)
2958 {
2959 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2960
2961 if (!shader_with_so)
2962 return;
2963
2964 sctx->streamout.enabled_stream_buffers_mask =
2965 shader_with_so->enabled_streamout_buffer_mask;
2966 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2967 }
2968
2969 static void si_update_clip_regs(struct si_context *sctx,
2970 struct si_shader_selector *old_hw_vs,
2971 struct si_shader *old_hw_vs_variant,
2972 struct si_shader_selector *next_hw_vs,
2973 struct si_shader *next_hw_vs_variant)
2974 {
2975 if (next_hw_vs &&
2976 (!old_hw_vs ||
2977 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2978 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2979 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2980 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2981 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2982 !old_hw_vs_variant ||
2983 !next_hw_vs_variant ||
2984 old_hw_vs_variant->key.opt.clip_disable !=
2985 next_hw_vs_variant->key.opt.clip_disable))
2986 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2987 }
2988
2989 static void si_update_common_shader_state(struct si_context *sctx)
2990 {
2991 sctx->uses_bindless_samplers =
2992 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2993 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2994 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2995 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2996 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2997 sctx->uses_bindless_images =
2998 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2999 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
3000 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
3001 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
3002 si_shader_uses_bindless_images(sctx->tes_shader.cso);
3003 sctx->do_update_shaders = true;
3004 }
3005
3006 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
3007 {
3008 struct si_context *sctx = (struct si_context *)ctx;
3009 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3010 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3011 struct si_shader_selector *sel = state;
3012
3013 if (sctx->vs_shader.cso == sel)
3014 return;
3015
3016 sctx->vs_shader.cso = sel;
3017 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
3018 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;
3019
3020 if (si_update_ngg(sctx))
3021 si_shader_change_notify(sctx);
3022
3023 si_update_common_shader_state(sctx);
3024 si_update_vs_viewport_state(sctx);
3025 si_set_active_descriptors_for_shader(sctx, sel);
3026 si_update_streamout_state(sctx);
3027 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3028 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3029 }
3030
3031 static void si_update_tess_uses_prim_id(struct si_context *sctx)
3032 {
3033 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
3034 (sctx->tes_shader.cso &&
3035 sctx->tes_shader.cso->info.uses_primid) ||
3036 (sctx->tcs_shader.cso &&
3037 sctx->tcs_shader.cso->info.uses_primid) ||
3038 (sctx->gs_shader.cso &&
3039 sctx->gs_shader.cso->info.uses_primid) ||
3040 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
3041 sctx->ps_shader.cso->info.uses_primid);
3042 }
3043
3044 bool si_update_ngg(struct si_context *sctx)
3045 {
3046 if (!sctx->screen->use_ngg) {
3047 assert(!sctx->ngg);
3048 return false;
3049 }
3050
3051 bool new_ngg = true;
3052
3053 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
3054 sctx->gs_shader.cso->tess_turns_off_ngg) {
3055 new_ngg = false;
3056 } else if (!sctx->screen->use_ngg_streamout) {
3057 struct si_shader_selector *last = si_get_vs(sctx)->cso;
3058
3059 if ((last && last->so.num_outputs) ||
3060 sctx->streamout.prims_gen_query_enabled)
3061 new_ngg = false;
3062 }
3063
3064 if (new_ngg != sctx->ngg) {
3065 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3066 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3067 * pointers are set.
3068 */
3069 if ((sctx->family == CHIP_NAVI10 ||
3070 sctx->family == CHIP_NAVI12 ||
3071 sctx->family == CHIP_NAVI14) &&
3072 !new_ngg)
3073 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
3074
3075 sctx->ngg = new_ngg;
3076 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3077 return true;
3078 }
3079 return false;
3080 }
3081
3082 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3083 {
3084 struct si_context *sctx = (struct si_context *)ctx;
3085 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3086 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3087 struct si_shader_selector *sel = state;
3088 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3089 bool ngg_changed;
3090
3091 if (sctx->gs_shader.cso == sel)
3092 return;
3093
3094 sctx->gs_shader.cso = sel;
3095 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3096 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3097
3098 si_update_common_shader_state(sctx);
3099 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3100
3101 ngg_changed = si_update_ngg(sctx);
3102 if (ngg_changed || enable_changed)
3103 si_shader_change_notify(sctx);
3104 if (enable_changed) {
3105 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3106 si_update_tess_uses_prim_id(sctx);
3107 }
3108 si_update_vs_viewport_state(sctx);
3109 si_set_active_descriptors_for_shader(sctx, sel);
3110 si_update_streamout_state(sctx);
3111 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3112 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3113 }
3114
3115 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3116 {
3117 struct si_context *sctx = (struct si_context *)ctx;
3118 struct si_shader_selector *sel = state;
3119 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3120
3121 if (sctx->tcs_shader.cso == sel)
3122 return;
3123
3124 sctx->tcs_shader.cso = sel;
3125 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3126 si_update_tess_uses_prim_id(sctx);
3127
3128 si_update_common_shader_state(sctx);
3129
3130 if (enable_changed)
3131 sctx->last_tcs = NULL; /* invalidate derived tess state */
3132
3133 si_set_active_descriptors_for_shader(sctx, sel);
3134 }
3135
3136 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3137 {
3138 struct si_context *sctx = (struct si_context *)ctx;
3139 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3140 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3141 struct si_shader_selector *sel = state;
3142 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3143
3144 if (sctx->tes_shader.cso == sel)
3145 return;
3146
3147 sctx->tes_shader.cso = sel;
3148 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3149 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3150 si_update_tess_uses_prim_id(sctx);
3151
3152 si_update_common_shader_state(sctx);
3153 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3154
3155 bool ngg_changed = si_update_ngg(sctx);
3156 if (ngg_changed || enable_changed)
3157 si_shader_change_notify(sctx);
3158 if (enable_changed)
3159 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3160 si_update_vs_viewport_state(sctx);
3161 si_set_active_descriptors_for_shader(sctx, sel);
3162 si_update_streamout_state(sctx);
3163 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3164 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3165 }
3166
3167 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3168 {
3169 struct si_context *sctx = (struct si_context *)ctx;
3170 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3171 struct si_shader_selector *sel = state;
3172
3173 /* skip if supplied shader is one already in use */
3174 if (old_sel == sel)
3175 return;
3176
3177 sctx->ps_shader.cso = sel;
3178 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3179
3180 si_update_common_shader_state(sctx);
3181 if (sel) {
3182 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3183 si_update_tess_uses_prim_id(sctx);
3184
3185 if (!old_sel ||
3186 old_sel->info.colors_written != sel->info.colors_written)
3187 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3188
3189 if (sctx->screen->has_out_of_order_rast &&
3190 (!old_sel ||
3191 old_sel->info.writes_memory != sel->info.writes_memory ||
3192 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3193 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3194 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3195 }
3196 si_set_active_descriptors_for_shader(sctx, sel);
3197 si_update_ps_colorbuf0_slot(sctx);
3198 }
3199
3200 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3201 {
3202 if (shader->is_optimized) {
3203 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3204 &shader->ready);
3205 }
3206
3207 util_queue_fence_destroy(&shader->ready);
3208
3209 if (shader->pm4) {
3210 /* If destroyed shaders were not unbound, the next compiled
3211 * shader variant could get the same pointer address and so
3212 * binding it to the same shader stage would be considered
3213 * a no-op, causing random behavior.
3214 */
3215 switch (shader->selector->type) {
3216 case PIPE_SHADER_VERTEX:
3217 if (shader->key.as_ls) {
3218 assert(sctx->chip_class <= GFX8);
3219 si_pm4_delete_state(sctx, ls, shader->pm4);
3220 } else if (shader->key.as_es) {
3221 assert(sctx->chip_class <= GFX8);
3222 si_pm4_delete_state(sctx, es, shader->pm4);
3223 } else if (shader->key.as_ngg) {
3224 si_pm4_delete_state(sctx, gs, shader->pm4);
3225 } else {
3226 si_pm4_delete_state(sctx, vs, shader->pm4);
3227 }
3228 break;
3229 case PIPE_SHADER_TESS_CTRL:
3230 si_pm4_delete_state(sctx, hs, shader->pm4);
3231 break;
3232 case PIPE_SHADER_TESS_EVAL:
3233 if (shader->key.as_es) {
3234 assert(sctx->chip_class <= GFX8);
3235 si_pm4_delete_state(sctx, es, shader->pm4);
3236 } else if (shader->key.as_ngg) {
3237 si_pm4_delete_state(sctx, gs, shader->pm4);
3238 } else {
3239 si_pm4_delete_state(sctx, vs, shader->pm4);
3240 }
3241 break;
3242 case PIPE_SHADER_GEOMETRY:
3243 if (shader->is_gs_copy_shader)
3244 si_pm4_delete_state(sctx, vs, shader->pm4);
3245 else
3246 si_pm4_delete_state(sctx, gs, shader->pm4);
3247 break;
3248 case PIPE_SHADER_FRAGMENT:
3249 si_pm4_delete_state(sctx, ps, shader->pm4);
3250 break;
3251 default:;
3252 }
3253 }
3254
3255 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3256 si_shader_destroy(shader);
3257 free(shader);
3258 }
3259
3260 void si_destroy_shader_selector(struct si_context *sctx,
3261 struct si_shader_selector *sel)
3262 {
3263 struct si_shader *p = sel->first_variant, *c;
3264 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3265 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3266 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3267 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3268 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3269 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3270 };
3271
3272 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3273
3274 if (current_shader[sel->type]->cso == sel) {
3275 current_shader[sel->type]->cso = NULL;
3276 current_shader[sel->type]->current = NULL;
3277 }
3278
3279 while (p) {
3280 c = p->next_variant;
3281 si_delete_shader(sctx, p);
3282 p = c;
3283 }
3284
3285 if (sel->main_shader_part)
3286 si_delete_shader(sctx, sel->main_shader_part);
3287 if (sel->main_shader_part_ls)
3288 si_delete_shader(sctx, sel->main_shader_part_ls);
3289 if (sel->main_shader_part_es)
3290 si_delete_shader(sctx, sel->main_shader_part_es);
3291 if (sel->main_shader_part_ngg)
3292 si_delete_shader(sctx, sel->main_shader_part_ngg);
3293 if (sel->gs_copy_shader)
3294 si_delete_shader(sctx, sel->gs_copy_shader);
3295
3296 util_queue_fence_destroy(&sel->ready);
3297 simple_mtx_destroy(&sel->mutex);
3298 ralloc_free(sel->nir);
3299 free(sel->nir_binary);
3300 free(sel);
3301 }
3302
3303 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3304 {
3305 struct si_context *sctx = (struct si_context *)ctx;
3306 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3307
3308 si_shader_selector_reference(sctx, &sel, NULL);
3309 }
3310
3311 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3312 struct si_shader *vs, unsigned name,
3313 unsigned index, unsigned interpolate)
3314 {
3315 struct si_shader_info *vsinfo = &vs->selector->info;
3316 unsigned j, offset, ps_input_cntl = 0;
3317
3318 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3319 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3320 name == TGSI_SEMANTIC_PRIMID)
3321 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3322
3323 if (name == TGSI_SEMANTIC_PCOORD ||
3324 (name == TGSI_SEMANTIC_TEXCOORD &&
3325 sctx->sprite_coord_enable & (1 << index))) {
3326 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3327 }
3328
3329 for (j = 0; j < vsinfo->num_outputs; j++) {
3330 if (name == vsinfo->output_semantic_name[j] &&
3331 index == vsinfo->output_semantic_index[j]) {
3332 offset = vs->info.vs_output_param_offset[j];
3333
3334 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3335 /* The input is loaded from parameter memory. */
3336 ps_input_cntl |= S_028644_OFFSET(offset);
3337 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3338 if (offset == AC_EXP_PARAM_UNDEFINED) {
3339 /* This can happen with depth-only rendering. */
3340 offset = 0;
3341 } else {
3342 /* The input is a DEFAULT_VAL constant. */
3343 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3344 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3345 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3346 }
3347
3348 ps_input_cntl = S_028644_OFFSET(0x20) |
3349 S_028644_DEFAULT_VAL(offset);
3350 }
3351 break;
3352 }
3353 }
3354
3355 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3356 /* PrimID is written after the last output when HW VS is used. */
3357 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3358 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3359 /* No corresponding output found, load defaults into input.
3360 * Don't set any other bits.
3361 * (FLAT_SHADE=1 completely changes behavior) */
3362 ps_input_cntl = S_028644_OFFSET(0x20);
3363 /* D3D 9 behaviour. GL is undefined */
3364 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3365 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3366 }
3367 return ps_input_cntl;
3368 }
3369
3370 static void si_emit_spi_map(struct si_context *sctx)
3371 {
3372 struct si_shader *ps = sctx->ps_shader.current;
3373 struct si_shader *vs = si_get_vs_state(sctx);
3374 struct si_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3375 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3376 unsigned spi_ps_input_cntl[32];
3377
3378 if (!ps || !ps->selector->info.num_inputs)
3379 return;
3380
3381 num_interp = si_get_ps_num_interp(ps);
3382 assert(num_interp > 0);
3383
3384 for (i = 0; i < psinfo->num_inputs; i++) {
3385 unsigned name = psinfo->input_semantic_name[i];
3386 unsigned index = psinfo->input_semantic_index[i];
3387 unsigned interpolate = psinfo->input_interpolate[i];
3388
3389 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3390 index, interpolate);
3391
3392 if (name == TGSI_SEMANTIC_COLOR) {
3393 assert(index < ARRAY_SIZE(bcol_interp));
3394 bcol_interp[index] = interpolate;
3395 }
3396 }
3397
3398 if (ps->key.part.ps.prolog.color_two_side) {
3399 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3400
3401 for (i = 0; i < 2; i++) {
3402 if (!(psinfo->colors_read & (0xf << (i * 4))))
3403 continue;
3404
3405 spi_ps_input_cntl[num_written++] =
3406 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3407
3408 }
3409 }
3410 assert(num_interp == num_written);
3411
3412 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3413 /* Dota 2: Only ~16% of SPI map updates set different values. */
3414 /* Talos: Only ~9% of SPI map updates set different values. */
3415 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3416 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3417 spi_ps_input_cntl,
3418 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3419
3420 if (initial_cdw != sctx->gfx_cs->current.cdw)
3421 sctx->context_roll = true;
3422 }
3423
3424 /**
3425 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3426 */
3427 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3428 {
3429 if (sctx->init_config_has_vgt_flush)
3430 return;
3431
3432 /* Done by Vulkan before VGT_FLUSH. */
3433 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3434 si_pm4_cmd_add(sctx->init_config,
3435 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3436 si_pm4_cmd_end(sctx->init_config, false);
3437
3438 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3439 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3440 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3441 si_pm4_cmd_end(sctx->init_config, false);
3442 sctx->init_config_has_vgt_flush = true;
3443 }
3444
3445 /* Initialize state related to ESGS / GSVS ring buffers */
3446 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3447 {
3448 struct si_shader_selector *es =
3449 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3450 struct si_shader_selector *gs = sctx->gs_shader.cso;
3451 struct si_pm4_state *pm4;
3452
3453 /* Chip constants. */
3454 unsigned num_se = sctx->screen->info.max_se;
3455 unsigned wave_size = 64;
3456 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3457 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3458 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3459 */
3460 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3461 unsigned alignment = 256 * num_se;
3462 /* The maximum size is 63.999 MB per SE. */
3463 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3464
3465 /* Calculate the minimum size. */
3466 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3467 wave_size, alignment);
3468
3469 /* These are recommended sizes, not minimum sizes. */
3470 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3471 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3472 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3473 gs->max_gsvs_emit_size;
3474
3475 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3476 esgs_ring_size = align(esgs_ring_size, alignment);
3477 gsvs_ring_size = align(gsvs_ring_size, alignment);
3478
3479 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3480 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3481
3482 /* Some rings don't have to be allocated if shaders don't use them.
3483 * (e.g. no varyings between ES and GS or GS and VS)
3484 *
3485 * GFX9 doesn't have the ESGS ring.
3486 */
3487 bool update_esgs = sctx->chip_class <= GFX8 &&
3488 esgs_ring_size &&
3489 (!sctx->esgs_ring ||
3490 sctx->esgs_ring->width0 < esgs_ring_size);
3491 bool update_gsvs = gsvs_ring_size &&
3492 (!sctx->gsvs_ring ||
3493 sctx->gsvs_ring->width0 < gsvs_ring_size);
3494
3495 if (!update_esgs && !update_gsvs)
3496 return true;
3497
3498 if (update_esgs) {
3499 pipe_resource_reference(&sctx->esgs_ring, NULL);
3500 sctx->esgs_ring =
3501 pipe_aligned_buffer_create(sctx->b.screen,
3502 SI_RESOURCE_FLAG_UNMAPPABLE,
3503 PIPE_USAGE_DEFAULT,
3504 esgs_ring_size,
3505 sctx->screen->info.pte_fragment_size);
3506 if (!sctx->esgs_ring)
3507 return false;
3508 }
3509
3510 if (update_gsvs) {
3511 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3512 sctx->gsvs_ring =
3513 pipe_aligned_buffer_create(sctx->b.screen,
3514 SI_RESOURCE_FLAG_UNMAPPABLE,
3515 PIPE_USAGE_DEFAULT,
3516 gsvs_ring_size,
3517 sctx->screen->info.pte_fragment_size);
3518 if (!sctx->gsvs_ring)
3519 return false;
3520 }
3521
3522 /* Create the "init_config_gs_rings" state. */
3523 pm4 = CALLOC_STRUCT(si_pm4_state);
3524 if (!pm4)
3525 return false;
3526
3527 if (sctx->chip_class >= GFX7) {
3528 if (sctx->esgs_ring) {
3529 assert(sctx->chip_class <= GFX8);
3530 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3531 sctx->esgs_ring->width0 / 256);
3532 }
3533 if (sctx->gsvs_ring)
3534 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3535 sctx->gsvs_ring->width0 / 256);
3536 } else {
3537 if (sctx->esgs_ring)
3538 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3539 sctx->esgs_ring->width0 / 256);
3540 if (sctx->gsvs_ring)
3541 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3542 sctx->gsvs_ring->width0 / 256);
3543 }
3544
3545 /* Set the state. */
3546 if (sctx->init_config_gs_rings)
3547 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3548 sctx->init_config_gs_rings = pm4;
3549
3550 if (!sctx->init_config_has_vgt_flush) {
3551 si_init_config_add_vgt_flush(sctx);
3552 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3553 }
3554
3555 /* Flush the context to re-emit both init_config states. */
3556 sctx->initial_gfx_cs_size = 0; /* force flush */
3557 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3558
3559 /* Set ring bindings. */
3560 if (sctx->esgs_ring) {
3561 assert(sctx->chip_class <= GFX8);
3562 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3563 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3564 true, true, 4, 64, 0);
3565 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3566 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3567 false, false, 0, 0, 0);
3568 }
3569 if (sctx->gsvs_ring) {
3570 si_set_ring_buffer(sctx, SI_RING_GSVS,
3571 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3572 false, false, 0, 0, 0);
3573 }
3574
3575 return true;
3576 }
3577
3578 static void si_shader_lock(struct si_shader *shader)
3579 {
3580 simple_mtx_lock(&shader->selector->mutex);
3581 if (shader->previous_stage_sel) {
3582 assert(shader->previous_stage_sel != shader->selector);
3583 simple_mtx_lock(&shader->previous_stage_sel->mutex);
3584 }
3585 }
3586
3587 static void si_shader_unlock(struct si_shader *shader)
3588 {
3589 if (shader->previous_stage_sel)
3590 simple_mtx_unlock(&shader->previous_stage_sel->mutex);
3591 simple_mtx_unlock(&shader->selector->mutex);
3592 }
3593
3594 /**
3595 * @returns 1 if \p sel has been updated to use a new scratch buffer
3596 * 0 if not
3597 * < 0 if there was a failure
3598 */
3599 static int si_update_scratch_buffer(struct si_context *sctx,
3600 struct si_shader *shader)
3601 {
3602 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3603
3604 if (!shader)
3605 return 0;
3606
3607 /* This shader doesn't need a scratch buffer */
3608 if (shader->config.scratch_bytes_per_wave == 0)
3609 return 0;
3610
3611 /* Prevent race conditions when updating:
3612 * - si_shader::scratch_bo
3613 * - si_shader::binary::code
3614 * - si_shader::previous_stage::binary::code.
3615 */
3616 si_shader_lock(shader);
3617
3618 /* This shader is already configured to use the current
3619 * scratch buffer. */
3620 if (shader->scratch_bo == sctx->scratch_buffer) {
3621 si_shader_unlock(shader);
3622 return 0;
3623 }
3624
3625 assert(sctx->scratch_buffer);
3626
3627 /* Replace the shader bo with a new bo that has the relocs applied. */
3628 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3629 si_shader_unlock(shader);
3630 return -1;
3631 }
3632
3633 /* Update the shader state to use the new shader bo. */
3634 si_shader_init_pm4_state(sctx->screen, shader);
3635
3636 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3637
3638 si_shader_unlock(shader);
3639 return 1;
3640 }
3641
3642 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3643 {
3644 return shader ? shader->config.scratch_bytes_per_wave : 0;
3645 }
3646
3647 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3648 {
3649 if (!sctx->tes_shader.cso)
3650 return NULL; /* tessellation disabled */
3651
3652 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3653 sctx->fixed_func_tcs_shader.current;
3654 }
3655
3656 static bool si_update_scratch_relocs(struct si_context *sctx)
3657 {
3658 struct si_shader *tcs = si_get_tcs_current(sctx);
3659 int r;
3660
3661 /* Update the shaders, so that they are using the latest scratch.
3662 * The scratch buffer may have been changed since these shaders were
3663 * last used, so we still need to try to update them, even if they
3664 * require scratch buffers smaller than the current size.
3665 */
3666 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3667 if (r < 0)
3668 return false;
3669 if (r == 1)
3670 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3671
3672 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3673 if (r < 0)
3674 return false;
3675 if (r == 1)
3676 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3677
3678 r = si_update_scratch_buffer(sctx, tcs);
3679 if (r < 0)
3680 return false;
3681 if (r == 1)
3682 si_pm4_bind_state(sctx, hs, tcs->pm4);
3683
3684 /* VS can be bound as LS, ES, or VS. */
3685 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3686 if (r < 0)
3687 return false;
3688 if (r == 1) {
3689 if (sctx->vs_shader.current->key.as_ls)
3690 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3691 else if (sctx->vs_shader.current->key.as_es)
3692 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3693 else if (sctx->vs_shader.current->key.as_ngg)
3694 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3695 else
3696 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3697 }
3698
3699 /* TES can be bound as ES or VS. */
3700 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3701 if (r < 0)
3702 return false;
3703 if (r == 1) {
3704 if (sctx->tes_shader.current->key.as_es)
3705 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3706 else if (sctx->tes_shader.current->key.as_ngg)
3707 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3708 else
3709 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3710 }
3711
3712 return true;
3713 }
3714
3715 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3716 {
3717 /* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer.
3718 * There are 2 cases to handle:
3719 *
3720 * - If the current needed size is less than the maximum seen size,
3721 * use the maximum seen size, so that WAVESIZE remains the same.
3722 *
3723 * - If the current needed size is greater than the maximum seen size,
3724 * the scratch buffer is reallocated, so we can increase WAVESIZE.
3725 *
3726 * Shaders that set SCRATCH_EN=0 don't allocate scratch space.
3727 * Otherwise, the number of waves that can use scratch is
3728 * SPI_TMPRING_SIZE.WAVES.
3729 */
3730 unsigned bytes = 0;
3731
3732 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3733 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3734 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3735
3736 if (sctx->tes_shader.cso) {
3737 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3738 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(si_get_tcs_current(sctx)));
3739 }
3740
3741 sctx->max_seen_scratch_bytes_per_wave =
3742 MAX2(sctx->max_seen_scratch_bytes_per_wave, bytes);
3743
3744 unsigned scratch_needed_size =
3745 sctx->max_seen_scratch_bytes_per_wave * sctx->scratch_waves;
3746 unsigned spi_tmpring_size;
3747
3748 if (scratch_needed_size > 0) {
3749 if (!sctx->scratch_buffer ||
3750 scratch_needed_size > sctx->scratch_buffer->b.b.width0) {
3751 /* Create a bigger scratch buffer */
3752 si_resource_reference(&sctx->scratch_buffer, NULL);
3753
3754 sctx->scratch_buffer =
3755 si_aligned_buffer_create(&sctx->screen->b,
3756 SI_RESOURCE_FLAG_UNMAPPABLE,
3757 PIPE_USAGE_DEFAULT,
3758 scratch_needed_size,
3759 sctx->screen->info.pte_fragment_size);
3760 if (!sctx->scratch_buffer)
3761 return false;
3762
3763 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3764 si_context_add_resource_size(sctx,
3765 &sctx->scratch_buffer->b.b);
3766 }
3767
3768 if (!si_update_scratch_relocs(sctx))
3769 return false;
3770 }
3771
3772 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3773 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3774 "scratch size should already be aligned correctly.");
3775
3776 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3777 S_0286E8_WAVESIZE(sctx->max_seen_scratch_bytes_per_wave >> 10);
3778 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3779 sctx->spi_tmpring_size = spi_tmpring_size;
3780 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3781 }
3782 return true;
3783 }
3784
3785 static void si_init_tess_factor_ring(struct si_context *sctx)
3786 {
3787 assert(!sctx->tess_rings);
3788 assert(((sctx->screen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
3789
3790 /* The address must be aligned to 2^19, because the shader only
3791 * receives the high 13 bits.
3792 */
3793 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3794 SI_RESOURCE_FLAG_32BIT,
3795 PIPE_USAGE_DEFAULT,
3796 sctx->screen->tess_offchip_ring_size +
3797 sctx->screen->tess_factor_ring_size,
3798 1 << 19);
3799 if (!sctx->tess_rings)
3800 return;
3801
3802 si_init_config_add_vgt_flush(sctx);
3803
3804 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3805 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3806
3807 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3808 sctx->screen->tess_offchip_ring_size;
3809
3810 /* Append these registers to the init config state. */
3811 if (sctx->chip_class >= GFX7) {
3812 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3813 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3814 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3815 factor_va >> 8);
3816 if (sctx->chip_class >= GFX10)
3817 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3818 S_030984_BASE_HI(factor_va >> 40));
3819 else if (sctx->chip_class == GFX9)
3820 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3821 S_030944_BASE_HI(factor_va >> 40));
3822 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3823 sctx->screen->vgt_hs_offchip_param);
3824 } else {
3825 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3826 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3827 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3828 factor_va >> 8);
3829 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3830 sctx->screen->vgt_hs_offchip_param);
3831 }
3832
3833 /* Flush the context to re-emit the init_config state.
3834 * This is done only once in a lifetime of a context.
3835 */
3836 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3837 sctx->initial_gfx_cs_size = 0; /* force flush */
3838 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3839 }
3840
3841 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3842 union si_vgt_stages_key key)
3843 {
3844 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3845 uint32_t stages = 0;
3846
3847 if (key.u.tess) {
3848 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3849 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3850
3851 if (key.u.gs)
3852 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3853 S_028B54_GS_EN(1);
3854 else if (key.u.ngg)
3855 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3856 else
3857 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3858 } else if (key.u.gs) {
3859 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3860 S_028B54_GS_EN(1);
3861 } else if (key.u.ngg) {
3862 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3863 }
3864
3865 if (key.u.ngg) {
3866 stages |= S_028B54_PRIMGEN_EN(1) |
3867 S_028B54_NGG_WAVE_ID_EN(key.u.streamout) |
3868 S_028B54_PRIMGEN_PASSTHRU_EN(key.u.ngg_passthrough);
3869 } else if (key.u.gs)
3870 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3871
3872 if (screen->info.chip_class >= GFX9)
3873 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3874
3875 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3876 stages |= S_028B54_HS_W32_EN(1) |
3877 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3878 S_028B54_VS_W32_EN(1);
3879 }
3880
3881 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3882 return pm4;
3883 }
3884
3885 static void si_update_vgt_shader_config(struct si_context *sctx,
3886 union si_vgt_stages_key key)
3887 {
3888 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3889
3890 if (unlikely(!*pm4))
3891 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3892 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3893 }
3894
3895 bool si_update_shaders(struct si_context *sctx)
3896 {
3897 struct pipe_context *ctx = (struct pipe_context*)sctx;
3898 struct si_compiler_ctx_state compiler_state;
3899 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3900 struct si_shader *old_vs = si_get_vs_state(sctx);
3901 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3902 struct si_shader *old_ps = sctx->ps_shader.current;
3903 union si_vgt_stages_key key;
3904 unsigned old_spi_shader_col_format =
3905 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3906 int r;
3907
3908 if (!sctx->compiler.passes)
3909 si_init_compiler(sctx->screen, &sctx->compiler);
3910
3911 compiler_state.compiler = &sctx->compiler;
3912 compiler_state.debug = sctx->debug;
3913 compiler_state.is_debug_context = sctx->is_debug;
3914
3915 key.index = 0;
3916
3917 if (sctx->tes_shader.cso)
3918 key.u.tess = 1;
3919 if (sctx->gs_shader.cso)
3920 key.u.gs = 1;
3921
3922 if (sctx->ngg) {
3923 key.u.ngg = 1;
3924 key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
3925 }
3926
3927 /* Update TCS and TES. */
3928 if (sctx->tes_shader.cso) {
3929 if (!sctx->tess_rings) {
3930 si_init_tess_factor_ring(sctx);
3931 if (!sctx->tess_rings)
3932 return false;
3933 }
3934
3935 if (sctx->tcs_shader.cso) {
3936 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3937 &compiler_state);
3938 if (r)
3939 return false;
3940 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3941 } else {
3942 if (!sctx->fixed_func_tcs_shader.cso) {
3943 sctx->fixed_func_tcs_shader.cso =
3944 si_create_fixed_func_tcs(sctx);
3945 if (!sctx->fixed_func_tcs_shader.cso)
3946 return false;
3947 }
3948
3949 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3950 key, &compiler_state);
3951 if (r)
3952 return false;
3953 si_pm4_bind_state(sctx, hs,
3954 sctx->fixed_func_tcs_shader.current->pm4);
3955 }
3956
3957 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3958 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3959 if (r)
3960 return false;
3961
3962 if (sctx->gs_shader.cso) {
3963 /* TES as ES */
3964 assert(sctx->chip_class <= GFX8);
3965 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3966 } else if (key.u.ngg) {
3967 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3968 } else {
3969 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3970 }
3971 }
3972 } else {
3973 if (sctx->chip_class <= GFX8)
3974 si_pm4_bind_state(sctx, ls, NULL);
3975 si_pm4_bind_state(sctx, hs, NULL);
3976 }
3977
3978 /* Update GS. */
3979 if (sctx->gs_shader.cso) {
3980 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3981 if (r)
3982 return false;
3983 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3984 if (!key.u.ngg) {
3985 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3986
3987 if (!si_update_gs_ring_buffers(sctx))
3988 return false;
3989 } else {
3990 si_pm4_bind_state(sctx, vs, NULL);
3991 }
3992 } else {
3993 if (!key.u.ngg) {
3994 si_pm4_bind_state(sctx, gs, NULL);
3995 if (sctx->chip_class <= GFX8)
3996 si_pm4_bind_state(sctx, es, NULL);
3997 }
3998 }
3999
4000 /* Update VS. */
4001 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
4002 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
4003 if (r)
4004 return false;
4005
4006 if (!key.u.tess && !key.u.gs) {
4007 if (key.u.ngg) {
4008 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
4009 si_pm4_bind_state(sctx, vs, NULL);
4010 } else {
4011 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
4012 }
4013 } else if (sctx->tes_shader.cso) {
4014 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
4015 } else {
4016 assert(sctx->gs_shader.cso);
4017 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
4018 }
4019 }
4020
4021 /* This must be done after the shader variant is selected. */
4022 if (sctx->ngg)
4023 key.u.ngg_passthrough = gfx10_is_ngg_passthrough(si_get_vs(sctx)->current);
4024
4025 si_update_vgt_shader_config(sctx, key);
4026
4027 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
4028 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
4029
4030 if (sctx->ps_shader.cso) {
4031 unsigned db_shader_control;
4032
4033 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
4034 if (r)
4035 return false;
4036 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
4037
4038 db_shader_control =
4039 sctx->ps_shader.cso->db_shader_control |
4040 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
4041
4042 if (si_pm4_state_changed(sctx, ps) ||
4043 si_pm4_state_changed(sctx, vs) ||
4044 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
4045 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
4046 sctx->flatshade != rs->flatshade) {
4047 sctx->sprite_coord_enable = rs->sprite_coord_enable;
4048 sctx->flatshade = rs->flatshade;
4049 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
4050 }
4051
4052 if (sctx->screen->info.rbplus_allowed &&
4053 si_pm4_state_changed(sctx, ps) &&
4054 (!old_ps ||
4055 old_spi_shader_col_format !=
4056 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
4057 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
4058
4059 if (sctx->ps_db_shader_control != db_shader_control) {
4060 sctx->ps_db_shader_control = db_shader_control;
4061 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4062 if (sctx->screen->dpbb_allowed)
4063 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
4064 }
4065
4066 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
4067 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
4068 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
4069
4070 if (sctx->chip_class == GFX6)
4071 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4072
4073 if (sctx->framebuffer.nr_samples <= 1)
4074 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
4075 }
4076 }
4077
4078 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
4079 si_pm4_state_enabled_and_changed(sctx, hs) ||
4080 si_pm4_state_enabled_and_changed(sctx, es) ||
4081 si_pm4_state_enabled_and_changed(sctx, gs) ||
4082 si_pm4_state_enabled_and_changed(sctx, vs) ||
4083 si_pm4_state_enabled_and_changed(sctx, ps)) {
4084 if (!si_update_spi_tmpring_size(sctx))
4085 return false;
4086 }
4087
4088 if (sctx->chip_class >= GFX7) {
4089 if (si_pm4_state_enabled_and_changed(sctx, ls))
4090 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
4091 else if (!sctx->queued.named.ls)
4092 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
4093
4094 if (si_pm4_state_enabled_and_changed(sctx, hs))
4095 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4096 else if (!sctx->queued.named.hs)
4097 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4098
4099 if (si_pm4_state_enabled_and_changed(sctx, es))
4100 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4101 else if (!sctx->queued.named.es)
4102 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4103
4104 if (si_pm4_state_enabled_and_changed(sctx, gs))
4105 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4106 else if (!sctx->queued.named.gs)
4107 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4108
4109 if (si_pm4_state_enabled_and_changed(sctx, vs))
4110 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4111 else if (!sctx->queued.named.vs)
4112 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4113
4114 if (si_pm4_state_enabled_and_changed(sctx, ps))
4115 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4116 else if (!sctx->queued.named.ps)
4117 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4118 }
4119
4120 sctx->do_update_shaders = false;
4121 return true;
4122 }
4123
4124 static void si_emit_scratch_state(struct si_context *sctx)
4125 {
4126 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4127
4128 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4129 sctx->spi_tmpring_size);
4130
4131 if (sctx->scratch_buffer) {
4132 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4133 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4134 RADEON_PRIO_SCRATCH_BUFFER);
4135 }
4136 }
4137
4138 void si_init_shader_functions(struct si_context *sctx)
4139 {
4140 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4141 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4142
4143 sctx->b.create_vs_state = si_create_shader_selector;
4144 sctx->b.create_tcs_state = si_create_shader_selector;
4145 sctx->b.create_tes_state = si_create_shader_selector;
4146 sctx->b.create_gs_state = si_create_shader_selector;
4147 sctx->b.create_fs_state = si_create_shader_selector;
4148
4149 sctx->b.bind_vs_state = si_bind_vs_shader;
4150 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4151 sctx->b.bind_tes_state = si_bind_tes_shader;
4152 sctx->b.bind_gs_state = si_bind_gs_shader;
4153 sctx->b.bind_fs_state = si_bind_ps_shader;
4154
4155 sctx->b.delete_vs_state = si_delete_shader_selector;
4156 sctx->b.delete_tcs_state = si_delete_shader_selector;
4157 sctx->b.delete_tes_state = si_delete_shader_selector;
4158 sctx->b.delete_gs_state = si_delete_shader_selector;
4159 sctx->b.delete_fs_state = si_delete_shader_selector;
4160 }