1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
26 #include "git_sha1.h" /* For MESA_GIT_SHA1 */
27 #include "util/u_format.h"
28 #include "util/u_memory.h"
29 #include "util/u_inlines.h"
30 #include "util/u_string.h"
31 #include "util/u_math.h"
33 #include "os/os_process.h"
35 #include "svga_winsys.h"
36 #include "svga_public.h"
37 #include "svga_context.h"
38 #include "svga_format.h"
40 #include "svga_screen.h"
41 #include "svga_tgsi.h"
42 #include "svga_resource_texture.h"
43 #include "svga_resource.h"
44 #include "svga_debug.h"
46 #include "svga3d_shaderdefs.h"
47 #include "VGPU10ShaderTokens.h"
49 /* NOTE: this constant may get moved into a svga3d*.h header file */
50 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
55 static const struct debug_named_value svga_debug_flags
[] = {
56 { "dma", DEBUG_DMA
, NULL
},
57 { "tgsi", DEBUG_TGSI
, NULL
},
58 { "pipe", DEBUG_PIPE
, NULL
},
59 { "state", DEBUG_STATE
, NULL
},
60 { "screen", DEBUG_SCREEN
, NULL
},
61 { "tex", DEBUG_TEX
, NULL
},
62 { "swtnl", DEBUG_SWTNL
, NULL
},
63 { "const", DEBUG_CONSTS
, NULL
},
64 { "viewport", DEBUG_VIEWPORT
, NULL
},
65 { "views", DEBUG_VIEWS
, NULL
},
66 { "perf", DEBUG_PERF
, NULL
},
67 { "flush", DEBUG_FLUSH
, NULL
},
68 { "sync", DEBUG_SYNC
, NULL
},
69 { "cache", DEBUG_CACHE
, NULL
},
70 { "streamout", DEBUG_STREAMOUT
, NULL
},
71 { "query", DEBUG_QUERY
, NULL
},
72 { "samplers", DEBUG_SAMPLERS
, NULL
},
78 svga_get_vendor( struct pipe_screen
*pscreen
)
80 return "VMware, Inc.";
85 svga_get_name( struct pipe_screen
*pscreen
)
87 const char *build
= "", *llvm
= "", *mutex
= "";
88 static char name
[100];
90 /* Only return internal details in the DEBUG version:
92 build
= "build: DEBUG;";
93 mutex
= "mutex: " PIPE_ATOMIC
";";
94 #elif defined(VMX86_STATS)
95 build
= "build: OPT;";
97 build
= "build: RELEASE;";
103 util_snprintf(name
, sizeof(name
), "SVGA3D; %s %s %s", build
, mutex
, llvm
);
108 /** Helper for querying float-valued device cap */
110 get_float_cap(struct svga_winsys_screen
*sws
, unsigned cap
, float defaultVal
)
112 SVGA3dDevCapResult result
;
113 if (sws
->get_cap(sws
, cap
, &result
))
120 /** Helper for querying uint-valued device cap */
122 get_uint_cap(struct svga_winsys_screen
*sws
, unsigned cap
, unsigned defaultVal
)
124 SVGA3dDevCapResult result
;
125 if (sws
->get_cap(sws
, cap
, &result
))
132 /** Helper for querying boolean-valued device cap */
134 get_bool_cap(struct svga_winsys_screen
*sws
, unsigned cap
, boolean defaultVal
)
136 SVGA3dDevCapResult result
;
137 if (sws
->get_cap(sws
, cap
, &result
))
145 svga_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
147 struct svga_screen
*svgascreen
= svga_screen(screen
);
148 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
151 case PIPE_CAPF_MAX_LINE_WIDTH
:
152 return svgascreen
->maxLineWidth
;
153 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
154 return svgascreen
->maxLineWidthAA
;
156 case PIPE_CAPF_MAX_POINT_WIDTH
:
158 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
159 return svgascreen
->maxPointSize
;
161 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
162 return (float) get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY
, 4);
164 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
167 case PIPE_CAPF_GUARD_BAND_LEFT
:
168 case PIPE_CAPF_GUARD_BAND_TOP
:
169 case PIPE_CAPF_GUARD_BAND_RIGHT
:
170 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
174 debug_printf("Unexpected PIPE_CAPF_ query %u\n", param
);
180 svga_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
182 struct svga_screen
*svgascreen
= svga_screen(screen
);
183 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
184 SVGA3dDevCapResult result
;
187 case PIPE_CAP_NPOT_TEXTURES
:
188 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
189 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
191 case PIPE_CAP_TWO_SIDED_STENCIL
:
193 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
195 * "In virtually every OpenGL implementation and hardware,
196 * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
197 * http://www.opengl.org/wiki/Blending
199 return sws
->have_vgpu10
? 1 : 0;
200 case PIPE_CAP_ANISOTROPIC_FILTER
:
202 case PIPE_CAP_POINT_SPRITE
:
204 case PIPE_CAP_TGSI_TEXCOORD
:
206 case PIPE_CAP_MAX_RENDER_TARGETS
:
207 return svgascreen
->max_color_buffers
;
208 case PIPE_CAP_OCCLUSION_QUERY
:
210 case PIPE_CAP_QUERY_TIME_ELAPSED
:
212 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
213 return sws
->have_vgpu10
;
214 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
216 case PIPE_CAP_TEXTURE_SWIZZLE
:
218 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
220 case PIPE_CAP_USER_VERTEX_BUFFERS
:
222 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
224 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
227 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
229 unsigned levels
= SVGA_MAX_TEXTURE_LEVELS
;
230 if (sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH
, &result
))
231 levels
= MIN2(util_logbase2(result
.u
) + 1, levels
);
233 levels
= 12 /* 2048x2048 */;
234 if (sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT
, &result
))
235 levels
= MIN2(util_logbase2(result
.u
) + 1, levels
);
237 levels
= 12 /* 2048x2048 */;
241 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
242 if (!sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT
, &result
))
243 return 8; /* max 128x128x128 */
244 return MIN2(util_logbase2(result
.u
) + 1, SVGA_MAX_TEXTURE_LEVELS
);
246 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
248 * No mechanism to query the host, and at least limited to 2048x2048 on
251 return MIN2(screen
->get_param(screen
, PIPE_CAP_MAX_TEXTURE_2D_LEVELS
),
254 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
255 return sws
->have_vgpu10
? SVGA3D_MAX_SURFACE_ARRAYSIZE
: 0;
257 case PIPE_CAP_BLEND_EQUATION_SEPARATE
: /* req. for GL 1.5 */
260 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
262 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
263 return sws
->have_vgpu10
;
264 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
266 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
267 return !sws
->have_vgpu10
;
269 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
270 return 1; /* The color outputs of vertex shaders are not clamped */
271 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
272 return 0; /* The driver can't clamp vertex colors */
273 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
274 return 0; /* The driver can't clamp fragment colors */
276 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
277 return 1; /* expected for GL_ARB_framebuffer_object */
279 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
280 return sws
->have_vgpu10
? 330 : 120;
282 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
288 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
289 case PIPE_CAP_INDEP_BLEND_ENABLE
:
290 case PIPE_CAP_CONDITIONAL_RENDER
:
291 case PIPE_CAP_QUERY_TIMESTAMP
:
292 case PIPE_CAP_TGSI_INSTANCEID
:
293 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
294 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
295 case PIPE_CAP_FAKE_SW_MSAA
:
296 return sws
->have_vgpu10
;
298 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
299 return sws
->have_vgpu10
? SVGA3D_DX_MAX_SOTARGETS
: 0;
300 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
301 return sws
->have_vgpu10
? 4 : 0;
302 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
303 return sws
->have_vgpu10
? SVGA3D_MAX_STREAMOUT_DECLS
: 0;
304 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
305 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
307 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
308 return svgascreen
->ms_samples
? 1 : 0;
310 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
311 /* convert bytes to texels for the case of the largest texel
314 return SVGA3D_DX_MAX_RESOURCE_SIZE
/ (4 * sizeof(float));
316 case PIPE_CAP_MIN_TEXEL_OFFSET
:
317 return sws
->have_vgpu10
? VGPU10_MIN_TEXEL_FETCH_OFFSET
: 0;
318 case PIPE_CAP_MAX_TEXEL_OFFSET
:
319 return sws
->have_vgpu10
? VGPU10_MAX_TEXEL_FETCH_OFFSET
: 0;
321 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
322 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
325 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
326 return sws
->have_vgpu10
? 256 : 0;
327 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
328 return sws
->have_vgpu10
? 1024 : 0;
330 case PIPE_CAP_PRIMITIVE_RESTART
:
331 return 1; /* may be a sw fallback, depending on restart index */
333 case PIPE_CAP_GENERATE_MIPMAP
:
334 return sws
->have_generate_mipmap_cmd
;
336 case PIPE_CAP_NATIVE_FENCE_FD
:
337 return sws
->have_fence_fd
;
339 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
342 /* Unsupported features */
343 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
344 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
345 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
346 case PIPE_CAP_INDEP_BLEND_FUNC
:
347 case PIPE_CAP_TEXTURE_BARRIER
:
348 case PIPE_CAP_MAX_VERTEX_STREAMS
:
349 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
350 case PIPE_CAP_COMPUTE
:
351 case PIPE_CAP_START_INSTANCE
:
352 case PIPE_CAP_CUBE_MAP_ARRAY
:
353 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
354 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
355 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
356 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
357 case PIPE_CAP_TEXTURE_GATHER_SM5
:
358 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
359 case PIPE_CAP_TEXTURE_QUERY_LOD
:
360 case PIPE_CAP_SAMPLE_SHADING
:
361 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
362 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
363 case PIPE_CAP_DRAW_INDIRECT
:
364 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
365 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
366 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
367 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
368 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
369 case PIPE_CAP_CLIP_HALFZ
:
370 case PIPE_CAP_VERTEXID_NOBASE
:
371 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
372 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
373 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
374 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
375 case PIPE_CAP_INVALIDATE_BUFFER
:
376 case PIPE_CAP_STRING_MARKER
:
377 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
378 case PIPE_CAP_QUERY_MEMORY_INFO
:
379 case PIPE_CAP_PCI_GROUP
:
380 case PIPE_CAP_PCI_BUS
:
381 case PIPE_CAP_PCI_DEVICE
:
382 case PIPE_CAP_PCI_FUNCTION
:
383 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
385 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
387 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
388 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
389 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
390 return 1; /* need 4-byte alignment for all offsets and strides */
391 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
393 case PIPE_CAP_MAX_VIEWPORTS
:
395 case PIPE_CAP_ENDIANNESS
:
396 return PIPE_ENDIAN_LITTLE
;
398 case PIPE_CAP_VENDOR_ID
:
399 return 0x15ad; /* VMware Inc. */
400 case PIPE_CAP_DEVICE_ID
:
401 return 0x0405; /* assume SVGA II */
402 case PIPE_CAP_ACCELERATED
:
404 case PIPE_CAP_VIDEO_MEMORY
:
405 /* XXX: Query the host ? */
407 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
408 return sws
->have_vgpu10
;
409 case PIPE_CAP_CLEAR_TEXTURE
:
410 return sws
->have_vgpu10
;
412 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
413 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
414 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
415 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
416 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
417 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
418 case PIPE_CAP_TGSI_TXQS
:
419 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
420 case PIPE_CAP_SHAREABLE_SHADERS
:
421 case PIPE_CAP_DRAW_PARAMETERS
:
422 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
423 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
424 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
425 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
426 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
427 case PIPE_CAP_CULL_DISTANCE
:
428 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
429 case PIPE_CAP_TGSI_VOTE
:
430 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
431 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
432 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
433 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
434 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
435 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
436 case PIPE_CAP_TGSI_FS_FBFETCH
:
437 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
438 case PIPE_CAP_DOUBLES
:
440 case PIPE_CAP_INT64_DIVMOD
:
441 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
442 case PIPE_CAP_TGSI_CLOCK
:
443 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
444 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
445 case PIPE_CAP_TGSI_BALLOT
:
446 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
447 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
448 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
449 case PIPE_CAP_POST_DEPTH_COVERAGE
:
450 case PIPE_CAP_BINDLESS_TEXTURE
:
451 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
452 case PIPE_CAP_QUERY_SO_OVERFLOW
:
453 case PIPE_CAP_MEMOBJ
:
454 case PIPE_CAP_LOAD_CONSTBUF
:
455 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
456 case PIPE_CAP_TILE_RASTER_ORDER
:
457 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
458 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
462 debug_printf("Unexpected PIPE_CAP_ query %u\n", param
);
468 vgpu9_get_shader_param(struct pipe_screen
*screen
,
469 enum pipe_shader_type shader
,
470 enum pipe_shader_cap param
)
472 struct svga_screen
*svgascreen
= svga_screen(screen
);
473 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
476 assert(!sws
->have_vgpu10
);
480 case PIPE_SHADER_FRAGMENT
:
483 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
484 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
485 return get_uint_cap(sws
,
486 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS
,
488 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
489 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
491 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
492 return SVGA3D_MAX_NESTING_LEVEL
;
493 case PIPE_SHADER_CAP_MAX_INPUTS
:
495 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
496 return svgascreen
->max_color_buffers
;
497 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
498 return 224 * sizeof(float[4]);
499 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
501 case PIPE_SHADER_CAP_MAX_TEMPS
:
502 val
= get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS
, 32);
503 return MIN2(val
, SVGA3D_TEMPREG_MAX
);
504 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
506 * Although PS 3.0 has some addressing abilities it can only represent
507 * loops that can be statically determined and unrolled. Given we can
508 * only handle a subset of the cases that the state tracker already
509 * does it is better to defer loop unrolling to the state tracker.
512 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
514 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
516 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
517 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
518 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
520 case PIPE_SHADER_CAP_SUBROUTINES
:
522 case PIPE_SHADER_CAP_INT64_ATOMICS
:
523 case PIPE_SHADER_CAP_INTEGERS
:
525 case PIPE_SHADER_CAP_FP16
:
527 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
528 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
530 case PIPE_SHADER_CAP_PREFERRED_IR
:
531 return PIPE_SHADER_IR_TGSI
;
532 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
534 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
535 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
536 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
537 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
538 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
539 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
540 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
541 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
542 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
543 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
544 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
546 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
549 /* If we get here, we failed to handle a cap above */
550 debug_printf("Unexpected fragment shader query %u\n", param
);
552 case PIPE_SHADER_VERTEX
:
555 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
556 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
557 return get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS
,
559 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
560 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
561 /* XXX: until we have vertex texture support */
563 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
564 return SVGA3D_MAX_NESTING_LEVEL
;
565 case PIPE_SHADER_CAP_MAX_INPUTS
:
567 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
569 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
570 return 256 * sizeof(float[4]);
571 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
573 case PIPE_SHADER_CAP_MAX_TEMPS
:
574 val
= get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS
, 32);
575 return MIN2(val
, SVGA3D_TEMPREG_MAX
);
576 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
578 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
580 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
581 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
583 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
585 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
587 case PIPE_SHADER_CAP_SUBROUTINES
:
589 case PIPE_SHADER_CAP_INT64_ATOMICS
:
590 case PIPE_SHADER_CAP_INTEGERS
:
592 case PIPE_SHADER_CAP_FP16
:
594 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
595 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
597 case PIPE_SHADER_CAP_PREFERRED_IR
:
598 return PIPE_SHADER_IR_TGSI
;
599 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
601 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
602 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
603 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
604 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
605 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
606 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
607 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
608 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
609 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
610 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
611 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
613 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
616 /* If we get here, we failed to handle a cap above */
617 debug_printf("Unexpected vertex shader query %u\n", param
);
619 case PIPE_SHADER_GEOMETRY
:
620 case PIPE_SHADER_COMPUTE
:
621 case PIPE_SHADER_TESS_CTRL
:
622 case PIPE_SHADER_TESS_EVAL
:
623 /* no support for geometry, tess or compute shaders at this time */
626 debug_printf("Unexpected shader type (%u) query\n", shader
);
634 vgpu10_get_shader_param(struct pipe_screen
*screen
,
635 enum pipe_shader_type shader
,
636 enum pipe_shader_cap param
)
638 struct svga_screen
*svgascreen
= svga_screen(screen
);
639 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
641 assert(sws
->have_vgpu10
);
642 (void) sws
; /* silence unused var warnings in non-debug builds */
644 /* Only VS, GS, FS supported */
645 if (shader
!= PIPE_SHADER_VERTEX
&&
646 shader
!= PIPE_SHADER_GEOMETRY
&&
647 shader
!= PIPE_SHADER_FRAGMENT
) {
651 /* NOTE: we do not query the device for any caps/limits at this time */
653 /* Generally the same limits for vertex, geometry and fragment shaders */
655 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
656 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
657 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
658 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
660 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
662 case PIPE_SHADER_CAP_MAX_INPUTS
:
663 if (shader
== PIPE_SHADER_FRAGMENT
)
664 return VGPU10_MAX_FS_INPUTS
;
665 else if (shader
== PIPE_SHADER_GEOMETRY
)
666 return VGPU10_MAX_GS_INPUTS
;
668 return VGPU10_MAX_VS_INPUTS
;
669 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
670 if (shader
== PIPE_SHADER_FRAGMENT
)
671 return VGPU10_MAX_FS_OUTPUTS
;
672 else if (shader
== PIPE_SHADER_GEOMETRY
)
673 return VGPU10_MAX_GS_OUTPUTS
;
675 return VGPU10_MAX_VS_OUTPUTS
;
676 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
677 return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT
* sizeof(float[4]);
678 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
679 return svgascreen
->max_const_buffers
;
680 case PIPE_SHADER_CAP_MAX_TEMPS
:
681 return VGPU10_MAX_TEMPS
;
682 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
683 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
684 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
685 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
686 return TRUE
; /* XXX verify */
687 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
688 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
689 case PIPE_SHADER_CAP_SUBROUTINES
:
690 case PIPE_SHADER_CAP_INTEGERS
:
692 case PIPE_SHADER_CAP_FP16
:
694 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
695 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
696 return SVGA3D_DX_MAX_SAMPLERS
;
697 case PIPE_SHADER_CAP_PREFERRED_IR
:
698 return PIPE_SHADER_IR_TGSI
;
699 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
701 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
702 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
703 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
704 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
705 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
706 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
707 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
708 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
709 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
710 case PIPE_SHADER_CAP_INT64_ATOMICS
:
711 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
712 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
714 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
717 debug_printf("Unexpected vgpu10 shader query %u\n", param
);
725 svga_get_shader_param(struct pipe_screen
*screen
, enum pipe_shader_type shader
,
726 enum pipe_shader_cap param
)
728 struct svga_screen
*svgascreen
= svga_screen(screen
);
729 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
730 if (sws
->have_vgpu10
) {
731 return vgpu10_get_shader_param(screen
, shader
, param
);
734 return vgpu9_get_shader_param(screen
, shader
, param
);
740 * Implement pipe_screen::is_format_supported().
741 * \param bindings bitmask of PIPE_BIND_x flags
744 svga_is_format_supported( struct pipe_screen
*screen
,
745 enum pipe_format format
,
746 enum pipe_texture_target target
,
747 unsigned sample_count
,
750 struct svga_screen
*ss
= svga_screen(screen
);
751 SVGA3dSurfaceFormat svga_format
;
752 SVGA3dSurfaceFormatCaps caps
;
753 SVGA3dSurfaceFormatCaps mask
;
757 if (sample_count
> 1) {
758 /* In ms_samples, if bit N is set it means that we support
759 * multisample with N+1 samples per pixel.
761 if ((ss
->ms_samples
& (1 << (sample_count
- 1))) == 0) {
766 svga_format
= svga_translate_format(ss
, format
, bindings
);
767 if (svga_format
== SVGA3D_FORMAT_INVALID
) {
771 if (!ss
->sws
->have_vgpu10
&&
772 util_format_is_srgb(format
) &&
773 (bindings
& PIPE_BIND_DISPLAY_TARGET
)) {
774 /* We only support sRGB rendering with vgpu10 */
779 * For VGPU10 vertex formats, skip querying host capabilities
782 if (ss
->sws
->have_vgpu10
&& (bindings
& PIPE_BIND_VERTEX_BUFFER
)) {
783 SVGA3dSurfaceFormat svga_format
;
785 svga_translate_vertex_format_vgpu10(format
, &svga_format
, &flags
);
786 return svga_format
!= SVGA3D_FORMAT_INVALID
;
790 * Override host capabilities, so that we end up with the same
791 * visuals for all virtual hardware implementations.
794 if (bindings
& PIPE_BIND_DISPLAY_TARGET
) {
795 switch (svga_format
) {
796 case SVGA3D_A8R8G8B8
:
797 case SVGA3D_X8R8G8B8
:
802 case SVGA3D_B8G8R8A8_UNORM
:
803 case SVGA3D_B8G8R8X8_UNORM
:
804 case SVGA3D_B5G6R5_UNORM
:
805 case SVGA3D_B8G8R8X8_UNORM_SRGB
:
806 case SVGA3D_B8G8R8A8_UNORM_SRGB
:
807 case SVGA3D_R8G8B8A8_UNORM_SRGB
:
810 /* Often unsupported/problematic. This means we end up with the same
811 * visuals for all virtual hardware implementations.
813 case SVGA3D_A4R4G4B4
:
814 case SVGA3D_A1R5G5B5
:
823 * Query the host capabilities.
826 svga_get_format_cap(ss
, svga_format
, &caps
);
828 if (bindings
& PIPE_BIND_RENDER_TARGET
) {
829 /* Check that the color surface is blendable, unless it's an
832 if (!svga_format_is_integer(svga_format
) &&
833 (caps
.value
& SVGA3DFORMAT_OP_NOALPHABLEND
)) {
839 if (bindings
& PIPE_BIND_RENDER_TARGET
) {
840 mask
.value
|= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
;
842 if (bindings
& PIPE_BIND_DEPTH_STENCIL
) {
843 mask
.value
|= SVGA3DFORMAT_OP_ZSTENCIL
;
845 if (bindings
& PIPE_BIND_SAMPLER_VIEW
) {
846 mask
.value
|= SVGA3DFORMAT_OP_TEXTURE
;
849 if (target
== PIPE_TEXTURE_CUBE
) {
850 mask
.value
|= SVGA3DFORMAT_OP_CUBETEXTURE
;
852 else if (target
== PIPE_TEXTURE_3D
) {
853 mask
.value
|= SVGA3DFORMAT_OP_VOLUMETEXTURE
;
856 return (caps
.value
& mask
.value
) == mask
.value
;
861 svga_fence_reference(struct pipe_screen
*screen
,
862 struct pipe_fence_handle
**ptr
,
863 struct pipe_fence_handle
*fence
)
865 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
866 sws
->fence_reference(sws
, ptr
, fence
);
871 svga_fence_finish(struct pipe_screen
*screen
,
872 struct pipe_context
*ctx
,
873 struct pipe_fence_handle
*fence
,
876 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
879 SVGA_STATS_TIME_PUSH(sws
, SVGA_STATS_TIME_FENCEFINISH
);
882 retVal
= sws
->fence_signalled(sws
, fence
, 0) == 0;
885 SVGA_DBG(DEBUG_DMA
|DEBUG_PERF
, "%s fence_ptr %p\n",
886 __FUNCTION__
, fence
);
888 retVal
= sws
->fence_finish(sws
, fence
, timeout
, 0) == 0;
891 SVGA_STATS_TIME_POP(sws
);
898 svga_fence_get_fd(struct pipe_screen
*screen
,
899 struct pipe_fence_handle
*fence
)
901 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
903 return sws
->fence_get_fd(sws
, fence
, TRUE
);
908 svga_get_driver_query_info(struct pipe_screen
*screen
,
910 struct pipe_driver_query_info
*info
)
912 #define QUERY(NAME, ENUM, UNITS) \
913 {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
915 static const struct pipe_driver_query_info queries
[] = {
916 /* per-frame counters */
917 QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS
,
918 PIPE_DRIVER_QUERY_TYPE_UINT64
),
919 QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS
,
920 PIPE_DRIVER_QUERY_TYPE_UINT64
),
921 QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES
,
922 PIPE_DRIVER_QUERY_TYPE_UINT64
),
923 QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS
,
924 PIPE_DRIVER_QUERY_TYPE_UINT64
),
925 QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME
,
926 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS
),
927 QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED
,
928 PIPE_DRIVER_QUERY_TYPE_UINT64
),
929 QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED
,
930 PIPE_DRIVER_QUERY_TYPE_UINT64
),
931 QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED
,
932 PIPE_DRIVER_QUERY_TYPE_BYTES
),
933 QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE
,
934 PIPE_DRIVER_QUERY_TYPE_BYTES
),
935 QUERY("flush-time", SVGA_QUERY_FLUSH_TIME
,
936 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS
),
937 QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES
,
938 PIPE_DRIVER_QUERY_TYPE_UINT64
),
939 QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS
,
940 PIPE_DRIVER_QUERY_TYPE_UINT64
),
941 QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES
,
942 PIPE_DRIVER_QUERY_TYPE_UINT64
),
943 QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS
,
944 PIPE_DRIVER_QUERY_TYPE_UINT64
),
945 QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES
,
946 PIPE_DRIVER_QUERY_TYPE_UINT64
),
947 QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES
,
948 PIPE_DRIVER_QUERY_TYPE_UINT64
),
950 /* running total counters */
951 QUERY("memory-used", SVGA_QUERY_MEMORY_USED
,
952 PIPE_DRIVER_QUERY_TYPE_BYTES
),
953 QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS
,
954 PIPE_DRIVER_QUERY_TYPE_UINT64
),
955 QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES
,
956 PIPE_DRIVER_QUERY_TYPE_UINT64
),
957 QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS
,
958 PIPE_DRIVER_QUERY_TYPE_UINT64
),
959 QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS
,
960 PIPE_DRIVER_QUERY_TYPE_UINT64
),
961 QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP
,
962 PIPE_DRIVER_QUERY_TYPE_UINT64
),
963 QUERY("num-failed-allocations", SVGA_QUERY_NUM_FAILED_ALLOCATIONS
,
964 PIPE_DRIVER_QUERY_TYPE_UINT64
),
969 return ARRAY_SIZE(queries
);
971 if (index
>= ARRAY_SIZE(queries
))
974 *info
= queries
[index
];
980 init_logging(struct pipe_screen
*screen
)
982 static const char *log_prefix
= "Mesa: ";
985 /* Log Version to Host */
986 util_snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
987 "%s%s", log_prefix
, svga_get_name(screen
));
988 svga_host_log(host_log
);
990 util_snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
993 " (" MESA_GIT_SHA1
")"
995 , log_prefix
, PACKAGE_VERSION
);
996 svga_host_log(host_log
);
998 /* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
999 * line (program name and arguments).
1001 if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE
)) {
1003 if (os_get_command_line(cmdline
, sizeof(cmdline
))) {
1004 util_snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
1005 "%s%s", log_prefix
, cmdline
);
1006 svga_host_log(host_log
);
1013 svga_destroy_screen( struct pipe_screen
*screen
)
1015 struct svga_screen
*svgascreen
= svga_screen(screen
);
1017 svga_screen_cache_cleanup(svgascreen
);
1019 mtx_destroy(&svgascreen
->swc_mutex
);
1020 mtx_destroy(&svgascreen
->tex_mutex
);
1022 svgascreen
->sws
->destroy(svgascreen
->sws
);
1029 * Create a new svga_screen object
1031 struct pipe_screen
*
1032 svga_screen_create(struct svga_winsys_screen
*sws
)
1034 struct svga_screen
*svgascreen
;
1035 struct pipe_screen
*screen
;
1038 SVGA_DEBUG
= debug_get_flags_option("SVGA_DEBUG", svga_debug_flags
, 0 );
1041 svgascreen
= CALLOC_STRUCT(svga_screen
);
1045 svgascreen
->debug
.force_level_surface_view
=
1046 debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE
);
1047 svgascreen
->debug
.force_surface_view
=
1048 debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE
);
1049 svgascreen
->debug
.force_sampler_view
=
1050 debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE
);
1051 svgascreen
->debug
.no_surface_view
=
1052 debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE
);
1053 svgascreen
->debug
.no_sampler_view
=
1054 debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE
);
1055 svgascreen
->debug
.no_cache_index_buffers
=
1056 debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE
);
1058 screen
= &svgascreen
->screen
;
1060 screen
->destroy
= svga_destroy_screen
;
1061 screen
->get_name
= svga_get_name
;
1062 screen
->get_vendor
= svga_get_vendor
;
1063 screen
->get_device_vendor
= svga_get_vendor
; // TODO actual device vendor
1064 screen
->get_param
= svga_get_param
;
1065 screen
->get_shader_param
= svga_get_shader_param
;
1066 screen
->get_paramf
= svga_get_paramf
;
1067 screen
->get_timestamp
= NULL
;
1068 screen
->is_format_supported
= svga_is_format_supported
;
1069 screen
->context_create
= svga_context_create
;
1070 screen
->fence_reference
= svga_fence_reference
;
1071 screen
->fence_finish
= svga_fence_finish
;
1072 screen
->fence_get_fd
= svga_fence_get_fd
;
1074 screen
->get_driver_query_info
= svga_get_driver_query_info
;
1075 svgascreen
->sws
= sws
;
1077 svga_init_screen_resource_functions(svgascreen
);
1079 if (sws
->get_hw_version
) {
1080 svgascreen
->hw_version
= sws
->get_hw_version(sws
);
1082 svgascreen
->hw_version
= SVGA3D_HWVERSION_WS65_B1
;
1085 if (svgascreen
->hw_version
< SVGA3D_HWVERSION_WS8_B1
) {
1086 /* too old for 3D acceleration */
1087 debug_printf("Hardware version 0x%x is too old for accerated 3D\n",
1088 svgascreen
->hw_version
);
1093 * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
1094 * when sampled from, where as the DF16, DF24, and D24S8_INT do not. So
1095 * we prefer the later when available.
1097 * This mimics hardware vendors extensions for D3D depth sampling. See also
1098 * http://aras-p.info/texts/D3D9GPUHacks.html
1102 boolean has_df16
, has_df24
, has_d24s8_int
;
1103 SVGA3dSurfaceFormatCaps caps
;
1104 SVGA3dSurfaceFormatCaps mask
;
1109 svgascreen
->depth
.z16
= SVGA3D_Z_D16
;
1110 svgascreen
->depth
.x8z24
= SVGA3D_Z_D24X8
;
1111 svgascreen
->depth
.s8z24
= SVGA3D_Z_D24S8
;
1113 svga_get_format_cap(svgascreen
, SVGA3D_Z_DF16
, &caps
);
1114 has_df16
= (caps
.value
& mask
.value
) == mask
.value
;
1116 svga_get_format_cap(svgascreen
, SVGA3D_Z_DF24
, &caps
);
1117 has_df24
= (caps
.value
& mask
.value
) == mask
.value
;
1119 svga_get_format_cap(svgascreen
, SVGA3D_Z_D24S8_INT
, &caps
);
1120 has_d24s8_int
= (caps
.value
& mask
.value
) == mask
.value
;
1122 /* XXX: We might want some other logic here.
1123 * Like if we only have d24s8_int we should
1124 * emulate the other formats with that.
1127 svgascreen
->depth
.z16
= SVGA3D_Z_DF16
;
1130 svgascreen
->depth
.x8z24
= SVGA3D_Z_DF24
;
1132 if (has_d24s8_int
) {
1133 svgascreen
->depth
.s8z24
= SVGA3D_Z_D24S8_INT
;
1137 /* Query device caps
1139 if (sws
->have_vgpu10
) {
1140 svgascreen
->haveProvokingVertex
1141 = get_bool_cap(sws
, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX
, FALSE
);
1142 svgascreen
->haveLineSmooth
= TRUE
;
1143 svgascreen
->maxPointSize
= 80.0F
;
1144 svgascreen
->max_color_buffers
= SVGA3D_DX_MAX_RENDER_TARGETS
;
1146 /* Multisample samples per pixel */
1147 if (debug_get_bool_option("SVGA_MSAA", TRUE
)) {
1148 svgascreen
->ms_samples
=
1149 get_uint_cap(sws
, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES
, 0);
1152 /* We only support 4x, 8x, 16x MSAA */
1153 svgascreen
->ms_samples
&= ((1 << (4-1)) |
1157 /* Maximum number of constant buffers */
1158 svgascreen
->max_const_buffers
=
1159 get_uint_cap(sws
, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS
, 1);
1160 assert(svgascreen
->max_const_buffers
<= SVGA_MAX_CONST_BUFS
);
1164 unsigned vs_ver
= get_uint_cap(sws
, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION
,
1165 SVGA3DVSVERSION_NONE
);
1166 unsigned fs_ver
= get_uint_cap(sws
, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION
,
1167 SVGA3DPSVERSION_NONE
);
1169 /* we require Shader model 3.0 or later */
1170 if (fs_ver
< SVGA3DPSVERSION_30
|| vs_ver
< SVGA3DVSVERSION_30
) {
1174 svgascreen
->haveProvokingVertex
= FALSE
;
1176 svgascreen
->haveLineSmooth
=
1177 get_bool_cap(sws
, SVGA3D_DEVCAP_LINE_AA
, FALSE
);
1179 svgascreen
->maxPointSize
=
1180 get_float_cap(sws
, SVGA3D_DEVCAP_MAX_POINT_SIZE
, 1.0f
);
1181 /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1182 svgascreen
->maxPointSize
= MIN2(svgascreen
->maxPointSize
, 80.0f
);
1184 /* The SVGA3D device always supports 4 targets at this time, regardless
1185 * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1187 svgascreen
->max_color_buffers
= 4;
1189 /* Only support one constant buffer
1191 svgascreen
->max_const_buffers
= 1;
1193 /* No multisampling */
1194 svgascreen
->ms_samples
= 0;
1197 /* common VGPU9 / VGPU10 caps */
1198 svgascreen
->haveLineStipple
=
1199 get_bool_cap(sws
, SVGA3D_DEVCAP_LINE_STIPPLE
, FALSE
);
1201 svgascreen
->maxLineWidth
=
1202 MAX2(1.0, get_float_cap(sws
, SVGA3D_DEVCAP_MAX_LINE_WIDTH
, 1.0f
));
1204 svgascreen
->maxLineWidthAA
=
1205 MAX2(1.0, get_float_cap(sws
, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH
, 1.0f
));
1208 debug_printf("svga: haveProvokingVertex %u\n",
1209 svgascreen
->haveProvokingVertex
);
1210 debug_printf("svga: haveLineStip %u "
1211 "haveLineSmooth %u maxLineWidth %.2f maxLineWidthAA %.2f\n",
1212 svgascreen
->haveLineStipple
, svgascreen
->haveLineSmooth
,
1213 svgascreen
->maxLineWidth
, svgascreen
->maxLineWidthAA
);
1214 debug_printf("svga: maxPointSize %g\n", svgascreen
->maxPointSize
);
1215 debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen
->ms_samples
);
1218 (void) mtx_init(&svgascreen
->tex_mutex
, mtx_plain
);
1219 (void) mtx_init(&svgascreen
->swc_mutex
, mtx_recursive
);
1221 svga_screen_cache_init(svgascreen
);
1223 init_logging(screen
);
1233 struct svga_winsys_screen
*
1234 svga_winsys_screen(struct pipe_screen
*screen
)
1236 return svga_screen(screen
)->sws
;
1241 struct svga_screen
*
1242 svga_screen(struct pipe_screen
*screen
)
1245 assert(screen
->destroy
== svga_destroy_screen
);
1246 return (struct svga_screen
*)screen
;