1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
26 #include "git_sha1.h" /* For MESA_GIT_SHA1 */
27 #include "util/u_format.h"
28 #include "util/u_memory.h"
29 #include "util/u_inlines.h"
30 #include "util/u_screen.h"
31 #include "util/u_string.h"
32 #include "util/u_math.h"
34 #include "os/os_process.h"
36 #include "svga_winsys.h"
37 #include "svga_public.h"
38 #include "svga_context.h"
39 #include "svga_format.h"
41 #include "svga_screen.h"
42 #include "svga_tgsi.h"
43 #include "svga_resource_texture.h"
44 #include "svga_resource.h"
45 #include "svga_debug.h"
47 #include "svga3d_shaderdefs.h"
48 #include "VGPU10ShaderTokens.h"
50 /* NOTE: this constant may get moved into a svga3d*.h header file */
51 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
56 static const struct debug_named_value svga_debug_flags
[] = {
57 { "dma", DEBUG_DMA
, NULL
},
58 { "tgsi", DEBUG_TGSI
, NULL
},
59 { "pipe", DEBUG_PIPE
, NULL
},
60 { "state", DEBUG_STATE
, NULL
},
61 { "screen", DEBUG_SCREEN
, NULL
},
62 { "tex", DEBUG_TEX
, NULL
},
63 { "swtnl", DEBUG_SWTNL
, NULL
},
64 { "const", DEBUG_CONSTS
, NULL
},
65 { "viewport", DEBUG_VIEWPORT
, NULL
},
66 { "views", DEBUG_VIEWS
, NULL
},
67 { "perf", DEBUG_PERF
, NULL
},
68 { "flush", DEBUG_FLUSH
, NULL
},
69 { "sync", DEBUG_SYNC
, NULL
},
70 { "cache", DEBUG_CACHE
, NULL
},
71 { "streamout", DEBUG_STREAMOUT
, NULL
},
72 { "query", DEBUG_QUERY
, NULL
},
73 { "samplers", DEBUG_SAMPLERS
, NULL
},
79 svga_get_vendor( struct pipe_screen
*pscreen
)
81 return "VMware, Inc.";
86 svga_get_name( struct pipe_screen
*pscreen
)
88 const char *build
= "", *llvm
= "", *mutex
= "";
89 static char name
[100];
91 /* Only return internal details in the DEBUG version:
93 build
= "build: DEBUG;";
94 mutex
= "mutex: " PIPE_ATOMIC
";";
95 #elif defined(VMX86_STATS)
96 build
= "build: OPT;";
98 build
= "build: RELEASE;";
104 util_snprintf(name
, sizeof(name
), "SVGA3D; %s %s %s", build
, mutex
, llvm
);
109 /** Helper for querying float-valued device cap */
111 get_float_cap(struct svga_winsys_screen
*sws
, SVGA3dDevCapIndex cap
,
114 SVGA3dDevCapResult result
;
115 if (sws
->get_cap(sws
, cap
, &result
))
122 /** Helper for querying uint-valued device cap */
124 get_uint_cap(struct svga_winsys_screen
*sws
, SVGA3dDevCapIndex cap
,
127 SVGA3dDevCapResult result
;
128 if (sws
->get_cap(sws
, cap
, &result
))
135 /** Helper for querying boolean-valued device cap */
137 get_bool_cap(struct svga_winsys_screen
*sws
, SVGA3dDevCapIndex cap
,
140 SVGA3dDevCapResult result
;
141 if (sws
->get_cap(sws
, cap
, &result
))
149 svga_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
151 struct svga_screen
*svgascreen
= svga_screen(screen
);
152 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
155 case PIPE_CAPF_MAX_LINE_WIDTH
:
156 return svgascreen
->maxLineWidth
;
157 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
158 return svgascreen
->maxLineWidthAA
;
160 case PIPE_CAPF_MAX_POINT_WIDTH
:
162 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
163 return svgascreen
->maxPointSize
;
165 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
166 return (float) get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY
, 4);
168 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
171 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
173 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
175 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
180 debug_printf("Unexpected PIPE_CAPF_ query %u\n", param
);
186 svga_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
188 struct svga_screen
*svgascreen
= svga_screen(screen
);
189 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
190 SVGA3dDevCapResult result
;
193 case PIPE_CAP_NPOT_TEXTURES
:
194 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
195 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
197 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
199 * "In virtually every OpenGL implementation and hardware,
200 * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
201 * http://www.opengl.org/wiki/Blending
203 return sws
->have_vgpu10
? 1 : 0;
204 case PIPE_CAP_ANISOTROPIC_FILTER
:
206 case PIPE_CAP_POINT_SPRITE
:
208 case PIPE_CAP_TGSI_TEXCOORD
:
210 case PIPE_CAP_MAX_RENDER_TARGETS
:
211 return svgascreen
->max_color_buffers
;
212 case PIPE_CAP_OCCLUSION_QUERY
:
214 case PIPE_CAP_QUERY_TIME_ELAPSED
:
216 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
217 return sws
->have_vgpu10
;
218 case PIPE_CAP_TEXTURE_SWIZZLE
:
220 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
222 case PIPE_CAP_USER_VERTEX_BUFFERS
:
224 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
227 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
229 unsigned levels
= SVGA_MAX_TEXTURE_LEVELS
;
230 if (sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH
, &result
))
231 levels
= MIN2(util_logbase2(result
.u
) + 1, levels
);
233 levels
= 12 /* 2048x2048 */;
234 if (sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT
, &result
))
235 levels
= MIN2(util_logbase2(result
.u
) + 1, levels
);
237 levels
= 12 /* 2048x2048 */;
241 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
242 if (!sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT
, &result
))
243 return 8; /* max 128x128x128 */
244 return MIN2(util_logbase2(result
.u
) + 1, SVGA_MAX_TEXTURE_LEVELS
);
246 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
248 * No mechanism to query the host, and at least limited to 2048x2048 on
251 return MIN2(screen
->get_param(screen
, PIPE_CAP_MAX_TEXTURE_2D_LEVELS
),
254 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
255 return sws
->have_vgpu10
? SVGA3D_MAX_SURFACE_ARRAYSIZE
: 0;
257 case PIPE_CAP_BLEND_EQUATION_SEPARATE
: /* req. for GL 1.5 */
260 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
262 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
263 return sws
->have_vgpu10
;
264 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
266 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
267 return !sws
->have_vgpu10
;
269 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
270 return 1; /* The color outputs of vertex shaders are not clamped */
271 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
272 return 0; /* The driver can't clamp vertex colors */
273 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
274 return 0; /* The driver can't clamp fragment colors */
276 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
277 return 1; /* expected for GL_ARB_framebuffer_object */
279 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
280 return sws
->have_vgpu10
? 330 : 120;
282 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
283 return sws
->have_vgpu10
? 140 : 120;
285 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
286 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
292 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
293 case PIPE_CAP_INDEP_BLEND_ENABLE
:
294 case PIPE_CAP_CONDITIONAL_RENDER
:
295 case PIPE_CAP_QUERY_TIMESTAMP
:
296 case PIPE_CAP_TGSI_INSTANCEID
:
297 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
298 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
299 case PIPE_CAP_FAKE_SW_MSAA
:
300 return sws
->have_vgpu10
;
302 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
303 return sws
->have_vgpu10
? SVGA3D_DX_MAX_SOTARGETS
: 0;
304 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
305 return sws
->have_vgpu10
? 4 : 0;
306 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
307 return sws
->have_vgpu10
? SVGA3D_MAX_STREAMOUT_DECLS
: 0;
308 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
309 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
311 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
312 return svgascreen
->ms_samples
? 1 : 0;
314 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
315 /* convert bytes to texels for the case of the largest texel
318 return SVGA3D_DX_MAX_RESOURCE_SIZE
/ (4 * sizeof(float));
320 case PIPE_CAP_MIN_TEXEL_OFFSET
:
321 return sws
->have_vgpu10
? VGPU10_MIN_TEXEL_FETCH_OFFSET
: 0;
322 case PIPE_CAP_MAX_TEXEL_OFFSET
:
323 return sws
->have_vgpu10
? VGPU10_MAX_TEXEL_FETCH_OFFSET
: 0;
325 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
326 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
329 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
330 return sws
->have_vgpu10
? 256 : 0;
331 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
332 return sws
->have_vgpu10
? 1024 : 0;
334 case PIPE_CAP_PRIMITIVE_RESTART
:
335 return 1; /* may be a sw fallback, depending on restart index */
337 case PIPE_CAP_GENERATE_MIPMAP
:
338 return sws
->have_generate_mipmap_cmd
;
340 case PIPE_CAP_NATIVE_FENCE_FD
:
341 return sws
->have_fence_fd
;
343 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
346 /* Unsupported features */
347 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
348 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
:
349 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
350 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
351 case PIPE_CAP_INDEP_BLEND_FUNC
:
352 case PIPE_CAP_TEXTURE_BARRIER
:
353 case PIPE_CAP_MAX_VERTEX_STREAMS
:
354 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
355 case PIPE_CAP_COMPUTE
:
356 case PIPE_CAP_START_INSTANCE
:
357 case PIPE_CAP_CUBE_MAP_ARRAY
:
358 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
359 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
360 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
361 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
362 case PIPE_CAP_TEXTURE_GATHER_SM5
:
363 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
364 case PIPE_CAP_TEXTURE_QUERY_LOD
:
365 case PIPE_CAP_SAMPLE_SHADING
:
366 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
367 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
368 case PIPE_CAP_DRAW_INDIRECT
:
369 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
370 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
371 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
372 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
373 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
374 case PIPE_CAP_CLIP_HALFZ
:
375 case PIPE_CAP_VERTEXID_NOBASE
:
376 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
377 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
378 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
379 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
380 case PIPE_CAP_INVALIDATE_BUFFER
:
381 case PIPE_CAP_STRING_MARKER
:
382 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
383 case PIPE_CAP_QUERY_MEMORY_INFO
:
384 case PIPE_CAP_PCI_GROUP
:
385 case PIPE_CAP_PCI_BUS
:
386 case PIPE_CAP_PCI_DEVICE
:
387 case PIPE_CAP_PCI_FUNCTION
:
388 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
389 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES
:
390 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES
:
391 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES
:
392 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES
:
393 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE
:
394 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS
:
396 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
398 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
399 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
400 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
401 return 1; /* need 4-byte alignment for all offsets and strides */
402 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
404 case PIPE_CAP_MAX_VIEWPORTS
:
406 case PIPE_CAP_ENDIANNESS
:
407 return PIPE_ENDIAN_LITTLE
;
409 case PIPE_CAP_VENDOR_ID
:
410 return 0x15ad; /* VMware Inc. */
411 case PIPE_CAP_DEVICE_ID
:
412 return 0x0405; /* assume SVGA II */
413 case PIPE_CAP_ACCELERATED
:
415 case PIPE_CAP_VIDEO_MEMORY
:
416 /* XXX: Query the host ? */
418 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
419 return sws
->have_vgpu10
;
420 case PIPE_CAP_CLEAR_TEXTURE
:
421 return sws
->have_vgpu10
;
423 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
424 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
425 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
426 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
427 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
428 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
429 case PIPE_CAP_TGSI_TXQS
:
430 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
431 case PIPE_CAP_SHAREABLE_SHADERS
:
432 case PIPE_CAP_DRAW_PARAMETERS
:
433 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
434 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
435 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
436 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
437 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
438 case PIPE_CAP_CULL_DISTANCE
:
439 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
440 case PIPE_CAP_TGSI_VOTE
:
441 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
442 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
443 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
444 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
445 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
446 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
447 case PIPE_CAP_TGSI_FS_FBFETCH
:
448 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
449 case PIPE_CAP_DOUBLES
:
451 case PIPE_CAP_INT64_DIVMOD
:
452 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
453 case PIPE_CAP_TGSI_CLOCK
:
454 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
455 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
456 case PIPE_CAP_TGSI_BALLOT
:
457 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
458 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
459 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
460 case PIPE_CAP_POST_DEPTH_COVERAGE
:
461 case PIPE_CAP_BINDLESS_TEXTURE
:
462 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
463 case PIPE_CAP_QUERY_SO_OVERFLOW
:
464 case PIPE_CAP_MEMOBJ
:
465 case PIPE_CAP_LOAD_CONSTBUF
:
466 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
467 case PIPE_CAP_TILE_RASTER_ORDER
:
468 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
469 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS
:
470 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
471 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
472 case PIPE_CAP_FENCE_SIGNAL
:
473 case PIPE_CAP_CONSTBUF0_FLAGS
:
474 case PIPE_CAP_PACKED_UNIFORMS
:
475 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS
:
477 case PIPE_CAP_MAX_GS_INVOCATIONS
:
479 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
482 return u_pipe_screen_get_param_defaults(screen
, param
);
488 vgpu9_get_shader_param(struct pipe_screen
*screen
,
489 enum pipe_shader_type shader
,
490 enum pipe_shader_cap param
)
492 struct svga_screen
*svgascreen
= svga_screen(screen
);
493 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
496 assert(!sws
->have_vgpu10
);
500 case PIPE_SHADER_FRAGMENT
:
503 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
504 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
505 return get_uint_cap(sws
,
506 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS
,
508 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
509 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
511 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
512 return SVGA3D_MAX_NESTING_LEVEL
;
513 case PIPE_SHADER_CAP_MAX_INPUTS
:
515 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
516 return svgascreen
->max_color_buffers
;
517 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
518 return 224 * sizeof(float[4]);
519 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
521 case PIPE_SHADER_CAP_MAX_TEMPS
:
522 val
= get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS
, 32);
523 return MIN2(val
, SVGA3D_TEMPREG_MAX
);
524 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
526 * Although PS 3.0 has some addressing abilities it can only represent
527 * loops that can be statically determined and unrolled. Given we can
528 * only handle a subset of the cases that the state tracker already
529 * does it is better to defer loop unrolling to the state tracker.
532 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
534 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
536 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
537 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
538 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
540 case PIPE_SHADER_CAP_SUBROUTINES
:
542 case PIPE_SHADER_CAP_INT64_ATOMICS
:
543 case PIPE_SHADER_CAP_INTEGERS
:
545 case PIPE_SHADER_CAP_FP16
:
547 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
548 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
550 case PIPE_SHADER_CAP_PREFERRED_IR
:
551 return PIPE_SHADER_IR_TGSI
;
552 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
554 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
555 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
556 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
557 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
558 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
559 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
560 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
561 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
562 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
563 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
564 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
566 case PIPE_SHADER_CAP_SCALAR_ISA
:
568 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
571 /* If we get here, we failed to handle a cap above */
572 debug_printf("Unexpected fragment shader query %u\n", param
);
574 case PIPE_SHADER_VERTEX
:
577 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
578 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
579 return get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS
,
581 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
582 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
583 /* XXX: until we have vertex texture support */
585 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
586 return SVGA3D_MAX_NESTING_LEVEL
;
587 case PIPE_SHADER_CAP_MAX_INPUTS
:
589 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
591 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
592 return 256 * sizeof(float[4]);
593 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
595 case PIPE_SHADER_CAP_MAX_TEMPS
:
596 val
= get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS
, 32);
597 return MIN2(val
, SVGA3D_TEMPREG_MAX
);
598 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
600 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
602 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
603 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
605 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
607 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
609 case PIPE_SHADER_CAP_SUBROUTINES
:
611 case PIPE_SHADER_CAP_INT64_ATOMICS
:
612 case PIPE_SHADER_CAP_INTEGERS
:
614 case PIPE_SHADER_CAP_FP16
:
616 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
617 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
619 case PIPE_SHADER_CAP_PREFERRED_IR
:
620 return PIPE_SHADER_IR_TGSI
;
621 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
623 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
624 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
625 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
626 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
627 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
628 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
629 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
630 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
631 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
632 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
633 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
635 case PIPE_SHADER_CAP_SCALAR_ISA
:
637 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
640 /* If we get here, we failed to handle a cap above */
641 debug_printf("Unexpected vertex shader query %u\n", param
);
643 case PIPE_SHADER_GEOMETRY
:
644 case PIPE_SHADER_COMPUTE
:
645 case PIPE_SHADER_TESS_CTRL
:
646 case PIPE_SHADER_TESS_EVAL
:
647 /* no support for geometry, tess or compute shaders at this time */
650 debug_printf("Unexpected shader type (%u) query\n", shader
);
658 vgpu10_get_shader_param(struct pipe_screen
*screen
,
659 enum pipe_shader_type shader
,
660 enum pipe_shader_cap param
)
662 struct svga_screen
*svgascreen
= svga_screen(screen
);
663 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
665 assert(sws
->have_vgpu10
);
666 (void) sws
; /* silence unused var warnings in non-debug builds */
668 /* Only VS, GS, FS supported */
669 if (shader
!= PIPE_SHADER_VERTEX
&&
670 shader
!= PIPE_SHADER_GEOMETRY
&&
671 shader
!= PIPE_SHADER_FRAGMENT
) {
675 /* NOTE: we do not query the device for any caps/limits at this time */
677 /* Generally the same limits for vertex, geometry and fragment shaders */
679 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
680 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
681 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
682 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
684 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
686 case PIPE_SHADER_CAP_MAX_INPUTS
:
687 if (shader
== PIPE_SHADER_FRAGMENT
)
688 return VGPU10_MAX_FS_INPUTS
;
689 else if (shader
== PIPE_SHADER_GEOMETRY
)
690 return VGPU10_MAX_GS_INPUTS
;
692 return VGPU10_MAX_VS_INPUTS
;
693 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
694 if (shader
== PIPE_SHADER_FRAGMENT
)
695 return VGPU10_MAX_FS_OUTPUTS
;
696 else if (shader
== PIPE_SHADER_GEOMETRY
)
697 return VGPU10_MAX_GS_OUTPUTS
;
699 return VGPU10_MAX_VS_OUTPUTS
;
700 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
701 return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT
* sizeof(float[4]);
702 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
703 return svgascreen
->max_const_buffers
;
704 case PIPE_SHADER_CAP_MAX_TEMPS
:
705 return VGPU10_MAX_TEMPS
;
706 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
707 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
708 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
709 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
710 return TRUE
; /* XXX verify */
711 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
712 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
713 case PIPE_SHADER_CAP_SUBROUTINES
:
714 case PIPE_SHADER_CAP_INTEGERS
:
716 case PIPE_SHADER_CAP_FP16
:
718 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
719 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
720 return SVGA3D_DX_MAX_SAMPLERS
;
721 case PIPE_SHADER_CAP_PREFERRED_IR
:
722 return PIPE_SHADER_IR_TGSI
;
723 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
725 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
726 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
727 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
728 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
729 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
730 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
731 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
732 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
733 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
734 case PIPE_SHADER_CAP_INT64_ATOMICS
:
735 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
736 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
738 case PIPE_SHADER_CAP_SCALAR_ISA
:
740 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
743 debug_printf("Unexpected vgpu10 shader query %u\n", param
);
751 svga_get_shader_param(struct pipe_screen
*screen
, enum pipe_shader_type shader
,
752 enum pipe_shader_cap param
)
754 struct svga_screen
*svgascreen
= svga_screen(screen
);
755 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
756 if (sws
->have_vgpu10
) {
757 return vgpu10_get_shader_param(screen
, shader
, param
);
760 return vgpu9_get_shader_param(screen
, shader
, param
);
766 svga_fence_reference(struct pipe_screen
*screen
,
767 struct pipe_fence_handle
**ptr
,
768 struct pipe_fence_handle
*fence
)
770 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
771 sws
->fence_reference(sws
, ptr
, fence
);
776 svga_fence_finish(struct pipe_screen
*screen
,
777 struct pipe_context
*ctx
,
778 struct pipe_fence_handle
*fence
,
781 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
784 SVGA_STATS_TIME_PUSH(sws
, SVGA_STATS_TIME_FENCEFINISH
);
787 retVal
= sws
->fence_signalled(sws
, fence
, 0) == 0;
790 SVGA_DBG(DEBUG_DMA
|DEBUG_PERF
, "%s fence_ptr %p\n",
791 __FUNCTION__
, fence
);
793 retVal
= sws
->fence_finish(sws
, fence
, timeout
, 0) == 0;
796 SVGA_STATS_TIME_POP(sws
);
803 svga_fence_get_fd(struct pipe_screen
*screen
,
804 struct pipe_fence_handle
*fence
)
806 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
808 return sws
->fence_get_fd(sws
, fence
, TRUE
);
813 svga_get_driver_query_info(struct pipe_screen
*screen
,
815 struct pipe_driver_query_info
*info
)
817 #define QUERY(NAME, ENUM, UNITS) \
818 {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
820 static const struct pipe_driver_query_info queries
[] = {
821 /* per-frame counters */
822 QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS
,
823 PIPE_DRIVER_QUERY_TYPE_UINT64
),
824 QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS
,
825 PIPE_DRIVER_QUERY_TYPE_UINT64
),
826 QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES
,
827 PIPE_DRIVER_QUERY_TYPE_UINT64
),
828 QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS
,
829 PIPE_DRIVER_QUERY_TYPE_UINT64
),
830 QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME
,
831 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS
),
832 QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED
,
833 PIPE_DRIVER_QUERY_TYPE_UINT64
),
834 QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED
,
835 PIPE_DRIVER_QUERY_TYPE_UINT64
),
836 QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED
,
837 PIPE_DRIVER_QUERY_TYPE_BYTES
),
838 QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE
,
839 PIPE_DRIVER_QUERY_TYPE_BYTES
),
840 QUERY("flush-time", SVGA_QUERY_FLUSH_TIME
,
841 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS
),
842 QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES
,
843 PIPE_DRIVER_QUERY_TYPE_UINT64
),
844 QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS
,
845 PIPE_DRIVER_QUERY_TYPE_UINT64
),
846 QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES
,
847 PIPE_DRIVER_QUERY_TYPE_UINT64
),
848 QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS
,
849 PIPE_DRIVER_QUERY_TYPE_UINT64
),
850 QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES
,
851 PIPE_DRIVER_QUERY_TYPE_UINT64
),
852 QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES
,
853 PIPE_DRIVER_QUERY_TYPE_UINT64
),
855 /* running total counters */
856 QUERY("memory-used", SVGA_QUERY_MEMORY_USED
,
857 PIPE_DRIVER_QUERY_TYPE_BYTES
),
858 QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS
,
859 PIPE_DRIVER_QUERY_TYPE_UINT64
),
860 QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES
,
861 PIPE_DRIVER_QUERY_TYPE_UINT64
),
862 QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS
,
863 PIPE_DRIVER_QUERY_TYPE_UINT64
),
864 QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS
,
865 PIPE_DRIVER_QUERY_TYPE_UINT64
),
866 QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP
,
867 PIPE_DRIVER_QUERY_TYPE_UINT64
),
868 QUERY("num-failed-allocations", SVGA_QUERY_NUM_FAILED_ALLOCATIONS
,
869 PIPE_DRIVER_QUERY_TYPE_UINT64
),
870 QUERY("num-commands-per-draw", SVGA_QUERY_NUM_COMMANDS_PER_DRAW
,
871 PIPE_DRIVER_QUERY_TYPE_FLOAT
),
876 return ARRAY_SIZE(queries
);
878 if (index
>= ARRAY_SIZE(queries
))
881 *info
= queries
[index
];
887 init_logging(struct pipe_screen
*screen
)
889 static const char *log_prefix
= "Mesa: ";
892 /* Log Version to Host */
893 util_snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
894 "%s%s", log_prefix
, svga_get_name(screen
));
895 svga_host_log(host_log
);
897 util_snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
898 "%s" PACKAGE_VERSION MESA_GIT_SHA1
, log_prefix
);
899 svga_host_log(host_log
);
901 /* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
902 * line (program name and arguments).
904 if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE
)) {
906 if (os_get_command_line(cmdline
, sizeof(cmdline
))) {
907 util_snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
908 "%s%s", log_prefix
, cmdline
);
909 svga_host_log(host_log
);
916 svga_destroy_screen( struct pipe_screen
*screen
)
918 struct svga_screen
*svgascreen
= svga_screen(screen
);
920 svga_screen_cache_cleanup(svgascreen
);
922 mtx_destroy(&svgascreen
->swc_mutex
);
923 mtx_destroy(&svgascreen
->tex_mutex
);
925 svgascreen
->sws
->destroy(svgascreen
->sws
);
932 * Create a new svga_screen object
935 svga_screen_create(struct svga_winsys_screen
*sws
)
937 struct svga_screen
*svgascreen
;
938 struct pipe_screen
*screen
;
941 SVGA_DEBUG
= debug_get_flags_option("SVGA_DEBUG", svga_debug_flags
, 0 );
944 svgascreen
= CALLOC_STRUCT(svga_screen
);
948 svgascreen
->debug
.force_level_surface_view
=
949 debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE
);
950 svgascreen
->debug
.force_surface_view
=
951 debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE
);
952 svgascreen
->debug
.force_sampler_view
=
953 debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE
);
954 svgascreen
->debug
.no_surface_view
=
955 debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE
);
956 svgascreen
->debug
.no_sampler_view
=
957 debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE
);
958 svgascreen
->debug
.no_cache_index_buffers
=
959 debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE
);
961 screen
= &svgascreen
->screen
;
963 screen
->destroy
= svga_destroy_screen
;
964 screen
->get_name
= svga_get_name
;
965 screen
->get_vendor
= svga_get_vendor
;
966 screen
->get_device_vendor
= svga_get_vendor
; // TODO actual device vendor
967 screen
->get_param
= svga_get_param
;
968 screen
->get_shader_param
= svga_get_shader_param
;
969 screen
->get_paramf
= svga_get_paramf
;
970 screen
->get_timestamp
= NULL
;
971 screen
->is_format_supported
= svga_is_format_supported
;
972 screen
->context_create
= svga_context_create
;
973 screen
->fence_reference
= svga_fence_reference
;
974 screen
->fence_finish
= svga_fence_finish
;
975 screen
->fence_get_fd
= svga_fence_get_fd
;
977 screen
->get_driver_query_info
= svga_get_driver_query_info
;
978 svgascreen
->sws
= sws
;
980 svga_init_screen_resource_functions(svgascreen
);
982 if (sws
->get_hw_version
) {
983 svgascreen
->hw_version
= sws
->get_hw_version(sws
);
985 svgascreen
->hw_version
= SVGA3D_HWVERSION_WS65_B1
;
988 if (svgascreen
->hw_version
< SVGA3D_HWVERSION_WS8_B1
) {
989 /* too old for 3D acceleration */
990 debug_printf("Hardware version 0x%x is too old for accerated 3D\n",
991 svgascreen
->hw_version
);
996 * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
997 * when sampled from, where as the DF16, DF24, and D24S8_INT do not. So
998 * we prefer the later when available.
1000 * This mimics hardware vendors extensions for D3D depth sampling. See also
1001 * http://aras-p.info/texts/D3D9GPUHacks.html
1005 boolean has_df16
, has_df24
, has_d24s8_int
;
1006 SVGA3dSurfaceFormatCaps caps
;
1007 SVGA3dSurfaceFormatCaps mask
;
1012 svgascreen
->depth
.z16
= SVGA3D_Z_D16
;
1013 svgascreen
->depth
.x8z24
= SVGA3D_Z_D24X8
;
1014 svgascreen
->depth
.s8z24
= SVGA3D_Z_D24S8
;
1016 svga_get_format_cap(svgascreen
, SVGA3D_Z_DF16
, &caps
);
1017 has_df16
= (caps
.value
& mask
.value
) == mask
.value
;
1019 svga_get_format_cap(svgascreen
, SVGA3D_Z_DF24
, &caps
);
1020 has_df24
= (caps
.value
& mask
.value
) == mask
.value
;
1022 svga_get_format_cap(svgascreen
, SVGA3D_Z_D24S8_INT
, &caps
);
1023 has_d24s8_int
= (caps
.value
& mask
.value
) == mask
.value
;
1025 /* XXX: We might want some other logic here.
1026 * Like if we only have d24s8_int we should
1027 * emulate the other formats with that.
1030 svgascreen
->depth
.z16
= SVGA3D_Z_DF16
;
1033 svgascreen
->depth
.x8z24
= SVGA3D_Z_DF24
;
1035 if (has_d24s8_int
) {
1036 svgascreen
->depth
.s8z24
= SVGA3D_Z_D24S8_INT
;
1040 /* Query device caps
1042 if (sws
->have_vgpu10
) {
1043 svgascreen
->haveProvokingVertex
1044 = get_bool_cap(sws
, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX
, FALSE
);
1045 svgascreen
->haveLineSmooth
= TRUE
;
1046 svgascreen
->maxPointSize
= 80.0F
;
1047 svgascreen
->max_color_buffers
= SVGA3D_DX_MAX_RENDER_TARGETS
;
1049 /* Maximum number of constant buffers */
1050 svgascreen
->max_const_buffers
=
1051 get_uint_cap(sws
, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS
, 1);
1052 assert(svgascreen
->max_const_buffers
<= SVGA_MAX_CONST_BUFS
);
1056 unsigned vs_ver
= get_uint_cap(sws
, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION
,
1057 SVGA3DVSVERSION_NONE
);
1058 unsigned fs_ver
= get_uint_cap(sws
, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION
,
1059 SVGA3DPSVERSION_NONE
);
1061 /* we require Shader model 3.0 or later */
1062 if (fs_ver
< SVGA3DPSVERSION_30
|| vs_ver
< SVGA3DVSVERSION_30
) {
1066 svgascreen
->haveProvokingVertex
= FALSE
;
1068 svgascreen
->haveLineSmooth
=
1069 get_bool_cap(sws
, SVGA3D_DEVCAP_LINE_AA
, FALSE
);
1071 svgascreen
->maxPointSize
=
1072 get_float_cap(sws
, SVGA3D_DEVCAP_MAX_POINT_SIZE
, 1.0f
);
1073 /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1074 svgascreen
->maxPointSize
= MIN2(svgascreen
->maxPointSize
, 80.0f
);
1076 /* The SVGA3D device always supports 4 targets at this time, regardless
1077 * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1079 svgascreen
->max_color_buffers
= 4;
1081 /* Only support one constant buffer
1083 svgascreen
->max_const_buffers
= 1;
1085 /* No multisampling */
1086 svgascreen
->ms_samples
= 0;
1089 /* common VGPU9 / VGPU10 caps */
1090 svgascreen
->haveLineStipple
=
1091 get_bool_cap(sws
, SVGA3D_DEVCAP_LINE_STIPPLE
, FALSE
);
1093 svgascreen
->maxLineWidth
=
1094 MAX2(1.0, get_float_cap(sws
, SVGA3D_DEVCAP_MAX_LINE_WIDTH
, 1.0f
));
1096 svgascreen
->maxLineWidthAA
=
1097 MAX2(1.0, get_float_cap(sws
, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH
, 1.0f
));
1100 debug_printf("svga: haveProvokingVertex %u\n",
1101 svgascreen
->haveProvokingVertex
);
1102 debug_printf("svga: haveLineStip %u "
1103 "haveLineSmooth %u maxLineWidth %.2f maxLineWidthAA %.2f\n",
1104 svgascreen
->haveLineStipple
, svgascreen
->haveLineSmooth
,
1105 svgascreen
->maxLineWidth
, svgascreen
->maxLineWidthAA
);
1106 debug_printf("svga: maxPointSize %g\n", svgascreen
->maxPointSize
);
1107 debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen
->ms_samples
);
1110 (void) mtx_init(&svgascreen
->tex_mutex
, mtx_plain
);
1111 (void) mtx_init(&svgascreen
->swc_mutex
, mtx_recursive
);
1113 svga_screen_cache_init(svgascreen
);
1115 init_logging(screen
);
1125 struct svga_winsys_screen
*
1126 svga_winsys_screen(struct pipe_screen
*screen
)
1128 return svga_screen(screen
)->sws
;
1133 struct svga_screen
*
1134 svga_screen(struct pipe_screen
*screen
)
1137 assert(screen
->destroy
== svga_destroy_screen
);
1138 return (struct svga_screen
*)screen
;