2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "tgsi/tgsi_dump.h"
32 #include "tgsi/tgsi_info.h"
34 #include "vc4_context.h"
37 #ifdef USE_VC4_SIMULATOR
38 #include "simpenrose/simpenrose.h"
42 struct pipe_shader_state
*shader_state
;
44 enum pipe_format format
;
45 unsigned compare_mode
:1;
46 unsigned compare_func
:3;
48 } tex
[VC4_MAX_TEXTURE_SAMPLERS
];
53 enum pipe_format color_format
;
58 struct pipe_rt_blend_state blend
;
63 enum pipe_format attr_formats
[8];
67 add_uniform(struct vc4_compile
*c
,
68 enum quniform_contents contents
,
71 uint32_t uniform
= c
->num_uniforms
++;
72 struct qreg u
= { QFILE_UNIF
, uniform
};
74 c
->uniform_contents
[uniform
] = contents
;
75 c
->uniform_data
[uniform
] = data
;
81 get_temp_for_uniform(struct vc4_compile
*c
, enum quniform_contents contents
,
84 for (int i
= 0; i
< c
->num_uniforms
; i
++) {
85 if (c
->uniform_contents
[i
] == contents
&&
86 c
->uniform_data
[i
] == data
)
87 return c
->uniforms
[i
];
90 struct qreg u
= add_uniform(c
, contents
, data
);
91 struct qreg t
= qir_MOV(c
, u
);
93 c
->uniforms
[u
.index
] = t
;
98 qir_uniform_ui(struct vc4_compile
*c
, uint32_t ui
)
100 return get_temp_for_uniform(c
, QUNIFORM_CONSTANT
, ui
);
104 qir_uniform_f(struct vc4_compile
*c
, float f
)
106 return qir_uniform_ui(c
, fui(f
));
110 get_src(struct vc4_compile
*c
, unsigned tgsi_op
,
111 struct tgsi_src_register
*src
, int i
)
113 struct qreg r
= c
->undef
;
133 assert(!src
->Indirect
);
138 case TGSI_FILE_TEMPORARY
:
139 r
= c
->temps
[src
->Index
* 4 + s
];
141 case TGSI_FILE_IMMEDIATE
:
142 r
= c
->consts
[src
->Index
* 4 + s
];
144 case TGSI_FILE_CONSTANT
:
145 r
= get_temp_for_uniform(c
, QUNIFORM_UNIFORM
,
148 case TGSI_FILE_INPUT
:
149 r
= c
->inputs
[src
->Index
* 4 + s
];
151 case TGSI_FILE_SAMPLER
:
152 case TGSI_FILE_SAMPLER_VIEW
:
156 fprintf(stderr
, "unknown src file %d\n", src
->File
);
161 r
= qir_FMAXABS(c
, r
, r
);
164 switch (tgsi_opcode_infer_src_type(tgsi_op
)) {
165 case TGSI_TYPE_SIGNED
:
166 case TGSI_TYPE_UNSIGNED
:
167 r
= qir_SUB(c
, qir_uniform_ui(c
, 0), r
);
170 r
= qir_FSUB(c
, qir_uniform_f(c
, 0.0), r
);
180 update_dst(struct vc4_compile
*c
, struct tgsi_full_instruction
*tgsi_inst
,
181 int i
, struct qreg val
)
183 struct tgsi_dst_register
*tgsi_dst
= &tgsi_inst
->Dst
[0].Register
;
185 assert(!tgsi_dst
->Indirect
);
187 switch (tgsi_dst
->File
) {
188 case TGSI_FILE_TEMPORARY
:
189 c
->temps
[tgsi_dst
->Index
* 4 + i
] = val
;
191 case TGSI_FILE_OUTPUT
:
192 c
->outputs
[tgsi_dst
->Index
* 4 + i
] = val
;
193 c
->num_outputs
= MAX2(c
->num_outputs
,
194 tgsi_dst
->Index
* 4 + i
+ 1);
197 fprintf(stderr
, "unknown dst file %d\n", tgsi_dst
->File
);
203 get_swizzled_channel(struct vc4_compile
*c
,
204 struct qreg
*srcs
, int swiz
)
208 case UTIL_FORMAT_SWIZZLE_NONE
:
209 fprintf(stderr
, "warning: unknown swizzle\n");
211 case UTIL_FORMAT_SWIZZLE_0
:
212 return qir_uniform_f(c
, 0.0);
213 case UTIL_FORMAT_SWIZZLE_1
:
214 return qir_uniform_f(c
, 1.0);
215 case UTIL_FORMAT_SWIZZLE_X
:
216 case UTIL_FORMAT_SWIZZLE_Y
:
217 case UTIL_FORMAT_SWIZZLE_Z
:
218 case UTIL_FORMAT_SWIZZLE_W
:
224 tgsi_to_qir_alu(struct vc4_compile
*c
,
225 struct tgsi_full_instruction
*tgsi_inst
,
226 enum qop op
, struct qreg
*src
, int i
)
228 struct qreg dst
= qir_get_temp(c
);
229 qir_emit(c
, qir_inst4(op
, dst
,
238 tgsi_to_qir_umul(struct vc4_compile
*c
,
239 struct tgsi_full_instruction
*tgsi_inst
,
240 enum qop op
, struct qreg
*src
, int i
)
242 struct qreg src0_hi
= qir_SHR(c
, src
[0 * 4 + i
],
243 qir_uniform_ui(c
, 16));
244 struct qreg src0_lo
= qir_AND(c
, src
[0 * 4 + i
],
245 qir_uniform_ui(c
, 0xffff));
246 struct qreg src1_hi
= qir_SHR(c
, src
[1 * 4 + i
],
247 qir_uniform_ui(c
, 16));
248 struct qreg src1_lo
= qir_AND(c
, src
[1 * 4 + i
],
249 qir_uniform_ui(c
, 0xffff));
251 struct qreg hilo
= qir_MUL24(c
, src0_hi
, src1_lo
);
252 struct qreg lohi
= qir_MUL24(c
, src0_lo
, src1_hi
);
253 struct qreg lolo
= qir_MUL24(c
, src0_lo
, src1_lo
);
255 return qir_ADD(c
, lolo
, qir_SHL(c
,
256 qir_ADD(c
, hilo
, lohi
),
257 qir_uniform_ui(c
, 16)));
261 tgsi_to_qir_idiv(struct vc4_compile
*c
,
262 struct tgsi_full_instruction
*tgsi_inst
,
263 enum qop op
, struct qreg
*src
, int i
)
265 return qir_FTOI(c
, qir_FMUL(c
,
266 qir_ITOF(c
, src
[0 * 4 + i
]),
267 qir_RCP(c
, qir_ITOF(c
, src
[1 * 4 + i
]))));
271 tgsi_to_qir_ineg(struct vc4_compile
*c
,
272 struct tgsi_full_instruction
*tgsi_inst
,
273 enum qop op
, struct qreg
*src
, int i
)
275 return qir_SUB(c
, qir_uniform_ui(c
, 0), src
[0 * 4 + i
]);
279 tgsi_to_qir_seq(struct vc4_compile
*c
,
280 struct tgsi_full_instruction
*tgsi_inst
,
281 enum qop op
, struct qreg
*src
, int i
)
283 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
284 return qir_SEL_X_0_ZS(c
, qir_uniform_f(c
, 1.0));
288 tgsi_to_qir_sne(struct vc4_compile
*c
,
289 struct tgsi_full_instruction
*tgsi_inst
,
290 enum qop op
, struct qreg
*src
, int i
)
292 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
293 return qir_SEL_X_0_ZC(c
, qir_uniform_f(c
, 1.0));
297 tgsi_to_qir_slt(struct vc4_compile
*c
,
298 struct tgsi_full_instruction
*tgsi_inst
,
299 enum qop op
, struct qreg
*src
, int i
)
301 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
302 return qir_SEL_X_0_NS(c
, qir_uniform_f(c
, 1.0));
306 tgsi_to_qir_sge(struct vc4_compile
*c
,
307 struct tgsi_full_instruction
*tgsi_inst
,
308 enum qop op
, struct qreg
*src
, int i
)
310 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
311 return qir_SEL_X_0_NC(c
, qir_uniform_f(c
, 1.0));
315 tgsi_to_qir_fseq(struct vc4_compile
*c
,
316 struct tgsi_full_instruction
*tgsi_inst
,
317 enum qop op
, struct qreg
*src
, int i
)
319 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
320 return qir_SEL_X_0_ZS(c
, qir_uniform_ui(c
, ~0));
324 tgsi_to_qir_fsne(struct vc4_compile
*c
,
325 struct tgsi_full_instruction
*tgsi_inst
,
326 enum qop op
, struct qreg
*src
, int i
)
328 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
329 return qir_SEL_X_0_ZC(c
, qir_uniform_ui(c
, ~0));
333 tgsi_to_qir_fslt(struct vc4_compile
*c
,
334 struct tgsi_full_instruction
*tgsi_inst
,
335 enum qop op
, struct qreg
*src
, int i
)
337 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
338 return qir_SEL_X_0_NS(c
, qir_uniform_ui(c
, ~0));
342 tgsi_to_qir_fsge(struct vc4_compile
*c
,
343 struct tgsi_full_instruction
*tgsi_inst
,
344 enum qop op
, struct qreg
*src
, int i
)
346 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
347 return qir_SEL_X_0_NC(c
, qir_uniform_ui(c
, ~0));
351 tgsi_to_qir_useq(struct vc4_compile
*c
,
352 struct tgsi_full_instruction
*tgsi_inst
,
353 enum qop op
, struct qreg
*src
, int i
)
355 qir_SF(c
, qir_SUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
356 return qir_SEL_X_0_ZS(c
, qir_uniform_ui(c
, ~0));
360 tgsi_to_qir_usne(struct vc4_compile
*c
,
361 struct tgsi_full_instruction
*tgsi_inst
,
362 enum qop op
, struct qreg
*src
, int i
)
364 qir_SF(c
, qir_SUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
365 return qir_SEL_X_0_ZC(c
, qir_uniform_ui(c
, ~0));
369 tgsi_to_qir_islt(struct vc4_compile
*c
,
370 struct tgsi_full_instruction
*tgsi_inst
,
371 enum qop op
, struct qreg
*src
, int i
)
373 qir_SF(c
, qir_SUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
374 return qir_SEL_X_0_NS(c
, qir_uniform_ui(c
, ~0));
378 tgsi_to_qir_isge(struct vc4_compile
*c
,
379 struct tgsi_full_instruction
*tgsi_inst
,
380 enum qop op
, struct qreg
*src
, int i
)
382 qir_SF(c
, qir_SUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
383 return qir_SEL_X_0_NC(c
, qir_uniform_ui(c
, ~0));
387 tgsi_to_qir_cmp(struct vc4_compile
*c
,
388 struct tgsi_full_instruction
*tgsi_inst
,
389 enum qop op
, struct qreg
*src
, int i
)
391 qir_SF(c
, src
[0 * 4 + i
]);
392 return qir_SEL_X_Y_NS(c
,
398 tgsi_to_qir_mad(struct vc4_compile
*c
,
399 struct tgsi_full_instruction
*tgsi_inst
,
400 enum qop op
, struct qreg
*src
, int i
)
410 tgsi_to_qir_lit(struct vc4_compile
*c
,
411 struct tgsi_full_instruction
*tgsi_inst
,
412 enum qop op
, struct qreg
*src
, int i
)
414 struct qreg x
= src
[0 * 4 + 0];
415 struct qreg y
= src
[0 * 4 + 1];
416 struct qreg w
= src
[0 * 4 + 3];
421 return qir_uniform_f(c
, 1.0);
423 return qir_FMAX(c
, src
[0 * 4 + 0], qir_uniform_f(c
, 0.0));
425 struct qreg zero
= qir_uniform_f(c
, 0.0);
428 /* XXX: Clamp w to -128..128 */
429 return qir_SEL_X_0_NC(c
,
430 qir_EXP2(c
, qir_FMUL(c
,
438 assert(!"not reached");
444 tgsi_to_qir_lrp(struct vc4_compile
*c
,
445 struct tgsi_full_instruction
*tgsi_inst
,
446 enum qop op
, struct qreg
*src
, int i
)
448 struct qreg src0
= src
[0 * 4 + i
];
449 struct qreg src1
= src
[1 * 4 + i
];
450 struct qreg src2
= src
[2 * 4 + i
];
453 * src0 * src1 + (1 - src0) * src2.
454 * -> src0 * src1 + src2 - src0 * src2
455 * -> src2 + src0 * (src1 - src2)
457 return qir_FADD(c
, src2
, qir_FMUL(c
, src0
, qir_FSUB(c
, src1
, src2
)));
462 tgsi_to_qir_tex(struct vc4_compile
*c
,
463 struct tgsi_full_instruction
*tgsi_inst
,
464 enum qop op
, struct qreg
*src
)
466 assert(!tgsi_inst
->Instruction
.Saturate
);
468 struct qreg s
= src
[0 * 4 + 0];
469 struct qreg t
= src
[0 * 4 + 1];
470 uint32_t unit
= tgsi_inst
->Src
[1].Register
.Index
;
472 struct qreg proj
= c
->undef
;
473 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
474 proj
= qir_RCP(c
, src
[0 * 4 + 3]);
475 s
= qir_FMUL(c
, s
, proj
);
476 t
= qir_FMUL(c
, t
, proj
);
479 /* There is no native support for GL texture rectangle coordinates, so
480 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
483 if (tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_RECT
||
484 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
) {
486 get_temp_for_uniform(c
,
487 QUNIFORM_TEXRECT_SCALE_X
,
490 get_temp_for_uniform(c
,
491 QUNIFORM_TEXRECT_SCALE_Y
,
495 qir_TEX_T(c
, t
, add_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P0
, unit
));
497 struct qreg sampler_p1
= add_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P1
,
499 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB
) {
500 qir_TEX_B(c
, src
[0 * 4 + 3], sampler_p1
);
501 qir_TEX_S(c
, s
, add_uniform(c
, QUNIFORM_CONSTANT
, 0));
503 qir_TEX_S(c
, s
, sampler_p1
);
506 c
->num_texture_samples
++;
507 struct qreg r4
= qir_TEX_RESULT(c
);
509 enum pipe_format format
= c
->key
->tex
[unit
].format
;
511 struct qreg unpacked
[4];
512 if (util_format_is_depth_or_stencil(format
)) {
513 struct qreg depthf
= qir_ITOF(c
, qir_SHR(c
, r4
,
514 qir_uniform_ui(c
, 8)));
515 struct qreg normalized
= qir_FMUL(c
, depthf
,
516 qir_uniform_f(c
, 1.0f
/0xffffff));
518 struct qreg depth_output
;
520 struct qreg compare
= src
[0 * 4 + 2];
522 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
)
523 compare
= qir_FMUL(c
, compare
, proj
);
525 struct qreg one
= qir_uniform_f(c
, 1.0f
);
526 if (c
->key
->tex
[unit
].compare_mode
) {
527 switch (c
->key
->tex
[unit
].compare_func
) {
528 case PIPE_FUNC_NEVER
:
529 depth_output
= qir_uniform_f(c
, 0.0f
);
531 case PIPE_FUNC_ALWAYS
:
534 case PIPE_FUNC_EQUAL
:
535 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
536 depth_output
= qir_SEL_X_0_ZS(c
, one
);
538 case PIPE_FUNC_NOTEQUAL
:
539 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
540 depth_output
= qir_SEL_X_0_ZC(c
, one
);
542 case PIPE_FUNC_GREATER
:
543 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
544 depth_output
= qir_SEL_X_0_NC(c
, one
);
546 case PIPE_FUNC_GEQUAL
:
547 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
548 depth_output
= qir_SEL_X_0_NS(c
, one
);
551 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
552 depth_output
= qir_SEL_X_0_NS(c
, one
);
554 case PIPE_FUNC_LEQUAL
:
555 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
556 depth_output
= qir_SEL_X_0_NC(c
, one
);
560 depth_output
= normalized
;
563 for (int i
= 0; i
< 4; i
++)
564 unpacked
[i
] = depth_output
;
566 for (int i
= 0; i
< 4; i
++)
567 unpacked
[i
] = qir_R4_UNPACK(c
, r4
, i
);
570 const uint8_t *format_swiz
= vc4_get_format_swizzle(format
);
572 util_format_compose_swizzles(format_swiz
, c
->key
->tex
[unit
].swizzle
, swiz
);
573 for (int i
= 0; i
< 4; i
++) {
574 if (!(tgsi_inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
577 update_dst(c
, tgsi_inst
, i
,
578 get_swizzled_channel(c
, unpacked
, swiz
[i
]));
583 tgsi_to_qir_pow(struct vc4_compile
*c
,
584 struct tgsi_full_instruction
*tgsi_inst
,
585 enum qop op
, struct qreg
*src
, int i
)
587 /* Note that this instruction replicates its result from the x channel
589 return qir_EXP2(c
, qir_FMUL(c
,
591 qir_LOG2(c
, src
[0 * 4 + 0])));
595 tgsi_to_qir_trunc(struct vc4_compile
*c
,
596 struct tgsi_full_instruction
*tgsi_inst
,
597 enum qop op
, struct qreg
*src
, int i
)
599 return qir_ITOF(c
, qir_FTOI(c
, src
[0 * 4 + i
]));
603 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
607 tgsi_to_qir_frc(struct vc4_compile
*c
,
608 struct tgsi_full_instruction
*tgsi_inst
,
609 enum qop op
, struct qreg
*src
, int i
)
611 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
[0 * 4 + i
]));
612 struct qreg diff
= qir_FSUB(c
, src
[0 * 4 + i
], trunc
);
614 return qir_SEL_X_Y_NS(c
,
615 qir_FADD(c
, diff
, qir_uniform_f(c
, 1.0)),
620 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
624 tgsi_to_qir_flr(struct vc4_compile
*c
,
625 struct tgsi_full_instruction
*tgsi_inst
,
626 enum qop op
, struct qreg
*src
, int i
)
628 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
[0 * 4 + i
]));
630 /* This will be < 0 if we truncated and the truncation was of a value
631 * that was < 0 in the first place.
633 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], trunc
));
635 return qir_SEL_X_Y_NS(c
,
636 qir_FSUB(c
, trunc
, qir_uniform_f(c
, 1.0)),
641 tgsi_to_qir_dp(struct vc4_compile
*c
,
642 struct tgsi_full_instruction
*tgsi_inst
,
643 int num
, struct qreg
*src
, int i
)
645 struct qreg sum
= qir_FMUL(c
, src
[0 * 4 + 0], src
[1 * 4 + 0]);
646 for (int j
= 1; j
< num
; j
++) {
647 sum
= qir_FADD(c
, sum
, qir_FMUL(c
,
655 tgsi_to_qir_dp2(struct vc4_compile
*c
,
656 struct tgsi_full_instruction
*tgsi_inst
,
657 enum qop op
, struct qreg
*src
, int i
)
659 return tgsi_to_qir_dp(c
, tgsi_inst
, 2, src
, i
);
663 tgsi_to_qir_dp3(struct vc4_compile
*c
,
664 struct tgsi_full_instruction
*tgsi_inst
,
665 enum qop op
, struct qreg
*src
, int i
)
667 return tgsi_to_qir_dp(c
, tgsi_inst
, 3, src
, i
);
671 tgsi_to_qir_dp4(struct vc4_compile
*c
,
672 struct tgsi_full_instruction
*tgsi_inst
,
673 enum qop op
, struct qreg
*src
, int i
)
675 return tgsi_to_qir_dp(c
, tgsi_inst
, 4, src
, i
);
679 tgsi_to_qir_abs(struct vc4_compile
*c
,
680 struct tgsi_full_instruction
*tgsi_inst
,
681 enum qop op
, struct qreg
*src
, int i
)
683 struct qreg arg
= src
[0 * 4 + i
];
684 return qir_FMAXABS(c
, arg
, arg
);
687 /* Note that this instruction replicates its result from the x channel */
689 tgsi_to_qir_sin(struct vc4_compile
*c
,
690 struct tgsi_full_instruction
*tgsi_inst
,
691 enum qop op
, struct qreg
*src
, int i
)
695 -pow(2.0 * M_PI
, 3) / (3 * 2 * 1),
696 pow(2.0 * M_PI
, 5) / (5 * 4 * 3 * 2 * 1),
697 -pow(2.0 * M_PI
, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
700 struct qreg scaled_x
=
703 qir_uniform_f(c
, 1.0f
/ (M_PI
* 2.0f
)));
706 struct qreg x
= tgsi_to_qir_frc(c
, NULL
, 0, &scaled_x
, 0);
707 struct qreg x2
= qir_FMUL(c
, x
, x
);
708 struct qreg sum
= qir_FMUL(c
, x
, qir_uniform_f(c
, coeff
[0]));
709 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
710 x
= qir_FMUL(c
, x
, x2
);
715 qir_uniform_f(c
, coeff
[i
])));
720 /* Note that this instruction replicates its result from the x channel */
722 tgsi_to_qir_cos(struct vc4_compile
*c
,
723 struct tgsi_full_instruction
*tgsi_inst
,
724 enum qop op
, struct qreg
*src
, int i
)
728 -pow(2.0 * M_PI
, 2) / (2 * 1),
729 pow(2.0 * M_PI
, 4) / (4 * 3 * 2 * 1),
730 -pow(2.0 * M_PI
, 6) / (6 * 5 * 4 * 3 * 2 * 1),
733 struct qreg scaled_x
=
734 qir_FMUL(c
, src
[0 * 4 + 0],
735 qir_uniform_f(c
, 1.0f
/ (M_PI
* 2.0f
)));
736 struct qreg x_frac
= tgsi_to_qir_frc(c
, NULL
, 0, &scaled_x
, 0);
738 struct qreg sum
= qir_uniform_f(c
, coeff
[0]);
739 struct qreg x2
= qir_FMUL(c
, x_frac
, x_frac
);
740 struct qreg x
= x2
; /* Current x^2, x^4, or x^6 */
741 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
743 x
= qir_FMUL(c
, x
, x2
);
745 struct qreg mul
= qir_FMUL(c
,
747 qir_uniform_f(c
, coeff
[i
]));
751 sum
= qir_FADD(c
, sum
, mul
);
757 emit_vertex_input(struct vc4_compile
*c
, int attr
)
759 enum pipe_format format
= c
->vs_key
->attr_formats
[attr
];
760 struct qreg vpm_reads
[4];
762 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
763 * time, so we always read 4 32-bit VPM entries.
765 for (int i
= 0; i
< 4; i
++) {
766 vpm_reads
[i
] = qir_get_temp(c
);
767 qir_emit(c
, qir_inst(QOP_VPM_READ
,
774 bool format_warned
= false;
775 const struct util_format_description
*desc
=
776 util_format_description(format
);
778 for (int i
= 0; i
< 4; i
++) {
779 uint8_t swiz
= desc
->swizzle
[i
];
781 if (swiz
<= UTIL_FORMAT_SWIZZLE_W
&&
783 (desc
->channel
[swiz
].type
!= UTIL_FORMAT_TYPE_FLOAT
||
784 desc
->channel
[swiz
].size
!= 32)) {
786 "vtx element %d unsupported type: %s\n",
787 attr
, util_format_name(format
));
788 format_warned
= true;
791 c
->inputs
[attr
* 4 + i
] =
792 get_swizzled_channel(c
, vpm_reads
, swiz
);
797 tgsi_to_qir_kill_if(struct vc4_compile
*c
, struct qreg
*src
, int i
)
799 if (c
->discard
.file
== QFILE_NULL
)
800 c
->discard
= qir_uniform_f(c
, 0.0);
801 qir_SF(c
, src
[0 * 4 + i
]);
802 c
->discard
= qir_SEL_X_Y_NS(c
, qir_uniform_f(c
, 1.0),
807 emit_fragcoord_input(struct vc4_compile
*c
, int attr
)
809 c
->inputs
[attr
* 4 + 0] = qir_FRAG_X(c
);
810 c
->inputs
[attr
* 4 + 1] = qir_FRAG_Y(c
);
811 c
->inputs
[attr
* 4 + 2] =
814 qir_uniform_f(c
, 1.0 / 0xffffff));
815 c
->inputs
[attr
* 4 + 3] = qir_FRAG_RCP_W(c
);
819 emit_fragment_varying(struct vc4_compile
*c
, int index
)
826 /* XXX: multiply by W */
827 return qir_VARY_ADD_C(c
, qir_MOV(c
, vary
));
831 emit_fragment_input(struct vc4_compile
*c
, int attr
)
833 for (int i
= 0; i
< 4; i
++) {
834 c
->inputs
[attr
* 4 + i
] =
835 emit_fragment_varying(c
, attr
* 4 + i
);
841 emit_tgsi_declaration(struct vc4_compile
*c
,
842 struct tgsi_full_declaration
*decl
)
844 switch (decl
->Declaration
.File
) {
845 case TGSI_FILE_INPUT
:
846 for (int i
= decl
->Range
.First
;
847 i
<= decl
->Range
.Last
;
849 if (c
->stage
== QSTAGE_FRAG
) {
850 if (decl
->Semantic
.Name
==
851 TGSI_SEMANTIC_POSITION
) {
852 emit_fragcoord_input(c
, i
);
854 emit_fragment_input(c
, i
);
857 emit_vertex_input(c
, i
);
865 emit_tgsi_instruction(struct vc4_compile
*c
,
866 struct tgsi_full_instruction
*tgsi_inst
)
870 struct qreg (*func
)(struct vc4_compile
*c
,
871 struct tgsi_full_instruction
*tgsi_inst
,
873 struct qreg
*src
, int i
);
875 [TGSI_OPCODE_MOV
] = { QOP_MOV
, tgsi_to_qir_alu
},
876 [TGSI_OPCODE_ABS
] = { 0, tgsi_to_qir_abs
},
877 [TGSI_OPCODE_MUL
] = { QOP_FMUL
, tgsi_to_qir_alu
},
878 [TGSI_OPCODE_ADD
] = { QOP_FADD
, tgsi_to_qir_alu
},
879 [TGSI_OPCODE_SUB
] = { QOP_FSUB
, tgsi_to_qir_alu
},
880 [TGSI_OPCODE_MIN
] = { QOP_FMIN
, tgsi_to_qir_alu
},
881 [TGSI_OPCODE_MAX
] = { QOP_FMAX
, tgsi_to_qir_alu
},
882 [TGSI_OPCODE_F2I
] = { QOP_FTOI
, tgsi_to_qir_alu
},
883 [TGSI_OPCODE_I2F
] = { QOP_ITOF
, tgsi_to_qir_alu
},
884 [TGSI_OPCODE_UADD
] = { QOP_ADD
, tgsi_to_qir_alu
},
885 [TGSI_OPCODE_USHR
] = { QOP_SHR
, tgsi_to_qir_alu
},
886 [TGSI_OPCODE_ISHR
] = { QOP_ASR
, tgsi_to_qir_alu
},
887 [TGSI_OPCODE_SHL
] = { QOP_SHL
, tgsi_to_qir_alu
},
888 [TGSI_OPCODE_IMIN
] = { QOP_MIN
, tgsi_to_qir_alu
},
889 [TGSI_OPCODE_IMAX
] = { QOP_MAX
, tgsi_to_qir_alu
},
890 [TGSI_OPCODE_AND
] = { QOP_AND
, tgsi_to_qir_alu
},
891 [TGSI_OPCODE_OR
] = { QOP_OR
, tgsi_to_qir_alu
},
892 [TGSI_OPCODE_XOR
] = { QOP_XOR
, tgsi_to_qir_alu
},
893 [TGSI_OPCODE_NOT
] = { QOP_NOT
, tgsi_to_qir_alu
},
895 [TGSI_OPCODE_UMUL
] = { 0, tgsi_to_qir_umul
},
896 [TGSI_OPCODE_IDIV
] = { 0, tgsi_to_qir_idiv
},
897 [TGSI_OPCODE_INEG
] = { 0, tgsi_to_qir_ineg
},
899 [TGSI_OPCODE_RSQ
] = { QOP_RSQ
, tgsi_to_qir_alu
},
900 [TGSI_OPCODE_SEQ
] = { 0, tgsi_to_qir_seq
},
901 [TGSI_OPCODE_SNE
] = { 0, tgsi_to_qir_sne
},
902 [TGSI_OPCODE_SGE
] = { 0, tgsi_to_qir_sge
},
903 [TGSI_OPCODE_SLT
] = { 0, tgsi_to_qir_slt
},
904 [TGSI_OPCODE_FSEQ
] = { 0, tgsi_to_qir_fseq
},
905 [TGSI_OPCODE_FSNE
] = { 0, tgsi_to_qir_fsne
},
906 [TGSI_OPCODE_FSGE
] = { 0, tgsi_to_qir_fsge
},
907 [TGSI_OPCODE_FSLT
] = { 0, tgsi_to_qir_fslt
},
908 [TGSI_OPCODE_USEQ
] = { 0, tgsi_to_qir_useq
},
909 [TGSI_OPCODE_USNE
] = { 0, tgsi_to_qir_usne
},
910 [TGSI_OPCODE_ISGE
] = { 0, tgsi_to_qir_isge
},
911 [TGSI_OPCODE_ISLT
] = { 0, tgsi_to_qir_islt
},
913 [TGSI_OPCODE_CMP
] = { 0, tgsi_to_qir_cmp
},
914 [TGSI_OPCODE_MAD
] = { 0, tgsi_to_qir_mad
},
915 [TGSI_OPCODE_DP2
] = { 0, tgsi_to_qir_dp2
},
916 [TGSI_OPCODE_DP3
] = { 0, tgsi_to_qir_dp3
},
917 [TGSI_OPCODE_DP4
] = { 0, tgsi_to_qir_dp4
},
918 [TGSI_OPCODE_RCP
] = { QOP_RCP
, tgsi_to_qir_alu
},
919 [TGSI_OPCODE_RSQ
] = { QOP_RSQ
, tgsi_to_qir_alu
},
920 [TGSI_OPCODE_EX2
] = { QOP_EXP2
, tgsi_to_qir_alu
},
921 [TGSI_OPCODE_LG2
] = { QOP_LOG2
, tgsi_to_qir_alu
},
922 [TGSI_OPCODE_LIT
] = { 0, tgsi_to_qir_lit
},
923 [TGSI_OPCODE_LRP
] = { 0, tgsi_to_qir_lrp
},
924 [TGSI_OPCODE_POW
] = { 0, tgsi_to_qir_pow
},
925 [TGSI_OPCODE_TRUNC
] = { 0, tgsi_to_qir_trunc
},
926 [TGSI_OPCODE_FRC
] = { 0, tgsi_to_qir_frc
},
927 [TGSI_OPCODE_FLR
] = { 0, tgsi_to_qir_flr
},
928 [TGSI_OPCODE_SIN
] = { 0, tgsi_to_qir_sin
},
929 [TGSI_OPCODE_COS
] = { 0, tgsi_to_qir_cos
},
932 uint32_t tgsi_op
= tgsi_inst
->Instruction
.Opcode
;
934 if (tgsi_op
== TGSI_OPCODE_END
)
937 struct qreg src_regs
[12];
938 for (int s
= 0; s
< 3; s
++) {
939 for (int i
= 0; i
< 4; i
++) {
940 src_regs
[4 * s
+ i
] =
941 get_src(c
, tgsi_inst
->Instruction
.Opcode
,
942 &tgsi_inst
->Src
[s
].Register
, i
);
947 case TGSI_OPCODE_TEX
:
948 case TGSI_OPCODE_TXP
:
949 case TGSI_OPCODE_TXB
:
950 tgsi_to_qir_tex(c
, tgsi_inst
,
951 op_trans
[tgsi_op
].op
, src_regs
);
953 case TGSI_OPCODE_KILL
:
954 c
->discard
= qir_uniform_f(c
, 1.0);
956 case TGSI_OPCODE_KILL_IF
:
957 for (int i
= 0; i
< 4; i
++)
958 tgsi_to_qir_kill_if(c
, src_regs
, i
);
964 if (tgsi_op
> ARRAY_SIZE(op_trans
) || !(op_trans
[tgsi_op
].func
)) {
965 fprintf(stderr
, "unknown tgsi inst: ");
966 tgsi_dump_instruction(tgsi_inst
, asdf
++);
967 fprintf(stderr
, "\n");
971 for (int i
= 0; i
< 4; i
++) {
972 if (!(tgsi_inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
977 result
= op_trans
[tgsi_op
].func(c
, tgsi_inst
,
978 op_trans
[tgsi_op
].op
,
981 if (tgsi_inst
->Instruction
.Saturate
) {
982 float low
= (tgsi_inst
->Instruction
.Saturate
==
983 TGSI_SAT_MINUS_PLUS_ONE
? -1.0 : 0.0);
987 qir_uniform_f(c
, 1.0)),
988 qir_uniform_f(c
, low
));
991 update_dst(c
, tgsi_inst
, i
, result
);
996 parse_tgsi_immediate(struct vc4_compile
*c
, struct tgsi_full_immediate
*imm
)
998 for (int i
= 0; i
< 4; i
++) {
999 unsigned n
= c
->num_consts
++;
1000 c
->consts
[n
] = qir_uniform_ui(c
, imm
->u
[i
].Uint
);
1005 vc4_blend_channel(struct vc4_compile
*c
,
1013 case PIPE_BLENDFACTOR_ONE
:
1015 case PIPE_BLENDFACTOR_SRC_COLOR
:
1016 return qir_FMUL(c
, val
, src
[channel
]);
1017 case PIPE_BLENDFACTOR_SRC_ALPHA
:
1018 return qir_FMUL(c
, val
, src
[3]);
1019 case PIPE_BLENDFACTOR_DST_ALPHA
:
1020 return qir_FMUL(c
, val
, dst
[3]);
1021 case PIPE_BLENDFACTOR_DST_COLOR
:
1022 return qir_FMUL(c
, val
, dst
[channel
]);
1023 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
1024 return qir_FMIN(c
, src
[3], qir_FSUB(c
,
1025 qir_uniform_f(c
, 1.0),
1027 case PIPE_BLENDFACTOR_CONST_COLOR
:
1028 return qir_FMUL(c
, val
,
1029 get_temp_for_uniform(c
,
1030 QUNIFORM_BLEND_CONST_COLOR
,
1032 case PIPE_BLENDFACTOR_CONST_ALPHA
:
1033 return qir_FMUL(c
, val
,
1034 get_temp_for_uniform(c
,
1035 QUNIFORM_BLEND_CONST_COLOR
,
1037 case PIPE_BLENDFACTOR_ZERO
:
1038 return qir_uniform_f(c
, 0.0);
1039 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
1040 return qir_FMUL(c
, val
, qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1042 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
1043 return qir_FMUL(c
, val
, qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1045 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
1046 return qir_FMUL(c
, val
, qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1048 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
1049 return qir_FMUL(c
, val
, qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1051 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
1052 return qir_FMUL(c
, val
,
1053 qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1054 get_temp_for_uniform(c
,
1055 QUNIFORM_BLEND_CONST_COLOR
,
1057 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
1058 return qir_FMUL(c
, val
,
1059 qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1060 get_temp_for_uniform(c
,
1061 QUNIFORM_BLEND_CONST_COLOR
,
1065 case PIPE_BLENDFACTOR_SRC1_COLOR
:
1066 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
1067 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
1068 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
1070 fprintf(stderr
, "Unknown blend factor %d\n", factor
);
1076 vc4_blend_func(struct vc4_compile
*c
,
1077 struct qreg src
, struct qreg dst
,
1081 case PIPE_BLEND_ADD
:
1082 return qir_FADD(c
, src
, dst
);
1083 case PIPE_BLEND_SUBTRACT
:
1084 return qir_FSUB(c
, src
, dst
);
1085 case PIPE_BLEND_REVERSE_SUBTRACT
:
1086 return qir_FSUB(c
, dst
, src
);
1087 case PIPE_BLEND_MIN
:
1088 return qir_FMIN(c
, src
, dst
);
1089 case PIPE_BLEND_MAX
:
1090 return qir_FMAX(c
, src
, dst
);
1094 fprintf(stderr
, "Unknown blend func %d\n", func
);
1101 * Implements fixed function blending in shader code.
1103 * VC4 doesn't have any hardware support for blending. Instead, you read the
1104 * current contents of the destination from the tile buffer after having
1105 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1106 * math using your output color and that destination value, and update the
1107 * output color appropriately.
1110 vc4_blend(struct vc4_compile
*c
, struct qreg
*result
,
1111 struct qreg
*dst_color
, struct qreg
*src_color
)
1113 struct pipe_rt_blend_state
*blend
= &c
->fs_key
->blend
;
1115 if (!blend
->blend_enable
) {
1116 for (int i
= 0; i
< 4; i
++)
1117 result
[i
] = src_color
[i
];
1121 struct qreg src_blend
[4], dst_blend
[4];
1122 for (int i
= 0; i
< 3; i
++) {
1123 src_blend
[i
] = vc4_blend_channel(c
,
1124 dst_color
, src_color
,
1126 blend
->rgb_src_factor
, i
);
1127 dst_blend
[i
] = vc4_blend_channel(c
,
1128 dst_color
, src_color
,
1130 blend
->rgb_dst_factor
, i
);
1132 src_blend
[3] = vc4_blend_channel(c
,
1133 dst_color
, src_color
,
1135 blend
->alpha_src_factor
, 3);
1136 dst_blend
[3] = vc4_blend_channel(c
,
1137 dst_color
, src_color
,
1139 blend
->alpha_dst_factor
, 3);
1141 for (int i
= 0; i
< 3; i
++) {
1142 result
[i
] = vc4_blend_func(c
,
1143 src_blend
[i
], dst_blend
[i
],
1146 result
[3] = vc4_blend_func(c
,
1147 src_blend
[3], dst_blend
[3],
1152 emit_frag_end(struct vc4_compile
*c
)
1154 struct qreg src_color
[4] = {
1155 c
->outputs
[0], c
->outputs
[1], c
->outputs
[2], c
->outputs
[3],
1158 enum pipe_format color_format
= c
->fs_key
->color_format
;
1159 const uint8_t *format_swiz
= vc4_get_format_swizzle(color_format
);
1160 struct qreg tlb_read_color
[4] = { c
->undef
, c
->undef
, c
->undef
, c
->undef
};
1161 struct qreg dst_color
[4] = { c
->undef
, c
->undef
, c
->undef
, c
->undef
};
1162 if (c
->fs_key
->blend
.blend_enable
||
1163 c
->fs_key
->blend
.colormask
!= 0xf) {
1164 struct qreg r4
= qir_TLB_COLOR_READ(c
);
1165 for (int i
= 0; i
< 4; i
++)
1166 tlb_read_color
[i
] = qir_R4_UNPACK(c
, r4
, i
);
1167 for (int i
= 0; i
< 4; i
++)
1168 dst_color
[i
] = get_swizzled_channel(c
,
1173 struct qreg blend_color
[4];
1174 vc4_blend(c
, blend_color
, dst_color
, src_color
);
1176 /* If the bit isn't set in the color mask, then just return the
1177 * original dst color, instead.
1179 for (int i
= 0; i
< 4; i
++) {
1180 if (!(c
->fs_key
->blend
.colormask
& (1 << i
))) {
1181 blend_color
[i
] = dst_color
[i
];
1185 /* Debug: Sometimes you're getting a black output and just want to see
1186 * if the FS is getting executed at all. Spam magenta into the color
1190 blend_color
[0] = qir_uniform_f(c
, 1.0);
1191 blend_color
[1] = qir_uniform_f(c
, 0.0);
1192 blend_color
[2] = qir_uniform_f(c
, 1.0);
1193 blend_color
[3] = qir_uniform_f(c
, 0.5);
1196 struct qreg swizzled_outputs
[4];
1197 for (int i
= 0; i
< 4; i
++) {
1198 swizzled_outputs
[i
] = get_swizzled_channel(c
, blend_color
,
1202 if (c
->discard
.file
!= QFILE_NULL
)
1203 qir_TLB_DISCARD_SETUP(c
, c
->discard
);
1205 if (c
->fs_key
->depth_enabled
) {
1206 qir_emit(c
, qir_inst(QOP_TLB_PASSTHROUGH_Z_WRITE
, c
->undef
,
1207 c
->undef
, c
->undef
));
1210 bool color_written
= false;
1211 for (int i
= 0; i
< 4; i
++) {
1212 if (swizzled_outputs
[i
].file
!= QFILE_NULL
)
1213 color_written
= true;
1216 struct qreg packed_color
;
1217 if (color_written
) {
1218 /* Fill in any undefined colors. The simulator will assertion
1219 * fail if we read something that wasn't written, and I don't
1220 * know what hardware does.
1222 for (int i
= 0; i
< 4; i
++) {
1223 if (swizzled_outputs
[i
].file
== QFILE_NULL
)
1224 swizzled_outputs
[i
] = qir_uniform_f(c
, 0.0);
1226 packed_color
= qir_get_temp(c
);
1227 qir_emit(c
, qir_inst4(QOP_PACK_COLORS
, packed_color
,
1228 swizzled_outputs
[0],
1229 swizzled_outputs
[1],
1230 swizzled_outputs
[2],
1231 swizzled_outputs
[3]));
1233 packed_color
= qir_uniform_ui(c
, 0);
1236 qir_emit(c
, qir_inst(QOP_TLB_COLOR_WRITE
, c
->undef
,
1237 packed_color
, c
->undef
));
1241 emit_scaled_viewport_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1245 for (int i
= 0; i
< 2; i
++) {
1247 add_uniform(c
, QUNIFORM_VIEWPORT_X_SCALE
+ i
, 0);
1249 xyi
[i
] = qir_FTOI(c
, qir_FMUL(c
,
1256 qir_VPM_WRITE(c
, qir_PACK_SCALED(c
, xyi
[0], xyi
[1]));
1260 emit_zs_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1262 struct qreg zscale
= add_uniform(c
, QUNIFORM_VIEWPORT_Z_SCALE
, 0);
1263 struct qreg zoffset
= add_uniform(c
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0);
1265 qir_VPM_WRITE(c
, qir_FMUL(c
, qir_FADD(c
, qir_FMUL(c
,
1273 emit_rcp_wc_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1275 qir_VPM_WRITE(c
, rcp_w
);
1279 emit_vert_end(struct vc4_compile
*c
)
1281 struct qreg rcp_w
= qir_RCP(c
, c
->outputs
[3]);
1283 emit_scaled_viewport_write(c
, rcp_w
);
1284 emit_zs_write(c
, rcp_w
);
1285 emit_rcp_wc_write(c
, rcp_w
);
1287 for (int i
= 4; i
< c
->num_outputs
; i
++) {
1288 qir_VPM_WRITE(c
, c
->outputs
[i
]);
1293 emit_coord_end(struct vc4_compile
*c
)
1295 struct qreg rcp_w
= qir_RCP(c
, c
->outputs
[3]);
1297 for (int i
= 0; i
< 4; i
++)
1298 qir_VPM_WRITE(c
, c
->outputs
[i
]);
1300 emit_scaled_viewport_write(c
, rcp_w
);
1301 emit_zs_write(c
, rcp_w
);
1302 emit_rcp_wc_write(c
, rcp_w
);
1305 static struct vc4_compile
*
1306 vc4_shader_tgsi_to_qir(struct vc4_compiled_shader
*shader
, enum qstage stage
,
1307 struct vc4_key
*key
)
1309 struct vc4_compile
*c
= qir_compile_init();
1315 c
->temps
= calloc(sizeof(struct qreg
), 1024);
1316 c
->inputs
= calloc(sizeof(struct qreg
), 8 * 4);
1317 c
->outputs
= calloc(sizeof(struct qreg
), 1024);
1318 c
->uniforms
= calloc(sizeof(struct qreg
), 1024);
1319 c
->consts
= calloc(sizeof(struct qreg
), 1024);
1321 c
->uniform_data
= calloc(sizeof(uint32_t), 1024);
1322 c
->uniform_contents
= calloc(sizeof(enum quniform_contents
), 1024);
1324 c
->shader_state
= key
->shader_state
;
1325 ret
= tgsi_parse_init(&c
->parser
, c
->shader_state
->tokens
);
1326 assert(ret
== TGSI_PARSE_OK
);
1328 if (vc4_debug
& VC4_DEBUG_TGSI
) {
1329 fprintf(stderr
, "TGSI:\n");
1330 tgsi_dump(c
->shader_state
->tokens
, 0);
1336 c
->fs_key
= (struct vc4_fs_key
*)key
;
1337 if (c
->fs_key
->is_points
) {
1338 c
->point_x
= emit_fragment_varying(c
, 0);
1339 c
->point_y
= emit_fragment_varying(c
, 0);
1340 } else if (c
->fs_key
->is_lines
) {
1341 c
->line_x
= emit_fragment_varying(c
, 0);
1345 c
->vs_key
= (struct vc4_vs_key
*)key
;
1348 c
->vs_key
= (struct vc4_vs_key
*)key
;
1352 while (!tgsi_parse_end_of_tokens(&c
->parser
)) {
1353 tgsi_parse_token(&c
->parser
);
1355 switch (c
->parser
.FullToken
.Token
.Type
) {
1356 case TGSI_TOKEN_TYPE_DECLARATION
:
1357 emit_tgsi_declaration(c
,
1358 &c
->parser
.FullToken
.FullDeclaration
);
1361 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1362 emit_tgsi_instruction(c
,
1363 &c
->parser
.FullToken
.FullInstruction
);
1366 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1367 parse_tgsi_immediate(c
,
1368 &c
->parser
.FullToken
.FullImmediate
);
1385 tgsi_parse_free(&c
->parser
);
1390 if (vc4_debug
& VC4_DEBUG_QIR
) {
1391 fprintf(stderr
, "QIR:\n");
1394 vc4_generate_code(c
);
1396 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
1397 fprintf(stderr
, "SHADER-DB: %s: %d instructions\n",
1398 qir_get_stage_name(c
->stage
), c
->qpu_inst_count
);
1399 fprintf(stderr
, "SHADER-DB: %s: %d uniforms\n",
1400 qir_get_stage_name(c
->stage
), c
->num_uniforms
);
1407 vc4_shader_state_create(struct pipe_context
*pctx
,
1408 const struct pipe_shader_state
*cso
)
1410 struct pipe_shader_state
*so
= CALLOC_STRUCT(pipe_shader_state
);
1414 so
->tokens
= tgsi_dup_tokens(cso
->tokens
);
1420 copy_uniform_state_to_shader(struct vc4_compiled_shader
*shader
,
1422 struct vc4_compile
*c
)
1424 int count
= c
->num_uniforms
;
1425 struct vc4_shader_uniform_info
*uinfo
= &shader
->uniforms
[shader_index
];
1427 uinfo
->count
= count
;
1428 uinfo
->data
= malloc(count
* sizeof(*uinfo
->data
));
1429 memcpy(uinfo
->data
, c
->uniform_data
,
1430 count
* sizeof(*uinfo
->data
));
1431 uinfo
->contents
= malloc(count
* sizeof(*uinfo
->contents
));
1432 memcpy(uinfo
->contents
, c
->uniform_contents
,
1433 count
* sizeof(*uinfo
->contents
));
1434 uinfo
->num_texture_samples
= c
->num_texture_samples
;
1438 vc4_fs_compile(struct vc4_context
*vc4
, struct vc4_compiled_shader
*shader
,
1439 struct vc4_fs_key
*key
)
1441 struct vc4_compile
*c
= vc4_shader_tgsi_to_qir(shader
, QSTAGE_FRAG
,
1443 shader
->num_inputs
= c
->num_inputs
;
1444 copy_uniform_state_to_shader(shader
, 0, c
);
1445 shader
->bo
= vc4_bo_alloc_mem(vc4
->screen
, c
->qpu_insts
,
1446 c
->qpu_inst_count
* sizeof(uint64_t),
1449 qir_compile_destroy(c
);
1453 vc4_vs_compile(struct vc4_context
*vc4
, struct vc4_compiled_shader
*shader
,
1454 struct vc4_vs_key
*key
)
1456 struct vc4_compile
*vs_c
= vc4_shader_tgsi_to_qir(shader
,
1459 copy_uniform_state_to_shader(shader
, 0, vs_c
);
1461 struct vc4_compile
*cs_c
= vc4_shader_tgsi_to_qir(shader
,
1464 copy_uniform_state_to_shader(shader
, 1, cs_c
);
1466 uint32_t vs_size
= vs_c
->qpu_inst_count
* sizeof(uint64_t);
1467 uint32_t cs_size
= cs_c
->qpu_inst_count
* sizeof(uint64_t);
1468 shader
->coord_shader_offset
= vs_size
; /* XXX: alignment? */
1469 shader
->bo
= vc4_bo_alloc(vc4
->screen
,
1470 shader
->coord_shader_offset
+ cs_size
,
1473 void *map
= vc4_bo_map(shader
->bo
);
1474 memcpy(map
, vs_c
->qpu_insts
, vs_size
);
1475 memcpy(map
+ shader
->coord_shader_offset
,
1476 cs_c
->qpu_insts
, cs_size
);
1478 qir_compile_destroy(vs_c
);
1479 qir_compile_destroy(cs_c
);
1483 vc4_setup_shared_key(struct vc4_key
*key
, struct vc4_texture_stateobj
*texstate
)
1485 for (int i
= 0; i
< texstate
->num_textures
; i
++) {
1486 struct pipe_sampler_view
*sampler
= texstate
->textures
[i
];
1487 struct pipe_sampler_state
*sampler_state
=
1488 texstate
->samplers
[i
];
1491 struct pipe_resource
*prsc
= sampler
->texture
;
1492 key
->tex
[i
].format
= prsc
->format
;
1493 key
->tex
[i
].swizzle
[0] = sampler
->swizzle_r
;
1494 key
->tex
[i
].swizzle
[1] = sampler
->swizzle_g
;
1495 key
->tex
[i
].swizzle
[2] = sampler
->swizzle_b
;
1496 key
->tex
[i
].swizzle
[3] = sampler
->swizzle_a
;
1497 key
->tex
[i
].compare_mode
= sampler_state
->compare_mode
;
1498 key
->tex
[i
].compare_func
= sampler_state
->compare_func
;
1504 vc4_update_compiled_fs(struct vc4_context
*vc4
, uint8_t prim_mode
)
1506 struct vc4_fs_key local_key
;
1507 struct vc4_fs_key
*key
= &local_key
;
1509 memset(key
, 0, sizeof(*key
));
1510 vc4_setup_shared_key(&key
->base
, &vc4
->fragtex
);
1511 key
->base
.shader_state
= vc4
->prog
.bind_fs
;
1512 key
->is_points
= (prim_mode
== PIPE_PRIM_POINTS
);
1513 key
->is_lines
= (prim_mode
>= PIPE_PRIM_LINES
&&
1514 prim_mode
<= PIPE_PRIM_LINE_STRIP
);
1515 key
->blend
= vc4
->blend
->rt
[0];
1517 if (vc4
->framebuffer
.cbufs
[0])
1518 key
->color_format
= vc4
->framebuffer
.cbufs
[0]->format
;
1520 key
->depth_enabled
= vc4
->zsa
->base
.depth
.enabled
;
1522 vc4
->prog
.fs
= util_hash_table_get(vc4
->fs_cache
, key
);
1526 key
= malloc(sizeof(*key
));
1527 memcpy(key
, &local_key
, sizeof(*key
));
1529 struct vc4_compiled_shader
*shader
= CALLOC_STRUCT(vc4_compiled_shader
);
1530 vc4_fs_compile(vc4
, shader
, key
);
1531 util_hash_table_set(vc4
->fs_cache
, key
, shader
);
1533 vc4
->prog
.fs
= shader
;
1537 vc4_update_compiled_vs(struct vc4_context
*vc4
)
1539 struct vc4_vs_key local_key
;
1540 struct vc4_vs_key
*key
= &local_key
;
1542 memset(key
, 0, sizeof(*key
));
1543 vc4_setup_shared_key(&key
->base
, &vc4
->verttex
);
1544 key
->base
.shader_state
= vc4
->prog
.bind_vs
;
1546 for (int i
= 0; i
< ARRAY_SIZE(key
->attr_formats
); i
++)
1547 key
->attr_formats
[i
] = vc4
->vtx
->pipe
[i
].src_format
;
1549 vc4
->prog
.vs
= util_hash_table_get(vc4
->vs_cache
, key
);
1553 key
= malloc(sizeof(*key
));
1554 memcpy(key
, &local_key
, sizeof(*key
));
1556 struct vc4_compiled_shader
*shader
= CALLOC_STRUCT(vc4_compiled_shader
);
1557 vc4_vs_compile(vc4
, shader
, key
);
1558 util_hash_table_set(vc4
->vs_cache
, key
, shader
);
1560 vc4
->prog
.vs
= shader
;
1564 vc4_update_compiled_shaders(struct vc4_context
*vc4
, uint8_t prim_mode
)
1566 vc4_update_compiled_fs(vc4
, prim_mode
);
1567 vc4_update_compiled_vs(vc4
);
1571 fs_cache_hash(void *key
)
1573 return util_hash_crc32(key
, sizeof(struct vc4_fs_key
));
1577 vs_cache_hash(void *key
)
1579 return util_hash_crc32(key
, sizeof(struct vc4_vs_key
));
1583 fs_cache_compare(void *key1
, void *key2
)
1585 return memcmp(key1
, key2
, sizeof(struct vc4_fs_key
));
1589 vs_cache_compare(void *key1
, void *key2
)
1591 return memcmp(key1
, key2
, sizeof(struct vc4_vs_key
));
1594 struct delete_state
{
1595 struct vc4_context
*vc4
;
1596 struct pipe_shader_state
*shader_state
;
1599 static enum pipe_error
1600 fs_delete_from_cache(void *in_key
, void *in_value
, void *data
)
1602 struct delete_state
*del
= data
;
1603 struct vc4_fs_key
*key
= in_key
;
1604 struct vc4_compiled_shader
*shader
= in_value
;
1606 if (key
->base
.shader_state
== data
) {
1607 util_hash_table_remove(del
->vc4
->fs_cache
, key
);
1608 vc4_bo_unreference(&shader
->bo
);
1615 static enum pipe_error
1616 vs_delete_from_cache(void *in_key
, void *in_value
, void *data
)
1618 struct delete_state
*del
= data
;
1619 struct vc4_vs_key
*key
= in_key
;
1620 struct vc4_compiled_shader
*shader
= in_value
;
1622 if (key
->base
.shader_state
== data
) {
1623 util_hash_table_remove(del
->vc4
->vs_cache
, key
);
1624 vc4_bo_unreference(&shader
->bo
);
1632 vc4_shader_state_delete(struct pipe_context
*pctx
, void *hwcso
)
1634 struct vc4_context
*vc4
= vc4_context(pctx
);
1635 struct pipe_shader_state
*so
= hwcso
;
1636 struct delete_state del
;
1639 del
.shader_state
= so
;
1640 util_hash_table_foreach(vc4
->fs_cache
, fs_delete_from_cache
, &del
);
1641 util_hash_table_foreach(vc4
->vs_cache
, vs_delete_from_cache
, &del
);
1643 free((void *)so
->tokens
);
1647 static uint32_t translate_wrap(uint32_t p_wrap
)
1650 case PIPE_TEX_WRAP_REPEAT
:
1652 case PIPE_TEX_WRAP_CLAMP
:
1653 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1655 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1657 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1660 fprintf(stderr
, "Unknown wrap mode %d\n", p_wrap
);
1661 assert(!"not reached");
1667 write_texture_p0(struct vc4_context
*vc4
,
1668 struct vc4_texture_stateobj
*texstate
,
1671 struct pipe_sampler_view
*texture
= texstate
->textures
[unit
];
1672 struct vc4_resource
*rsc
= vc4_resource(texture
->texture
);
1674 cl_reloc(vc4
, &vc4
->uniforms
, rsc
->bo
,
1675 rsc
->slices
[0].offset
| texture
->u
.tex
.last_level
|
1676 ((rsc
->vc4_format
& 7) << 4));
1680 write_texture_p1(struct vc4_context
*vc4
,
1681 struct vc4_texture_stateobj
*texstate
,
1684 struct pipe_sampler_view
*texture
= texstate
->textures
[unit
];
1685 struct vc4_resource
*rsc
= vc4_resource(texture
->texture
);
1686 struct pipe_sampler_state
*sampler
= texstate
->samplers
[unit
];
1687 static const uint32_t mipfilter_map
[] = {
1688 [PIPE_TEX_MIPFILTER_NEAREST
] = 2,
1689 [PIPE_TEX_MIPFILTER_LINEAR
] = 4,
1690 [PIPE_TEX_MIPFILTER_NONE
] = 0
1692 static const uint32_t imgfilter_map
[] = {
1693 [PIPE_TEX_FILTER_NEAREST
] = 1,
1694 [PIPE_TEX_FILTER_LINEAR
] = 0,
1697 cl_u32(&vc4
->uniforms
,
1698 ((rsc
->vc4_format
>> 4) << 31) |
1699 (texture
->texture
->height0
<< 20) |
1700 (texture
->texture
->width0
<< 8) |
1701 (imgfilter_map
[sampler
->mag_img_filter
] << 7) |
1702 ((imgfilter_map
[sampler
->min_img_filter
] +
1703 mipfilter_map
[sampler
->min_mip_filter
]) << 4) |
1704 (translate_wrap(sampler
->wrap_t
) << 2) |
1705 (translate_wrap(sampler
->wrap_s
) << 0));
1709 get_texrect_scale(struct vc4_texture_stateobj
*texstate
,
1710 enum quniform_contents contents
,
1713 struct pipe_sampler_view
*texture
= texstate
->textures
[data
];
1716 if (contents
== QUNIFORM_TEXRECT_SCALE_X
)
1717 dim
= texture
->texture
->width0
;
1719 dim
= texture
->texture
->height0
;
1721 return fui(1.0f
/ dim
);
1725 vc4_write_uniforms(struct vc4_context
*vc4
, struct vc4_compiled_shader
*shader
,
1726 struct vc4_constbuf_stateobj
*cb
,
1727 struct vc4_texture_stateobj
*texstate
,
1730 struct vc4_shader_uniform_info
*uinfo
= &shader
->uniforms
[shader_index
];
1731 const uint32_t *gallium_uniforms
= cb
->cb
[0].user_buffer
;
1733 cl_start_shader_reloc(&vc4
->uniforms
, uinfo
->num_texture_samples
);
1735 for (int i
= 0; i
< uinfo
->count
; i
++) {
1737 switch (uinfo
->contents
[i
]) {
1738 case QUNIFORM_CONSTANT
:
1739 cl_u32(&vc4
->uniforms
, uinfo
->data
[i
]);
1741 case QUNIFORM_UNIFORM
:
1742 cl_u32(&vc4
->uniforms
,
1743 gallium_uniforms
[uinfo
->data
[i
]]);
1745 case QUNIFORM_VIEWPORT_X_SCALE
:
1746 cl_f(&vc4
->uniforms
, vc4
->viewport
.scale
[0] * 16.0f
);
1748 case QUNIFORM_VIEWPORT_Y_SCALE
:
1749 cl_f(&vc4
->uniforms
, vc4
->viewport
.scale
[1] * 16.0f
);
1752 case QUNIFORM_VIEWPORT_Z_OFFSET
:
1753 cl_f(&vc4
->uniforms
, vc4
->viewport
.translate
[2]);
1755 case QUNIFORM_VIEWPORT_Z_SCALE
:
1756 cl_f(&vc4
->uniforms
, vc4
->viewport
.scale
[2]);
1759 case QUNIFORM_TEXTURE_CONFIG_P0
:
1760 write_texture_p0(vc4
, texstate
, uinfo
->data
[i
]);
1763 case QUNIFORM_TEXTURE_CONFIG_P1
:
1764 write_texture_p1(vc4
, texstate
, uinfo
->data
[i
]);
1767 case QUNIFORM_TEXRECT_SCALE_X
:
1768 case QUNIFORM_TEXRECT_SCALE_Y
:
1769 cl_u32(&vc4
->uniforms
,
1770 get_texrect_scale(texstate
,
1775 case QUNIFORM_BLEND_CONST_COLOR
:
1776 cl_f(&vc4
->uniforms
,
1777 vc4
->blend_color
.color
[uinfo
->data
[i
]]);
1781 uint32_t written_val
= *(uint32_t *)(vc4
->uniforms
.next
- 4);
1782 fprintf(stderr
, "%p/%d: %d: 0x%08x (%f)\n",
1783 shader
, shader_index
, i
, written_val
, uif(written_val
));
1789 vc4_fp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
1791 struct vc4_context
*vc4
= vc4_context(pctx
);
1792 vc4
->prog
.bind_fs
= hwcso
;
1793 vc4
->prog
.dirty
|= VC4_SHADER_DIRTY_FP
;
1794 vc4
->dirty
|= VC4_DIRTY_PROG
;
1798 vc4_vp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
1800 struct vc4_context
*vc4
= vc4_context(pctx
);
1801 vc4
->prog
.bind_vs
= hwcso
;
1802 vc4
->prog
.dirty
|= VC4_SHADER_DIRTY_VP
;
1803 vc4
->dirty
|= VC4_DIRTY_PROG
;
1807 vc4_program_init(struct pipe_context
*pctx
)
1809 struct vc4_context
*vc4
= vc4_context(pctx
);
1811 pctx
->create_vs_state
= vc4_shader_state_create
;
1812 pctx
->delete_vs_state
= vc4_shader_state_delete
;
1814 pctx
->create_fs_state
= vc4_shader_state_create
;
1815 pctx
->delete_fs_state
= vc4_shader_state_delete
;
1817 pctx
->bind_fs_state
= vc4_fp_state_bind
;
1818 pctx
->bind_vs_state
= vc4_vp_state_bind
;
1820 vc4
->fs_cache
= util_hash_table_create(fs_cache_hash
, fs_cache_compare
);
1821 vc4
->vs_cache
= util_hash_table_create(vs_cache_hash
, vs_cache_compare
);