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Added few more stubs so that control reaches to DestroyDevice().
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "util/format/u_format.h"
27 #include "util/crc32.h"
28 #include "util/u_helpers.h"
29 #include "util/u_math.h"
30 #include "util/u_memory.h"
31 #include "util/ralloc.h"
32 #include "util/hash_table.h"
33 #include "tgsi/tgsi_dump.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "compiler/nir/nir.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "compiler/nir_types.h"
38 #include "nir/tgsi_to_nir.h"
39 #include "vc4_context.h"
40 #include "vc4_qpu.h"
41 #include "vc4_qir.h"
42
43 static struct qreg
44 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
45 static void
46 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
47
48 static int
49 type_size(const struct glsl_type *type, bool bindless)
50 {
51 return glsl_count_attribute_slots(type, false);
52 }
53
54 static void
55 resize_qreg_array(struct vc4_compile *c,
56 struct qreg **regs,
57 uint32_t *size,
58 uint32_t decl_size)
59 {
60 if (*size >= decl_size)
61 return;
62
63 uint32_t old_size = *size;
64 *size = MAX2(*size * 2, decl_size);
65 *regs = reralloc(c, *regs, struct qreg, *size);
66 if (!*regs) {
67 fprintf(stderr, "Malloc failure\n");
68 abort();
69 }
70
71 for (uint32_t i = old_size; i < *size; i++)
72 (*regs)[i] = c->undef;
73 }
74
75 static void
76 ntq_emit_thrsw(struct vc4_compile *c)
77 {
78 if (!c->fs_threaded)
79 return;
80
81 /* Always thread switch after each texture operation for now.
82 *
83 * We could do better by batching a bunch of texture fetches up and
84 * then doing one thread switch and collecting all their results
85 * afterward.
86 */
87 qir_emit_nondef(c, qir_inst(QOP_THRSW, c->undef,
88 c->undef, c->undef));
89 c->last_thrsw_at_top_level = (c->execute.file == QFILE_NULL);
90 }
91
92 static struct qreg
93 indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
94 {
95 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
96
97 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
98 uint32_t range = nir_intrinsic_range(intr);
99 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
100 indirect_offset = qir_MIN_NOIMM(c, indirect_offset,
101 qir_uniform_ui(c, range - 4));
102
103 qir_ADD_dest(c, qir_reg(QFILE_TEX_S_DIRECT, 0),
104 indirect_offset,
105 qir_uniform(c, QUNIFORM_UBO0_ADDR,
106 nir_intrinsic_base(intr)));
107
108 c->num_texture_samples++;
109
110 ntq_emit_thrsw(c);
111
112 return qir_TEX_RESULT(c);
113 }
114
115 static struct qreg
116 vc4_ubo_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
117 {
118 ASSERTED int buffer_index = nir_src_as_uint(intr->src[0]);
119 assert(buffer_index == 1);
120 assert(c->stage == QSTAGE_FRAG);
121
122 struct qreg offset = ntq_get_src(c, intr->src[1], 0);
123
124 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
125 offset = qir_MAX(c, offset, qir_uniform_ui(c, 0));
126 offset = qir_MIN_NOIMM(c, offset,
127 qir_uniform_ui(c, c->fs_key->ubo_1_size - 4));
128
129 qir_ADD_dest(c, qir_reg(QFILE_TEX_S_DIRECT, 0),
130 offset,
131 qir_uniform(c, QUNIFORM_UBO1_ADDR, 0));
132
133 c->num_texture_samples++;
134
135 ntq_emit_thrsw(c);
136
137 return qir_TEX_RESULT(c);
138 }
139
140 nir_ssa_def *
141 vc4_nir_get_swizzled_channel(nir_builder *b, nir_ssa_def **srcs, int swiz)
142 {
143 switch (swiz) {
144 default:
145 case PIPE_SWIZZLE_NONE:
146 fprintf(stderr, "warning: unknown swizzle\n");
147 /* FALLTHROUGH */
148 case PIPE_SWIZZLE_0:
149 return nir_imm_float(b, 0.0);
150 case PIPE_SWIZZLE_1:
151 return nir_imm_float(b, 1.0);
152 case PIPE_SWIZZLE_X:
153 case PIPE_SWIZZLE_Y:
154 case PIPE_SWIZZLE_Z:
155 case PIPE_SWIZZLE_W:
156 return srcs[swiz];
157 }
158 }
159
160 static struct qreg *
161 ntq_init_ssa_def(struct vc4_compile *c, nir_ssa_def *def)
162 {
163 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
164 def->num_components);
165 _mesa_hash_table_insert(c->def_ht, def, qregs);
166 return qregs;
167 }
168
169 /**
170 * This function is responsible for getting QIR results into the associated
171 * storage for a NIR instruction.
172 *
173 * If it's a NIR SSA def, then we just set the associated hash table entry to
174 * the new result.
175 *
176 * If it's a NIR reg, then we need to update the existing qreg assigned to the
177 * NIR destination with the incoming value. To do that without introducing
178 * new MOVs, we require that the incoming qreg either be a uniform, or be
179 * SSA-defined by the previous QIR instruction in the block and rewritable by
180 * this function. That lets us sneak ahead and insert the SF flag beforehand
181 * (knowing that the previous instruction doesn't depend on flags) and rewrite
182 * its destination to be the NIR reg's destination
183 */
184 static void
185 ntq_store_dest(struct vc4_compile *c, nir_dest *dest, int chan,
186 struct qreg result)
187 {
188 struct qinst *last_inst = NULL;
189 if (!list_is_empty(&c->cur_block->instructions))
190 last_inst = (struct qinst *)c->cur_block->instructions.prev;
191
192 assert(result.file == QFILE_UNIF ||
193 (result.file == QFILE_TEMP &&
194 last_inst && last_inst == c->defs[result.index]));
195
196 if (dest->is_ssa) {
197 assert(chan < dest->ssa.num_components);
198
199 struct qreg *qregs;
200 struct hash_entry *entry =
201 _mesa_hash_table_search(c->def_ht, &dest->ssa);
202
203 if (entry)
204 qregs = entry->data;
205 else
206 qregs = ntq_init_ssa_def(c, &dest->ssa);
207
208 qregs[chan] = result;
209 } else {
210 nir_register *reg = dest->reg.reg;
211 assert(dest->reg.base_offset == 0);
212 assert(reg->num_array_elems == 0);
213 struct hash_entry *entry =
214 _mesa_hash_table_search(c->def_ht, reg);
215 struct qreg *qregs = entry->data;
216
217 /* Insert a MOV if the source wasn't an SSA def in the
218 * previous instruction.
219 */
220 if (result.file == QFILE_UNIF) {
221 result = qir_MOV(c, result);
222 last_inst = c->defs[result.index];
223 }
224
225 /* We know they're both temps, so just rewrite index. */
226 c->defs[last_inst->dst.index] = NULL;
227 last_inst->dst.index = qregs[chan].index;
228
229 /* If we're in control flow, then make this update of the reg
230 * conditional on the execution mask.
231 */
232 if (c->execute.file != QFILE_NULL) {
233 last_inst->dst.index = qregs[chan].index;
234
235 /* Set the flags to the current exec mask. To insert
236 * the SF, we temporarily remove our SSA instruction.
237 */
238 list_del(&last_inst->link);
239 qir_SF(c, c->execute);
240 list_addtail(&last_inst->link,
241 &c->cur_block->instructions);
242
243 last_inst->cond = QPU_COND_ZS;
244 last_inst->cond_is_exec_mask = true;
245 }
246 }
247 }
248
249 static struct qreg *
250 ntq_get_dest(struct vc4_compile *c, nir_dest *dest)
251 {
252 if (dest->is_ssa) {
253 struct qreg *qregs = ntq_init_ssa_def(c, &dest->ssa);
254 for (int i = 0; i < dest->ssa.num_components; i++)
255 qregs[i] = c->undef;
256 return qregs;
257 } else {
258 nir_register *reg = dest->reg.reg;
259 assert(dest->reg.base_offset == 0);
260 assert(reg->num_array_elems == 0);
261 struct hash_entry *entry =
262 _mesa_hash_table_search(c->def_ht, reg);
263 return entry->data;
264 }
265 }
266
267 static struct qreg
268 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
269 {
270 struct hash_entry *entry;
271 if (src.is_ssa) {
272 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
273 assert(i < src.ssa->num_components);
274 } else {
275 nir_register *reg = src.reg.reg;
276 entry = _mesa_hash_table_search(c->def_ht, reg);
277 assert(reg->num_array_elems == 0);
278 assert(src.reg.base_offset == 0);
279 assert(i < reg->num_components);
280 }
281
282 struct qreg *qregs = entry->data;
283 return qregs[i];
284 }
285
286 static struct qreg
287 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
288 unsigned src)
289 {
290 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
291 unsigned chan = ffs(instr->dest.write_mask) - 1;
292 struct qreg r = ntq_get_src(c, instr->src[src].src,
293 instr->src[src].swizzle[chan]);
294
295 assert(!instr->src[src].abs);
296 assert(!instr->src[src].negate);
297
298 return r;
299 };
300
301 static inline struct qreg
302 qir_SAT(struct vc4_compile *c, struct qreg val)
303 {
304 return qir_FMAX(c,
305 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
306 qir_uniform_f(c, 0.0));
307 }
308
309 static struct qreg
310 ntq_rcp(struct vc4_compile *c, struct qreg x)
311 {
312 struct qreg r = qir_RCP(c, x);
313
314 /* Apply a Newton-Raphson step to improve the accuracy. */
315 r = qir_FMUL(c, r, qir_FSUB(c,
316 qir_uniform_f(c, 2.0),
317 qir_FMUL(c, x, r)));
318
319 return r;
320 }
321
322 static struct qreg
323 ntq_rsq(struct vc4_compile *c, struct qreg x)
324 {
325 struct qreg r = qir_RSQ(c, x);
326
327 /* Apply a Newton-Raphson step to improve the accuracy. */
328 r = qir_FMUL(c, r, qir_FSUB(c,
329 qir_uniform_f(c, 1.5),
330 qir_FMUL(c,
331 qir_uniform_f(c, 0.5),
332 qir_FMUL(c, x,
333 qir_FMUL(c, r, r)))));
334
335 return r;
336 }
337
338 static struct qreg
339 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
340 {
341 struct qreg src0_hi = qir_SHR(c, src0,
342 qir_uniform_ui(c, 24));
343 struct qreg src1_hi = qir_SHR(c, src1,
344 qir_uniform_ui(c, 24));
345
346 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
347 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
348 struct qreg lolo = qir_MUL24(c, src0, src1);
349
350 return qir_ADD(c, lolo, qir_SHL(c,
351 qir_ADD(c, hilo, lohi),
352 qir_uniform_ui(c, 24)));
353 }
354
355 static struct qreg
356 ntq_scale_depth_texture(struct vc4_compile *c, struct qreg src)
357 {
358 struct qreg depthf = qir_ITOF(c, qir_SHR(c, src,
359 qir_uniform_ui(c, 8)));
360 return qir_FMUL(c, depthf, qir_uniform_f(c, 1.0f/0xffffff));
361 }
362
363 /**
364 * Emits a lowered TXF_MS from an MSAA texture.
365 *
366 * The addressing math has been lowered in NIR, and now we just need to read
367 * it like a UBO.
368 */
369 static void
370 ntq_emit_txf(struct vc4_compile *c, nir_tex_instr *instr)
371 {
372 uint32_t tile_width = 32;
373 uint32_t tile_height = 32;
374 uint32_t tile_size = (tile_height * tile_width *
375 VC4_MAX_SAMPLES * sizeof(uint32_t));
376
377 unsigned unit = instr->texture_index;
378 uint32_t w = align(c->key->tex[unit].msaa_width, tile_width);
379 uint32_t w_tiles = w / tile_width;
380 uint32_t h = align(c->key->tex[unit].msaa_height, tile_height);
381 uint32_t h_tiles = h / tile_height;
382 uint32_t size = w_tiles * h_tiles * tile_size;
383
384 struct qreg addr;
385 assert(instr->num_srcs == 1);
386 assert(instr->src[0].src_type == nir_tex_src_coord);
387 addr = ntq_get_src(c, instr->src[0].src, 0);
388
389 /* Perform the clamping required by kernel validation. */
390 addr = qir_MAX(c, addr, qir_uniform_ui(c, 0));
391 addr = qir_MIN_NOIMM(c, addr, qir_uniform_ui(c, size - 4));
392
393 qir_ADD_dest(c, qir_reg(QFILE_TEX_S_DIRECT, 0),
394 addr, qir_uniform(c, QUNIFORM_TEXTURE_MSAA_ADDR, unit));
395
396 ntq_emit_thrsw(c);
397
398 struct qreg tex = qir_TEX_RESULT(c);
399 c->num_texture_samples++;
400
401 enum pipe_format format = c->key->tex[unit].format;
402 if (util_format_is_depth_or_stencil(format)) {
403 struct qreg scaled = ntq_scale_depth_texture(c, tex);
404 for (int i = 0; i < 4; i++)
405 ntq_store_dest(c, &instr->dest, i, qir_MOV(c, scaled));
406 } else {
407 for (int i = 0; i < 4; i++)
408 ntq_store_dest(c, &instr->dest, i,
409 qir_UNPACK_8_F(c, tex, i));
410 }
411 }
412
413 static void
414 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
415 {
416 struct qreg s, t, r, lod, compare;
417 bool is_txb = false, is_txl = false;
418 unsigned unit = instr->texture_index;
419
420 if (instr->op == nir_texop_txf) {
421 ntq_emit_txf(c, instr);
422 return;
423 }
424
425 for (unsigned i = 0; i < instr->num_srcs; i++) {
426 switch (instr->src[i].src_type) {
427 case nir_tex_src_coord:
428 s = ntq_get_src(c, instr->src[i].src, 0);
429 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
430 t = qir_uniform_f(c, 0.5);
431 else
432 t = ntq_get_src(c, instr->src[i].src, 1);
433 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
434 r = ntq_get_src(c, instr->src[i].src, 2);
435 break;
436 case nir_tex_src_bias:
437 lod = ntq_get_src(c, instr->src[i].src, 0);
438 is_txb = true;
439 break;
440 case nir_tex_src_lod:
441 lod = ntq_get_src(c, instr->src[i].src, 0);
442 is_txl = true;
443 break;
444 case nir_tex_src_comparator:
445 compare = ntq_get_src(c, instr->src[i].src, 0);
446 break;
447 default:
448 unreachable("unknown texture source");
449 }
450 }
451
452 if (c->stage != QSTAGE_FRAG && !is_txl) {
453 /* From the GLSL 1.20 spec:
454 *
455 * "If it is mip-mapped and running on the vertex shader,
456 * then the base texture is used."
457 */
458 is_txl = true;
459 lod = qir_uniform_ui(c, 0);
460 }
461
462 if (c->key->tex[unit].force_first_level) {
463 lod = qir_uniform(c, QUNIFORM_TEXTURE_FIRST_LEVEL, unit);
464 is_txl = true;
465 is_txb = false;
466 }
467
468 struct qreg texture_u[] = {
469 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
470 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
471 qir_uniform(c, QUNIFORM_CONSTANT, 0),
472 qir_uniform(c, QUNIFORM_CONSTANT, 0),
473 };
474 uint32_t next_texture_u = 0;
475
476 /* There is no native support for GL texture rectangle coordinates, so
477 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
478 * 1]).
479 */
480 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
481 s = qir_FMUL(c, s,
482 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
483 t = qir_FMUL(c, t,
484 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
485 }
486
487 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
488 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
489 unit | (is_txl << 16));
490 }
491
492 struct qinst *tmu;
493 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
494 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_R, 0), r);
495 tmu->src[qir_get_tex_uniform_src(tmu)] =
496 texture_u[next_texture_u++];
497 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
498 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
499 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
500 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
501 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_R, 0),
502 qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR,
503 unit));
504 tmu->src[qir_get_tex_uniform_src(tmu)] =
505 texture_u[next_texture_u++];
506 }
507
508 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
509 s = qir_SAT(c, s);
510 }
511
512 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
513 t = qir_SAT(c, t);
514 }
515
516 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_T, 0), t);
517 tmu->src[qir_get_tex_uniform_src(tmu)] =
518 texture_u[next_texture_u++];
519
520 if (is_txl || is_txb) {
521 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_B, 0), lod);
522 tmu->src[qir_get_tex_uniform_src(tmu)] =
523 texture_u[next_texture_u++];
524 }
525
526 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_S, 0), s);
527 tmu->src[qir_get_tex_uniform_src(tmu)] = texture_u[next_texture_u++];
528
529 c->num_texture_samples++;
530
531 ntq_emit_thrsw(c);
532
533 struct qreg tex = qir_TEX_RESULT(c);
534
535 enum pipe_format format = c->key->tex[unit].format;
536
537 struct qreg *dest = ntq_get_dest(c, &instr->dest);
538 if (util_format_is_depth_or_stencil(format)) {
539 struct qreg normalized = ntq_scale_depth_texture(c, tex);
540 struct qreg depth_output;
541
542 struct qreg u0 = qir_uniform_f(c, 0.0f);
543 struct qreg u1 = qir_uniform_f(c, 1.0f);
544 if (c->key->tex[unit].compare_mode) {
545 /* From the GL_ARB_shadow spec:
546 *
547 * "Let Dt (D subscript t) be the depth texture
548 * value, in the range [0, 1]. Let R be the
549 * interpolated texture coordinate clamped to the
550 * range [0, 1]."
551 */
552 compare = qir_SAT(c, compare);
553
554 switch (c->key->tex[unit].compare_func) {
555 case PIPE_FUNC_NEVER:
556 depth_output = qir_uniform_f(c, 0.0f);
557 break;
558 case PIPE_FUNC_ALWAYS:
559 depth_output = u1;
560 break;
561 case PIPE_FUNC_EQUAL:
562 qir_SF(c, qir_FSUB(c, compare, normalized));
563 depth_output = qir_SEL(c, QPU_COND_ZS, u1, u0);
564 break;
565 case PIPE_FUNC_NOTEQUAL:
566 qir_SF(c, qir_FSUB(c, compare, normalized));
567 depth_output = qir_SEL(c, QPU_COND_ZC, u1, u0);
568 break;
569 case PIPE_FUNC_GREATER:
570 qir_SF(c, qir_FSUB(c, compare, normalized));
571 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
572 break;
573 case PIPE_FUNC_GEQUAL:
574 qir_SF(c, qir_FSUB(c, normalized, compare));
575 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
576 break;
577 case PIPE_FUNC_LESS:
578 qir_SF(c, qir_FSUB(c, compare, normalized));
579 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
580 break;
581 case PIPE_FUNC_LEQUAL:
582 qir_SF(c, qir_FSUB(c, normalized, compare));
583 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
584 break;
585 }
586 } else {
587 depth_output = normalized;
588 }
589
590 for (int i = 0; i < 4; i++)
591 dest[i] = depth_output;
592 } else {
593 for (int i = 0; i < 4; i++)
594 dest[i] = qir_UNPACK_8_F(c, tex, i);
595 }
596 }
597
598 /**
599 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
600 * to zero).
601 */
602 static struct qreg
603 ntq_ffract(struct vc4_compile *c, struct qreg src)
604 {
605 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
606 struct qreg diff = qir_FSUB(c, src, trunc);
607 qir_SF(c, diff);
608
609 qir_FADD_dest(c, diff,
610 diff, qir_uniform_f(c, 1.0))->cond = QPU_COND_NS;
611
612 return qir_MOV(c, diff);
613 }
614
615 /**
616 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
617 * zero).
618 */
619 static struct qreg
620 ntq_ffloor(struct vc4_compile *c, struct qreg src)
621 {
622 struct qreg result = qir_ITOF(c, qir_FTOI(c, src));
623
624 /* This will be < 0 if we truncated and the truncation was of a value
625 * that was < 0 in the first place.
626 */
627 qir_SF(c, qir_FSUB(c, src, result));
628
629 struct qinst *sub = qir_FSUB_dest(c, result,
630 result, qir_uniform_f(c, 1.0));
631 sub->cond = QPU_COND_NS;
632
633 return qir_MOV(c, result);
634 }
635
636 /**
637 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
638 * zero).
639 */
640 static struct qreg
641 ntq_fceil(struct vc4_compile *c, struct qreg src)
642 {
643 struct qreg result = qir_ITOF(c, qir_FTOI(c, src));
644
645 /* This will be < 0 if we truncated and the truncation was of a value
646 * that was > 0 in the first place.
647 */
648 qir_SF(c, qir_FSUB(c, result, src));
649
650 qir_FADD_dest(c, result,
651 result, qir_uniform_f(c, 1.0))->cond = QPU_COND_NS;
652
653 return qir_MOV(c, result);
654 }
655
656 static struct qreg
657 ntq_shrink_sincos_input_range(struct vc4_compile *c, struct qreg x)
658 {
659 /* Since we're using a Taylor approximation, we want to have a small
660 * number of coefficients and take advantage of sin/cos repeating
661 * every 2pi. We keep our x as close to 0 as we can, since the series
662 * will be less accurate as |x| increases. (Also, be careful of
663 * shifting the input x value to be tricky with sin/cos relations,
664 * because getting accurate values for x==0 is very important for SDL
665 * rendering)
666 */
667 struct qreg scaled_x =
668 qir_FMUL(c, x,
669 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
670 /* Note: FTOI truncates toward 0. */
671 struct qreg x_frac = qir_FSUB(c, scaled_x,
672 qir_ITOF(c, qir_FTOI(c, scaled_x)));
673 /* Map [0.5, 1] to [-0.5, 0] */
674 qir_SF(c, qir_FSUB(c, x_frac, qir_uniform_f(c, 0.5)));
675 qir_FSUB_dest(c, x_frac, x_frac, qir_uniform_f(c, 1.0))->cond = QPU_COND_NC;
676 /* Map [-1, -0.5] to [0, 0.5] */
677 qir_SF(c, qir_FADD(c, x_frac, qir_uniform_f(c, 0.5)));
678 qir_FADD_dest(c, x_frac, x_frac, qir_uniform_f(c, 1.0))->cond = QPU_COND_NS;
679
680 return x_frac;
681 }
682
683 static struct qreg
684 ntq_fsin(struct vc4_compile *c, struct qreg src)
685 {
686 float coeff[] = {
687 2.0 * M_PI,
688 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
689 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
690 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
691 pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
692 };
693
694 struct qreg x = ntq_shrink_sincos_input_range(c, src);
695 struct qreg x2 = qir_FMUL(c, x, x);
696 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
697 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
698 x = qir_FMUL(c, x, x2);
699 sum = qir_FADD(c,
700 sum,
701 qir_FMUL(c,
702 x,
703 qir_uniform_f(c, coeff[i])));
704 }
705 return sum;
706 }
707
708 static struct qreg
709 ntq_fcos(struct vc4_compile *c, struct qreg src)
710 {
711 float coeff[] = {
712 1.0f,
713 -pow(2.0 * M_PI, 2) / (2 * 1),
714 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
715 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
716 pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
717 -pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
718 };
719
720 struct qreg x_frac = ntq_shrink_sincos_input_range(c, src);
721 struct qreg sum = qir_uniform_f(c, coeff[0]);
722 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
723 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
724 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
725 if (i != 1)
726 x = qir_FMUL(c, x, x2);
727
728 sum = qir_FADD(c, qir_FMUL(c,
729 x,
730 qir_uniform_f(c, coeff[i])),
731 sum);
732 }
733 return sum;
734 }
735
736 static struct qreg
737 ntq_fsign(struct vc4_compile *c, struct qreg src)
738 {
739 struct qreg t = qir_get_temp(c);
740
741 qir_SF(c, src);
742 qir_MOV_dest(c, t, qir_uniform_f(c, 0.0));
743 qir_MOV_dest(c, t, qir_uniform_f(c, 1.0))->cond = QPU_COND_ZC;
744 qir_MOV_dest(c, t, qir_uniform_f(c, -1.0))->cond = QPU_COND_NS;
745 return qir_MOV(c, t);
746 }
747
748 static void
749 emit_vertex_input(struct vc4_compile *c, int attr)
750 {
751 enum pipe_format format = c->vs_key->attr_formats[attr];
752 uint32_t attr_size = util_format_get_blocksize(format);
753
754 c->vattr_sizes[attr] = align(attr_size, 4);
755 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
756 c->inputs[attr * 4 + i] =
757 qir_MOV(c, qir_reg(QFILE_VPM, attr * 4 + i));
758 c->num_inputs++;
759 }
760 }
761
762 static void
763 emit_fragcoord_input(struct vc4_compile *c, int attr)
764 {
765 c->inputs[attr * 4 + 0] = qir_ITOF(c, qir_reg(QFILE_FRAG_X, 0));
766 c->inputs[attr * 4 + 1] = qir_ITOF(c, qir_reg(QFILE_FRAG_Y, 0));
767 c->inputs[attr * 4 + 2] =
768 qir_FMUL(c,
769 qir_ITOF(c, qir_FRAG_Z(c)),
770 qir_uniform_f(c, 1.0 / 0xffffff));
771 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
772 }
773
774 static struct qreg
775 emit_fragment_varying(struct vc4_compile *c, gl_varying_slot slot,
776 uint8_t swizzle)
777 {
778 uint32_t i = c->num_input_slots++;
779 struct qreg vary = {
780 QFILE_VARY,
781 i
782 };
783
784 if (c->num_input_slots >= c->input_slots_array_size) {
785 c->input_slots_array_size =
786 MAX2(4, c->input_slots_array_size * 2);
787
788 c->input_slots = reralloc(c, c->input_slots,
789 struct vc4_varying_slot,
790 c->input_slots_array_size);
791 }
792
793 c->input_slots[i].slot = slot;
794 c->input_slots[i].swizzle = swizzle;
795
796 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
797 }
798
799 static void
800 emit_fragment_input(struct vc4_compile *c, int attr, gl_varying_slot slot)
801 {
802 for (int i = 0; i < 4; i++) {
803 c->inputs[attr * 4 + i] =
804 emit_fragment_varying(c, slot, i);
805 c->num_inputs++;
806 }
807 }
808
809 static void
810 add_output(struct vc4_compile *c,
811 uint32_t decl_offset,
812 uint8_t slot,
813 uint8_t swizzle)
814 {
815 uint32_t old_array_size = c->outputs_array_size;
816 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
817 decl_offset + 1);
818
819 if (old_array_size != c->outputs_array_size) {
820 c->output_slots = reralloc(c,
821 c->output_slots,
822 struct vc4_varying_slot,
823 c->outputs_array_size);
824 }
825
826 c->output_slots[decl_offset].slot = slot;
827 c->output_slots[decl_offset].swizzle = swizzle;
828 }
829
830 static bool
831 ntq_src_is_only_ssa_def_user(nir_src *src)
832 {
833 if (!src->is_ssa)
834 return false;
835
836 if (!list_is_empty(&src->ssa->if_uses))
837 return false;
838
839 return (src->ssa->uses.next == &src->use_link &&
840 src->ssa->uses.next->next == &src->ssa->uses);
841 }
842
843 /**
844 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
845 * bit set.
846 *
847 * However, as an optimization, it tries to find the instructions generating
848 * the sources to be packed and just emit the pack flag there, if possible.
849 */
850 static void
851 ntq_emit_pack_unorm_4x8(struct vc4_compile *c, nir_alu_instr *instr)
852 {
853 struct qreg result = qir_get_temp(c);
854 struct nir_alu_instr *vec4 = NULL;
855
856 /* If packing from a vec4 op (as expected), identify it so that we can
857 * peek back at what generated its sources.
858 */
859 if (instr->src[0].src.is_ssa &&
860 instr->src[0].src.ssa->parent_instr->type == nir_instr_type_alu &&
861 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr)->op ==
862 nir_op_vec4) {
863 vec4 = nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
864 }
865
866 /* If the pack is replicating the same channel 4 times, use the 8888
867 * pack flag. This is common for blending using the alpha
868 * channel.
869 */
870 if (instr->src[0].swizzle[0] == instr->src[0].swizzle[1] &&
871 instr->src[0].swizzle[0] == instr->src[0].swizzle[2] &&
872 instr->src[0].swizzle[0] == instr->src[0].swizzle[3]) {
873 struct qreg rep = ntq_get_src(c,
874 instr->src[0].src,
875 instr->src[0].swizzle[0]);
876 ntq_store_dest(c, &instr->dest.dest, 0, qir_PACK_8888_F(c, rep));
877 return;
878 }
879
880 for (int i = 0; i < 4; i++) {
881 int swiz = instr->src[0].swizzle[i];
882 struct qreg src;
883 if (vec4) {
884 src = ntq_get_src(c, vec4->src[swiz].src,
885 vec4->src[swiz].swizzle[0]);
886 } else {
887 src = ntq_get_src(c, instr->src[0].src, swiz);
888 }
889
890 if (vec4 &&
891 ntq_src_is_only_ssa_def_user(&vec4->src[swiz].src) &&
892 src.file == QFILE_TEMP &&
893 c->defs[src.index] &&
894 qir_is_mul(c->defs[src.index]) &&
895 !c->defs[src.index]->dst.pack) {
896 struct qinst *rewrite = c->defs[src.index];
897 c->defs[src.index] = NULL;
898 rewrite->dst = result;
899 rewrite->dst.pack = QPU_PACK_MUL_8A + i;
900 continue;
901 }
902
903 qir_PACK_8_F(c, result, src, i);
904 }
905
906 ntq_store_dest(c, &instr->dest.dest, 0, qir_MOV(c, result));
907 }
908
909 /** Handles sign-extended bitfield extracts for 16 bits. */
910 static struct qreg
911 ntq_emit_ibfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
912 struct qreg bits)
913 {
914 assert(bits.file == QFILE_UNIF &&
915 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
916 c->uniform_data[bits.index] == 16);
917
918 assert(offset.file == QFILE_UNIF &&
919 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
920 int offset_bit = c->uniform_data[offset.index];
921 assert(offset_bit % 16 == 0);
922
923 return qir_UNPACK_16_I(c, base, offset_bit / 16);
924 }
925
926 /** Handles unsigned bitfield extracts for 8 bits. */
927 static struct qreg
928 ntq_emit_ubfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
929 struct qreg bits)
930 {
931 assert(bits.file == QFILE_UNIF &&
932 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
933 c->uniform_data[bits.index] == 8);
934
935 assert(offset.file == QFILE_UNIF &&
936 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
937 int offset_bit = c->uniform_data[offset.index];
938 assert(offset_bit % 8 == 0);
939
940 return qir_UNPACK_8_I(c, base, offset_bit / 8);
941 }
942
943 /**
944 * If compare_instr is a valid comparison instruction, emits the
945 * compare_instr's comparison and returns the sel_instr's return value based
946 * on the compare_instr's result.
947 */
948 static bool
949 ntq_emit_comparison(struct vc4_compile *c, struct qreg *dest,
950 nir_alu_instr *compare_instr,
951 nir_alu_instr *sel_instr)
952 {
953 enum qpu_cond cond;
954
955 switch (compare_instr->op) {
956 case nir_op_feq32:
957 case nir_op_ieq32:
958 case nir_op_seq:
959 cond = QPU_COND_ZS;
960 break;
961 case nir_op_fneu32:
962 case nir_op_ine32:
963 case nir_op_sne:
964 cond = QPU_COND_ZC;
965 break;
966 case nir_op_fge32:
967 case nir_op_ige32:
968 case nir_op_uge32:
969 case nir_op_sge:
970 cond = QPU_COND_NC;
971 break;
972 case nir_op_flt32:
973 case nir_op_ilt32:
974 case nir_op_slt:
975 cond = QPU_COND_NS;
976 break;
977 default:
978 return false;
979 }
980
981 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
982 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
983
984 unsigned unsized_type =
985 nir_alu_type_get_base_type(nir_op_infos[compare_instr->op].input_types[0]);
986 if (unsized_type == nir_type_float)
987 qir_SF(c, qir_FSUB(c, src0, src1));
988 else
989 qir_SF(c, qir_SUB(c, src0, src1));
990
991 switch (sel_instr->op) {
992 case nir_op_seq:
993 case nir_op_sne:
994 case nir_op_sge:
995 case nir_op_slt:
996 *dest = qir_SEL(c, cond,
997 qir_uniform_f(c, 1.0), qir_uniform_f(c, 0.0));
998 break;
999
1000 case nir_op_b32csel:
1001 *dest = qir_SEL(c, cond,
1002 ntq_get_alu_src(c, sel_instr, 1),
1003 ntq_get_alu_src(c, sel_instr, 2));
1004 break;
1005
1006 default:
1007 *dest = qir_SEL(c, cond,
1008 qir_uniform_ui(c, ~0), qir_uniform_ui(c, 0));
1009 break;
1010 }
1011
1012 /* Make the temporary for nir_store_dest(). */
1013 *dest = qir_MOV(c, *dest);
1014
1015 return true;
1016 }
1017
1018 /**
1019 * Attempts to fold a comparison generating a boolean result into the
1020 * condition code for selecting between two values, instead of comparing the
1021 * boolean result against 0 to generate the condition code.
1022 */
1023 static struct qreg ntq_emit_bcsel(struct vc4_compile *c, nir_alu_instr *instr,
1024 struct qreg *src)
1025 {
1026 if (!instr->src[0].src.is_ssa)
1027 goto out;
1028 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
1029 goto out;
1030 nir_alu_instr *compare =
1031 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
1032 if (!compare)
1033 goto out;
1034
1035 struct qreg dest;
1036 if (ntq_emit_comparison(c, &dest, compare, instr))
1037 return dest;
1038
1039 out:
1040 qir_SF(c, src[0]);
1041 return qir_MOV(c, qir_SEL(c, QPU_COND_NS, src[1], src[2]));
1042 }
1043
1044 static struct qreg
1045 ntq_fddx(struct vc4_compile *c, struct qreg src)
1046 {
1047 /* Make sure that we have a bare temp to use for MUL rotation, so it
1048 * can be allocated to an accumulator.
1049 */
1050 if (src.pack || src.file != QFILE_TEMP)
1051 src = qir_MOV(c, src);
1052
1053 struct qreg from_left = qir_ROT_MUL(c, src, 1);
1054 struct qreg from_right = qir_ROT_MUL(c, src, 15);
1055
1056 /* Distinguish left/right pixels of the quad. */
1057 qir_SF(c, qir_AND(c, qir_reg(QFILE_QPU_ELEMENT, 0),
1058 qir_uniform_ui(c, 1)));
1059
1060 return qir_MOV(c, qir_SEL(c, QPU_COND_ZS,
1061 qir_FSUB(c, from_right, src),
1062 qir_FSUB(c, src, from_left)));
1063 }
1064
1065 static struct qreg
1066 ntq_fddy(struct vc4_compile *c, struct qreg src)
1067 {
1068 if (src.pack || src.file != QFILE_TEMP)
1069 src = qir_MOV(c, src);
1070
1071 struct qreg from_bottom = qir_ROT_MUL(c, src, 2);
1072 struct qreg from_top = qir_ROT_MUL(c, src, 14);
1073
1074 /* Distinguish top/bottom pixels of the quad. */
1075 qir_SF(c, qir_AND(c,
1076 qir_reg(QFILE_QPU_ELEMENT, 0),
1077 qir_uniform_ui(c, 2)));
1078
1079 return qir_MOV(c, qir_SEL(c, QPU_COND_ZS,
1080 qir_FSUB(c, from_top, src),
1081 qir_FSUB(c, src, from_bottom)));
1082 }
1083
1084 static void
1085 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
1086 {
1087 /* This should always be lowered to ALU operations for VC4. */
1088 assert(!instr->dest.saturate);
1089
1090 /* Vectors are special in that they have non-scalarized writemasks,
1091 * and just take the first swizzle channel for each argument in order
1092 * into each writemask channel.
1093 */
1094 if (instr->op == nir_op_vec2 ||
1095 instr->op == nir_op_vec3 ||
1096 instr->op == nir_op_vec4) {
1097 struct qreg srcs[4];
1098 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1099 srcs[i] = ntq_get_src(c, instr->src[i].src,
1100 instr->src[i].swizzle[0]);
1101 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1102 ntq_store_dest(c, &instr->dest.dest, i,
1103 qir_MOV(c, srcs[i]));
1104 return;
1105 }
1106
1107 if (instr->op == nir_op_pack_unorm_4x8) {
1108 ntq_emit_pack_unorm_4x8(c, instr);
1109 return;
1110 }
1111
1112 if (instr->op == nir_op_unpack_unorm_4x8) {
1113 struct qreg src = ntq_get_src(c, instr->src[0].src,
1114 instr->src[0].swizzle[0]);
1115 for (int i = 0; i < 4; i++) {
1116 if (instr->dest.write_mask & (1 << i))
1117 ntq_store_dest(c, &instr->dest.dest, i,
1118 qir_UNPACK_8_F(c, src, i));
1119 }
1120 return;
1121 }
1122
1123 /* General case: We can just grab the one used channel per src. */
1124 struct qreg src[nir_op_infos[instr->op].num_inputs];
1125 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
1126 src[i] = ntq_get_alu_src(c, instr, i);
1127 }
1128
1129 struct qreg result;
1130
1131 switch (instr->op) {
1132 case nir_op_mov:
1133 result = qir_MOV(c, src[0]);
1134 break;
1135 case nir_op_fmul:
1136 result = qir_FMUL(c, src[0], src[1]);
1137 break;
1138 case nir_op_fadd:
1139 result = qir_FADD(c, src[0], src[1]);
1140 break;
1141 case nir_op_fsub:
1142 result = qir_FSUB(c, src[0], src[1]);
1143 break;
1144 case nir_op_fmin:
1145 result = qir_FMIN(c, src[0], src[1]);
1146 break;
1147 case nir_op_fmax:
1148 result = qir_FMAX(c, src[0], src[1]);
1149 break;
1150
1151 case nir_op_f2i32:
1152 case nir_op_f2u32:
1153 result = qir_FTOI(c, src[0]);
1154 break;
1155 case nir_op_i2f32:
1156 case nir_op_u2f32:
1157 result = qir_ITOF(c, src[0]);
1158 break;
1159 case nir_op_b2f32:
1160 result = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
1161 break;
1162 case nir_op_b2i32:
1163 result = qir_AND(c, src[0], qir_uniform_ui(c, 1));
1164 break;
1165 case nir_op_i2b32:
1166 case nir_op_f2b32:
1167 qir_SF(c, src[0]);
1168 result = qir_MOV(c, qir_SEL(c, QPU_COND_ZC,
1169 qir_uniform_ui(c, ~0),
1170 qir_uniform_ui(c, 0)));
1171 break;
1172
1173 case nir_op_iadd:
1174 result = qir_ADD(c, src[0], src[1]);
1175 break;
1176 case nir_op_ushr:
1177 result = qir_SHR(c, src[0], src[1]);
1178 break;
1179 case nir_op_isub:
1180 result = qir_SUB(c, src[0], src[1]);
1181 break;
1182 case nir_op_ishr:
1183 result = qir_ASR(c, src[0], src[1]);
1184 break;
1185 case nir_op_ishl:
1186 result = qir_SHL(c, src[0], src[1]);
1187 break;
1188 case nir_op_imin:
1189 result = qir_MIN(c, src[0], src[1]);
1190 break;
1191 case nir_op_imax:
1192 result = qir_MAX(c, src[0], src[1]);
1193 break;
1194 case nir_op_iand:
1195 result = qir_AND(c, src[0], src[1]);
1196 break;
1197 case nir_op_ior:
1198 result = qir_OR(c, src[0], src[1]);
1199 break;
1200 case nir_op_ixor:
1201 result = qir_XOR(c, src[0], src[1]);
1202 break;
1203 case nir_op_inot:
1204 result = qir_NOT(c, src[0]);
1205 break;
1206
1207 case nir_op_imul:
1208 result = ntq_umul(c, src[0], src[1]);
1209 break;
1210
1211 case nir_op_seq:
1212 case nir_op_sne:
1213 case nir_op_sge:
1214 case nir_op_slt:
1215 case nir_op_feq32:
1216 case nir_op_fneu32:
1217 case nir_op_fge32:
1218 case nir_op_flt32:
1219 case nir_op_ieq32:
1220 case nir_op_ine32:
1221 case nir_op_ige32:
1222 case nir_op_uge32:
1223 case nir_op_ilt32:
1224 if (!ntq_emit_comparison(c, &result, instr, instr)) {
1225 fprintf(stderr, "Bad comparison instruction\n");
1226 }
1227 break;
1228
1229 case nir_op_b32csel:
1230 result = ntq_emit_bcsel(c, instr, src);
1231 break;
1232 case nir_op_fcsel:
1233 qir_SF(c, src[0]);
1234 result = qir_MOV(c, qir_SEL(c, QPU_COND_ZC, src[1], src[2]));
1235 break;
1236
1237 case nir_op_frcp:
1238 result = ntq_rcp(c, src[0]);
1239 break;
1240 case nir_op_frsq:
1241 result = ntq_rsq(c, src[0]);
1242 break;
1243 case nir_op_fexp2:
1244 result = qir_EXP2(c, src[0]);
1245 break;
1246 case nir_op_flog2:
1247 result = qir_LOG2(c, src[0]);
1248 break;
1249
1250 case nir_op_ftrunc:
1251 result = qir_ITOF(c, qir_FTOI(c, src[0]));
1252 break;
1253 case nir_op_fceil:
1254 result = ntq_fceil(c, src[0]);
1255 break;
1256 case nir_op_ffract:
1257 result = ntq_ffract(c, src[0]);
1258 break;
1259 case nir_op_ffloor:
1260 result = ntq_ffloor(c, src[0]);
1261 break;
1262
1263 case nir_op_fsin:
1264 result = ntq_fsin(c, src[0]);
1265 break;
1266 case nir_op_fcos:
1267 result = ntq_fcos(c, src[0]);
1268 break;
1269
1270 case nir_op_fsign:
1271 result = ntq_fsign(c, src[0]);
1272 break;
1273
1274 case nir_op_fabs:
1275 result = qir_FMAXABS(c, src[0], src[0]);
1276 break;
1277 case nir_op_iabs:
1278 result = qir_MAX(c, src[0],
1279 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1280 break;
1281
1282 case nir_op_ibitfield_extract:
1283 result = ntq_emit_ibfe(c, src[0], src[1], src[2]);
1284 break;
1285
1286 case nir_op_ubitfield_extract:
1287 result = ntq_emit_ubfe(c, src[0], src[1], src[2]);
1288 break;
1289
1290 case nir_op_usadd_4x8:
1291 result = qir_V8ADDS(c, src[0], src[1]);
1292 break;
1293
1294 case nir_op_ussub_4x8:
1295 result = qir_V8SUBS(c, src[0], src[1]);
1296 break;
1297
1298 case nir_op_umin_4x8:
1299 result = qir_V8MIN(c, src[0], src[1]);
1300 break;
1301
1302 case nir_op_umax_4x8:
1303 result = qir_V8MAX(c, src[0], src[1]);
1304 break;
1305
1306 case nir_op_umul_unorm_4x8:
1307 result = qir_V8MULD(c, src[0], src[1]);
1308 break;
1309
1310 case nir_op_fddx:
1311 case nir_op_fddx_coarse:
1312 case nir_op_fddx_fine:
1313 result = ntq_fddx(c, src[0]);
1314 break;
1315
1316 case nir_op_fddy:
1317 case nir_op_fddy_coarse:
1318 case nir_op_fddy_fine:
1319 result = ntq_fddy(c, src[0]);
1320 break;
1321
1322 default:
1323 fprintf(stderr, "unknown NIR ALU inst: ");
1324 nir_print_instr(&instr->instr, stderr);
1325 fprintf(stderr, "\n");
1326 abort();
1327 }
1328
1329 /* We have a scalar result, so the instruction should only have a
1330 * single channel written to.
1331 */
1332 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1333 ntq_store_dest(c, &instr->dest.dest,
1334 ffs(instr->dest.write_mask) - 1, result);
1335 }
1336
1337 static void
1338 emit_frag_end(struct vc4_compile *c)
1339 {
1340 struct qreg color;
1341 if (c->output_color_index != -1) {
1342 color = c->outputs[c->output_color_index];
1343 } else {
1344 color = qir_uniform_ui(c, 0);
1345 }
1346
1347 uint32_t discard_cond = QPU_COND_ALWAYS;
1348 if (c->s->info.fs.uses_discard) {
1349 qir_SF(c, c->discard);
1350 discard_cond = QPU_COND_ZS;
1351 }
1352
1353 if (c->fs_key->stencil_enabled) {
1354 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1355 qir_uniform(c, QUNIFORM_STENCIL, 0));
1356 if (c->fs_key->stencil_twoside) {
1357 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1358 qir_uniform(c, QUNIFORM_STENCIL, 1));
1359 }
1360 if (c->fs_key->stencil_full_writemasks) {
1361 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1362 qir_uniform(c, QUNIFORM_STENCIL, 2));
1363 }
1364 }
1365
1366 if (c->output_sample_mask_index != -1) {
1367 qir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1368 }
1369
1370 if (c->fs_key->depth_enabled) {
1371 if (c->output_position_index != -1) {
1372 qir_FTOI_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1373 qir_FMUL(c,
1374 c->outputs[c->output_position_index],
1375 qir_uniform_f(c, 0xffffff)))->cond = discard_cond;
1376 } else {
1377 qir_MOV_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1378 qir_FRAG_Z(c))->cond = discard_cond;
1379 }
1380 }
1381
1382 if (!c->msaa_per_sample_output) {
1383 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE, 0),
1384 color)->cond = discard_cond;
1385 } else {
1386 for (int i = 0; i < VC4_MAX_SAMPLES; i++) {
1387 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE_MS, 0),
1388 c->sample_colors[i])->cond = discard_cond;
1389 }
1390 }
1391 }
1392
1393 static void
1394 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1395 {
1396 struct qreg packed = qir_get_temp(c);
1397
1398 for (int i = 0; i < 2; i++) {
1399 struct qreg scale =
1400 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1401
1402 struct qreg packed_chan = packed;
1403 packed_chan.pack = QPU_PACK_A_16A + i;
1404
1405 qir_FTOI_dest(c, packed_chan,
1406 qir_FMUL(c,
1407 qir_FMUL(c,
1408 c->outputs[c->output_position_index + i],
1409 scale),
1410 rcp_w));
1411 }
1412
1413 qir_VPM_WRITE(c, packed);
1414 }
1415
1416 static void
1417 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1418 {
1419 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1420 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1421
1422 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1423 c->outputs[c->output_position_index + 2],
1424 zscale),
1425 rcp_w),
1426 zoffset));
1427 }
1428
1429 static void
1430 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1431 {
1432 qir_VPM_WRITE(c, rcp_w);
1433 }
1434
1435 static void
1436 emit_point_size_write(struct vc4_compile *c)
1437 {
1438 struct qreg point_size;
1439
1440 if (c->output_point_size_index != -1)
1441 point_size = c->outputs[c->output_point_size_index];
1442 else
1443 point_size = qir_uniform_f(c, 1.0);
1444
1445 qir_VPM_WRITE(c, point_size);
1446 }
1447
1448 /**
1449 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1450 *
1451 * The simulator insists that there be at least one vertex attribute, so
1452 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1453 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1454 * to consume it here.
1455 */
1456 static void
1457 emit_stub_vpm_read(struct vc4_compile *c)
1458 {
1459 if (c->num_inputs)
1460 return;
1461
1462 c->vattr_sizes[0] = 4;
1463 (void)qir_MOV(c, qir_reg(QFILE_VPM, 0));
1464 c->num_inputs++;
1465 }
1466
1467 static void
1468 emit_vert_end(struct vc4_compile *c,
1469 struct vc4_varying_slot *fs_inputs,
1470 uint32_t num_fs_inputs)
1471 {
1472 struct qreg rcp_w = ntq_rcp(c, c->outputs[c->output_position_index + 3]);
1473
1474 emit_stub_vpm_read(c);
1475
1476 emit_scaled_viewport_write(c, rcp_w);
1477 emit_zs_write(c, rcp_w);
1478 emit_rcp_wc_write(c, rcp_w);
1479 if (c->vs_key->per_vertex_point_size)
1480 emit_point_size_write(c);
1481
1482 for (int i = 0; i < num_fs_inputs; i++) {
1483 struct vc4_varying_slot *input = &fs_inputs[i];
1484 int j;
1485
1486 for (j = 0; j < c->num_outputs; j++) {
1487 struct vc4_varying_slot *output =
1488 &c->output_slots[j];
1489
1490 if (input->slot == output->slot &&
1491 input->swizzle == output->swizzle) {
1492 qir_VPM_WRITE(c, c->outputs[j]);
1493 break;
1494 }
1495 }
1496 /* Emit padding if we didn't find a declared VS output for
1497 * this FS input.
1498 */
1499 if (j == c->num_outputs)
1500 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1501 }
1502 }
1503
1504 static void
1505 emit_coord_end(struct vc4_compile *c)
1506 {
1507 struct qreg rcp_w = ntq_rcp(c, c->outputs[c->output_position_index + 3]);
1508
1509 emit_stub_vpm_read(c);
1510
1511 for (int i = 0; i < 4; i++)
1512 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1513
1514 emit_scaled_viewport_write(c, rcp_w);
1515 emit_zs_write(c, rcp_w);
1516 emit_rcp_wc_write(c, rcp_w);
1517 if (c->vs_key->per_vertex_point_size)
1518 emit_point_size_write(c);
1519 }
1520
1521 static void
1522 vc4_optimize_nir(struct nir_shader *s)
1523 {
1524 bool progress;
1525 unsigned lower_flrp =
1526 (s->options->lower_flrp16 ? 16 : 0) |
1527 (s->options->lower_flrp32 ? 32 : 0) |
1528 (s->options->lower_flrp64 ? 64 : 0);
1529
1530 do {
1531 progress = false;
1532
1533 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1534 NIR_PASS(progress, s, nir_lower_alu_to_scalar, NULL, NULL);
1535 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1536 NIR_PASS(progress, s, nir_copy_prop);
1537 NIR_PASS(progress, s, nir_opt_remove_phis);
1538 NIR_PASS(progress, s, nir_opt_dce);
1539 NIR_PASS(progress, s, nir_opt_dead_cf);
1540 NIR_PASS(progress, s, nir_opt_cse);
1541 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1542 NIR_PASS(progress, s, nir_opt_algebraic);
1543 NIR_PASS(progress, s, nir_opt_constant_folding);
1544 if (lower_flrp != 0) {
1545 bool lower_flrp_progress = false;
1546
1547 NIR_PASS(lower_flrp_progress, s, nir_lower_flrp,
1548 lower_flrp,
1549 false /* always_precise */);
1550 if (lower_flrp_progress) {
1551 NIR_PASS(progress, s, nir_opt_constant_folding);
1552 progress = true;
1553 }
1554
1555 /* Nothing should rematerialize any flrps, so we only
1556 * need to do this lowering once.
1557 */
1558 lower_flrp = 0;
1559 }
1560
1561 NIR_PASS(progress, s, nir_opt_undef);
1562 NIR_PASS(progress, s, nir_opt_loop_unroll,
1563 nir_var_shader_in |
1564 nir_var_shader_out |
1565 nir_var_function_temp);
1566 } while (progress);
1567 }
1568
1569 static int
1570 driver_location_compare(const void *in_a, const void *in_b)
1571 {
1572 const nir_variable *const *a = in_a;
1573 const nir_variable *const *b = in_b;
1574
1575 return (*a)->data.driver_location - (*b)->data.driver_location;
1576 }
1577
1578 static void
1579 ntq_setup_inputs(struct vc4_compile *c)
1580 {
1581 unsigned num_entries = 0;
1582 nir_foreach_shader_in_variable(var, c->s)
1583 num_entries++;
1584
1585 nir_variable *vars[num_entries];
1586
1587 unsigned i = 0;
1588 nir_foreach_shader_in_variable(var, c->s)
1589 vars[i++] = var;
1590
1591 /* Sort the variables so that we emit the input setup in
1592 * driver_location order. This is required for VPM reads, whose data
1593 * is fetched into the VPM in driver_location (TGSI register index)
1594 * order.
1595 */
1596 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1597
1598 for (unsigned i = 0; i < num_entries; i++) {
1599 nir_variable *var = vars[i];
1600 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1601 unsigned loc = var->data.driver_location;
1602
1603 assert(array_len == 1);
1604 (void)array_len;
1605 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1606 (loc + 1) * 4);
1607
1608 if (c->stage == QSTAGE_FRAG) {
1609 if (var->data.location == VARYING_SLOT_POS) {
1610 emit_fragcoord_input(c, loc);
1611 } else if (util_varying_is_point_coord(var->data.location,
1612 c->fs_key->point_sprite_mask)) {
1613 c->inputs[loc * 4 + 0] = c->point_x;
1614 c->inputs[loc * 4 + 1] = c->point_y;
1615 } else {
1616 emit_fragment_input(c, loc, var->data.location);
1617 }
1618 } else {
1619 emit_vertex_input(c, loc);
1620 }
1621 }
1622 }
1623
1624 static void
1625 ntq_setup_outputs(struct vc4_compile *c)
1626 {
1627 nir_foreach_shader_out_variable(var, c->s) {
1628 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1629 unsigned loc = var->data.driver_location * 4;
1630
1631 assert(array_len == 1);
1632 (void)array_len;
1633
1634 for (int i = 0; i < 4; i++)
1635 add_output(c, loc + i, var->data.location, i);
1636
1637 if (c->stage == QSTAGE_FRAG) {
1638 switch (var->data.location) {
1639 case FRAG_RESULT_COLOR:
1640 case FRAG_RESULT_DATA0:
1641 c->output_color_index = loc;
1642 break;
1643 case FRAG_RESULT_DEPTH:
1644 c->output_position_index = loc;
1645 break;
1646 case FRAG_RESULT_SAMPLE_MASK:
1647 c->output_sample_mask_index = loc;
1648 break;
1649 }
1650 } else {
1651 switch (var->data.location) {
1652 case VARYING_SLOT_POS:
1653 c->output_position_index = loc;
1654 break;
1655 case VARYING_SLOT_PSIZ:
1656 c->output_point_size_index = loc;
1657 break;
1658 }
1659 }
1660 }
1661 }
1662
1663 /**
1664 * Sets up the mapping from nir_register to struct qreg *.
1665 *
1666 * Each nir_register gets a struct qreg per 32-bit component being stored.
1667 */
1668 static void
1669 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1670 {
1671 foreach_list_typed(nir_register, nir_reg, node, list) {
1672 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1673 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1674 array_len *
1675 nir_reg->num_components);
1676
1677 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1678
1679 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1680 qregs[i] = qir_get_temp(c);
1681 }
1682 }
1683
1684 static void
1685 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1686 {
1687 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1688 for (int i = 0; i < instr->def.num_components; i++)
1689 qregs[i] = qir_uniform_ui(c, instr->value[i].u32);
1690
1691 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1692 }
1693
1694 static void
1695 ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
1696 {
1697 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1698
1699 /* QIR needs there to be *some* value, so pick 0 (same as for
1700 * ntq_setup_registers().
1701 */
1702 for (int i = 0; i < instr->def.num_components; i++)
1703 qregs[i] = qir_uniform_ui(c, 0);
1704 }
1705
1706 static void
1707 ntq_emit_color_read(struct vc4_compile *c, nir_intrinsic_instr *instr)
1708 {
1709 assert(nir_src_as_uint(instr->src[0]) == 0);
1710
1711 /* Reads of the per-sample color need to be done in
1712 * order.
1713 */
1714 int sample_index = (nir_intrinsic_base(instr) -
1715 VC4_NIR_TLB_COLOR_READ_INPUT);
1716 for (int i = 0; i <= sample_index; i++) {
1717 if (c->color_reads[i].file == QFILE_NULL) {
1718 c->color_reads[i] =
1719 qir_TLB_COLOR_READ(c);
1720 }
1721 }
1722 ntq_store_dest(c, &instr->dest, 0,
1723 qir_MOV(c, c->color_reads[sample_index]));
1724 }
1725
1726 static void
1727 ntq_emit_load_input(struct vc4_compile *c, nir_intrinsic_instr *instr)
1728 {
1729 assert(instr->num_components == 1);
1730 assert(nir_src_is_const(instr->src[0]) &&
1731 "vc4 doesn't support indirect inputs");
1732
1733 if (c->stage == QSTAGE_FRAG &&
1734 nir_intrinsic_base(instr) >= VC4_NIR_TLB_COLOR_READ_INPUT) {
1735 ntq_emit_color_read(c, instr);
1736 return;
1737 }
1738
1739 uint32_t offset = nir_intrinsic_base(instr) +
1740 nir_src_as_uint(instr->src[0]);
1741 int comp = nir_intrinsic_component(instr);
1742 ntq_store_dest(c, &instr->dest, 0,
1743 qir_MOV(c, c->inputs[offset * 4 + comp]));
1744 }
1745
1746 static void
1747 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1748 {
1749 unsigned offset;
1750
1751 switch (instr->intrinsic) {
1752 case nir_intrinsic_load_uniform:
1753 assert(instr->num_components == 1);
1754 if (nir_src_is_const(instr->src[0])) {
1755 offset = nir_intrinsic_base(instr) +
1756 nir_src_as_uint(instr->src[0]);
1757 assert(offset % 4 == 0);
1758 /* We need dwords */
1759 offset = offset / 4;
1760 ntq_store_dest(c, &instr->dest, 0,
1761 qir_uniform(c, QUNIFORM_UNIFORM,
1762 offset));
1763 } else {
1764 ntq_store_dest(c, &instr->dest, 0,
1765 indirect_uniform_load(c, instr));
1766 }
1767 break;
1768
1769 case nir_intrinsic_load_ubo:
1770 assert(instr->num_components == 1);
1771 ntq_store_dest(c, &instr->dest, 0, vc4_ubo_load(c, instr));
1772 break;
1773
1774 case nir_intrinsic_load_user_clip_plane:
1775 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++) {
1776 ntq_store_dest(c, &instr->dest, i,
1777 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1778 nir_intrinsic_ucp_id(instr) *
1779 4 + i));
1780 }
1781 break;
1782
1783 case nir_intrinsic_load_blend_const_color_r_float:
1784 case nir_intrinsic_load_blend_const_color_g_float:
1785 case nir_intrinsic_load_blend_const_color_b_float:
1786 case nir_intrinsic_load_blend_const_color_a_float:
1787 ntq_store_dest(c, &instr->dest, 0,
1788 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_X +
1789 (instr->intrinsic -
1790 nir_intrinsic_load_blend_const_color_r_float),
1791 0));
1792 break;
1793
1794 case nir_intrinsic_load_blend_const_color_rgba8888_unorm:
1795 ntq_store_dest(c, &instr->dest, 0,
1796 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_RGBA,
1797 0));
1798 break;
1799
1800 case nir_intrinsic_load_blend_const_color_aaaa8888_unorm:
1801 ntq_store_dest(c, &instr->dest, 0,
1802 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_AAAA,
1803 0));
1804 break;
1805
1806 case nir_intrinsic_load_alpha_ref_float:
1807 ntq_store_dest(c, &instr->dest, 0,
1808 qir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1809 break;
1810
1811 case nir_intrinsic_load_sample_mask_in:
1812 ntq_store_dest(c, &instr->dest, 0,
1813 qir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1814 break;
1815
1816 case nir_intrinsic_load_front_face:
1817 /* The register contains 0 (front) or 1 (back), and we need to
1818 * turn it into a NIR bool where true means front.
1819 */
1820 ntq_store_dest(c, &instr->dest, 0,
1821 qir_ADD(c,
1822 qir_uniform_ui(c, -1),
1823 qir_reg(QFILE_FRAG_REV_FLAG, 0)));
1824 break;
1825
1826 case nir_intrinsic_load_input:
1827 ntq_emit_load_input(c, instr);
1828 break;
1829
1830 case nir_intrinsic_store_output:
1831 assert(nir_src_is_const(instr->src[1]) &&
1832 "vc4 doesn't support indirect outputs");
1833 offset = nir_intrinsic_base(instr) +
1834 nir_src_as_uint(instr->src[1]);
1835
1836 /* MSAA color outputs are the only case where we have an
1837 * output that's not lowered to being a store of a single 32
1838 * bit value.
1839 */
1840 if (c->stage == QSTAGE_FRAG && instr->num_components == 4) {
1841 assert(offset == c->output_color_index);
1842 for (int i = 0; i < 4; i++) {
1843 c->sample_colors[i] =
1844 qir_MOV(c, ntq_get_src(c, instr->src[0],
1845 i));
1846 }
1847 } else {
1848 offset = offset * 4 + nir_intrinsic_component(instr);
1849 assert(instr->num_components == 1);
1850 c->outputs[offset] =
1851 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1852 c->num_outputs = MAX2(c->num_outputs, offset + 1);
1853 }
1854 break;
1855
1856 case nir_intrinsic_discard:
1857 if (c->execute.file != QFILE_NULL) {
1858 qir_SF(c, c->execute);
1859 qir_MOV_cond(c, QPU_COND_ZS, c->discard,
1860 qir_uniform_ui(c, ~0));
1861 } else {
1862 qir_MOV_dest(c, c->discard, qir_uniform_ui(c, ~0));
1863 }
1864 break;
1865
1866 case nir_intrinsic_discard_if: {
1867 /* true (~0) if we're discarding */
1868 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1869
1870 if (c->execute.file != QFILE_NULL) {
1871 /* execute == 0 means the channel is active. Invert
1872 * the condition so that we can use zero as "executing
1873 * and discarding."
1874 */
1875 qir_SF(c, qir_AND(c, c->execute, qir_NOT(c, cond)));
1876 qir_MOV_cond(c, QPU_COND_ZS, c->discard, cond);
1877 } else {
1878 qir_OR_dest(c, c->discard, c->discard,
1879 ntq_get_src(c, instr->src[0], 0));
1880 }
1881
1882 break;
1883 }
1884
1885 default:
1886 fprintf(stderr, "Unknown intrinsic: ");
1887 nir_print_instr(&instr->instr, stderr);
1888 fprintf(stderr, "\n");
1889 break;
1890 }
1891 }
1892
1893 /* Clears (activates) the execute flags for any channels whose jump target
1894 * matches this block.
1895 */
1896 static void
1897 ntq_activate_execute_for_block(struct vc4_compile *c)
1898 {
1899 qir_SF(c, qir_SUB(c,
1900 c->execute,
1901 qir_uniform_ui(c, c->cur_block->index)));
1902 qir_MOV_cond(c, QPU_COND_ZS, c->execute, qir_uniform_ui(c, 0));
1903 }
1904
1905 static void
1906 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1907 {
1908 if (!c->vc4->screen->has_control_flow) {
1909 fprintf(stderr,
1910 "IF statement support requires updated kernel.\n");
1911 return;
1912 }
1913
1914 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1915 bool empty_else_block =
1916 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1917 exec_list_is_empty(&nir_else_block->instr_list));
1918
1919 struct qblock *then_block = qir_new_block(c);
1920 struct qblock *after_block = qir_new_block(c);
1921 struct qblock *else_block;
1922 if (empty_else_block)
1923 else_block = after_block;
1924 else
1925 else_block = qir_new_block(c);
1926
1927 bool was_top_level = false;
1928 if (c->execute.file == QFILE_NULL) {
1929 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
1930 was_top_level = true;
1931 }
1932
1933 /* Set ZS for executing (execute == 0) and jumping (if->condition ==
1934 * 0) channels, and then update execute flags for those to point to
1935 * the ELSE block.
1936 */
1937 qir_SF(c, qir_OR(c,
1938 c->execute,
1939 ntq_get_src(c, if_stmt->condition, 0)));
1940 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1941 qir_uniform_ui(c, else_block->index));
1942
1943 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1944 * through.
1945 */
1946 qir_SF(c, c->execute);
1947 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZC);
1948 qir_link_blocks(c->cur_block, else_block);
1949 qir_link_blocks(c->cur_block, then_block);
1950
1951 /* Process the THEN block. */
1952 qir_set_emit_block(c, then_block);
1953 ntq_emit_cf_list(c, &if_stmt->then_list);
1954
1955 if (!empty_else_block) {
1956 /* Handle the end of the THEN block. First, all currently
1957 * active channels update their execute flags to point to
1958 * ENDIF
1959 */
1960 qir_SF(c, c->execute);
1961 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1962 qir_uniform_ui(c, after_block->index));
1963
1964 /* If everything points at ENDIF, then jump there immediately. */
1965 qir_SF(c, qir_SUB(c, c->execute, qir_uniform_ui(c, after_block->index)));
1966 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZS);
1967 qir_link_blocks(c->cur_block, after_block);
1968 qir_link_blocks(c->cur_block, else_block);
1969
1970 qir_set_emit_block(c, else_block);
1971 ntq_activate_execute_for_block(c);
1972 ntq_emit_cf_list(c, &if_stmt->else_list);
1973 }
1974
1975 qir_link_blocks(c->cur_block, after_block);
1976
1977 qir_set_emit_block(c, after_block);
1978 if (was_top_level) {
1979 c->execute = c->undef;
1980 c->last_top_block = c->cur_block;
1981 } else {
1982 ntq_activate_execute_for_block(c);
1983 }
1984 }
1985
1986 static void
1987 ntq_emit_jump(struct vc4_compile *c, nir_jump_instr *jump)
1988 {
1989 struct qblock *jump_block;
1990 switch (jump->type) {
1991 case nir_jump_break:
1992 jump_block = c->loop_break_block;
1993 break;
1994 case nir_jump_continue:
1995 jump_block = c->loop_cont_block;
1996 break;
1997 default:
1998 unreachable("Unsupported jump type\n");
1999 }
2000
2001 qir_SF(c, c->execute);
2002 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
2003 qir_uniform_ui(c, jump_block->index));
2004
2005 /* Jump to the destination block if everyone has taken the jump. */
2006 qir_SF(c, qir_SUB(c, c->execute, qir_uniform_ui(c, jump_block->index)));
2007 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZS);
2008 struct qblock *new_block = qir_new_block(c);
2009 qir_link_blocks(c->cur_block, jump_block);
2010 qir_link_blocks(c->cur_block, new_block);
2011 qir_set_emit_block(c, new_block);
2012 }
2013
2014 static void
2015 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
2016 {
2017 switch (instr->type) {
2018 case nir_instr_type_alu:
2019 ntq_emit_alu(c, nir_instr_as_alu(instr));
2020 break;
2021
2022 case nir_instr_type_intrinsic:
2023 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2024 break;
2025
2026 case nir_instr_type_load_const:
2027 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2028 break;
2029
2030 case nir_instr_type_ssa_undef:
2031 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2032 break;
2033
2034 case nir_instr_type_tex:
2035 ntq_emit_tex(c, nir_instr_as_tex(instr));
2036 break;
2037
2038 case nir_instr_type_jump:
2039 ntq_emit_jump(c, nir_instr_as_jump(instr));
2040 break;
2041
2042 default:
2043 fprintf(stderr, "Unknown NIR instr type: ");
2044 nir_print_instr(instr, stderr);
2045 fprintf(stderr, "\n");
2046 abort();
2047 }
2048 }
2049
2050 static void
2051 ntq_emit_block(struct vc4_compile *c, nir_block *block)
2052 {
2053 nir_foreach_instr(instr, block) {
2054 ntq_emit_instr(c, instr);
2055 }
2056 }
2057
2058 static void ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
2059
2060 static void
2061 ntq_emit_loop(struct vc4_compile *c, nir_loop *loop)
2062 {
2063 if (!c->vc4->screen->has_control_flow) {
2064 fprintf(stderr,
2065 "loop support requires updated kernel.\n");
2066 ntq_emit_cf_list(c, &loop->body);
2067 return;
2068 }
2069
2070 bool was_top_level = false;
2071 if (c->execute.file == QFILE_NULL) {
2072 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
2073 was_top_level = true;
2074 }
2075
2076 struct qblock *save_loop_cont_block = c->loop_cont_block;
2077 struct qblock *save_loop_break_block = c->loop_break_block;
2078
2079 c->loop_cont_block = qir_new_block(c);
2080 c->loop_break_block = qir_new_block(c);
2081
2082 qir_link_blocks(c->cur_block, c->loop_cont_block);
2083 qir_set_emit_block(c, c->loop_cont_block);
2084 ntq_activate_execute_for_block(c);
2085
2086 ntq_emit_cf_list(c, &loop->body);
2087
2088 /* If anything had explicitly continued, or is here at the end of the
2089 * loop, then we need to loop again. SF updates are masked by the
2090 * instruction's condition, so we can do the OR of the two conditions
2091 * within SF.
2092 */
2093 qir_SF(c, c->execute);
2094 struct qinst *cont_check =
2095 qir_SUB_dest(c,
2096 c->undef,
2097 c->execute,
2098 qir_uniform_ui(c, c->loop_cont_block->index));
2099 cont_check->cond = QPU_COND_ZC;
2100 cont_check->sf = true;
2101
2102 qir_BRANCH(c, QPU_COND_BRANCH_ANY_ZS);
2103 qir_link_blocks(c->cur_block, c->loop_cont_block);
2104 qir_link_blocks(c->cur_block, c->loop_break_block);
2105
2106 qir_set_emit_block(c, c->loop_break_block);
2107 if (was_top_level) {
2108 c->execute = c->undef;
2109 c->last_top_block = c->cur_block;
2110 } else {
2111 ntq_activate_execute_for_block(c);
2112 }
2113
2114 c->loop_break_block = save_loop_break_block;
2115 c->loop_cont_block = save_loop_cont_block;
2116 }
2117
2118 static void
2119 ntq_emit_function(struct vc4_compile *c, nir_function_impl *func)
2120 {
2121 fprintf(stderr, "FUNCTIONS not handled.\n");
2122 abort();
2123 }
2124
2125 static void
2126 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
2127 {
2128 foreach_list_typed(nir_cf_node, node, node, list) {
2129 switch (node->type) {
2130 case nir_cf_node_block:
2131 ntq_emit_block(c, nir_cf_node_as_block(node));
2132 break;
2133
2134 case nir_cf_node_if:
2135 ntq_emit_if(c, nir_cf_node_as_if(node));
2136 break;
2137
2138 case nir_cf_node_loop:
2139 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2140 break;
2141
2142 case nir_cf_node_function:
2143 ntq_emit_function(c, nir_cf_node_as_function(node));
2144 break;
2145
2146 default:
2147 fprintf(stderr, "Unknown NIR node type\n");
2148 abort();
2149 }
2150 }
2151 }
2152
2153 static void
2154 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
2155 {
2156 ntq_setup_registers(c, &impl->registers);
2157 ntq_emit_cf_list(c, &impl->body);
2158 }
2159
2160 static void
2161 nir_to_qir(struct vc4_compile *c)
2162 {
2163 if (c->stage == QSTAGE_FRAG && c->s->info.fs.uses_discard)
2164 c->discard = qir_MOV(c, qir_uniform_ui(c, 0));
2165
2166 ntq_setup_inputs(c);
2167 ntq_setup_outputs(c);
2168
2169 /* Find the main function and emit the body. */
2170 nir_foreach_function(function, c->s) {
2171 assert(strcmp(function->name, "main") == 0);
2172 assert(function->impl);
2173 ntq_emit_impl(c, function->impl);
2174 }
2175 }
2176
2177 static const nir_shader_compiler_options nir_options = {
2178 .lower_all_io_to_temps = true,
2179 .lower_extract_byte = true,
2180 .lower_extract_word = true,
2181 .lower_fdiv = true,
2182 .lower_ffma = true,
2183 .lower_flrp32 = true,
2184 .lower_fmod = true,
2185 .lower_fpow = true,
2186 .lower_fsat = true,
2187 .lower_fsqrt = true,
2188 .lower_ldexp = true,
2189 .lower_negate = true,
2190 .lower_rotate = true,
2191 .lower_to_scalar = true,
2192 .max_unroll_iterations = 32,
2193 };
2194
2195 const void *
2196 vc4_screen_get_compiler_options(struct pipe_screen *pscreen,
2197 enum pipe_shader_ir ir,
2198 enum pipe_shader_type shader)
2199 {
2200 return &nir_options;
2201 }
2202
2203 static int
2204 count_nir_instrs(nir_shader *nir)
2205 {
2206 int count = 0;
2207 nir_foreach_function(function, nir) {
2208 if (!function->impl)
2209 continue;
2210 nir_foreach_block(block, function->impl) {
2211 nir_foreach_instr(instr, block)
2212 count++;
2213 }
2214 }
2215 return count;
2216 }
2217
2218 static struct vc4_compile *
2219 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
2220 struct vc4_key *key, bool fs_threaded)
2221 {
2222 struct vc4_compile *c = qir_compile_init();
2223
2224 c->vc4 = vc4;
2225 c->stage = stage;
2226 c->shader_state = &key->shader_state->base;
2227 c->program_id = key->shader_state->program_id;
2228 c->variant_id =
2229 p_atomic_inc_return(&key->shader_state->compiled_variant_count);
2230 c->fs_threaded = fs_threaded;
2231
2232 c->key = key;
2233 switch (stage) {
2234 case QSTAGE_FRAG:
2235 c->fs_key = (struct vc4_fs_key *)key;
2236 if (c->fs_key->is_points) {
2237 c->point_x = emit_fragment_varying(c, ~0, 0);
2238 c->point_y = emit_fragment_varying(c, ~0, 0);
2239 } else if (c->fs_key->is_lines) {
2240 c->line_x = emit_fragment_varying(c, ~0, 0);
2241 }
2242 break;
2243 case QSTAGE_VERT:
2244 c->vs_key = (struct vc4_vs_key *)key;
2245 break;
2246 case QSTAGE_COORD:
2247 c->vs_key = (struct vc4_vs_key *)key;
2248 break;
2249 }
2250
2251 c->s = nir_shader_clone(c, key->shader_state->base.ir.nir);
2252
2253 if (stage == QSTAGE_FRAG) {
2254 if (c->fs_key->alpha_test_func != COMPARE_FUNC_ALWAYS) {
2255 NIR_PASS_V(c->s, nir_lower_alpha_test,
2256 c->fs_key->alpha_test_func,
2257 c->fs_key->sample_alpha_to_one &&
2258 c->fs_key->msaa,
2259 NULL);
2260 }
2261 NIR_PASS_V(c->s, vc4_nir_lower_blend, c);
2262 }
2263
2264 struct nir_lower_tex_options tex_options = {
2265 /* We would need to implement txs, but we don't want the
2266 * int/float conversions
2267 */
2268 .lower_rect = false,
2269
2270 .lower_txp = ~0,
2271
2272 /* Apply swizzles to all samplers. */
2273 .swizzle_result = ~0,
2274 };
2275
2276 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
2277 * The format swizzling applies before sRGB decode, and
2278 * ARB_texture_swizzle is the last thing before returning the sample.
2279 */
2280 for (int i = 0; i < ARRAY_SIZE(key->tex); i++) {
2281 enum pipe_format format = c->key->tex[i].format;
2282
2283 if (!format)
2284 continue;
2285
2286 const uint8_t *format_swizzle = vc4_get_format_swizzle(format);
2287
2288 for (int j = 0; j < 4; j++) {
2289 uint8_t arb_swiz = c->key->tex[i].swizzle[j];
2290
2291 if (arb_swiz <= 3) {
2292 tex_options.swizzles[i][j] =
2293 format_swizzle[arb_swiz];
2294 } else {
2295 tex_options.swizzles[i][j] = arb_swiz;
2296 }
2297 }
2298
2299 if (util_format_is_srgb(format))
2300 tex_options.lower_srgb |= (1 << i);
2301 }
2302
2303 NIR_PASS_V(c->s, nir_lower_tex, &tex_options);
2304
2305 if (c->fs_key && c->fs_key->light_twoside)
2306 NIR_PASS_V(c->s, nir_lower_two_sided_color, true);
2307
2308 if (c->vs_key && c->vs_key->clamp_color)
2309 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
2310
2311 if (c->key->ucp_enables) {
2312 if (stage == QSTAGE_FRAG) {
2313 NIR_PASS_V(c->s, nir_lower_clip_fs,
2314 c->key->ucp_enables, false);
2315 } else {
2316 NIR_PASS_V(c->s, nir_lower_clip_vs,
2317 c->key->ucp_enables, false, false, NULL);
2318 NIR_PASS_V(c->s, nir_lower_io_to_scalar,
2319 nir_var_shader_out);
2320 }
2321 }
2322
2323 /* FS input scalarizing must happen after nir_lower_two_sided_color,
2324 * which only handles a vec4 at a time. Similarly, VS output
2325 * scalarizing must happen after nir_lower_clip_vs.
2326 */
2327 if (c->stage == QSTAGE_FRAG)
2328 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_in);
2329 else
2330 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_out);
2331
2332 NIR_PASS_V(c->s, vc4_nir_lower_io, c);
2333 NIR_PASS_V(c->s, vc4_nir_lower_txf_ms, c);
2334 NIR_PASS_V(c->s, nir_lower_idiv, nir_lower_idiv_fast);
2335
2336 vc4_optimize_nir(c->s);
2337
2338 /* Do late algebraic optimization to turn add(a, neg(b)) back into
2339 * subs, then the mandatory cleanup after algebraic. Note that it may
2340 * produce fnegs, and if so then we need to keep running to squash
2341 * fneg(fneg(a)).
2342 */
2343 bool more_late_algebraic = true;
2344 while (more_late_algebraic) {
2345 more_late_algebraic = false;
2346 NIR_PASS(more_late_algebraic, c->s, nir_opt_algebraic_late);
2347 NIR_PASS_V(c->s, nir_opt_constant_folding);
2348 NIR_PASS_V(c->s, nir_copy_prop);
2349 NIR_PASS_V(c->s, nir_opt_dce);
2350 NIR_PASS_V(c->s, nir_opt_cse);
2351 }
2352
2353 NIR_PASS_V(c->s, nir_lower_bool_to_int32);
2354
2355 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
2356
2357 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2358 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2359 qir_get_stage_name(c->stage),
2360 c->program_id, c->variant_id,
2361 count_nir_instrs(c->s));
2362 }
2363
2364 if (vc4_debug & VC4_DEBUG_NIR) {
2365 fprintf(stderr, "%s prog %d/%d NIR:\n",
2366 qir_get_stage_name(c->stage),
2367 c->program_id, c->variant_id);
2368 nir_print_shader(c->s, stderr);
2369 }
2370
2371 nir_to_qir(c);
2372
2373 switch (stage) {
2374 case QSTAGE_FRAG:
2375 /* FS threading requires that the thread execute
2376 * QPU_SIG_LAST_THREAD_SWITCH exactly once before terminating
2377 * (with no other THRSW afterwards, obviously). If we didn't
2378 * fetch a texture at a top level block, this wouldn't be
2379 * true.
2380 */
2381 if (c->fs_threaded && !c->last_thrsw_at_top_level) {
2382 c->failed = true;
2383 return c;
2384 }
2385
2386 emit_frag_end(c);
2387 break;
2388 case QSTAGE_VERT:
2389 emit_vert_end(c,
2390 c->vs_key->fs_inputs->input_slots,
2391 c->vs_key->fs_inputs->num_inputs);
2392 break;
2393 case QSTAGE_COORD:
2394 emit_coord_end(c);
2395 break;
2396 }
2397
2398 if (vc4_debug & VC4_DEBUG_QIR) {
2399 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
2400 qir_get_stage_name(c->stage),
2401 c->program_id, c->variant_id);
2402 qir_dump(c);
2403 fprintf(stderr, "\n");
2404 }
2405
2406 qir_optimize(c);
2407 qir_lower_uniforms(c);
2408
2409 qir_schedule_instructions(c);
2410 qir_emit_uniform_stream_resets(c);
2411
2412 if (vc4_debug & VC4_DEBUG_QIR) {
2413 fprintf(stderr, "%s prog %d/%d QIR:\n",
2414 qir_get_stage_name(c->stage),
2415 c->program_id, c->variant_id);
2416 qir_dump(c);
2417 fprintf(stderr, "\n");
2418 }
2419
2420 qir_reorder_uniforms(c);
2421 vc4_generate_code(vc4, c);
2422
2423 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2424 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2425 qir_get_stage_name(c->stage),
2426 c->program_id, c->variant_id,
2427 c->qpu_inst_count);
2428 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2429 qir_get_stage_name(c->stage),
2430 c->program_id, c->variant_id,
2431 c->num_uniforms);
2432 }
2433
2434 ralloc_free(c->s);
2435
2436 return c;
2437 }
2438
2439 static void *
2440 vc4_shader_state_create(struct pipe_context *pctx,
2441 const struct pipe_shader_state *cso)
2442 {
2443 struct vc4_context *vc4 = vc4_context(pctx);
2444 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2445 if (!so)
2446 return NULL;
2447
2448 so->program_id = vc4->next_uncompiled_program_id++;
2449
2450 nir_shader *s;
2451
2452 if (cso->type == PIPE_SHADER_IR_NIR) {
2453 /* The backend takes ownership of the NIR shader on state
2454 * creation.
2455 */
2456 s = cso->ir.nir;
2457 } else {
2458 assert(cso->type == PIPE_SHADER_IR_TGSI);
2459
2460 if (vc4_debug & VC4_DEBUG_TGSI) {
2461 fprintf(stderr, "prog %d TGSI:\n",
2462 so->program_id);
2463 tgsi_dump(cso->tokens, 0);
2464 fprintf(stderr, "\n");
2465 }
2466 s = tgsi_to_nir(cso->tokens, pctx->screen, false);
2467 }
2468
2469 if (s->info.stage == MESA_SHADER_VERTEX)
2470 NIR_PASS_V(s, nir_lower_point_size, 1.0f, 0.0f);
2471
2472 NIR_PASS_V(s, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
2473 type_size, (nir_lower_io_options)0);
2474
2475 NIR_PASS_V(s, nir_lower_regs_to_ssa);
2476 NIR_PASS_V(s, nir_normalize_cubemap_coords);
2477
2478 NIR_PASS_V(s, nir_lower_load_const_to_scalar);
2479
2480 vc4_optimize_nir(s);
2481
2482 NIR_PASS_V(s, nir_remove_dead_variables, nir_var_function_temp, NULL);
2483
2484 /* Garbage collect dead instructions */
2485 nir_sweep(s);
2486
2487 so->base.type = PIPE_SHADER_IR_NIR;
2488 so->base.ir.nir = s;
2489
2490 if (vc4_debug & VC4_DEBUG_NIR) {
2491 fprintf(stderr, "%s prog %d NIR:\n",
2492 gl_shader_stage_name(s->info.stage),
2493 so->program_id);
2494 nir_print_shader(s, stderr);
2495 fprintf(stderr, "\n");
2496 }
2497
2498 return so;
2499 }
2500
2501 static void
2502 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2503 struct vc4_compile *c)
2504 {
2505 int count = c->num_uniforms;
2506 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2507
2508 uinfo->count = count;
2509 uinfo->data = ralloc_array(shader, uint32_t, count);
2510 memcpy(uinfo->data, c->uniform_data,
2511 count * sizeof(*uinfo->data));
2512 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2513 memcpy(uinfo->contents, c->uniform_contents,
2514 count * sizeof(*uinfo->contents));
2515 uinfo->num_texture_samples = c->num_texture_samples;
2516
2517 vc4_set_shader_uniform_dirty_flags(shader);
2518 }
2519
2520 static void
2521 vc4_setup_compiled_fs_inputs(struct vc4_context *vc4, struct vc4_compile *c,
2522 struct vc4_compiled_shader *shader)
2523 {
2524 struct vc4_fs_inputs inputs;
2525
2526 memset(&inputs, 0, sizeof(inputs));
2527 inputs.input_slots = ralloc_array(shader,
2528 struct vc4_varying_slot,
2529 c->num_input_slots);
2530
2531 bool input_live[c->num_input_slots];
2532
2533 memset(input_live, 0, sizeof(input_live));
2534 qir_for_each_inst_inorder(inst, c) {
2535 for (int i = 0; i < qir_get_nsrc(inst); i++) {
2536 if (inst->src[i].file == QFILE_VARY)
2537 input_live[inst->src[i].index] = true;
2538 }
2539 }
2540
2541 for (int i = 0; i < c->num_input_slots; i++) {
2542 struct vc4_varying_slot *slot = &c->input_slots[i];
2543
2544 if (!input_live[i])
2545 continue;
2546
2547 /* Skip non-VS-output inputs. */
2548 if (slot->slot == (uint8_t)~0)
2549 continue;
2550
2551 if (slot->slot == VARYING_SLOT_COL0 ||
2552 slot->slot == VARYING_SLOT_COL1 ||
2553 slot->slot == VARYING_SLOT_BFC0 ||
2554 slot->slot == VARYING_SLOT_BFC1) {
2555 shader->color_inputs |= (1 << inputs.num_inputs);
2556 }
2557
2558 inputs.input_slots[inputs.num_inputs] = *slot;
2559 inputs.num_inputs++;
2560 }
2561 shader->num_inputs = inputs.num_inputs;
2562
2563 /* Add our set of inputs to the set of all inputs seen. This way, we
2564 * can have a single pointer that identifies an FS inputs set,
2565 * allowing VS to avoid recompiling when the FS is recompiled (or a
2566 * new one is bound using separate shader objects) but the inputs
2567 * don't change.
2568 */
2569 struct set_entry *entry = _mesa_set_search(vc4->fs_inputs_set, &inputs);
2570 if (entry) {
2571 shader->fs_inputs = entry->key;
2572 ralloc_free(inputs.input_slots);
2573 } else {
2574 struct vc4_fs_inputs *alloc_inputs;
2575
2576 alloc_inputs = rzalloc(vc4->fs_inputs_set, struct vc4_fs_inputs);
2577 memcpy(alloc_inputs, &inputs, sizeof(inputs));
2578 ralloc_steal(alloc_inputs, inputs.input_slots);
2579 _mesa_set_add(vc4->fs_inputs_set, alloc_inputs);
2580
2581 shader->fs_inputs = alloc_inputs;
2582 }
2583 }
2584
2585 static struct vc4_compiled_shader *
2586 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2587 struct vc4_key *key)
2588 {
2589 struct hash_table *ht;
2590 uint32_t key_size;
2591 bool try_threading;
2592
2593 if (stage == QSTAGE_FRAG) {
2594 ht = vc4->fs_cache;
2595 key_size = sizeof(struct vc4_fs_key);
2596 try_threading = vc4->screen->has_threaded_fs;
2597 } else {
2598 ht = vc4->vs_cache;
2599 key_size = sizeof(struct vc4_vs_key);
2600 try_threading = false;
2601 }
2602
2603 struct vc4_compiled_shader *shader;
2604 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2605 if (entry)
2606 return entry->data;
2607
2608 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key, try_threading);
2609 /* If the FS failed to compile threaded, fall back to single threaded. */
2610 if (try_threading && c->failed) {
2611 qir_compile_destroy(c);
2612 c = vc4_shader_ntq(vc4, stage, key, false);
2613 }
2614
2615 shader = rzalloc(NULL, struct vc4_compiled_shader);
2616
2617 shader->program_id = vc4->next_compiled_program_id++;
2618 if (stage == QSTAGE_FRAG) {
2619 vc4_setup_compiled_fs_inputs(vc4, c, shader);
2620
2621 /* Note: the temporary clone in c->s has been freed. */
2622 nir_shader *orig_shader = key->shader_state->base.ir.nir;
2623 if (orig_shader->info.outputs_written & (1 << FRAG_RESULT_DEPTH))
2624 shader->disable_early_z = true;
2625 } else {
2626 shader->num_inputs = c->num_inputs;
2627
2628 shader->vattr_offsets[0] = 0;
2629 for (int i = 0; i < 8; i++) {
2630 shader->vattr_offsets[i + 1] =
2631 shader->vattr_offsets[i] + c->vattr_sizes[i];
2632
2633 if (c->vattr_sizes[i])
2634 shader->vattrs_live |= (1 << i);
2635 }
2636 }
2637
2638 shader->failed = c->failed;
2639 if (c->failed) {
2640 shader->failed = true;
2641 } else {
2642 copy_uniform_state_to_shader(shader, c);
2643 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
2644 c->qpu_inst_count *
2645 sizeof(uint64_t));
2646 }
2647
2648 shader->fs_threaded = c->fs_threaded;
2649
2650 if ((vc4_debug & VC4_DEBUG_SHADERDB) && stage == QSTAGE_FRAG) {
2651 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d FS threads\n",
2652 qir_get_stage_name(c->stage),
2653 c->program_id, c->variant_id,
2654 1 + shader->fs_threaded);
2655 }
2656
2657 qir_compile_destroy(c);
2658
2659 struct vc4_key *dup_key;
2660 dup_key = rzalloc_size(shader, key_size); /* TODO: don't use rzalloc */
2661 memcpy(dup_key, key, key_size);
2662 _mesa_hash_table_insert(ht, dup_key, shader);
2663
2664 return shader;
2665 }
2666
2667 static void
2668 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2669 struct vc4_texture_stateobj *texstate)
2670 {
2671 for (int i = 0; i < texstate->num_textures; i++) {
2672 struct pipe_sampler_view *sampler = texstate->textures[i];
2673 struct vc4_sampler_view *vc4_sampler = vc4_sampler_view(sampler);
2674 struct pipe_sampler_state *sampler_state =
2675 texstate->samplers[i];
2676
2677 if (!sampler)
2678 continue;
2679
2680 key->tex[i].format = sampler->format;
2681 key->tex[i].swizzle[0] = sampler->swizzle_r;
2682 key->tex[i].swizzle[1] = sampler->swizzle_g;
2683 key->tex[i].swizzle[2] = sampler->swizzle_b;
2684 key->tex[i].swizzle[3] = sampler->swizzle_a;
2685
2686 if (sampler->texture->nr_samples > 1) {
2687 key->tex[i].msaa_width = sampler->texture->width0;
2688 key->tex[i].msaa_height = sampler->texture->height0;
2689 } else if (sampler){
2690 key->tex[i].compare_mode = sampler_state->compare_mode;
2691 key->tex[i].compare_func = sampler_state->compare_func;
2692 key->tex[i].wrap_s = sampler_state->wrap_s;
2693 key->tex[i].wrap_t = sampler_state->wrap_t;
2694 key->tex[i].force_first_level =
2695 vc4_sampler->force_first_level;
2696 }
2697 }
2698
2699 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2700 }
2701
2702 static void
2703 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2704 {
2705 struct vc4_job *job = vc4->job;
2706 struct vc4_fs_key local_key;
2707 struct vc4_fs_key *key = &local_key;
2708
2709 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2710 VC4_DIRTY_BLEND |
2711 VC4_DIRTY_FRAMEBUFFER |
2712 VC4_DIRTY_ZSA |
2713 VC4_DIRTY_RASTERIZER |
2714 VC4_DIRTY_SAMPLE_MASK |
2715 VC4_DIRTY_FRAGTEX |
2716 VC4_DIRTY_UNCOMPILED_FS |
2717 VC4_DIRTY_UBO_1_SIZE))) {
2718 return;
2719 }
2720
2721 memset(key, 0, sizeof(*key));
2722 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2723 key->base.shader_state = vc4->prog.bind_fs;
2724 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2725 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2726 prim_mode <= PIPE_PRIM_LINE_STRIP);
2727 key->blend = vc4->blend->rt[0];
2728 if (vc4->blend->logicop_enable) {
2729 key->logicop_func = vc4->blend->logicop_func;
2730 } else {
2731 key->logicop_func = PIPE_LOGICOP_COPY;
2732 }
2733 if (job->msaa) {
2734 key->msaa = vc4->rasterizer->base.multisample;
2735 key->sample_coverage = (vc4->sample_mask != (1 << VC4_MAX_SAMPLES) - 1);
2736 key->sample_alpha_to_coverage = vc4->blend->alpha_to_coverage;
2737 key->sample_alpha_to_one = vc4->blend->alpha_to_one;
2738 }
2739
2740 if (vc4->framebuffer.cbufs[0])
2741 key->color_format = vc4->framebuffer.cbufs[0]->format;
2742
2743 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2744 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2745 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2746 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2747 key->stencil_enabled);
2748 if (vc4->zsa->base.alpha.enabled)
2749 key->alpha_test_func = vc4->zsa->base.alpha.func;
2750 else
2751 key->alpha_test_func = COMPARE_FUNC_ALWAYS;
2752
2753 if (key->is_points) {
2754 key->point_sprite_mask =
2755 vc4->rasterizer->base.sprite_coord_enable;
2756 key->point_coord_upper_left =
2757 (vc4->rasterizer->base.sprite_coord_mode ==
2758 PIPE_SPRITE_COORD_UPPER_LEFT);
2759 }
2760
2761 key->ubo_1_size = vc4->constbuf[PIPE_SHADER_FRAGMENT].cb[1].buffer_size;
2762 key->light_twoside = vc4->rasterizer->base.light_twoside;
2763
2764 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2765 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2766 if (vc4->prog.fs == old_fs)
2767 return;
2768
2769 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2770
2771 if (vc4->rasterizer->base.flatshade &&
2772 (!old_fs || vc4->prog.fs->color_inputs != old_fs->color_inputs)) {
2773 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2774 }
2775
2776 if (!old_fs || vc4->prog.fs->fs_inputs != old_fs->fs_inputs)
2777 vc4->dirty |= VC4_DIRTY_FS_INPUTS;
2778 }
2779
2780 static void
2781 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2782 {
2783 struct vc4_vs_key local_key;
2784 struct vc4_vs_key *key = &local_key;
2785
2786 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2787 VC4_DIRTY_RASTERIZER |
2788 VC4_DIRTY_VERTTEX |
2789 VC4_DIRTY_VTXSTATE |
2790 VC4_DIRTY_UNCOMPILED_VS |
2791 VC4_DIRTY_FS_INPUTS))) {
2792 return;
2793 }
2794
2795 memset(key, 0, sizeof(*key));
2796 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2797 key->base.shader_state = vc4->prog.bind_vs;
2798 key->fs_inputs = vc4->prog.fs->fs_inputs;
2799 key->clamp_color = vc4->rasterizer->base.clamp_vertex_color;
2800
2801 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2802 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2803
2804 key->per_vertex_point_size =
2805 (prim_mode == PIPE_PRIM_POINTS &&
2806 vc4->rasterizer->base.point_size_per_vertex);
2807
2808 struct vc4_compiled_shader *vs =
2809 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2810 if (vs != vc4->prog.vs) {
2811 vc4->prog.vs = vs;
2812 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
2813 }
2814
2815 key->is_coord = true;
2816 /* Coord shaders don't care what the FS inputs are. */
2817 key->fs_inputs = NULL;
2818 struct vc4_compiled_shader *cs =
2819 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2820 if (cs != vc4->prog.cs) {
2821 vc4->prog.cs = cs;
2822 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
2823 }
2824 }
2825
2826 bool
2827 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2828 {
2829 vc4_update_compiled_fs(vc4, prim_mode);
2830 vc4_update_compiled_vs(vc4, prim_mode);
2831
2832 return !(vc4->prog.cs->failed ||
2833 vc4->prog.vs->failed ||
2834 vc4->prog.fs->failed);
2835 }
2836
2837 static uint32_t
2838 fs_cache_hash(const void *key)
2839 {
2840 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2841 }
2842
2843 static uint32_t
2844 vs_cache_hash(const void *key)
2845 {
2846 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2847 }
2848
2849 static bool
2850 fs_cache_compare(const void *key1, const void *key2)
2851 {
2852 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2853 }
2854
2855 static bool
2856 vs_cache_compare(const void *key1, const void *key2)
2857 {
2858 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2859 }
2860
2861 static uint32_t
2862 fs_inputs_hash(const void *key)
2863 {
2864 const struct vc4_fs_inputs *inputs = key;
2865
2866 return _mesa_hash_data(inputs->input_slots,
2867 sizeof(*inputs->input_slots) *
2868 inputs->num_inputs);
2869 }
2870
2871 static bool
2872 fs_inputs_compare(const void *key1, const void *key2)
2873 {
2874 const struct vc4_fs_inputs *inputs1 = key1;
2875 const struct vc4_fs_inputs *inputs2 = key2;
2876
2877 return (inputs1->num_inputs == inputs2->num_inputs &&
2878 memcmp(inputs1->input_slots,
2879 inputs2->input_slots,
2880 sizeof(*inputs1->input_slots) *
2881 inputs1->num_inputs) == 0);
2882 }
2883
2884 static void
2885 delete_from_cache_if_matches(struct hash_table *ht,
2886 struct vc4_compiled_shader **last_compile,
2887 struct hash_entry *entry,
2888 struct vc4_uncompiled_shader *so)
2889 {
2890 const struct vc4_key *key = entry->key;
2891
2892 if (key->shader_state == so) {
2893 struct vc4_compiled_shader *shader = entry->data;
2894 _mesa_hash_table_remove(ht, entry);
2895 vc4_bo_unreference(&shader->bo);
2896
2897 if (shader == *last_compile)
2898 *last_compile = NULL;
2899
2900 ralloc_free(shader);
2901 }
2902 }
2903
2904 static void
2905 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2906 {
2907 struct vc4_context *vc4 = vc4_context(pctx);
2908 struct vc4_uncompiled_shader *so = hwcso;
2909
2910 hash_table_foreach(vc4->fs_cache, entry) {
2911 delete_from_cache_if_matches(vc4->fs_cache, &vc4->prog.fs,
2912 entry, so);
2913 }
2914 hash_table_foreach(vc4->vs_cache, entry) {
2915 delete_from_cache_if_matches(vc4->vs_cache, &vc4->prog.vs,
2916 entry, so);
2917 }
2918
2919 ralloc_free(so->base.ir.nir);
2920 free(so);
2921 }
2922
2923 static void
2924 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2925 {
2926 struct vc4_context *vc4 = vc4_context(pctx);
2927 vc4->prog.bind_fs = hwcso;
2928 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2929 }
2930
2931 static void
2932 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2933 {
2934 struct vc4_context *vc4 = vc4_context(pctx);
2935 vc4->prog.bind_vs = hwcso;
2936 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2937 }
2938
2939 void
2940 vc4_program_init(struct pipe_context *pctx)
2941 {
2942 struct vc4_context *vc4 = vc4_context(pctx);
2943
2944 pctx->create_vs_state = vc4_shader_state_create;
2945 pctx->delete_vs_state = vc4_shader_state_delete;
2946
2947 pctx->create_fs_state = vc4_shader_state_create;
2948 pctx->delete_fs_state = vc4_shader_state_delete;
2949
2950 pctx->bind_fs_state = vc4_fp_state_bind;
2951 pctx->bind_vs_state = vc4_vp_state_bind;
2952
2953 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2954 fs_cache_compare);
2955 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2956 vs_cache_compare);
2957 vc4->fs_inputs_set = _mesa_set_create(pctx, fs_inputs_hash,
2958 fs_inputs_compare);
2959 }
2960
2961 void
2962 vc4_program_fini(struct pipe_context *pctx)
2963 {
2964 struct vc4_context *vc4 = vc4_context(pctx);
2965
2966 hash_table_foreach(vc4->fs_cache, entry) {
2967 struct vc4_compiled_shader *shader = entry->data;
2968 vc4_bo_unreference(&shader->bo);
2969 ralloc_free(shader);
2970 _mesa_hash_table_remove(vc4->fs_cache, entry);
2971 }
2972
2973 hash_table_foreach(vc4->vs_cache, entry) {
2974 struct vc4_compiled_shader *shader = entry->data;
2975 vc4_bo_unreference(&shader->bo);
2976 ralloc_free(shader);
2977 _mesa_hash_table_remove(vc4->vs_cache, entry);
2978 }
2979 }