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vc4: Add shader-db dumping of NIR instruction count.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash.h"
29 #include "util/u_math.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/format_srgb.h"
33 #include "util/ralloc.h"
34 #include "util/hash_table.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "tgsi/tgsi_info.h"
37 #include "tgsi/tgsi_lowering.h"
38 #include "tgsi/tgsi_parse.h"
39 #include "nir/tgsi_to_nir.h"
40
41 #include "vc4_context.h"
42 #include "vc4_qpu.h"
43 #include "vc4_qir.h"
44 #ifdef USE_VC4_SIMULATOR
45 #include "simpenrose/simpenrose.h"
46 #endif
47
48 struct vc4_key {
49 struct vc4_uncompiled_shader *shader_state;
50 struct {
51 enum pipe_format format;
52 unsigned compare_mode:1;
53 unsigned compare_func:3;
54 unsigned wrap_s:3;
55 unsigned wrap_t:3;
56 uint8_t swizzle[4];
57 } tex[VC4_MAX_TEXTURE_SAMPLERS];
58 uint8_t ucp_enables;
59 };
60
61 struct vc4_fs_key {
62 struct vc4_key base;
63 enum pipe_format color_format;
64 bool depth_enabled;
65 bool stencil_enabled;
66 bool stencil_twoside;
67 bool stencil_full_writemasks;
68 bool is_points;
69 bool is_lines;
70 bool alpha_test;
71 bool point_coord_upper_left;
72 bool light_twoside;
73 uint8_t alpha_test_func;
74 uint8_t logicop_func;
75 uint32_t point_sprite_mask;
76
77 struct pipe_rt_blend_state blend;
78 };
79
80 struct vc4_vs_key {
81 struct vc4_key base;
82
83 /**
84 * This is a proxy for the array of FS input semantics, which is
85 * larger than we would want to put in the key.
86 */
87 uint64_t compiled_fs_id;
88
89 enum pipe_format attr_formats[8];
90 bool is_coord;
91 bool per_vertex_point_size;
92 };
93
94 static void
95 resize_qreg_array(struct vc4_compile *c,
96 struct qreg **regs,
97 uint32_t *size,
98 uint32_t decl_size)
99 {
100 if (*size >= decl_size)
101 return;
102
103 uint32_t old_size = *size;
104 *size = MAX2(*size * 2, decl_size);
105 *regs = reralloc(c, *regs, struct qreg, *size);
106 if (!*regs) {
107 fprintf(stderr, "Malloc failure\n");
108 abort();
109 }
110
111 for (uint32_t i = old_size; i < *size; i++)
112 (*regs)[i] = c->undef;
113 }
114
115 static struct qreg
116 indirect_uniform_load(struct vc4_compile *c,
117 struct qreg indirect_offset,
118 unsigned offset)
119 {
120 struct vc4_compiler_ubo_range *range = NULL;
121 unsigned i;
122 for (i = 0; i < c->num_uniform_ranges; i++) {
123 range = &c->ubo_ranges[i];
124 if (offset >= range->src_offset &&
125 offset < range->src_offset + range->size) {
126 break;
127 }
128 }
129 /* The driver-location-based offset always has to be within a declared
130 * uniform range.
131 */
132 assert(range);
133 if (!range->used) {
134 range->used = true;
135 range->dst_offset = c->next_ubo_dst_offset;
136 c->next_ubo_dst_offset += range->size;
137 c->num_ubo_ranges++;
138 };
139
140 offset -= range->src_offset;
141 /* Translate the user's TGSI register index from the TGSI register
142 * base to a byte offset.
143 */
144 indirect_offset = qir_SHL(c, indirect_offset, qir_uniform_ui(c, 4));
145
146 /* Adjust for where we stored the TGSI register base. */
147 indirect_offset = qir_ADD(c, indirect_offset,
148 qir_uniform_ui(c, (range->dst_offset +
149 offset)));
150 indirect_offset = qir_MIN(c, indirect_offset,
151 qir_uniform_ui(c, (range->dst_offset +
152 range->size - 4)));
153
154 qir_TEX_DIRECT(c, indirect_offset, qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
155 struct qreg r4 = qir_TEX_RESULT(c);
156 c->num_texture_samples++;
157 return qir_MOV(c, r4);
158 }
159
160 static struct qreg *
161 ntq_get_dest(struct vc4_compile *c, nir_dest dest)
162 {
163 assert(!dest.is_ssa);
164 nir_register *reg = dest.reg.reg;
165 struct hash_entry *entry = _mesa_hash_table_search(c->def_ht, reg);
166 assert(reg->num_array_elems == 0);
167 assert(dest.reg.base_offset == 0);
168
169 struct qreg *qregs = entry->data;
170 return qregs;
171 }
172
173 static struct qreg
174 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
175 {
176 struct hash_entry *entry;
177 if (src.is_ssa) {
178 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
179 assert(i < src.ssa->num_components);
180 } else {
181 nir_register *reg = src.reg.reg;
182 entry = _mesa_hash_table_search(c->def_ht, reg);
183 assert(reg->num_array_elems == 0);
184 assert(src.reg.base_offset == 0);
185 assert(i < reg->num_components);
186 }
187
188 struct qreg *qregs = entry->data;
189 return qregs[i];
190 }
191
192 static struct qreg
193 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
194 unsigned src)
195 {
196 assert(util_is_power_of_two(instr->dest.write_mask));
197 unsigned chan = ffs(instr->dest.write_mask) - 1;
198 struct qreg r = ntq_get_src(c, instr->src[src].src,
199 instr->src[src].swizzle[chan]);
200
201 assert(!instr->src[src].abs);
202 assert(!instr->src[src].negate);
203
204 return r;
205 };
206
207 static struct qreg
208 get_swizzled_channel(struct vc4_compile *c,
209 struct qreg *srcs, int swiz)
210 {
211 switch (swiz) {
212 default:
213 case UTIL_FORMAT_SWIZZLE_NONE:
214 fprintf(stderr, "warning: unknown swizzle\n");
215 /* FALLTHROUGH */
216 case UTIL_FORMAT_SWIZZLE_0:
217 return qir_uniform_f(c, 0.0);
218 case UTIL_FORMAT_SWIZZLE_1:
219 return qir_uniform_f(c, 1.0);
220 case UTIL_FORMAT_SWIZZLE_X:
221 case UTIL_FORMAT_SWIZZLE_Y:
222 case UTIL_FORMAT_SWIZZLE_Z:
223 case UTIL_FORMAT_SWIZZLE_W:
224 return srcs[swiz];
225 }
226 }
227
228 static inline struct qreg
229 qir_SAT(struct vc4_compile *c, struct qreg val)
230 {
231 return qir_FMAX(c,
232 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
233 qir_uniform_f(c, 0.0));
234 }
235
236 static struct qreg
237 ntq_rcp(struct vc4_compile *c, struct qreg x)
238 {
239 struct qreg r = qir_RCP(c, x);
240
241 /* Apply a Newton-Raphson step to improve the accuracy. */
242 r = qir_FMUL(c, r, qir_FSUB(c,
243 qir_uniform_f(c, 2.0),
244 qir_FMUL(c, x, r)));
245
246 return r;
247 }
248
249 static struct qreg
250 ntq_rsq(struct vc4_compile *c, struct qreg x)
251 {
252 struct qreg r = qir_RSQ(c, x);
253
254 /* Apply a Newton-Raphson step to improve the accuracy. */
255 r = qir_FMUL(c, r, qir_FSUB(c,
256 qir_uniform_f(c, 1.5),
257 qir_FMUL(c,
258 qir_uniform_f(c, 0.5),
259 qir_FMUL(c, x,
260 qir_FMUL(c, r, r)))));
261
262 return r;
263 }
264
265 static struct qreg
266 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
267 {
268 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
269 struct qreg high = qir_POW(c,
270 qir_FMUL(c,
271 qir_FADD(c,
272 srgb,
273 qir_uniform_f(c, 0.055)),
274 qir_uniform_f(c, 1.0 / 1.055)),
275 qir_uniform_f(c, 2.4));
276
277 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
278 return qir_SEL_X_Y_NS(c, low, high);
279 }
280
281 static struct qreg
282 qir_srgb_encode(struct vc4_compile *c, struct qreg linear)
283 {
284 struct qreg low = qir_FMUL(c, linear, qir_uniform_f(c, 12.92));
285 struct qreg high = qir_FSUB(c,
286 qir_FMUL(c,
287 qir_uniform_f(c, 1.055),
288 qir_POW(c,
289 linear,
290 qir_uniform_f(c, 0.41666))),
291 qir_uniform_f(c, 0.055));
292
293 qir_SF(c, qir_FSUB(c, linear, qir_uniform_f(c, 0.0031308)));
294 return qir_SEL_X_Y_NS(c, low, high);
295 }
296
297 static struct qreg
298 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
299 {
300 struct qreg src0_hi = qir_SHR(c, src0,
301 qir_uniform_ui(c, 24));
302 struct qreg src1_hi = qir_SHR(c, src1,
303 qir_uniform_ui(c, 24));
304
305 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
306 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
307 struct qreg lolo = qir_MUL24(c, src0, src1);
308
309 return qir_ADD(c, lolo, qir_SHL(c,
310 qir_ADD(c, hilo, lohi),
311 qir_uniform_ui(c, 24)));
312 }
313
314 static struct qreg
315 ntq_idiv(struct vc4_compile *c, struct qreg src0, struct qreg src1)
316 {
317 return qir_FTOI(c, qir_FMUL(c,
318 qir_ITOF(c, src0),
319 qir_RCP(c, qir_ITOF(c, src1))));
320 }
321
322 static void
323 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
324 {
325 struct qreg s, t, r, lod, proj, compare;
326 bool is_txb = false, is_txl = false, has_proj = false;
327 unsigned unit = instr->sampler_index;
328
329 for (unsigned i = 0; i < instr->num_srcs; i++) {
330 switch (instr->src[i].src_type) {
331 case nir_tex_src_coord:
332 s = ntq_get_src(c, instr->src[i].src, 0);
333 if (instr->sampler_dim != GLSL_SAMPLER_DIM_1D)
334 t = ntq_get_src(c, instr->src[i].src, 1);
335 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
336 r = ntq_get_src(c, instr->src[i].src, 2);
337 break;
338 case nir_tex_src_bias:
339 lod = ntq_get_src(c, instr->src[i].src, 0);
340 is_txb = true;
341 break;
342 case nir_tex_src_lod:
343 lod = ntq_get_src(c, instr->src[i].src, 0);
344 is_txl = true;
345 break;
346 case nir_tex_src_comparitor:
347 compare = ntq_get_src(c, instr->src[i].src, 0);
348 break;
349 case nir_tex_src_projector:
350 proj = qir_RCP(c, ntq_get_src(c, instr->src[i].src, 0));
351 s = qir_FMUL(c, s, proj);
352 t = qir_FMUL(c, t, proj);
353 has_proj = true;
354 break;
355 default:
356 unreachable("unknown texture source");
357 }
358 }
359
360 struct qreg texture_u[] = {
361 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
362 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
363 qir_uniform(c, QUNIFORM_CONSTANT, 0),
364 qir_uniform(c, QUNIFORM_CONSTANT, 0),
365 };
366 uint32_t next_texture_u = 0;
367
368 /* There is no native support for GL texture rectangle coordinates, so
369 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
370 * 1]).
371 */
372 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
373 s = qir_FMUL(c, s,
374 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
375 t = qir_FMUL(c, t,
376 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
377 }
378
379 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
380 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
381 unit | (is_txl << 16));
382 }
383
384 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
385 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
386 struct qreg rcp_ma = qir_RCP(c, ma);
387 s = qir_FMUL(c, s, rcp_ma);
388 t = qir_FMUL(c, t, rcp_ma);
389 r = qir_FMUL(c, r, rcp_ma);
390
391 qir_TEX_R(c, r, texture_u[next_texture_u++]);
392 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
393 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
394 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
395 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
396 qir_TEX_R(c, qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
397 texture_u[next_texture_u++]);
398 }
399
400 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
401 s = qir_SAT(c, s);
402 }
403
404 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
405 t = qir_SAT(c, t);
406 }
407
408 qir_TEX_T(c, t, texture_u[next_texture_u++]);
409
410 if (is_txl || is_txb)
411 qir_TEX_B(c, lod, texture_u[next_texture_u++]);
412
413 qir_TEX_S(c, s, texture_u[next_texture_u++]);
414
415 c->num_texture_samples++;
416 struct qreg r4 = qir_TEX_RESULT(c);
417
418 enum pipe_format format = c->key->tex[unit].format;
419
420 struct qreg unpacked[4];
421 if (util_format_is_depth_or_stencil(format)) {
422 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
423 qir_uniform_ui(c, 8)));
424 struct qreg normalized = qir_FMUL(c, depthf,
425 qir_uniform_f(c, 1.0f/0xffffff));
426
427 struct qreg depth_output;
428
429 struct qreg one = qir_uniform_f(c, 1.0f);
430 if (c->key->tex[unit].compare_mode) {
431 if (has_proj)
432 compare = qir_FMUL(c, compare, proj);
433
434 switch (c->key->tex[unit].compare_func) {
435 case PIPE_FUNC_NEVER:
436 depth_output = qir_uniform_f(c, 0.0f);
437 break;
438 case PIPE_FUNC_ALWAYS:
439 depth_output = one;
440 break;
441 case PIPE_FUNC_EQUAL:
442 qir_SF(c, qir_FSUB(c, compare, normalized));
443 depth_output = qir_SEL_X_0_ZS(c, one);
444 break;
445 case PIPE_FUNC_NOTEQUAL:
446 qir_SF(c, qir_FSUB(c, compare, normalized));
447 depth_output = qir_SEL_X_0_ZC(c, one);
448 break;
449 case PIPE_FUNC_GREATER:
450 qir_SF(c, qir_FSUB(c, compare, normalized));
451 depth_output = qir_SEL_X_0_NC(c, one);
452 break;
453 case PIPE_FUNC_GEQUAL:
454 qir_SF(c, qir_FSUB(c, normalized, compare));
455 depth_output = qir_SEL_X_0_NS(c, one);
456 break;
457 case PIPE_FUNC_LESS:
458 qir_SF(c, qir_FSUB(c, compare, normalized));
459 depth_output = qir_SEL_X_0_NS(c, one);
460 break;
461 case PIPE_FUNC_LEQUAL:
462 qir_SF(c, qir_FSUB(c, normalized, compare));
463 depth_output = qir_SEL_X_0_NC(c, one);
464 break;
465 }
466 } else {
467 depth_output = normalized;
468 }
469
470 for (int i = 0; i < 4; i++)
471 unpacked[i] = depth_output;
472 } else {
473 for (int i = 0; i < 4; i++)
474 unpacked[i] = qir_R4_UNPACK(c, r4, i);
475 }
476
477 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
478 struct qreg texture_output[4];
479 for (int i = 0; i < 4; i++) {
480 texture_output[i] = get_swizzled_channel(c, unpacked,
481 format_swiz[i]);
482 }
483
484 if (util_format_is_srgb(format)) {
485 for (int i = 0; i < 3; i++)
486 texture_output[i] = qir_srgb_decode(c,
487 texture_output[i]);
488 }
489
490 struct qreg *dest = ntq_get_dest(c, instr->dest);
491 for (int i = 0; i < 4; i++) {
492 dest[i] = get_swizzled_channel(c, texture_output,
493 c->key->tex[unit].swizzle[i]);
494 }
495 }
496
497 /**
498 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
499 * to zero).
500 */
501 static struct qreg
502 ntq_ffract(struct vc4_compile *c, struct qreg src)
503 {
504 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
505 struct qreg diff = qir_FSUB(c, src, trunc);
506 qir_SF(c, diff);
507 return qir_SEL_X_Y_NS(c,
508 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
509 diff);
510 }
511
512 /**
513 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
514 * zero).
515 */
516 static struct qreg
517 ntq_ffloor(struct vc4_compile *c, struct qreg src)
518 {
519 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
520
521 /* This will be < 0 if we truncated and the truncation was of a value
522 * that was < 0 in the first place.
523 */
524 qir_SF(c, qir_FSUB(c, src, trunc));
525
526 return qir_SEL_X_Y_NS(c,
527 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
528 trunc);
529 }
530
531 /**
532 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
533 * zero).
534 */
535 static struct qreg
536 ntq_fceil(struct vc4_compile *c, struct qreg src)
537 {
538 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
539
540 /* This will be < 0 if we truncated and the truncation was of a value
541 * that was > 0 in the first place.
542 */
543 qir_SF(c, qir_FSUB(c, trunc, src));
544
545 return qir_SEL_X_Y_NS(c,
546 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),
547 trunc);
548 }
549
550 static struct qreg
551 ntq_fsin(struct vc4_compile *c, struct qreg src)
552 {
553 float coeff[] = {
554 -2.0 * M_PI,
555 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
556 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
557 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
558 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
559 };
560
561 struct qreg scaled_x =
562 qir_FMUL(c,
563 src,
564 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
565
566 struct qreg x = qir_FADD(c,
567 ntq_ffract(c, scaled_x),
568 qir_uniform_f(c, -0.5));
569 struct qreg x2 = qir_FMUL(c, x, x);
570 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
571 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
572 x = qir_FMUL(c, x, x2);
573 sum = qir_FADD(c,
574 sum,
575 qir_FMUL(c,
576 x,
577 qir_uniform_f(c, coeff[i])));
578 }
579 return sum;
580 }
581
582 static struct qreg
583 ntq_fcos(struct vc4_compile *c, struct qreg src)
584 {
585 float coeff[] = {
586 -1.0f,
587 pow(2.0 * M_PI, 2) / (2 * 1),
588 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
589 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
590 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
591 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
592 };
593
594 struct qreg scaled_x =
595 qir_FMUL(c, src,
596 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
597 struct qreg x_frac = qir_FADD(c,
598 ntq_ffract(c, scaled_x),
599 qir_uniform_f(c, -0.5));
600
601 struct qreg sum = qir_uniform_f(c, coeff[0]);
602 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
603 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
604 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
605 if (i != 1)
606 x = qir_FMUL(c, x, x2);
607
608 struct qreg mul = qir_FMUL(c,
609 x,
610 qir_uniform_f(c, coeff[i]));
611 if (i == 0)
612 sum = mul;
613 else
614 sum = qir_FADD(c, sum, mul);
615 }
616 return sum;
617 }
618
619 static struct qreg
620 ntq_fsign(struct vc4_compile *c, struct qreg src)
621 {
622 qir_SF(c, src);
623 return qir_SEL_X_Y_NC(c,
624 qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0)),
625 qir_uniform_f(c, -1.0));
626 }
627
628 static struct qreg
629 get_channel_from_vpm(struct vc4_compile *c,
630 struct qreg *vpm_reads,
631 uint8_t swiz,
632 const struct util_format_description *desc)
633 {
634 const struct util_format_channel_description *chan =
635 &desc->channel[swiz];
636 struct qreg temp;
637
638 if (swiz > UTIL_FORMAT_SWIZZLE_W)
639 return get_swizzled_channel(c, vpm_reads, swiz);
640 else if (chan->size == 32 &&
641 chan->type == UTIL_FORMAT_TYPE_FLOAT) {
642 return get_swizzled_channel(c, vpm_reads, swiz);
643 } else if (chan->size == 32 &&
644 chan->type == UTIL_FORMAT_TYPE_SIGNED) {
645 if (chan->normalized) {
646 return qir_FMUL(c,
647 qir_ITOF(c, vpm_reads[swiz]),
648 qir_uniform_f(c,
649 1.0 / 0x7fffffff));
650 } else {
651 return qir_ITOF(c, vpm_reads[swiz]);
652 }
653 } else if (chan->size == 8 &&
654 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
655 chan->type == UTIL_FORMAT_TYPE_SIGNED)) {
656 struct qreg vpm = vpm_reads[0];
657 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
658 temp = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
659 if (chan->normalized) {
660 return qir_FSUB(c, qir_FMUL(c,
661 qir_UNPACK_8_F(c, temp, swiz),
662 qir_uniform_f(c, 2.0)),
663 qir_uniform_f(c, 1.0));
664 } else {
665 return qir_FADD(c,
666 qir_ITOF(c,
667 qir_UNPACK_8_I(c, temp,
668 swiz)),
669 qir_uniform_f(c, -128.0));
670 }
671 } else {
672 if (chan->normalized) {
673 return qir_UNPACK_8_F(c, vpm, swiz);
674 } else {
675 return qir_ITOF(c, qir_UNPACK_8_I(c, vpm, swiz));
676 }
677 }
678 } else if (chan->size == 16 &&
679 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
680 chan->type == UTIL_FORMAT_TYPE_SIGNED)) {
681 struct qreg vpm = vpm_reads[swiz / 2];
682
683 /* Note that UNPACK_16F eats a half float, not ints, so we use
684 * UNPACK_16_I for all of these.
685 */
686 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
687 temp = qir_ITOF(c, qir_UNPACK_16_I(c, vpm, swiz % 2));
688 if (chan->normalized) {
689 return qir_FMUL(c, temp,
690 qir_uniform_f(c, 1/32768.0f));
691 } else {
692 return temp;
693 }
694 } else {
695 /* UNPACK_16I sign-extends, so we have to emit ANDs. */
696 temp = vpm;
697 if (swiz == 1 || swiz == 3)
698 temp = qir_UNPACK_16_I(c, temp, 1);
699 temp = qir_AND(c, temp, qir_uniform_ui(c, 0xffff));
700 temp = qir_ITOF(c, temp);
701
702 if (chan->normalized) {
703 return qir_FMUL(c, temp,
704 qir_uniform_f(c, 1 / 65535.0));
705 } else {
706 return temp;
707 }
708 }
709 } else {
710 return c->undef;
711 }
712 }
713
714 static void
715 emit_vertex_input(struct vc4_compile *c, int attr)
716 {
717 enum pipe_format format = c->vs_key->attr_formats[attr];
718 uint32_t attr_size = util_format_get_blocksize(format);
719 struct qreg vpm_reads[4];
720
721 c->vattr_sizes[attr] = align(attr_size, 4);
722 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
723 struct qreg vpm = { QFILE_VPM, attr * 4 + i };
724 vpm_reads[i] = qir_MOV(c, vpm);
725 c->num_inputs++;
726 }
727
728 bool format_warned = false;
729 const struct util_format_description *desc =
730 util_format_description(format);
731
732 for (int i = 0; i < 4; i++) {
733 uint8_t swiz = desc->swizzle[i];
734 struct qreg result = get_channel_from_vpm(c, vpm_reads,
735 swiz, desc);
736
737 if (result.file == QFILE_NULL) {
738 if (!format_warned) {
739 fprintf(stderr,
740 "vtx element %d unsupported type: %s\n",
741 attr, util_format_name(format));
742 format_warned = true;
743 }
744 result = qir_uniform_f(c, 0.0);
745 }
746 c->inputs[attr * 4 + i] = result;
747 }
748 }
749
750 static void
751 emit_fragcoord_input(struct vc4_compile *c, int attr)
752 {
753 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
754 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
755 c->inputs[attr * 4 + 2] =
756 qir_FMUL(c,
757 qir_ITOF(c, qir_FRAG_Z(c)),
758 qir_uniform_f(c, 1.0 / 0xffffff));
759 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
760 }
761
762 static void
763 emit_point_coord_input(struct vc4_compile *c, int attr)
764 {
765 if (c->point_x.file == QFILE_NULL) {
766 c->point_x = qir_uniform_f(c, 0.0);
767 c->point_y = qir_uniform_f(c, 0.0);
768 }
769
770 c->inputs[attr * 4 + 0] = c->point_x;
771 if (c->fs_key->point_coord_upper_left) {
772 c->inputs[attr * 4 + 1] = qir_FSUB(c,
773 qir_uniform_f(c, 1.0),
774 c->point_y);
775 } else {
776 c->inputs[attr * 4 + 1] = c->point_y;
777 }
778 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
779 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
780 }
781
782 static struct qreg
783 emit_fragment_varying(struct vc4_compile *c, uint8_t semantic,
784 uint8_t index, uint8_t swizzle)
785 {
786 uint32_t i = c->num_input_semantics++;
787 struct qreg vary = {
788 QFILE_VARY,
789 i
790 };
791
792 if (c->num_input_semantics >= c->input_semantics_array_size) {
793 c->input_semantics_array_size =
794 MAX2(4, c->input_semantics_array_size * 2);
795
796 c->input_semantics = reralloc(c, c->input_semantics,
797 struct vc4_varying_semantic,
798 c->input_semantics_array_size);
799 }
800
801 c->input_semantics[i].semantic = semantic;
802 c->input_semantics[i].index = index;
803 c->input_semantics[i].swizzle = swizzle;
804
805 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
806 }
807
808 static void
809 emit_fragment_input(struct vc4_compile *c, int attr,
810 unsigned semantic_name, unsigned semantic_index)
811 {
812 for (int i = 0; i < 4; i++) {
813 c->inputs[attr * 4 + i] =
814 emit_fragment_varying(c,
815 semantic_name,
816 semantic_index,
817 i);
818 c->num_inputs++;
819 }
820 }
821
822 static void
823 emit_face_input(struct vc4_compile *c, int attr)
824 {
825 c->inputs[attr * 4 + 0] = qir_FSUB(c,
826 qir_uniform_f(c, 1.0),
827 qir_FMUL(c,
828 qir_ITOF(c, qir_FRAG_REV_FLAG(c)),
829 qir_uniform_f(c, 2.0)));
830 c->inputs[attr * 4 + 1] = qir_uniform_f(c, 0.0);
831 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
832 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
833 }
834
835 static void
836 add_output(struct vc4_compile *c,
837 uint32_t decl_offset,
838 uint8_t semantic_name,
839 uint8_t semantic_index,
840 uint8_t semantic_swizzle)
841 {
842 uint32_t old_array_size = c->outputs_array_size;
843 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
844 decl_offset + 1);
845
846 if (old_array_size != c->outputs_array_size) {
847 c->output_semantics = reralloc(c,
848 c->output_semantics,
849 struct vc4_varying_semantic,
850 c->outputs_array_size);
851 }
852
853 c->output_semantics[decl_offset].semantic = semantic_name;
854 c->output_semantics[decl_offset].index = semantic_index;
855 c->output_semantics[decl_offset].swizzle = semantic_swizzle;
856 }
857
858 static void
859 declare_uniform_range(struct vc4_compile *c, uint32_t start, uint32_t size)
860 {
861 unsigned array_id = c->num_uniform_ranges++;
862 if (array_id >= c->ubo_ranges_array_size) {
863 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
864 array_id + 1);
865 c->ubo_ranges = reralloc(c, c->ubo_ranges,
866 struct vc4_compiler_ubo_range,
867 c->ubo_ranges_array_size);
868 }
869
870 c->ubo_ranges[array_id].dst_offset = 0;
871 c->ubo_ranges[array_id].src_offset = start;
872 c->ubo_ranges[array_id].size = size;
873 c->ubo_ranges[array_id].used = false;
874 }
875
876 static void
877 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
878 {
879 /* Vectors are special in that they have non-scalarized writemasks,
880 * and just take the first swizzle channel for each argument in order
881 * into each writemask channel.
882 */
883 if (instr->op == nir_op_vec2 ||
884 instr->op == nir_op_vec3 ||
885 instr->op == nir_op_vec4) {
886 struct qreg srcs[4];
887 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
888 srcs[i] = ntq_get_src(c, instr->src[i].src,
889 instr->src[i].swizzle[0]);
890 struct qreg *dest = ntq_get_dest(c, instr->dest.dest);
891 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
892 dest[i] = srcs[i];
893 return;
894 }
895
896 /* General case: We can just grab the one used channel per src. */
897 struct qreg src[nir_op_infos[instr->op].num_inputs];
898 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
899 src[i] = ntq_get_alu_src(c, instr, i);
900 }
901
902 /* Pick the channel to store the output in. */
903 assert(!instr->dest.saturate);
904 struct qreg *dest = ntq_get_dest(c, instr->dest.dest);
905 assert(util_is_power_of_two(instr->dest.write_mask));
906 dest += ffs(instr->dest.write_mask) - 1;
907
908 switch (instr->op) {
909 case nir_op_fmov:
910 case nir_op_imov:
911 *dest = qir_MOV(c, src[0]);
912 break;
913 case nir_op_fmul:
914 *dest = qir_FMUL(c, src[0], src[1]);
915 break;
916 case nir_op_fadd:
917 *dest = qir_FADD(c, src[0], src[1]);
918 break;
919 case nir_op_fsub:
920 *dest = qir_FSUB(c, src[0], src[1]);
921 break;
922 case nir_op_fmin:
923 *dest = qir_FMIN(c, src[0], src[1]);
924 break;
925 case nir_op_fmax:
926 *dest = qir_FMAX(c, src[0], src[1]);
927 break;
928 case nir_op_f2i:
929 *dest = qir_FTOI(c, src[0]);
930 break;
931 case nir_op_i2f:
932 *dest = qir_ITOF(c, src[0]);
933 break;
934 case nir_op_b2f:
935 *dest = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
936 break;
937 case nir_op_iadd:
938 *dest = qir_ADD(c, src[0], src[1]);
939 break;
940 case nir_op_ushr:
941 *dest = qir_SHR(c, src[0], src[1]);
942 break;
943 case nir_op_isub:
944 *dest = qir_SUB(c, src[0], src[1]);
945 break;
946 case nir_op_ishr:
947 *dest = qir_ASR(c, src[0], src[1]);
948 break;
949 case nir_op_ishl:
950 *dest = qir_SHL(c, src[0], src[1]);
951 break;
952 case nir_op_imin:
953 *dest = qir_MIN(c, src[0], src[1]);
954 break;
955 case nir_op_imax:
956 *dest = qir_MAX(c, src[0], src[1]);
957 break;
958 case nir_op_iand:
959 *dest = qir_AND(c, src[0], src[1]);
960 break;
961 case nir_op_ior:
962 *dest = qir_OR(c, src[0], src[1]);
963 break;
964 case nir_op_ixor:
965 *dest = qir_XOR(c, src[0], src[1]);
966 break;
967 case nir_op_inot:
968 *dest = qir_NOT(c, src[0]);
969 break;
970
971 case nir_op_imul:
972 *dest = ntq_umul(c, src[0], src[1]);
973 break;
974 case nir_op_idiv:
975 *dest = ntq_idiv(c, src[0], src[1]);
976 break;
977
978 case nir_op_seq:
979 qir_SF(c, qir_FSUB(c, src[0], src[1]));
980 *dest = qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
981 break;
982 case nir_op_sne:
983 qir_SF(c, qir_FSUB(c, src[0], src[1]));
984 *dest = qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
985 break;
986 case nir_op_sge:
987 qir_SF(c, qir_FSUB(c, src[0], src[1]));
988 *dest = qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
989 break;
990 case nir_op_slt:
991 qir_SF(c, qir_FSUB(c, src[0], src[1]));
992 *dest = qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
993 break;
994 case nir_op_feq:
995 qir_SF(c, qir_FSUB(c, src[0], src[1]));
996 *dest = qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
997 break;
998 case nir_op_fne:
999 qir_SF(c, qir_FSUB(c, src[0], src[1]));
1000 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
1001 break;
1002 case nir_op_fge:
1003 qir_SF(c, qir_FSUB(c, src[0], src[1]));
1004 *dest = qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
1005 break;
1006 case nir_op_flt:
1007 qir_SF(c, qir_FSUB(c, src[0], src[1]));
1008 *dest = qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
1009 break;
1010 case nir_op_ieq:
1011 qir_SF(c, qir_SUB(c, src[0], src[1]));
1012 *dest = qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
1013 break;
1014 case nir_op_ine:
1015 qir_SF(c, qir_SUB(c, src[0], src[1]));
1016 *dest = qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
1017 break;
1018 case nir_op_ige:
1019 qir_SF(c, qir_SUB(c, src[0], src[1]));
1020 *dest = qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
1021 break;
1022 case nir_op_ilt:
1023 qir_SF(c, qir_SUB(c, src[0], src[1]));
1024 *dest = qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
1025 break;
1026
1027 case nir_op_bcsel:
1028 qir_SF(c, src[0]);
1029 *dest = qir_SEL_X_Y_NS(c, src[1], src[2]);
1030 break;
1031 case nir_op_fcsel:
1032 qir_SF(c, src[0]);
1033 *dest = qir_SEL_X_Y_ZC(c, src[1], src[2]);
1034 break;
1035
1036 case nir_op_frcp:
1037 *dest = ntq_rcp(c, src[0]);
1038 break;
1039 case nir_op_frsq:
1040 *dest = ntq_rsq(c, src[0]);
1041 break;
1042 case nir_op_fexp2:
1043 *dest = qir_EXP2(c, src[0]);
1044 break;
1045 case nir_op_flog2:
1046 *dest = qir_LOG2(c, src[0]);
1047 break;
1048
1049 case nir_op_ftrunc:
1050 *dest = qir_ITOF(c, qir_FTOI(c, src[0]));
1051 break;
1052 case nir_op_fceil:
1053 *dest = ntq_fceil(c, src[0]);
1054 break;
1055 case nir_op_ffract:
1056 *dest = ntq_ffract(c, src[0]);
1057 break;
1058 case nir_op_ffloor:
1059 *dest = ntq_ffloor(c, src[0]);
1060 break;
1061
1062 case nir_op_fsin:
1063 *dest = ntq_fsin(c, src[0]);
1064 break;
1065 case nir_op_fcos:
1066 *dest = ntq_fcos(c, src[0]);
1067 break;
1068
1069 case nir_op_fsign:
1070 *dest = ntq_fsign(c, src[0]);
1071 break;
1072 case nir_op_fabs:
1073 *dest = qir_FMAXABS(c, src[0], src[0]);
1074 break;
1075
1076 default:
1077 fprintf(stderr, "unknown NIR ALU inst: ");
1078 nir_print_instr(&instr->instr, stderr);
1079 fprintf(stderr, "\n");
1080 abort();
1081 }
1082 }
1083
1084 static struct qreg
1085 vc4_blend_channel(struct vc4_compile *c,
1086 struct qreg *dst,
1087 struct qreg *src,
1088 struct qreg val,
1089 unsigned factor,
1090 int channel)
1091 {
1092 switch(factor) {
1093 case PIPE_BLENDFACTOR_ONE:
1094 return val;
1095 case PIPE_BLENDFACTOR_SRC_COLOR:
1096 return qir_FMUL(c, val, src[channel]);
1097 case PIPE_BLENDFACTOR_SRC_ALPHA:
1098 return qir_FMUL(c, val, src[3]);
1099 case PIPE_BLENDFACTOR_DST_ALPHA:
1100 return qir_FMUL(c, val, dst[3]);
1101 case PIPE_BLENDFACTOR_DST_COLOR:
1102 return qir_FMUL(c, val, dst[channel]);
1103 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1104 if (channel != 3) {
1105 return qir_FMUL(c,
1106 val,
1107 qir_FMIN(c,
1108 src[3],
1109 qir_FSUB(c,
1110 qir_uniform_f(c, 1.0),
1111 dst[3])));
1112 } else {
1113 return val;
1114 }
1115 case PIPE_BLENDFACTOR_CONST_COLOR:
1116 return qir_FMUL(c, val,
1117 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR,
1118 channel));
1119 case PIPE_BLENDFACTOR_CONST_ALPHA:
1120 return qir_FMUL(c, val,
1121 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR, 3));
1122 case PIPE_BLENDFACTOR_ZERO:
1123 return qir_uniform_f(c, 0.0);
1124 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1125 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1126 src[channel]));
1127 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1128 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1129 src[3]));
1130 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1131 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1132 dst[3]));
1133 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1134 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1135 dst[channel]));
1136 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1137 return qir_FMUL(c, val,
1138 qir_FSUB(c, qir_uniform_f(c, 1.0),
1139 qir_uniform(c,
1140 QUNIFORM_BLEND_CONST_COLOR,
1141 channel)));
1142 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1143 return qir_FMUL(c, val,
1144 qir_FSUB(c, qir_uniform_f(c, 1.0),
1145 qir_uniform(c,
1146 QUNIFORM_BLEND_CONST_COLOR,
1147 3)));
1148
1149 default:
1150 case PIPE_BLENDFACTOR_SRC1_COLOR:
1151 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1152 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1153 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1154 /* Unsupported. */
1155 fprintf(stderr, "Unknown blend factor %d\n", factor);
1156 return val;
1157 }
1158 }
1159
1160 static struct qreg
1161 vc4_blend_func(struct vc4_compile *c,
1162 struct qreg src, struct qreg dst,
1163 unsigned func)
1164 {
1165 switch (func) {
1166 case PIPE_BLEND_ADD:
1167 return qir_FADD(c, src, dst);
1168 case PIPE_BLEND_SUBTRACT:
1169 return qir_FSUB(c, src, dst);
1170 case PIPE_BLEND_REVERSE_SUBTRACT:
1171 return qir_FSUB(c, dst, src);
1172 case PIPE_BLEND_MIN:
1173 return qir_FMIN(c, src, dst);
1174 case PIPE_BLEND_MAX:
1175 return qir_FMAX(c, src, dst);
1176
1177 default:
1178 /* Unsupported. */
1179 fprintf(stderr, "Unknown blend func %d\n", func);
1180 return src;
1181
1182 }
1183 }
1184
1185 /**
1186 * Implements fixed function blending in shader code.
1187 *
1188 * VC4 doesn't have any hardware support for blending. Instead, you read the
1189 * current contents of the destination from the tile buffer after having
1190 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1191 * math using your output color and that destination value, and update the
1192 * output color appropriately.
1193 */
1194 static void
1195 vc4_blend(struct vc4_compile *c, struct qreg *result,
1196 struct qreg *dst_color, struct qreg *src_color)
1197 {
1198 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1199
1200 if (!blend->blend_enable) {
1201 for (int i = 0; i < 4; i++)
1202 result[i] = src_color[i];
1203 return;
1204 }
1205
1206 struct qreg clamped_src[4];
1207 struct qreg clamped_dst[4];
1208 for (int i = 0; i < 4; i++) {
1209 clamped_src[i] = qir_SAT(c, src_color[i]);
1210 clamped_dst[i] = qir_SAT(c, dst_color[i]);
1211 }
1212 src_color = clamped_src;
1213 dst_color = clamped_dst;
1214
1215 struct qreg src_blend[4], dst_blend[4];
1216 for (int i = 0; i < 3; i++) {
1217 src_blend[i] = vc4_blend_channel(c,
1218 dst_color, src_color,
1219 src_color[i],
1220 blend->rgb_src_factor, i);
1221 dst_blend[i] = vc4_blend_channel(c,
1222 dst_color, src_color,
1223 dst_color[i],
1224 blend->rgb_dst_factor, i);
1225 }
1226 src_blend[3] = vc4_blend_channel(c,
1227 dst_color, src_color,
1228 src_color[3],
1229 blend->alpha_src_factor, 3);
1230 dst_blend[3] = vc4_blend_channel(c,
1231 dst_color, src_color,
1232 dst_color[3],
1233 blend->alpha_dst_factor, 3);
1234
1235 for (int i = 0; i < 3; i++) {
1236 result[i] = vc4_blend_func(c,
1237 src_blend[i], dst_blend[i],
1238 blend->rgb_func);
1239 }
1240 result[3] = vc4_blend_func(c,
1241 src_blend[3], dst_blend[3],
1242 blend->alpha_func);
1243 }
1244
1245 static void
1246 clip_distance_discard(struct vc4_compile *c)
1247 {
1248 for (int i = 0; i < PIPE_MAX_CLIP_PLANES; i++) {
1249 if (!(c->key->ucp_enables & (1 << i)))
1250 continue;
1251
1252 struct qreg dist = emit_fragment_varying(c,
1253 TGSI_SEMANTIC_CLIPDIST,
1254 i,
1255 TGSI_SWIZZLE_X);
1256
1257 qir_SF(c, dist);
1258
1259 if (c->discard.file == QFILE_NULL)
1260 c->discard = qir_uniform_ui(c, 0);
1261
1262 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_ui(c, ~0),
1263 c->discard);
1264 }
1265 }
1266
1267 static void
1268 alpha_test_discard(struct vc4_compile *c)
1269 {
1270 struct qreg src_alpha;
1271 struct qreg alpha_ref = qir_uniform(c, QUNIFORM_ALPHA_REF, 0);
1272
1273 if (!c->fs_key->alpha_test)
1274 return;
1275
1276 if (c->output_color_index != -1)
1277 src_alpha = c->outputs[c->output_color_index + 3];
1278 else
1279 src_alpha = qir_uniform_f(c, 1.0);
1280
1281 if (c->discard.file == QFILE_NULL)
1282 c->discard = qir_uniform_ui(c, 0);
1283
1284 switch (c->fs_key->alpha_test_func) {
1285 case PIPE_FUNC_NEVER:
1286 c->discard = qir_uniform_ui(c, ~0);
1287 break;
1288 case PIPE_FUNC_ALWAYS:
1289 break;
1290 case PIPE_FUNC_EQUAL:
1291 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1292 c->discard = qir_SEL_X_Y_ZS(c, c->discard,
1293 qir_uniform_ui(c, ~0));
1294 break;
1295 case PIPE_FUNC_NOTEQUAL:
1296 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1297 c->discard = qir_SEL_X_Y_ZC(c, c->discard,
1298 qir_uniform_ui(c, ~0));
1299 break;
1300 case PIPE_FUNC_GREATER:
1301 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1302 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1303 qir_uniform_ui(c, ~0));
1304 break;
1305 case PIPE_FUNC_GEQUAL:
1306 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1307 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1308 qir_uniform_ui(c, ~0));
1309 break;
1310 case PIPE_FUNC_LESS:
1311 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1312 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1313 qir_uniform_ui(c, ~0));
1314 break;
1315 case PIPE_FUNC_LEQUAL:
1316 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1317 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1318 qir_uniform_ui(c, ~0));
1319 break;
1320 }
1321 }
1322
1323 static struct qreg
1324 vc4_logicop(struct vc4_compile *c, struct qreg src, struct qreg dst)
1325 {
1326 switch (c->fs_key->logicop_func) {
1327 case PIPE_LOGICOP_CLEAR:
1328 return qir_uniform_f(c, 0.0);
1329 case PIPE_LOGICOP_NOR:
1330 return qir_NOT(c, qir_OR(c, src, dst));
1331 case PIPE_LOGICOP_AND_INVERTED:
1332 return qir_AND(c, qir_NOT(c, src), dst);
1333 case PIPE_LOGICOP_COPY_INVERTED:
1334 return qir_NOT(c, src);
1335 case PIPE_LOGICOP_AND_REVERSE:
1336 return qir_AND(c, src, qir_NOT(c, dst));
1337 case PIPE_LOGICOP_INVERT:
1338 return qir_NOT(c, dst);
1339 case PIPE_LOGICOP_XOR:
1340 return qir_XOR(c, src, dst);
1341 case PIPE_LOGICOP_NAND:
1342 return qir_NOT(c, qir_AND(c, src, dst));
1343 case PIPE_LOGICOP_AND:
1344 return qir_AND(c, src, dst);
1345 case PIPE_LOGICOP_EQUIV:
1346 return qir_NOT(c, qir_XOR(c, src, dst));
1347 case PIPE_LOGICOP_NOOP:
1348 return dst;
1349 case PIPE_LOGICOP_OR_INVERTED:
1350 return qir_OR(c, qir_NOT(c, src), dst);
1351 case PIPE_LOGICOP_OR_REVERSE:
1352 return qir_OR(c, src, qir_NOT(c, dst));
1353 case PIPE_LOGICOP_OR:
1354 return qir_OR(c, src, dst);
1355 case PIPE_LOGICOP_SET:
1356 return qir_uniform_ui(c, ~0);
1357 case PIPE_LOGICOP_COPY:
1358 default:
1359 return src;
1360 }
1361 }
1362
1363 static void
1364 emit_frag_end(struct vc4_compile *c)
1365 {
1366 clip_distance_discard(c);
1367 alpha_test_discard(c);
1368
1369 enum pipe_format color_format = c->fs_key->color_format;
1370 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1371 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1372 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1373 struct qreg linear_dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1374 struct qreg packed_dst_color = c->undef;
1375
1376 if (c->fs_key->blend.blend_enable ||
1377 c->fs_key->blend.colormask != 0xf ||
1378 c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {
1379 struct qreg r4 = qir_TLB_COLOR_READ(c);
1380 for (int i = 0; i < 4; i++)
1381 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1382 for (int i = 0; i < 4; i++) {
1383 dst_color[i] = get_swizzled_channel(c,
1384 tlb_read_color,
1385 format_swiz[i]);
1386 if (util_format_is_srgb(color_format) && i != 3) {
1387 linear_dst_color[i] =
1388 qir_srgb_decode(c, dst_color[i]);
1389 } else {
1390 linear_dst_color[i] = dst_color[i];
1391 }
1392 }
1393
1394 /* Save the packed value for logic ops. Can't reuse r4
1395 * becuase other things might smash it (like sRGB)
1396 */
1397 packed_dst_color = qir_MOV(c, r4);
1398 }
1399
1400 struct qreg blend_color[4];
1401 struct qreg undef_array[4] = {
1402 c->undef, c->undef, c->undef, c->undef
1403 };
1404 vc4_blend(c, blend_color, linear_dst_color,
1405 (c->output_color_index != -1 ?
1406 c->outputs + c->output_color_index :
1407 undef_array));
1408
1409 if (util_format_is_srgb(color_format)) {
1410 for (int i = 0; i < 3; i++)
1411 blend_color[i] = qir_srgb_encode(c, blend_color[i]);
1412 }
1413
1414 /* Debug: Sometimes you're getting a black output and just want to see
1415 * if the FS is getting executed at all. Spam magenta into the color
1416 * output.
1417 */
1418 if (0) {
1419 blend_color[0] = qir_uniform_f(c, 1.0);
1420 blend_color[1] = qir_uniform_f(c, 0.0);
1421 blend_color[2] = qir_uniform_f(c, 1.0);
1422 blend_color[3] = qir_uniform_f(c, 0.5);
1423 }
1424
1425 struct qreg swizzled_outputs[4];
1426 for (int i = 0; i < 4; i++) {
1427 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1428 format_swiz[i]);
1429 }
1430
1431 if (c->discard.file != QFILE_NULL)
1432 qir_TLB_DISCARD_SETUP(c, c->discard);
1433
1434 if (c->fs_key->stencil_enabled) {
1435 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 0));
1436 if (c->fs_key->stencil_twoside) {
1437 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 1));
1438 }
1439 if (c->fs_key->stencil_full_writemasks) {
1440 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 2));
1441 }
1442 }
1443
1444 if (c->fs_key->depth_enabled) {
1445 struct qreg z;
1446 if (c->output_position_index != -1) {
1447 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1448 qir_uniform_f(c, 0xffffff)));
1449 } else {
1450 z = qir_FRAG_Z(c);
1451 }
1452 qir_TLB_Z_WRITE(c, z);
1453 }
1454
1455 struct qreg packed_color = c->undef;
1456 for (int i = 0; i < 4; i++) {
1457 if (swizzled_outputs[i].file == QFILE_NULL)
1458 continue;
1459 if (packed_color.file == QFILE_NULL) {
1460 packed_color = qir_PACK_8888_F(c, swizzled_outputs[i]);
1461 } else {
1462 packed_color = qir_PACK_8_F(c,
1463 packed_color,
1464 swizzled_outputs[i],
1465 i);
1466 }
1467 }
1468
1469 if (packed_color.file == QFILE_NULL)
1470 packed_color = qir_uniform_ui(c, 0);
1471
1472 if (c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {
1473 packed_color = vc4_logicop(c, packed_color, packed_dst_color);
1474 }
1475
1476 /* If the bit isn't set in the color mask, then just return the
1477 * original dst color, instead.
1478 */
1479 uint32_t colormask = 0xffffffff;
1480 for (int i = 0; i < 4; i++) {
1481 if (format_swiz[i] < 4 &&
1482 !(c->fs_key->blend.colormask & (1 << format_swiz[i]))) {
1483 colormask &= ~(0xff << (i * 8));
1484 }
1485 }
1486 if (colormask != 0xffffffff) {
1487 packed_color = qir_OR(c,
1488 qir_AND(c, packed_color,
1489 qir_uniform_ui(c, colormask)),
1490 qir_AND(c, packed_dst_color,
1491 qir_uniform_ui(c, ~colormask)));
1492 }
1493
1494 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1495 packed_color, c->undef));
1496 }
1497
1498 static void
1499 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1500 {
1501 struct qreg xyi[2];
1502
1503 for (int i = 0; i < 2; i++) {
1504 struct qreg scale =
1505 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1506
1507 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1508 qir_FMUL(c,
1509 c->outputs[c->output_position_index + i],
1510 scale),
1511 rcp_w));
1512 }
1513
1514 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1515 }
1516
1517 static void
1518 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1519 {
1520 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1521 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1522
1523 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1524 c->outputs[c->output_position_index + 2],
1525 zscale),
1526 rcp_w),
1527 zoffset));
1528 }
1529
1530 static void
1531 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1532 {
1533 qir_VPM_WRITE(c, rcp_w);
1534 }
1535
1536 static void
1537 emit_point_size_write(struct vc4_compile *c)
1538 {
1539 struct qreg point_size;
1540
1541 if (c->output_point_size_index != -1)
1542 point_size = c->outputs[c->output_point_size_index + 3];
1543 else
1544 point_size = qir_uniform_f(c, 1.0);
1545
1546 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1547 * BCM21553).
1548 */
1549 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1550
1551 qir_VPM_WRITE(c, point_size);
1552 }
1553
1554 /**
1555 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1556 *
1557 * The simulator insists that there be at least one vertex attribute, so
1558 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1559 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1560 * to consume it here.
1561 */
1562 static void
1563 emit_stub_vpm_read(struct vc4_compile *c)
1564 {
1565 if (c->num_inputs)
1566 return;
1567
1568 c->vattr_sizes[0] = 4;
1569 struct qreg vpm = { QFILE_VPM, 0 };
1570 (void)qir_MOV(c, vpm);
1571 c->num_inputs++;
1572 }
1573
1574 static void
1575 emit_ucp_clipdistance(struct vc4_compile *c)
1576 {
1577 unsigned cv;
1578 if (c->output_clipvertex_index != -1)
1579 cv = c->output_clipvertex_index;
1580 else if (c->output_position_index != -1)
1581 cv = c->output_position_index;
1582 else
1583 return;
1584
1585 for (int plane = 0; plane < PIPE_MAX_CLIP_PLANES; plane++) {
1586 if (!(c->key->ucp_enables & (1 << plane)))
1587 continue;
1588
1589 /* Pick the next outputs[] that hasn't been written to, since
1590 * there are no other program writes left to be processed at
1591 * this point. If something had been declared but not written
1592 * (like a w component), we'll just smash over the top of it.
1593 */
1594 uint32_t output_index = c->num_outputs++;
1595 add_output(c, output_index,
1596 TGSI_SEMANTIC_CLIPDIST,
1597 plane,
1598 TGSI_SWIZZLE_X);
1599
1600
1601 struct qreg dist = qir_uniform_f(c, 0.0);
1602 for (int i = 0; i < 4; i++) {
1603 struct qreg pos_chan = c->outputs[cv + i];
1604 struct qreg ucp =
1605 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1606 plane * 4 + i);
1607 dist = qir_FADD(c, dist, qir_FMUL(c, pos_chan, ucp));
1608 }
1609
1610 c->outputs[output_index] = dist;
1611 }
1612 }
1613
1614 static void
1615 emit_vert_end(struct vc4_compile *c,
1616 struct vc4_varying_semantic *fs_inputs,
1617 uint32_t num_fs_inputs)
1618 {
1619 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1620
1621 emit_stub_vpm_read(c);
1622 emit_ucp_clipdistance(c);
1623
1624 emit_scaled_viewport_write(c, rcp_w);
1625 emit_zs_write(c, rcp_w);
1626 emit_rcp_wc_write(c, rcp_w);
1627 if (c->vs_key->per_vertex_point_size)
1628 emit_point_size_write(c);
1629
1630 for (int i = 0; i < num_fs_inputs; i++) {
1631 struct vc4_varying_semantic *input = &fs_inputs[i];
1632 int j;
1633
1634 for (j = 0; j < c->num_outputs; j++) {
1635 struct vc4_varying_semantic *output =
1636 &c->output_semantics[j];
1637
1638 if (input->semantic == output->semantic &&
1639 input->index == output->index &&
1640 input->swizzle == output->swizzle) {
1641 qir_VPM_WRITE(c, c->outputs[j]);
1642 break;
1643 }
1644 }
1645 /* Emit padding if we didn't find a declared VS output for
1646 * this FS input.
1647 */
1648 if (j == c->num_outputs)
1649 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1650 }
1651 }
1652
1653 static void
1654 emit_coord_end(struct vc4_compile *c)
1655 {
1656 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1657
1658 emit_stub_vpm_read(c);
1659
1660 for (int i = 0; i < 4; i++)
1661 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1662
1663 emit_scaled_viewport_write(c, rcp_w);
1664 emit_zs_write(c, rcp_w);
1665 emit_rcp_wc_write(c, rcp_w);
1666 if (c->vs_key->per_vertex_point_size)
1667 emit_point_size_write(c);
1668 }
1669
1670 static void
1671 vc4_optimize_nir(struct nir_shader *s)
1672 {
1673 bool progress;
1674
1675 do {
1676 progress = false;
1677
1678 nir_lower_vars_to_ssa(s);
1679 nir_lower_alu_to_scalar(s);
1680
1681 progress = nir_copy_prop(s) || progress;
1682 progress = nir_opt_dce(s) || progress;
1683 progress = nir_opt_cse(s) || progress;
1684 progress = nir_opt_peephole_select(s) || progress;
1685 progress = nir_opt_algebraic(s) || progress;
1686 progress = nir_opt_constant_folding(s) || progress;
1687 } while (progress);
1688 }
1689
1690 static int
1691 driver_location_compare(const void *in_a, const void *in_b)
1692 {
1693 const nir_variable *const *a = in_a;
1694 const nir_variable *const *b = in_b;
1695
1696 return (*a)->data.driver_location - (*b)->data.driver_location;
1697 }
1698
1699 static void
1700 ntq_setup_inputs(struct vc4_compile *c)
1701 {
1702 unsigned num_entries = 0;
1703 foreach_list_typed(nir_variable, var, node, &c->s->inputs)
1704 num_entries++;
1705
1706 nir_variable *vars[num_entries];
1707
1708 unsigned i = 0;
1709 foreach_list_typed(nir_variable, var, node, &c->s->inputs)
1710 vars[i++] = var;
1711
1712 /* Sort the variables so that we emit the input setup in
1713 * driver_location order. This is required for VPM reads, whose data
1714 * is fetched into the VPM in driver_location (TGSI register index)
1715 * order.
1716 */
1717 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1718
1719 for (unsigned i = 0; i < num_entries; i++) {
1720 nir_variable *var = vars[i];
1721 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1722 /* XXX: map loc slots to semantics */
1723 unsigned semantic_name = var->data.location;
1724 unsigned semantic_index = var->data.index;
1725 unsigned loc = var->data.driver_location;
1726
1727 assert(array_len == 1);
1728 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1729 (loc + 1) * 4);
1730
1731 if (c->stage == QSTAGE_FRAG) {
1732 if (semantic_name == TGSI_SEMANTIC_POSITION) {
1733 emit_fragcoord_input(c, loc);
1734 } else if (semantic_name == TGSI_SEMANTIC_FACE) {
1735 emit_face_input(c, loc);
1736 } else if (semantic_name == TGSI_SEMANTIC_GENERIC &&
1737 (c->fs_key->point_sprite_mask &
1738 (1 << semantic_index))) {
1739 emit_point_coord_input(c, loc);
1740 } else {
1741 emit_fragment_input(c, loc,
1742 semantic_name,
1743 semantic_index);
1744 }
1745 } else {
1746 emit_vertex_input(c, loc);
1747 }
1748 }
1749 }
1750
1751 static void
1752 ntq_setup_outputs(struct vc4_compile *c)
1753 {
1754 foreach_list_typed(nir_variable, var, node, &c->s->outputs) {
1755 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1756 /* XXX: map loc slots to semantics */
1757 unsigned semantic_name = var->data.location;
1758 unsigned semantic_index = var->data.index;
1759 unsigned loc = var->data.driver_location * 4;
1760
1761 assert(array_len == 1);
1762
1763 for (int i = 0; i < 4; i++) {
1764 add_output(c,
1765 loc + i,
1766 semantic_name,
1767 semantic_index,
1768 i);
1769 }
1770
1771 switch (semantic_name) {
1772 case TGSI_SEMANTIC_POSITION:
1773 c->output_position_index = loc;
1774 break;
1775 case TGSI_SEMANTIC_CLIPVERTEX:
1776 c->output_clipvertex_index = loc;
1777 break;
1778 case TGSI_SEMANTIC_COLOR:
1779 c->output_color_index = loc;
1780 break;
1781 case TGSI_SEMANTIC_PSIZE:
1782 c->output_point_size_index = loc;
1783 break;
1784 }
1785
1786 }
1787 }
1788
1789 static void
1790 ntq_setup_uniforms(struct vc4_compile *c)
1791 {
1792 foreach_list_typed(nir_variable, var, node, &c->s->uniforms) {
1793 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1794 unsigned array_elem_size = 4 * sizeof(float);
1795
1796 declare_uniform_range(c, var->data.driver_location * array_elem_size,
1797 array_len * array_elem_size);
1798
1799 }
1800 }
1801
1802 /**
1803 * Sets up the mapping from nir_register to struct qreg *.
1804 *
1805 * Each nir_register gets a struct qreg per 32-bit component being stored.
1806 */
1807 static void
1808 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1809 {
1810 foreach_list_typed(nir_register, nir_reg, node, list) {
1811 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1812 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1813 array_len *
1814 nir_reg->num_components);
1815
1816 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1817
1818 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1819 qregs[i] = qir_uniform_ui(c, 0);
1820 }
1821 }
1822
1823 static void
1824 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1825 {
1826 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1827 instr->def.num_components);
1828 for (int i = 0; i < instr->def.num_components; i++)
1829 qregs[i] = qir_uniform_ui(c, instr->value.u[i]);
1830
1831 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1832 }
1833
1834 static void
1835 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1836 {
1837 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
1838 struct qreg *dest = NULL;
1839
1840 if (info->has_dest) {
1841 dest = ntq_get_dest(c, instr->dest);
1842 }
1843
1844 switch (instr->intrinsic) {
1845 case nir_intrinsic_load_uniform:
1846 assert(instr->const_index[1] == 1);
1847
1848 for (int i = 0; i < instr->num_components; i++) {
1849 dest[i] = qir_uniform(c, QUNIFORM_UNIFORM,
1850 instr->const_index[0] * 4 + i);
1851 }
1852 break;
1853
1854 case nir_intrinsic_load_uniform_indirect:
1855 assert(instr->const_index[1] == 1);
1856
1857 for (int i = 0; i < instr->num_components; i++) {
1858 dest[i] = indirect_uniform_load(c,
1859 ntq_get_src(c, instr->src[0], 0),
1860 (instr->const_index[0] *
1861 4 + i) * sizeof(float));
1862 }
1863
1864 break;
1865
1866 case nir_intrinsic_load_input:
1867 assert(instr->const_index[1] == 1);
1868
1869 for (int i = 0; i < instr->num_components; i++)
1870 dest[i] = c->inputs[instr->const_index[0] * 4 + i];
1871
1872 break;
1873
1874 case nir_intrinsic_store_output:
1875 for (int i = 0; i < instr->num_components; i++) {
1876 c->outputs[instr->const_index[0] * 4 + i] =
1877 qir_MOV(c, ntq_get_src(c, instr->src[0], i));
1878 }
1879 c->num_outputs = MAX2(c->num_outputs,
1880 instr->const_index[0] * 4 +
1881 instr->num_components + 1);
1882 break;
1883
1884 case nir_intrinsic_discard:
1885 c->discard = qir_uniform_ui(c, ~0);
1886 break;
1887
1888 case nir_intrinsic_discard_if:
1889 if (c->discard.file == QFILE_NULL)
1890 c->discard = qir_uniform_ui(c, 0);
1891 c->discard = qir_OR(c, c->discard,
1892 ntq_get_src(c, instr->src[0], 0));
1893 break;
1894
1895 default:
1896 fprintf(stderr, "Unknown intrinsic: ");
1897 nir_print_instr(&instr->instr, stderr);
1898 fprintf(stderr, "\n");
1899 break;
1900 }
1901 }
1902
1903 static void
1904 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1905 {
1906 fprintf(stderr, "general IF statements not handled.\n");
1907 }
1908
1909 static void
1910 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
1911 {
1912 switch (instr->type) {
1913 case nir_instr_type_alu:
1914 ntq_emit_alu(c, nir_instr_as_alu(instr));
1915 break;
1916
1917 case nir_instr_type_intrinsic:
1918 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1919 break;
1920
1921 case nir_instr_type_load_const:
1922 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1923 break;
1924
1925 case nir_instr_type_tex:
1926 ntq_emit_tex(c, nir_instr_as_tex(instr));
1927 break;
1928
1929 default:
1930 fprintf(stderr, "Unknown NIR instr type: ");
1931 nir_print_instr(instr, stderr);
1932 fprintf(stderr, "\n");
1933 abort();
1934 }
1935 }
1936
1937 static void
1938 ntq_emit_block(struct vc4_compile *c, nir_block *block)
1939 {
1940 nir_foreach_instr(block, instr) {
1941 ntq_emit_instr(c, instr);
1942 }
1943 }
1944
1945 static void
1946 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
1947 {
1948 foreach_list_typed(nir_cf_node, node, node, list) {
1949 switch (node->type) {
1950 /* case nir_cf_node_loop: */
1951 case nir_cf_node_block:
1952 ntq_emit_block(c, nir_cf_node_as_block(node));
1953 break;
1954
1955 case nir_cf_node_if:
1956 ntq_emit_if(c, nir_cf_node_as_if(node));
1957 break;
1958
1959 default:
1960 assert(0);
1961 }
1962 }
1963 }
1964
1965 static void
1966 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
1967 {
1968 ntq_setup_registers(c, &impl->registers);
1969 ntq_emit_cf_list(c, &impl->body);
1970 }
1971
1972 static void
1973 nir_to_qir(struct vc4_compile *c)
1974 {
1975 ntq_setup_inputs(c);
1976 ntq_setup_outputs(c);
1977 ntq_setup_uniforms(c);
1978 ntq_setup_registers(c, &c->s->registers);
1979
1980 /* Find the main function and emit the body. */
1981 nir_foreach_overload(c->s, overload) {
1982 assert(strcmp(overload->function->name, "main") == 0);
1983 assert(overload->impl);
1984 ntq_emit_impl(c, overload->impl);
1985 }
1986 }
1987
1988 static const nir_shader_compiler_options nir_options = {
1989 .lower_ffma = true,
1990 .lower_flrp = true,
1991 .lower_fpow = true,
1992 .lower_fsat = true,
1993 .lower_fsqrt = true,
1994 .lower_negate = true,
1995 };
1996
1997 static bool
1998 count_nir_instrs_in_block(nir_block *block, void *state)
1999 {
2000 int *count = (int *) state;
2001 nir_foreach_instr(block, instr) {
2002 *count = *count + 1;
2003 }
2004 return true;
2005 }
2006
2007 static int
2008 count_nir_instrs(nir_shader *nir)
2009 {
2010 int count = 0;
2011 nir_foreach_overload(nir, overload) {
2012 if (!overload->impl)
2013 continue;
2014 nir_foreach_block(overload->impl, count_nir_instrs_in_block, &count);
2015 }
2016 return count;
2017 }
2018
2019 static struct vc4_compile *
2020 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
2021 struct vc4_key *key)
2022 {
2023 struct vc4_compile *c = qir_compile_init();
2024
2025 c->stage = stage;
2026 c->shader_state = &key->shader_state->base;
2027 c->program_id = key->shader_state->program_id;
2028 c->variant_id = key->shader_state->compiled_variant_count++;
2029
2030 c->key = key;
2031 switch (stage) {
2032 case QSTAGE_FRAG:
2033 c->fs_key = (struct vc4_fs_key *)key;
2034 if (c->fs_key->is_points) {
2035 c->point_x = emit_fragment_varying(c, ~0, ~0, 0);
2036 c->point_y = emit_fragment_varying(c, ~0, ~0, 0);
2037 } else if (c->fs_key->is_lines) {
2038 c->line_x = emit_fragment_varying(c, ~0, ~0, 0);
2039 }
2040 break;
2041 case QSTAGE_VERT:
2042 c->vs_key = (struct vc4_vs_key *)key;
2043 break;
2044 case QSTAGE_COORD:
2045 c->vs_key = (struct vc4_vs_key *)key;
2046 break;
2047 }
2048
2049 const struct tgsi_token *tokens = key->shader_state->base.tokens;
2050 if (c->fs_key && c->fs_key->light_twoside) {
2051 if (!key->shader_state->twoside_tokens) {
2052 const struct tgsi_lowering_config lowering_config = {
2053 .color_two_side = true,
2054 };
2055 struct tgsi_shader_info info;
2056 key->shader_state->twoside_tokens =
2057 tgsi_transform_lowering(&lowering_config,
2058 key->shader_state->base.tokens,
2059 &info);
2060
2061 /* If no transformation occurred, then NULL is
2062 * returned and we just use our original tokens.
2063 */
2064 if (!key->shader_state->twoside_tokens) {
2065 key->shader_state->twoside_tokens =
2066 key->shader_state->base.tokens;
2067 }
2068 }
2069 tokens = key->shader_state->twoside_tokens;
2070 }
2071
2072 if (vc4_debug & VC4_DEBUG_TGSI) {
2073 fprintf(stderr, "%s prog %d/%d TGSI:\n",
2074 qir_get_stage_name(c->stage),
2075 c->program_id, c->variant_id);
2076 tgsi_dump(tokens, 0);
2077 }
2078
2079 c->s = tgsi_to_nir(tokens, &nir_options);
2080 nir_opt_global_to_local(c->s);
2081 nir_convert_to_ssa(c->s);
2082
2083 vc4_optimize_nir(c->s);
2084
2085 nir_remove_dead_variables(c->s);
2086
2087 nir_convert_from_ssa(c->s);
2088
2089 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2090 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2091 qir_get_stage_name(c->stage),
2092 c->program_id, c->variant_id,
2093 count_nir_instrs(c->s));
2094 }
2095
2096 if (vc4_debug & VC4_DEBUG_NIR) {
2097 fprintf(stderr, "%s prog %d/%d NIR:\n",
2098 qir_get_stage_name(c->stage),
2099 c->program_id, c->variant_id);
2100 nir_print_shader(c->s, stderr);
2101 }
2102
2103 nir_to_qir(c);
2104
2105 switch (stage) {
2106 case QSTAGE_FRAG:
2107 emit_frag_end(c);
2108 break;
2109 case QSTAGE_VERT:
2110 emit_vert_end(c,
2111 vc4->prog.fs->input_semantics,
2112 vc4->prog.fs->num_inputs);
2113 break;
2114 case QSTAGE_COORD:
2115 emit_coord_end(c);
2116 break;
2117 }
2118
2119 if (vc4_debug & VC4_DEBUG_QIR) {
2120 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
2121 qir_get_stage_name(c->stage),
2122 c->program_id, c->variant_id);
2123 qir_dump(c);
2124 }
2125
2126 qir_optimize(c);
2127 qir_lower_uniforms(c);
2128
2129 if (vc4_debug & VC4_DEBUG_QIR) {
2130 fprintf(stderr, "%s prog %d/%d QIR:\n",
2131 qir_get_stage_name(c->stage),
2132 c->program_id, c->variant_id);
2133 qir_dump(c);
2134 }
2135 qir_reorder_uniforms(c);
2136 vc4_generate_code(vc4, c);
2137
2138 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2139 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2140 qir_get_stage_name(c->stage),
2141 c->program_id, c->variant_id,
2142 c->qpu_inst_count);
2143 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2144 qir_get_stage_name(c->stage),
2145 c->program_id, c->variant_id,
2146 c->num_uniforms);
2147 }
2148
2149 ralloc_free(c->s);
2150
2151 return c;
2152 }
2153
2154 static void *
2155 vc4_shader_state_create(struct pipe_context *pctx,
2156 const struct pipe_shader_state *cso)
2157 {
2158 struct vc4_context *vc4 = vc4_context(pctx);
2159 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2160 if (!so)
2161 return NULL;
2162
2163 so->base.tokens = tgsi_dup_tokens(cso->tokens);
2164 so->program_id = vc4->next_uncompiled_program_id++;
2165
2166 return so;
2167 }
2168
2169 static void
2170 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2171 struct vc4_compile *c)
2172 {
2173 int count = c->num_uniforms;
2174 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2175
2176 uinfo->count = count;
2177 uinfo->data = ralloc_array(shader, uint32_t, count);
2178 memcpy(uinfo->data, c->uniform_data,
2179 count * sizeof(*uinfo->data));
2180 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2181 memcpy(uinfo->contents, c->uniform_contents,
2182 count * sizeof(*uinfo->contents));
2183 uinfo->num_texture_samples = c->num_texture_samples;
2184 }
2185
2186 static struct vc4_compiled_shader *
2187 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2188 struct vc4_key *key)
2189 {
2190 struct hash_table *ht;
2191 uint32_t key_size;
2192 if (stage == QSTAGE_FRAG) {
2193 ht = vc4->fs_cache;
2194 key_size = sizeof(struct vc4_fs_key);
2195 } else {
2196 ht = vc4->vs_cache;
2197 key_size = sizeof(struct vc4_vs_key);
2198 }
2199
2200 struct vc4_compiled_shader *shader;
2201 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2202 if (entry)
2203 return entry->data;
2204
2205 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key);
2206 shader = rzalloc(NULL, struct vc4_compiled_shader);
2207
2208 shader->program_id = vc4->next_compiled_program_id++;
2209 if (stage == QSTAGE_FRAG) {
2210 bool input_live[c->num_input_semantics];
2211 struct simple_node *node;
2212
2213 memset(input_live, 0, sizeof(input_live));
2214 foreach(node, &c->instructions) {
2215 struct qinst *inst = (struct qinst *)node;
2216 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
2217 if (inst->src[i].file == QFILE_VARY)
2218 input_live[inst->src[i].index] = true;
2219 }
2220 }
2221
2222 shader->input_semantics = ralloc_array(shader,
2223 struct vc4_varying_semantic,
2224 c->num_input_semantics);
2225
2226 for (int i = 0; i < c->num_input_semantics; i++) {
2227 struct vc4_varying_semantic *sem = &c->input_semantics[i];
2228
2229 if (!input_live[i])
2230 continue;
2231
2232 /* Skip non-VS-output inputs. */
2233 if (sem->semantic == (uint8_t)~0)
2234 continue;
2235
2236 if (sem->semantic == TGSI_SEMANTIC_COLOR ||
2237 sem->semantic == TGSI_SEMANTIC_BCOLOR) {
2238 shader->color_inputs |= (1 << shader->num_inputs);
2239 }
2240
2241 shader->input_semantics[shader->num_inputs] = *sem;
2242 shader->num_inputs++;
2243 }
2244 } else {
2245 shader->num_inputs = c->num_inputs;
2246
2247 shader->vattr_offsets[0] = 0;
2248 for (int i = 0; i < 8; i++) {
2249 shader->vattr_offsets[i + 1] =
2250 shader->vattr_offsets[i] + c->vattr_sizes[i];
2251
2252 if (c->vattr_sizes[i])
2253 shader->vattrs_live |= (1 << i);
2254 }
2255 }
2256
2257 copy_uniform_state_to_shader(shader, c);
2258 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
2259 c->qpu_inst_count * sizeof(uint64_t),
2260 "code");
2261
2262 /* Copy the compiler UBO range state to the compiled shader, dropping
2263 * out arrays that were never referenced by an indirect load.
2264 *
2265 * (Note that QIR dead code elimination of an array access still
2266 * leaves that array alive, though)
2267 */
2268 if (c->num_ubo_ranges) {
2269 shader->num_ubo_ranges = c->num_ubo_ranges;
2270 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2271 c->num_ubo_ranges);
2272 uint32_t j = 0;
2273 for (int i = 0; i < c->num_uniform_ranges; i++) {
2274 struct vc4_compiler_ubo_range *range =
2275 &c->ubo_ranges[i];
2276 if (!range->used)
2277 continue;
2278
2279 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2280 shader->ubo_ranges[j].src_offset = range->src_offset;
2281 shader->ubo_ranges[j].size = range->size;
2282 shader->ubo_size += c->ubo_ranges[i].size;
2283 j++;
2284 }
2285 }
2286 if (shader->ubo_size) {
2287 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2288 qir_get_stage_name(c->stage),
2289 c->program_id, c->variant_id,
2290 shader->ubo_size / 4);
2291 }
2292
2293 qir_compile_destroy(c);
2294
2295 struct vc4_key *dup_key;
2296 dup_key = ralloc_size(shader, key_size);
2297 memcpy(dup_key, key, key_size);
2298 _mesa_hash_table_insert(ht, dup_key, shader);
2299
2300 return shader;
2301 }
2302
2303 static void
2304 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2305 struct vc4_texture_stateobj *texstate)
2306 {
2307 for (int i = 0; i < texstate->num_textures; i++) {
2308 struct pipe_sampler_view *sampler = texstate->textures[i];
2309 struct pipe_sampler_state *sampler_state =
2310 texstate->samplers[i];
2311
2312 if (sampler) {
2313 key->tex[i].format = sampler->format;
2314 key->tex[i].swizzle[0] = sampler->swizzle_r;
2315 key->tex[i].swizzle[1] = sampler->swizzle_g;
2316 key->tex[i].swizzle[2] = sampler->swizzle_b;
2317 key->tex[i].swizzle[3] = sampler->swizzle_a;
2318 key->tex[i].compare_mode = sampler_state->compare_mode;
2319 key->tex[i].compare_func = sampler_state->compare_func;
2320 key->tex[i].wrap_s = sampler_state->wrap_s;
2321 key->tex[i].wrap_t = sampler_state->wrap_t;
2322 }
2323 }
2324
2325 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2326 }
2327
2328 static void
2329 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2330 {
2331 struct vc4_fs_key local_key;
2332 struct vc4_fs_key *key = &local_key;
2333
2334 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2335 VC4_DIRTY_BLEND |
2336 VC4_DIRTY_FRAMEBUFFER |
2337 VC4_DIRTY_ZSA |
2338 VC4_DIRTY_RASTERIZER |
2339 VC4_DIRTY_FRAGTEX |
2340 VC4_DIRTY_TEXSTATE |
2341 VC4_DIRTY_UNCOMPILED_FS))) {
2342 return;
2343 }
2344
2345 memset(key, 0, sizeof(*key));
2346 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2347 key->base.shader_state = vc4->prog.bind_fs;
2348 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2349 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2350 prim_mode <= PIPE_PRIM_LINE_STRIP);
2351 key->blend = vc4->blend->rt[0];
2352 if (vc4->blend->logicop_enable) {
2353 key->logicop_func = vc4->blend->logicop_func;
2354 } else {
2355 key->logicop_func = PIPE_LOGICOP_COPY;
2356 }
2357 if (vc4->framebuffer.cbufs[0])
2358 key->color_format = vc4->framebuffer.cbufs[0]->format;
2359
2360 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2361 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2362 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2363 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2364 key->stencil_enabled);
2365 if (vc4->zsa->base.alpha.enabled) {
2366 key->alpha_test = true;
2367 key->alpha_test_func = vc4->zsa->base.alpha.func;
2368 }
2369
2370 if (key->is_points) {
2371 key->point_sprite_mask =
2372 vc4->rasterizer->base.sprite_coord_enable;
2373 key->point_coord_upper_left =
2374 (vc4->rasterizer->base.sprite_coord_mode ==
2375 PIPE_SPRITE_COORD_UPPER_LEFT);
2376 }
2377
2378 key->light_twoside = vc4->rasterizer->base.light_twoside;
2379
2380 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2381 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2382 if (vc4->prog.fs == old_fs)
2383 return;
2384
2385 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2386 if (vc4->rasterizer->base.flatshade &&
2387 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2388 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2389 }
2390 }
2391
2392 static void
2393 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2394 {
2395 struct vc4_vs_key local_key;
2396 struct vc4_vs_key *key = &local_key;
2397
2398 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2399 VC4_DIRTY_RASTERIZER |
2400 VC4_DIRTY_VERTTEX |
2401 VC4_DIRTY_TEXSTATE |
2402 VC4_DIRTY_VTXSTATE |
2403 VC4_DIRTY_UNCOMPILED_VS |
2404 VC4_DIRTY_COMPILED_FS))) {
2405 return;
2406 }
2407
2408 memset(key, 0, sizeof(*key));
2409 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2410 key->base.shader_state = vc4->prog.bind_vs;
2411 key->compiled_fs_id = vc4->prog.fs->program_id;
2412
2413 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2414 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2415
2416 key->per_vertex_point_size =
2417 (prim_mode == PIPE_PRIM_POINTS &&
2418 vc4->rasterizer->base.point_size_per_vertex);
2419
2420 vc4->prog.vs = vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2421 key->is_coord = true;
2422 vc4->prog.cs = vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2423 }
2424
2425 void
2426 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2427 {
2428 vc4_update_compiled_fs(vc4, prim_mode);
2429 vc4_update_compiled_vs(vc4, prim_mode);
2430 }
2431
2432 static uint32_t
2433 fs_cache_hash(const void *key)
2434 {
2435 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2436 }
2437
2438 static uint32_t
2439 vs_cache_hash(const void *key)
2440 {
2441 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2442 }
2443
2444 static bool
2445 fs_cache_compare(const void *key1, const void *key2)
2446 {
2447 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2448 }
2449
2450 static bool
2451 vs_cache_compare(const void *key1, const void *key2)
2452 {
2453 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2454 }
2455
2456 static void
2457 delete_from_cache_if_matches(struct hash_table *ht,
2458 struct hash_entry *entry,
2459 struct vc4_uncompiled_shader *so)
2460 {
2461 const struct vc4_key *key = entry->key;
2462
2463 if (key->shader_state == so) {
2464 struct vc4_compiled_shader *shader = entry->data;
2465 _mesa_hash_table_remove(ht, entry);
2466 vc4_bo_unreference(&shader->bo);
2467 ralloc_free(shader);
2468 }
2469 }
2470
2471 static void
2472 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2473 {
2474 struct vc4_context *vc4 = vc4_context(pctx);
2475 struct vc4_uncompiled_shader *so = hwcso;
2476
2477 struct hash_entry *entry;
2478 hash_table_foreach(vc4->fs_cache, entry)
2479 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2480 hash_table_foreach(vc4->vs_cache, entry)
2481 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2482
2483 if (so->twoside_tokens != so->base.tokens)
2484 free((void *)so->twoside_tokens);
2485 free((void *)so->base.tokens);
2486 free(so);
2487 }
2488
2489 static uint32_t translate_wrap(uint32_t p_wrap, bool using_nearest)
2490 {
2491 switch (p_wrap) {
2492 case PIPE_TEX_WRAP_REPEAT:
2493 return 0;
2494 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2495 return 1;
2496 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2497 return 2;
2498 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2499 return 3;
2500 case PIPE_TEX_WRAP_CLAMP:
2501 return (using_nearest ? 1 : 3);
2502 default:
2503 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
2504 assert(!"not reached");
2505 return 0;
2506 }
2507 }
2508
2509 static void
2510 write_texture_p0(struct vc4_context *vc4,
2511 struct vc4_texture_stateobj *texstate,
2512 uint32_t unit)
2513 {
2514 struct pipe_sampler_view *texture = texstate->textures[unit];
2515 struct vc4_resource *rsc = vc4_resource(texture->texture);
2516
2517 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
2518 VC4_SET_FIELD(rsc->slices[0].offset >> 12, VC4_TEX_P0_OFFSET) |
2519 VC4_SET_FIELD(texture->u.tex.last_level -
2520 texture->u.tex.first_level, VC4_TEX_P0_MIPLVLS) |
2521 VC4_SET_FIELD(texture->target == PIPE_TEXTURE_CUBE,
2522 VC4_TEX_P0_CMMODE) |
2523 VC4_SET_FIELD(rsc->vc4_format & 15, VC4_TEX_P0_TYPE));
2524 }
2525
2526 static void
2527 write_texture_p1(struct vc4_context *vc4,
2528 struct vc4_texture_stateobj *texstate,
2529 uint32_t unit)
2530 {
2531 struct pipe_sampler_view *texture = texstate->textures[unit];
2532 struct vc4_resource *rsc = vc4_resource(texture->texture);
2533 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2534 static const uint8_t minfilter_map[6] = {
2535 VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR,
2536 VC4_TEX_P1_MINFILT_LIN_MIP_NEAR,
2537 VC4_TEX_P1_MINFILT_NEAR_MIP_LIN,
2538 VC4_TEX_P1_MINFILT_LIN_MIP_LIN,
2539 VC4_TEX_P1_MINFILT_NEAREST,
2540 VC4_TEX_P1_MINFILT_LINEAR,
2541 };
2542 static const uint32_t magfilter_map[] = {
2543 [PIPE_TEX_FILTER_NEAREST] = VC4_TEX_P1_MAGFILT_NEAREST,
2544 [PIPE_TEX_FILTER_LINEAR] = VC4_TEX_P1_MAGFILT_LINEAR,
2545 };
2546
2547 bool either_nearest =
2548 (sampler->mag_img_filter == PIPE_TEX_MIPFILTER_NEAREST ||
2549 sampler->min_img_filter == PIPE_TEX_MIPFILTER_NEAREST);
2550
2551 cl_aligned_u32(&vc4->uniforms,
2552 VC4_SET_FIELD(rsc->vc4_format >> 4, VC4_TEX_P1_TYPE4) |
2553 VC4_SET_FIELD(texture->texture->height0 & 2047,
2554 VC4_TEX_P1_HEIGHT) |
2555 VC4_SET_FIELD(texture->texture->width0 & 2047,
2556 VC4_TEX_P1_WIDTH) |
2557 VC4_SET_FIELD(magfilter_map[sampler->mag_img_filter],
2558 VC4_TEX_P1_MAGFILT) |
2559 VC4_SET_FIELD(minfilter_map[sampler->min_mip_filter * 2 +
2560 sampler->min_img_filter],
2561 VC4_TEX_P1_MINFILT) |
2562 VC4_SET_FIELD(translate_wrap(sampler->wrap_s, either_nearest),
2563 VC4_TEX_P1_WRAP_S) |
2564 VC4_SET_FIELD(translate_wrap(sampler->wrap_t, either_nearest),
2565 VC4_TEX_P1_WRAP_T));
2566 }
2567
2568 static void
2569 write_texture_p2(struct vc4_context *vc4,
2570 struct vc4_texture_stateobj *texstate,
2571 uint32_t data)
2572 {
2573 uint32_t unit = data & 0xffff;
2574 struct pipe_sampler_view *texture = texstate->textures[unit];
2575 struct vc4_resource *rsc = vc4_resource(texture->texture);
2576
2577 cl_aligned_u32(&vc4->uniforms,
2578 VC4_SET_FIELD(VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE,
2579 VC4_TEX_P2_PTYPE) |
2580 VC4_SET_FIELD(rsc->cube_map_stride >> 12, VC4_TEX_P2_CMST) |
2581 VC4_SET_FIELD((data >> 16) & 1, VC4_TEX_P2_BSLOD));
2582 }
2583
2584
2585 #define SWIZ(x,y,z,w) { \
2586 UTIL_FORMAT_SWIZZLE_##x, \
2587 UTIL_FORMAT_SWIZZLE_##y, \
2588 UTIL_FORMAT_SWIZZLE_##z, \
2589 UTIL_FORMAT_SWIZZLE_##w \
2590 }
2591
2592 static void
2593 write_texture_border_color(struct vc4_context *vc4,
2594 struct vc4_texture_stateobj *texstate,
2595 uint32_t unit)
2596 {
2597 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2598 struct pipe_sampler_view *texture = texstate->textures[unit];
2599 struct vc4_resource *rsc = vc4_resource(texture->texture);
2600 union util_color uc;
2601
2602 const struct util_format_description *tex_format_desc =
2603 util_format_description(texture->format);
2604
2605 float border_color[4];
2606 for (int i = 0; i < 4; i++)
2607 border_color[i] = sampler->border_color.f[i];
2608 if (util_format_is_srgb(texture->format)) {
2609 for (int i = 0; i < 3; i++)
2610 border_color[i] =
2611 util_format_linear_to_srgb_float(border_color[i]);
2612 }
2613
2614 /* Turn the border color into the layout of channels that it would
2615 * have when stored as texture contents.
2616 */
2617 float storage_color[4];
2618 util_format_unswizzle_4f(storage_color,
2619 border_color,
2620 tex_format_desc->swizzle);
2621
2622 /* Now, pack so that when the vc4_format-sampled texture contents are
2623 * replaced with our border color, the vc4_get_format_swizzle()
2624 * swizzling will get the right channels.
2625 */
2626 if (util_format_is_depth_or_stencil(texture->format)) {
2627 uc.ui[0] = util_pack_z(PIPE_FORMAT_Z24X8_UNORM,
2628 sampler->border_color.f[0]) << 8;
2629 } else {
2630 switch (rsc->vc4_format) {
2631 default:
2632 case VC4_TEXTURE_TYPE_RGBA8888:
2633 util_pack_color(storage_color,
2634 PIPE_FORMAT_R8G8B8A8_UNORM, &uc);
2635 break;
2636 case VC4_TEXTURE_TYPE_RGBA4444:
2637 util_pack_color(storage_color,
2638 PIPE_FORMAT_A8B8G8R8_UNORM, &uc);
2639 break;
2640 case VC4_TEXTURE_TYPE_RGB565:
2641 util_pack_color(storage_color,
2642 PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
2643 break;
2644 case VC4_TEXTURE_TYPE_ALPHA:
2645 uc.ui[0] = float_to_ubyte(storage_color[0]) << 24;
2646 break;
2647 case VC4_TEXTURE_TYPE_LUMALPHA:
2648 uc.ui[0] = ((float_to_ubyte(storage_color[1]) << 24) |
2649 (float_to_ubyte(storage_color[0]) << 0));
2650 break;
2651 }
2652 }
2653
2654 cl_aligned_u32(&vc4->uniforms, uc.ui[0]);
2655 }
2656
2657 static uint32_t
2658 get_texrect_scale(struct vc4_texture_stateobj *texstate,
2659 enum quniform_contents contents,
2660 uint32_t data)
2661 {
2662 struct pipe_sampler_view *texture = texstate->textures[data];
2663 uint32_t dim;
2664
2665 if (contents == QUNIFORM_TEXRECT_SCALE_X)
2666 dim = texture->texture->width0;
2667 else
2668 dim = texture->texture->height0;
2669
2670 return fui(1.0f / dim);
2671 }
2672
2673 static struct vc4_bo *
2674 vc4_upload_ubo(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2675 const uint32_t *gallium_uniforms)
2676 {
2677 if (!shader->ubo_size)
2678 return NULL;
2679
2680 struct vc4_bo *ubo = vc4_bo_alloc(vc4->screen, shader->ubo_size, "ubo");
2681 uint32_t *data = vc4_bo_map(ubo);
2682 for (uint32_t i = 0; i < shader->num_ubo_ranges; i++) {
2683 memcpy(data + shader->ubo_ranges[i].dst_offset,
2684 gallium_uniforms + shader->ubo_ranges[i].src_offset,
2685 shader->ubo_ranges[i].size);
2686 }
2687
2688 return ubo;
2689 }
2690
2691 void
2692 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2693 struct vc4_constbuf_stateobj *cb,
2694 struct vc4_texture_stateobj *texstate)
2695 {
2696 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2697 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
2698 struct vc4_bo *ubo = vc4_upload_ubo(vc4, shader, gallium_uniforms);
2699
2700 cl_ensure_space(&vc4->uniforms, (uinfo->count +
2701 uinfo->num_texture_samples) * 4);
2702
2703 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
2704
2705 for (int i = 0; i < uinfo->count; i++) {
2706
2707 switch (uinfo->contents[i]) {
2708 case QUNIFORM_CONSTANT:
2709 cl_aligned_u32(&vc4->uniforms, uinfo->data[i]);
2710 break;
2711 case QUNIFORM_UNIFORM:
2712 cl_aligned_u32(&vc4->uniforms,
2713 gallium_uniforms[uinfo->data[i]]);
2714 break;
2715 case QUNIFORM_VIEWPORT_X_SCALE:
2716 cl_aligned_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
2717 break;
2718 case QUNIFORM_VIEWPORT_Y_SCALE:
2719 cl_aligned_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
2720 break;
2721
2722 case QUNIFORM_VIEWPORT_Z_OFFSET:
2723 cl_aligned_f(&vc4->uniforms, vc4->viewport.translate[2]);
2724 break;
2725 case QUNIFORM_VIEWPORT_Z_SCALE:
2726 cl_aligned_f(&vc4->uniforms, vc4->viewport.scale[2]);
2727 break;
2728
2729 case QUNIFORM_USER_CLIP_PLANE:
2730 cl_aligned_f(&vc4->uniforms,
2731 vc4->clip.ucp[uinfo->data[i] / 4][uinfo->data[i] % 4]);
2732 break;
2733
2734 case QUNIFORM_TEXTURE_CONFIG_P0:
2735 write_texture_p0(vc4, texstate, uinfo->data[i]);
2736 break;
2737
2738 case QUNIFORM_TEXTURE_CONFIG_P1:
2739 write_texture_p1(vc4, texstate, uinfo->data[i]);
2740 break;
2741
2742 case QUNIFORM_TEXTURE_CONFIG_P2:
2743 write_texture_p2(vc4, texstate, uinfo->data[i]);
2744 break;
2745
2746 case QUNIFORM_UBO_ADDR:
2747 cl_aligned_reloc(vc4, &vc4->uniforms, ubo, 0);
2748 break;
2749
2750 case QUNIFORM_TEXTURE_BORDER_COLOR:
2751 write_texture_border_color(vc4, texstate, uinfo->data[i]);
2752 break;
2753
2754 case QUNIFORM_TEXRECT_SCALE_X:
2755 case QUNIFORM_TEXRECT_SCALE_Y:
2756 cl_aligned_u32(&vc4->uniforms,
2757 get_texrect_scale(texstate,
2758 uinfo->contents[i],
2759 uinfo->data[i]));
2760 break;
2761
2762 case QUNIFORM_BLEND_CONST_COLOR:
2763 cl_aligned_f(&vc4->uniforms,
2764 CLAMP(vc4->blend_color.color[uinfo->data[i]], 0, 1));
2765 break;
2766
2767 case QUNIFORM_STENCIL:
2768 cl_aligned_u32(&vc4->uniforms,
2769 vc4->zsa->stencil_uniforms[uinfo->data[i]] |
2770 (uinfo->data[i] <= 1 ?
2771 (vc4->stencil_ref.ref_value[uinfo->data[i]] << 8) :
2772 0));
2773 break;
2774
2775 case QUNIFORM_ALPHA_REF:
2776 cl_aligned_f(&vc4->uniforms,
2777 vc4->zsa->base.alpha.ref_value);
2778 break;
2779 }
2780 #if 0
2781 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
2782 fprintf(stderr, "%p: %d / 0x%08x (%f)\n",
2783 shader, i, written_val, uif(written_val));
2784 #endif
2785 }
2786 }
2787
2788 static void
2789 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2790 {
2791 struct vc4_context *vc4 = vc4_context(pctx);
2792 vc4->prog.bind_fs = hwcso;
2793 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2794 }
2795
2796 static void
2797 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2798 {
2799 struct vc4_context *vc4 = vc4_context(pctx);
2800 vc4->prog.bind_vs = hwcso;
2801 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2802 }
2803
2804 void
2805 vc4_program_init(struct pipe_context *pctx)
2806 {
2807 struct vc4_context *vc4 = vc4_context(pctx);
2808
2809 pctx->create_vs_state = vc4_shader_state_create;
2810 pctx->delete_vs_state = vc4_shader_state_delete;
2811
2812 pctx->create_fs_state = vc4_shader_state_create;
2813 pctx->delete_fs_state = vc4_shader_state_delete;
2814
2815 pctx->bind_fs_state = vc4_fp_state_bind;
2816 pctx->bind_vs_state = vc4_vp_state_bind;
2817
2818 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2819 fs_cache_compare);
2820 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2821 vs_cache_compare);
2822 }
2823
2824 void
2825 vc4_program_fini(struct pipe_context *pctx)
2826 {
2827 struct vc4_context *vc4 = vc4_context(pctx);
2828
2829 struct hash_entry *entry;
2830 hash_table_foreach(vc4->fs_cache, entry) {
2831 struct vc4_compiled_shader *shader = entry->data;
2832 vc4_bo_unreference(&shader->bo);
2833 ralloc_free(shader);
2834 _mesa_hash_table_remove(vc4->fs_cache, entry);
2835 }
2836
2837 hash_table_foreach(vc4->vs_cache, entry) {
2838 struct vc4_compiled_shader *shader = entry->data;
2839 vc4_bo_unreference(&shader->bo);
2840 ralloc_free(shader);
2841 _mesa_hash_table_remove(vc4->vs_cache, entry);
2842 }
2843 }