2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "util/ralloc.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_info.h"
35 #include "vc4_context.h"
38 #ifdef USE_VC4_SIMULATOR
39 #include "simpenrose/simpenrose.h"
43 struct pipe_shader_state
*shader_state
;
45 enum pipe_format format
;
46 unsigned compare_mode
:1;
47 unsigned compare_func
:3;
49 } tex
[VC4_MAX_TEXTURE_SAMPLERS
];
54 enum pipe_format color_format
;
59 struct pipe_rt_blend_state blend
;
64 enum pipe_format attr_formats
[8];
68 resize_qreg_array(struct vc4_compile
*c
,
73 if (*size
>= decl_size
)
76 *size
= MAX2(*size
* 2, decl_size
);
77 *regs
= reralloc(c
, *regs
, struct qreg
, *size
);
79 fprintf(stderr
, "Malloc failure\n");
85 add_uniform(struct vc4_compile
*c
,
86 enum quniform_contents contents
,
89 uint32_t uniform
= c
->num_uniforms
++;
90 struct qreg u
= { QFILE_UNIF
, uniform
};
92 c
->uniform_contents
[uniform
] = contents
;
93 c
->uniform_data
[uniform
] = data
;
99 get_temp_for_uniform(struct vc4_compile
*c
, enum quniform_contents contents
,
102 for (int i
= 0; i
< c
->num_uniforms
; i
++) {
103 if (c
->uniform_contents
[i
] == contents
&&
104 c
->uniform_data
[i
] == data
)
105 return c
->uniforms
[i
];
108 struct qreg u
= add_uniform(c
, contents
, data
);
109 struct qreg t
= qir_MOV(c
, u
);
111 resize_qreg_array(c
, &c
->uniforms
, &c
->uniforms_array_size
,
114 c
->uniforms
[u
.index
] = t
;
119 qir_uniform_ui(struct vc4_compile
*c
, uint32_t ui
)
121 return get_temp_for_uniform(c
, QUNIFORM_CONSTANT
, ui
);
125 qir_uniform_f(struct vc4_compile
*c
, float f
)
127 return qir_uniform_ui(c
, fui(f
));
131 get_src(struct vc4_compile
*c
, unsigned tgsi_op
,
132 struct tgsi_src_register
*src
, int i
)
134 struct qreg r
= c
->undef
;
154 assert(!src
->Indirect
);
159 case TGSI_FILE_TEMPORARY
:
160 r
= c
->temps
[src
->Index
* 4 + s
];
162 case TGSI_FILE_IMMEDIATE
:
163 r
= c
->consts
[src
->Index
* 4 + s
];
165 case TGSI_FILE_CONSTANT
:
166 r
= get_temp_for_uniform(c
, QUNIFORM_UNIFORM
,
169 case TGSI_FILE_INPUT
:
170 r
= c
->inputs
[src
->Index
* 4 + s
];
172 case TGSI_FILE_SAMPLER
:
173 case TGSI_FILE_SAMPLER_VIEW
:
177 fprintf(stderr
, "unknown src file %d\n", src
->File
);
182 r
= qir_FMAXABS(c
, r
, r
);
185 switch (tgsi_opcode_infer_src_type(tgsi_op
)) {
186 case TGSI_TYPE_SIGNED
:
187 case TGSI_TYPE_UNSIGNED
:
188 r
= qir_SUB(c
, qir_uniform_ui(c
, 0), r
);
191 r
= qir_FSUB(c
, qir_uniform_f(c
, 0.0), r
);
201 update_dst(struct vc4_compile
*c
, struct tgsi_full_instruction
*tgsi_inst
,
202 int i
, struct qreg val
)
204 struct tgsi_dst_register
*tgsi_dst
= &tgsi_inst
->Dst
[0].Register
;
206 assert(!tgsi_dst
->Indirect
);
208 switch (tgsi_dst
->File
) {
209 case TGSI_FILE_TEMPORARY
:
210 c
->temps
[tgsi_dst
->Index
* 4 + i
] = val
;
212 case TGSI_FILE_OUTPUT
:
213 c
->outputs
[tgsi_dst
->Index
* 4 + i
] = val
;
214 c
->num_outputs
= MAX2(c
->num_outputs
,
215 tgsi_dst
->Index
* 4 + i
+ 1);
218 fprintf(stderr
, "unknown dst file %d\n", tgsi_dst
->File
);
224 get_swizzled_channel(struct vc4_compile
*c
,
225 struct qreg
*srcs
, int swiz
)
229 case UTIL_FORMAT_SWIZZLE_NONE
:
230 fprintf(stderr
, "warning: unknown swizzle\n");
232 case UTIL_FORMAT_SWIZZLE_0
:
233 return qir_uniform_f(c
, 0.0);
234 case UTIL_FORMAT_SWIZZLE_1
:
235 return qir_uniform_f(c
, 1.0);
236 case UTIL_FORMAT_SWIZZLE_X
:
237 case UTIL_FORMAT_SWIZZLE_Y
:
238 case UTIL_FORMAT_SWIZZLE_Z
:
239 case UTIL_FORMAT_SWIZZLE_W
:
245 tgsi_to_qir_alu(struct vc4_compile
*c
,
246 struct tgsi_full_instruction
*tgsi_inst
,
247 enum qop op
, struct qreg
*src
, int i
)
249 struct qreg dst
= qir_get_temp(c
);
250 qir_emit(c
, qir_inst4(op
, dst
,
259 tgsi_to_qir_umul(struct vc4_compile
*c
,
260 struct tgsi_full_instruction
*tgsi_inst
,
261 enum qop op
, struct qreg
*src
, int i
)
263 struct qreg src0_hi
= qir_SHR(c
, src
[0 * 4 + i
],
264 qir_uniform_ui(c
, 16));
265 struct qreg src0_lo
= qir_AND(c
, src
[0 * 4 + i
],
266 qir_uniform_ui(c
, 0xffff));
267 struct qreg src1_hi
= qir_SHR(c
, src
[1 * 4 + i
],
268 qir_uniform_ui(c
, 16));
269 struct qreg src1_lo
= qir_AND(c
, src
[1 * 4 + i
],
270 qir_uniform_ui(c
, 0xffff));
272 struct qreg hilo
= qir_MUL24(c
, src0_hi
, src1_lo
);
273 struct qreg lohi
= qir_MUL24(c
, src0_lo
, src1_hi
);
274 struct qreg lolo
= qir_MUL24(c
, src0_lo
, src1_lo
);
276 return qir_ADD(c
, lolo
, qir_SHL(c
,
277 qir_ADD(c
, hilo
, lohi
),
278 qir_uniform_ui(c
, 16)));
282 tgsi_to_qir_idiv(struct vc4_compile
*c
,
283 struct tgsi_full_instruction
*tgsi_inst
,
284 enum qop op
, struct qreg
*src
, int i
)
286 return qir_FTOI(c
, qir_FMUL(c
,
287 qir_ITOF(c
, src
[0 * 4 + i
]),
288 qir_RCP(c
, qir_ITOF(c
, src
[1 * 4 + i
]))));
292 tgsi_to_qir_ineg(struct vc4_compile
*c
,
293 struct tgsi_full_instruction
*tgsi_inst
,
294 enum qop op
, struct qreg
*src
, int i
)
296 return qir_SUB(c
, qir_uniform_ui(c
, 0), src
[0 * 4 + i
]);
300 tgsi_to_qir_seq(struct vc4_compile
*c
,
301 struct tgsi_full_instruction
*tgsi_inst
,
302 enum qop op
, struct qreg
*src
, int i
)
304 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
305 return qir_SEL_X_0_ZS(c
, qir_uniform_f(c
, 1.0));
309 tgsi_to_qir_sne(struct vc4_compile
*c
,
310 struct tgsi_full_instruction
*tgsi_inst
,
311 enum qop op
, struct qreg
*src
, int i
)
313 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
314 return qir_SEL_X_0_ZC(c
, qir_uniform_f(c
, 1.0));
318 tgsi_to_qir_slt(struct vc4_compile
*c
,
319 struct tgsi_full_instruction
*tgsi_inst
,
320 enum qop op
, struct qreg
*src
, int i
)
322 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
323 return qir_SEL_X_0_NS(c
, qir_uniform_f(c
, 1.0));
327 tgsi_to_qir_sge(struct vc4_compile
*c
,
328 struct tgsi_full_instruction
*tgsi_inst
,
329 enum qop op
, struct qreg
*src
, int i
)
331 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
332 return qir_SEL_X_0_NC(c
, qir_uniform_f(c
, 1.0));
336 tgsi_to_qir_fseq(struct vc4_compile
*c
,
337 struct tgsi_full_instruction
*tgsi_inst
,
338 enum qop op
, struct qreg
*src
, int i
)
340 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
341 return qir_SEL_X_0_ZS(c
, qir_uniform_ui(c
, ~0));
345 tgsi_to_qir_fsne(struct vc4_compile
*c
,
346 struct tgsi_full_instruction
*tgsi_inst
,
347 enum qop op
, struct qreg
*src
, int i
)
349 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
350 return qir_SEL_X_0_ZC(c
, qir_uniform_ui(c
, ~0));
354 tgsi_to_qir_fslt(struct vc4_compile
*c
,
355 struct tgsi_full_instruction
*tgsi_inst
,
356 enum qop op
, struct qreg
*src
, int i
)
358 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
359 return qir_SEL_X_0_NS(c
, qir_uniform_ui(c
, ~0));
363 tgsi_to_qir_fsge(struct vc4_compile
*c
,
364 struct tgsi_full_instruction
*tgsi_inst
,
365 enum qop op
, struct qreg
*src
, int i
)
367 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
368 return qir_SEL_X_0_NC(c
, qir_uniform_ui(c
, ~0));
372 tgsi_to_qir_useq(struct vc4_compile
*c
,
373 struct tgsi_full_instruction
*tgsi_inst
,
374 enum qop op
, struct qreg
*src
, int i
)
376 qir_SF(c
, qir_SUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
377 return qir_SEL_X_0_ZS(c
, qir_uniform_ui(c
, ~0));
381 tgsi_to_qir_usne(struct vc4_compile
*c
,
382 struct tgsi_full_instruction
*tgsi_inst
,
383 enum qop op
, struct qreg
*src
, int i
)
385 qir_SF(c
, qir_SUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
386 return qir_SEL_X_0_ZC(c
, qir_uniform_ui(c
, ~0));
390 tgsi_to_qir_islt(struct vc4_compile
*c
,
391 struct tgsi_full_instruction
*tgsi_inst
,
392 enum qop op
, struct qreg
*src
, int i
)
394 qir_SF(c
, qir_SUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
395 return qir_SEL_X_0_NS(c
, qir_uniform_ui(c
, ~0));
399 tgsi_to_qir_isge(struct vc4_compile
*c
,
400 struct tgsi_full_instruction
*tgsi_inst
,
401 enum qop op
, struct qreg
*src
, int i
)
403 qir_SF(c
, qir_SUB(c
, src
[0 * 4 + i
], src
[1 * 4 + i
]));
404 return qir_SEL_X_0_NC(c
, qir_uniform_ui(c
, ~0));
408 tgsi_to_qir_cmp(struct vc4_compile
*c
,
409 struct tgsi_full_instruction
*tgsi_inst
,
410 enum qop op
, struct qreg
*src
, int i
)
412 qir_SF(c
, src
[0 * 4 + i
]);
413 return qir_SEL_X_Y_NS(c
,
419 tgsi_to_qir_mad(struct vc4_compile
*c
,
420 struct tgsi_full_instruction
*tgsi_inst
,
421 enum qop op
, struct qreg
*src
, int i
)
431 tgsi_to_qir_lit(struct vc4_compile
*c
,
432 struct tgsi_full_instruction
*tgsi_inst
,
433 enum qop op
, struct qreg
*src
, int i
)
435 struct qreg x
= src
[0 * 4 + 0];
436 struct qreg y
= src
[0 * 4 + 1];
437 struct qreg w
= src
[0 * 4 + 3];
442 return qir_uniform_f(c
, 1.0);
444 return qir_FMAX(c
, src
[0 * 4 + 0], qir_uniform_f(c
, 0.0));
446 struct qreg zero
= qir_uniform_f(c
, 0.0);
449 /* XXX: Clamp w to -128..128 */
450 return qir_SEL_X_0_NC(c
,
451 qir_EXP2(c
, qir_FMUL(c
,
459 assert(!"not reached");
465 tgsi_to_qir_lrp(struct vc4_compile
*c
,
466 struct tgsi_full_instruction
*tgsi_inst
,
467 enum qop op
, struct qreg
*src
, int i
)
469 struct qreg src0
= src
[0 * 4 + i
];
470 struct qreg src1
= src
[1 * 4 + i
];
471 struct qreg src2
= src
[2 * 4 + i
];
474 * src0 * src1 + (1 - src0) * src2.
475 * -> src0 * src1 + src2 - src0 * src2
476 * -> src2 + src0 * (src1 - src2)
478 return qir_FADD(c
, src2
, qir_FMUL(c
, src0
, qir_FSUB(c
, src1
, src2
)));
483 tgsi_to_qir_tex(struct vc4_compile
*c
,
484 struct tgsi_full_instruction
*tgsi_inst
,
485 enum qop op
, struct qreg
*src
)
487 assert(!tgsi_inst
->Instruction
.Saturate
);
489 struct qreg s
= src
[0 * 4 + 0];
490 struct qreg t
= src
[0 * 4 + 1];
491 uint32_t unit
= tgsi_inst
->Src
[1].Register
.Index
;
493 struct qreg proj
= c
->undef
;
494 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
495 proj
= qir_RCP(c
, src
[0 * 4 + 3]);
496 s
= qir_FMUL(c
, s
, proj
);
497 t
= qir_FMUL(c
, t
, proj
);
500 /* There is no native support for GL texture rectangle coordinates, so
501 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
504 if (tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_RECT
||
505 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
) {
507 get_temp_for_uniform(c
,
508 QUNIFORM_TEXRECT_SCALE_X
,
511 get_temp_for_uniform(c
,
512 QUNIFORM_TEXRECT_SCALE_Y
,
516 qir_TEX_T(c
, t
, add_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P0
, unit
));
518 struct qreg sampler_p1
= add_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P1
,
520 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB
) {
521 qir_TEX_B(c
, src
[0 * 4 + 3], sampler_p1
);
522 qir_TEX_S(c
, s
, add_uniform(c
, QUNIFORM_CONSTANT
, 0));
524 qir_TEX_S(c
, s
, sampler_p1
);
527 c
->num_texture_samples
++;
528 struct qreg r4
= qir_TEX_RESULT(c
);
530 enum pipe_format format
= c
->key
->tex
[unit
].format
;
532 struct qreg unpacked
[4];
533 if (util_format_is_depth_or_stencil(format
)) {
534 struct qreg depthf
= qir_ITOF(c
, qir_SHR(c
, r4
,
535 qir_uniform_ui(c
, 8)));
536 struct qreg normalized
= qir_FMUL(c
, depthf
,
537 qir_uniform_f(c
, 1.0f
/0xffffff));
539 struct qreg depth_output
;
541 struct qreg compare
= src
[0 * 4 + 2];
543 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
)
544 compare
= qir_FMUL(c
, compare
, proj
);
546 struct qreg one
= qir_uniform_f(c
, 1.0f
);
547 if (c
->key
->tex
[unit
].compare_mode
) {
548 switch (c
->key
->tex
[unit
].compare_func
) {
549 case PIPE_FUNC_NEVER
:
550 depth_output
= qir_uniform_f(c
, 0.0f
);
552 case PIPE_FUNC_ALWAYS
:
555 case PIPE_FUNC_EQUAL
:
556 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
557 depth_output
= qir_SEL_X_0_ZS(c
, one
);
559 case PIPE_FUNC_NOTEQUAL
:
560 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
561 depth_output
= qir_SEL_X_0_ZC(c
, one
);
563 case PIPE_FUNC_GREATER
:
564 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
565 depth_output
= qir_SEL_X_0_NC(c
, one
);
567 case PIPE_FUNC_GEQUAL
:
568 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
569 depth_output
= qir_SEL_X_0_NS(c
, one
);
572 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
573 depth_output
= qir_SEL_X_0_NS(c
, one
);
575 case PIPE_FUNC_LEQUAL
:
576 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
577 depth_output
= qir_SEL_X_0_NC(c
, one
);
581 depth_output
= normalized
;
584 for (int i
= 0; i
< 4; i
++)
585 unpacked
[i
] = depth_output
;
587 for (int i
= 0; i
< 4; i
++)
588 unpacked
[i
] = qir_R4_UNPACK(c
, r4
, i
);
591 const uint8_t *format_swiz
= vc4_get_format_swizzle(format
);
593 util_format_compose_swizzles(format_swiz
, c
->key
->tex
[unit
].swizzle
, swiz
);
594 for (int i
= 0; i
< 4; i
++) {
595 if (!(tgsi_inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
598 update_dst(c
, tgsi_inst
, i
,
599 get_swizzled_channel(c
, unpacked
, swiz
[i
]));
604 tgsi_to_qir_pow(struct vc4_compile
*c
,
605 struct tgsi_full_instruction
*tgsi_inst
,
606 enum qop op
, struct qreg
*src
, int i
)
608 /* Note that this instruction replicates its result from the x channel
610 return qir_EXP2(c
, qir_FMUL(c
,
612 qir_LOG2(c
, src
[0 * 4 + 0])));
616 tgsi_to_qir_trunc(struct vc4_compile
*c
,
617 struct tgsi_full_instruction
*tgsi_inst
,
618 enum qop op
, struct qreg
*src
, int i
)
620 return qir_ITOF(c
, qir_FTOI(c
, src
[0 * 4 + i
]));
624 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
628 tgsi_to_qir_frc(struct vc4_compile
*c
,
629 struct tgsi_full_instruction
*tgsi_inst
,
630 enum qop op
, struct qreg
*src
, int i
)
632 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
[0 * 4 + i
]));
633 struct qreg diff
= qir_FSUB(c
, src
[0 * 4 + i
], trunc
);
635 return qir_SEL_X_Y_NS(c
,
636 qir_FADD(c
, diff
, qir_uniform_f(c
, 1.0)),
641 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
645 tgsi_to_qir_flr(struct vc4_compile
*c
,
646 struct tgsi_full_instruction
*tgsi_inst
,
647 enum qop op
, struct qreg
*src
, int i
)
649 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
[0 * 4 + i
]));
651 /* This will be < 0 if we truncated and the truncation was of a value
652 * that was < 0 in the first place.
654 qir_SF(c
, qir_FSUB(c
, src
[0 * 4 + i
], trunc
));
656 return qir_SEL_X_Y_NS(c
,
657 qir_FSUB(c
, trunc
, qir_uniform_f(c
, 1.0)),
662 tgsi_to_qir_dp(struct vc4_compile
*c
,
663 struct tgsi_full_instruction
*tgsi_inst
,
664 int num
, struct qreg
*src
, int i
)
666 struct qreg sum
= qir_FMUL(c
, src
[0 * 4 + 0], src
[1 * 4 + 0]);
667 for (int j
= 1; j
< num
; j
++) {
668 sum
= qir_FADD(c
, sum
, qir_FMUL(c
,
676 tgsi_to_qir_dp2(struct vc4_compile
*c
,
677 struct tgsi_full_instruction
*tgsi_inst
,
678 enum qop op
, struct qreg
*src
, int i
)
680 return tgsi_to_qir_dp(c
, tgsi_inst
, 2, src
, i
);
684 tgsi_to_qir_dp3(struct vc4_compile
*c
,
685 struct tgsi_full_instruction
*tgsi_inst
,
686 enum qop op
, struct qreg
*src
, int i
)
688 return tgsi_to_qir_dp(c
, tgsi_inst
, 3, src
, i
);
692 tgsi_to_qir_dp4(struct vc4_compile
*c
,
693 struct tgsi_full_instruction
*tgsi_inst
,
694 enum qop op
, struct qreg
*src
, int i
)
696 return tgsi_to_qir_dp(c
, tgsi_inst
, 4, src
, i
);
700 tgsi_to_qir_abs(struct vc4_compile
*c
,
701 struct tgsi_full_instruction
*tgsi_inst
,
702 enum qop op
, struct qreg
*src
, int i
)
704 struct qreg arg
= src
[0 * 4 + i
];
705 return qir_FMAXABS(c
, arg
, arg
);
708 /* Note that this instruction replicates its result from the x channel */
710 tgsi_to_qir_sin(struct vc4_compile
*c
,
711 struct tgsi_full_instruction
*tgsi_inst
,
712 enum qop op
, struct qreg
*src
, int i
)
716 -pow(2.0 * M_PI
, 3) / (3 * 2 * 1),
717 pow(2.0 * M_PI
, 5) / (5 * 4 * 3 * 2 * 1),
718 -pow(2.0 * M_PI
, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
721 struct qreg scaled_x
=
724 qir_uniform_f(c
, 1.0f
/ (M_PI
* 2.0f
)));
727 struct qreg x
= tgsi_to_qir_frc(c
, NULL
, 0, &scaled_x
, 0);
728 struct qreg x2
= qir_FMUL(c
, x
, x
);
729 struct qreg sum
= qir_FMUL(c
, x
, qir_uniform_f(c
, coeff
[0]));
730 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
731 x
= qir_FMUL(c
, x
, x2
);
736 qir_uniform_f(c
, coeff
[i
])));
741 /* Note that this instruction replicates its result from the x channel */
743 tgsi_to_qir_cos(struct vc4_compile
*c
,
744 struct tgsi_full_instruction
*tgsi_inst
,
745 enum qop op
, struct qreg
*src
, int i
)
749 -pow(2.0 * M_PI
, 2) / (2 * 1),
750 pow(2.0 * M_PI
, 4) / (4 * 3 * 2 * 1),
751 -pow(2.0 * M_PI
, 6) / (6 * 5 * 4 * 3 * 2 * 1),
754 struct qreg scaled_x
=
755 qir_FMUL(c
, src
[0 * 4 + 0],
756 qir_uniform_f(c
, 1.0f
/ (M_PI
* 2.0f
)));
757 struct qreg x_frac
= tgsi_to_qir_frc(c
, NULL
, 0, &scaled_x
, 0);
759 struct qreg sum
= qir_uniform_f(c
, coeff
[0]);
760 struct qreg x2
= qir_FMUL(c
, x_frac
, x_frac
);
761 struct qreg x
= x2
; /* Current x^2, x^4, or x^6 */
762 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
764 x
= qir_FMUL(c
, x
, x2
);
766 struct qreg mul
= qir_FMUL(c
,
768 qir_uniform_f(c
, coeff
[i
]));
772 sum
= qir_FADD(c
, sum
, mul
);
778 emit_vertex_input(struct vc4_compile
*c
, int attr
)
780 enum pipe_format format
= c
->vs_key
->attr_formats
[attr
];
781 struct qreg vpm_reads
[4];
783 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
784 * time, so we always read 4 32-bit VPM entries.
786 for (int i
= 0; i
< 4; i
++) {
787 vpm_reads
[i
] = qir_get_temp(c
);
788 qir_emit(c
, qir_inst(QOP_VPM_READ
,
795 bool format_warned
= false;
796 const struct util_format_description
*desc
=
797 util_format_description(format
);
799 for (int i
= 0; i
< 4; i
++) {
800 uint8_t swiz
= desc
->swizzle
[i
];
802 if (swiz
<= UTIL_FORMAT_SWIZZLE_W
&&
804 (desc
->channel
[swiz
].type
!= UTIL_FORMAT_TYPE_FLOAT
||
805 desc
->channel
[swiz
].size
!= 32)) {
807 "vtx element %d unsupported type: %s\n",
808 attr
, util_format_name(format
));
809 format_warned
= true;
812 c
->inputs
[attr
* 4 + i
] =
813 get_swizzled_channel(c
, vpm_reads
, swiz
);
818 tgsi_to_qir_kill_if(struct vc4_compile
*c
, struct qreg
*src
, int i
)
820 if (c
->discard
.file
== QFILE_NULL
)
821 c
->discard
= qir_uniform_f(c
, 0.0);
822 qir_SF(c
, src
[0 * 4 + i
]);
823 c
->discard
= qir_SEL_X_Y_NS(c
, qir_uniform_f(c
, 1.0),
828 emit_fragcoord_input(struct vc4_compile
*c
, int attr
)
830 c
->inputs
[attr
* 4 + 0] = qir_FRAG_X(c
);
831 c
->inputs
[attr
* 4 + 1] = qir_FRAG_Y(c
);
832 c
->inputs
[attr
* 4 + 2] =
834 qir_ITOF(c
, qir_FRAG_Z(c
)),
835 qir_uniform_f(c
, 1.0 / 0xffffff));
836 c
->inputs
[attr
* 4 + 3] = qir_FRAG_RCP_W(c
);
840 emit_fragment_varying(struct vc4_compile
*c
, int index
)
847 /* XXX: multiply by W */
848 return qir_VARY_ADD_C(c
, qir_MOV(c
, vary
));
852 emit_fragment_input(struct vc4_compile
*c
, int attr
)
854 for (int i
= 0; i
< 4; i
++) {
855 c
->inputs
[attr
* 4 + i
] =
856 emit_fragment_varying(c
, attr
* 4 + i
);
862 emit_tgsi_declaration(struct vc4_compile
*c
,
863 struct tgsi_full_declaration
*decl
)
865 switch (decl
->Declaration
.File
) {
866 case TGSI_FILE_TEMPORARY
:
867 resize_qreg_array(c
, &c
->temps
, &c
->temps_array_size
,
868 (decl
->Range
.Last
+ 1) * 4);
871 case TGSI_FILE_INPUT
:
872 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
873 (decl
->Range
.Last
+ 1) * 4);
875 for (int i
= decl
->Range
.First
;
876 i
<= decl
->Range
.Last
;
878 if (c
->stage
== QSTAGE_FRAG
) {
879 if (decl
->Semantic
.Name
==
880 TGSI_SEMANTIC_POSITION
) {
881 emit_fragcoord_input(c
, i
);
883 emit_fragment_input(c
, i
);
886 emit_vertex_input(c
, i
);
891 case TGSI_FILE_OUTPUT
:
892 resize_qreg_array(c
, &c
->outputs
, &c
->outputs_array_size
,
893 (decl
->Range
.Last
+ 1) * 4);
899 emit_tgsi_instruction(struct vc4_compile
*c
,
900 struct tgsi_full_instruction
*tgsi_inst
)
904 struct qreg (*func
)(struct vc4_compile
*c
,
905 struct tgsi_full_instruction
*tgsi_inst
,
907 struct qreg
*src
, int i
);
909 [TGSI_OPCODE_MOV
] = { QOP_MOV
, tgsi_to_qir_alu
},
910 [TGSI_OPCODE_ABS
] = { 0, tgsi_to_qir_abs
},
911 [TGSI_OPCODE_MUL
] = { QOP_FMUL
, tgsi_to_qir_alu
},
912 [TGSI_OPCODE_ADD
] = { QOP_FADD
, tgsi_to_qir_alu
},
913 [TGSI_OPCODE_SUB
] = { QOP_FSUB
, tgsi_to_qir_alu
},
914 [TGSI_OPCODE_MIN
] = { QOP_FMIN
, tgsi_to_qir_alu
},
915 [TGSI_OPCODE_MAX
] = { QOP_FMAX
, tgsi_to_qir_alu
},
916 [TGSI_OPCODE_F2I
] = { QOP_FTOI
, tgsi_to_qir_alu
},
917 [TGSI_OPCODE_I2F
] = { QOP_ITOF
, tgsi_to_qir_alu
},
918 [TGSI_OPCODE_UADD
] = { QOP_ADD
, tgsi_to_qir_alu
},
919 [TGSI_OPCODE_USHR
] = { QOP_SHR
, tgsi_to_qir_alu
},
920 [TGSI_OPCODE_ISHR
] = { QOP_ASR
, tgsi_to_qir_alu
},
921 [TGSI_OPCODE_SHL
] = { QOP_SHL
, tgsi_to_qir_alu
},
922 [TGSI_OPCODE_IMIN
] = { QOP_MIN
, tgsi_to_qir_alu
},
923 [TGSI_OPCODE_IMAX
] = { QOP_MAX
, tgsi_to_qir_alu
},
924 [TGSI_OPCODE_AND
] = { QOP_AND
, tgsi_to_qir_alu
},
925 [TGSI_OPCODE_OR
] = { QOP_OR
, tgsi_to_qir_alu
},
926 [TGSI_OPCODE_XOR
] = { QOP_XOR
, tgsi_to_qir_alu
},
927 [TGSI_OPCODE_NOT
] = { QOP_NOT
, tgsi_to_qir_alu
},
929 [TGSI_OPCODE_UMUL
] = { 0, tgsi_to_qir_umul
},
930 [TGSI_OPCODE_IDIV
] = { 0, tgsi_to_qir_idiv
},
931 [TGSI_OPCODE_INEG
] = { 0, tgsi_to_qir_ineg
},
933 [TGSI_OPCODE_RSQ
] = { QOP_RSQ
, tgsi_to_qir_alu
},
934 [TGSI_OPCODE_SEQ
] = { 0, tgsi_to_qir_seq
},
935 [TGSI_OPCODE_SNE
] = { 0, tgsi_to_qir_sne
},
936 [TGSI_OPCODE_SGE
] = { 0, tgsi_to_qir_sge
},
937 [TGSI_OPCODE_SLT
] = { 0, tgsi_to_qir_slt
},
938 [TGSI_OPCODE_FSEQ
] = { 0, tgsi_to_qir_fseq
},
939 [TGSI_OPCODE_FSNE
] = { 0, tgsi_to_qir_fsne
},
940 [TGSI_OPCODE_FSGE
] = { 0, tgsi_to_qir_fsge
},
941 [TGSI_OPCODE_FSLT
] = { 0, tgsi_to_qir_fslt
},
942 [TGSI_OPCODE_USEQ
] = { 0, tgsi_to_qir_useq
},
943 [TGSI_OPCODE_USNE
] = { 0, tgsi_to_qir_usne
},
944 [TGSI_OPCODE_ISGE
] = { 0, tgsi_to_qir_isge
},
945 [TGSI_OPCODE_ISLT
] = { 0, tgsi_to_qir_islt
},
947 [TGSI_OPCODE_CMP
] = { 0, tgsi_to_qir_cmp
},
948 [TGSI_OPCODE_MAD
] = { 0, tgsi_to_qir_mad
},
949 [TGSI_OPCODE_DP2
] = { 0, tgsi_to_qir_dp2
},
950 [TGSI_OPCODE_DP3
] = { 0, tgsi_to_qir_dp3
},
951 [TGSI_OPCODE_DP4
] = { 0, tgsi_to_qir_dp4
},
952 [TGSI_OPCODE_RCP
] = { QOP_RCP
, tgsi_to_qir_alu
},
953 [TGSI_OPCODE_RSQ
] = { QOP_RSQ
, tgsi_to_qir_alu
},
954 [TGSI_OPCODE_EX2
] = { QOP_EXP2
, tgsi_to_qir_alu
},
955 [TGSI_OPCODE_LG2
] = { QOP_LOG2
, tgsi_to_qir_alu
},
956 [TGSI_OPCODE_LIT
] = { 0, tgsi_to_qir_lit
},
957 [TGSI_OPCODE_LRP
] = { 0, tgsi_to_qir_lrp
},
958 [TGSI_OPCODE_POW
] = { 0, tgsi_to_qir_pow
},
959 [TGSI_OPCODE_TRUNC
] = { 0, tgsi_to_qir_trunc
},
960 [TGSI_OPCODE_FRC
] = { 0, tgsi_to_qir_frc
},
961 [TGSI_OPCODE_FLR
] = { 0, tgsi_to_qir_flr
},
962 [TGSI_OPCODE_SIN
] = { 0, tgsi_to_qir_sin
},
963 [TGSI_OPCODE_COS
] = { 0, tgsi_to_qir_cos
},
966 uint32_t tgsi_op
= tgsi_inst
->Instruction
.Opcode
;
968 if (tgsi_op
== TGSI_OPCODE_END
)
971 struct qreg src_regs
[12];
972 for (int s
= 0; s
< 3; s
++) {
973 for (int i
= 0; i
< 4; i
++) {
974 src_regs
[4 * s
+ i
] =
975 get_src(c
, tgsi_inst
->Instruction
.Opcode
,
976 &tgsi_inst
->Src
[s
].Register
, i
);
981 case TGSI_OPCODE_TEX
:
982 case TGSI_OPCODE_TXP
:
983 case TGSI_OPCODE_TXB
:
984 tgsi_to_qir_tex(c
, tgsi_inst
,
985 op_trans
[tgsi_op
].op
, src_regs
);
987 case TGSI_OPCODE_KILL
:
988 c
->discard
= qir_uniform_f(c
, 1.0);
990 case TGSI_OPCODE_KILL_IF
:
991 for (int i
= 0; i
< 4; i
++)
992 tgsi_to_qir_kill_if(c
, src_regs
, i
);
998 if (tgsi_op
> ARRAY_SIZE(op_trans
) || !(op_trans
[tgsi_op
].func
)) {
999 fprintf(stderr
, "unknown tgsi inst: ");
1000 tgsi_dump_instruction(tgsi_inst
, asdf
++);
1001 fprintf(stderr
, "\n");
1005 for (int i
= 0; i
< 4; i
++) {
1006 if (!(tgsi_inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1011 result
= op_trans
[tgsi_op
].func(c
, tgsi_inst
,
1012 op_trans
[tgsi_op
].op
,
1015 if (tgsi_inst
->Instruction
.Saturate
) {
1016 float low
= (tgsi_inst
->Instruction
.Saturate
==
1017 TGSI_SAT_MINUS_PLUS_ONE
? -1.0 : 0.0);
1018 result
= qir_FMAX(c
,
1021 qir_uniform_f(c
, 1.0)),
1022 qir_uniform_f(c
, low
));
1025 update_dst(c
, tgsi_inst
, i
, result
);
1030 parse_tgsi_immediate(struct vc4_compile
*c
, struct tgsi_full_immediate
*imm
)
1032 for (int i
= 0; i
< 4; i
++) {
1033 unsigned n
= c
->num_consts
++;
1034 resize_qreg_array(c
, &c
->consts
, &c
->consts_array_size
, n
+ 1);
1035 c
->consts
[n
] = qir_uniform_ui(c
, imm
->u
[i
].Uint
);
1040 vc4_blend_channel(struct vc4_compile
*c
,
1048 case PIPE_BLENDFACTOR_ONE
:
1050 case PIPE_BLENDFACTOR_SRC_COLOR
:
1051 return qir_FMUL(c
, val
, src
[channel
]);
1052 case PIPE_BLENDFACTOR_SRC_ALPHA
:
1053 return qir_FMUL(c
, val
, src
[3]);
1054 case PIPE_BLENDFACTOR_DST_ALPHA
:
1055 return qir_FMUL(c
, val
, dst
[3]);
1056 case PIPE_BLENDFACTOR_DST_COLOR
:
1057 return qir_FMUL(c
, val
, dst
[channel
]);
1058 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
1059 return qir_FMIN(c
, src
[3], qir_FSUB(c
,
1060 qir_uniform_f(c
, 1.0),
1062 case PIPE_BLENDFACTOR_CONST_COLOR
:
1063 return qir_FMUL(c
, val
,
1064 get_temp_for_uniform(c
,
1065 QUNIFORM_BLEND_CONST_COLOR
,
1067 case PIPE_BLENDFACTOR_CONST_ALPHA
:
1068 return qir_FMUL(c
, val
,
1069 get_temp_for_uniform(c
,
1070 QUNIFORM_BLEND_CONST_COLOR
,
1072 case PIPE_BLENDFACTOR_ZERO
:
1073 return qir_uniform_f(c
, 0.0);
1074 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
1075 return qir_FMUL(c
, val
, qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1077 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
1078 return qir_FMUL(c
, val
, qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1080 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
1081 return qir_FMUL(c
, val
, qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1083 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
1084 return qir_FMUL(c
, val
, qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1086 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
1087 return qir_FMUL(c
, val
,
1088 qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1089 get_temp_for_uniform(c
,
1090 QUNIFORM_BLEND_CONST_COLOR
,
1092 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
1093 return qir_FMUL(c
, val
,
1094 qir_FSUB(c
, qir_uniform_f(c
, 1.0),
1095 get_temp_for_uniform(c
,
1096 QUNIFORM_BLEND_CONST_COLOR
,
1100 case PIPE_BLENDFACTOR_SRC1_COLOR
:
1101 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
1102 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
1103 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
1105 fprintf(stderr
, "Unknown blend factor %d\n", factor
);
1111 vc4_blend_func(struct vc4_compile
*c
,
1112 struct qreg src
, struct qreg dst
,
1116 case PIPE_BLEND_ADD
:
1117 return qir_FADD(c
, src
, dst
);
1118 case PIPE_BLEND_SUBTRACT
:
1119 return qir_FSUB(c
, src
, dst
);
1120 case PIPE_BLEND_REVERSE_SUBTRACT
:
1121 return qir_FSUB(c
, dst
, src
);
1122 case PIPE_BLEND_MIN
:
1123 return qir_FMIN(c
, src
, dst
);
1124 case PIPE_BLEND_MAX
:
1125 return qir_FMAX(c
, src
, dst
);
1129 fprintf(stderr
, "Unknown blend func %d\n", func
);
1136 * Implements fixed function blending in shader code.
1138 * VC4 doesn't have any hardware support for blending. Instead, you read the
1139 * current contents of the destination from the tile buffer after having
1140 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1141 * math using your output color and that destination value, and update the
1142 * output color appropriately.
1145 vc4_blend(struct vc4_compile
*c
, struct qreg
*result
,
1146 struct qreg
*dst_color
, struct qreg
*src_color
)
1148 struct pipe_rt_blend_state
*blend
= &c
->fs_key
->blend
;
1150 if (!blend
->blend_enable
) {
1151 for (int i
= 0; i
< 4; i
++)
1152 result
[i
] = src_color
[i
];
1156 struct qreg src_blend
[4], dst_blend
[4];
1157 for (int i
= 0; i
< 3; i
++) {
1158 src_blend
[i
] = vc4_blend_channel(c
,
1159 dst_color
, src_color
,
1161 blend
->rgb_src_factor
, i
);
1162 dst_blend
[i
] = vc4_blend_channel(c
,
1163 dst_color
, src_color
,
1165 blend
->rgb_dst_factor
, i
);
1167 src_blend
[3] = vc4_blend_channel(c
,
1168 dst_color
, src_color
,
1170 blend
->alpha_src_factor
, 3);
1171 dst_blend
[3] = vc4_blend_channel(c
,
1172 dst_color
, src_color
,
1174 blend
->alpha_dst_factor
, 3);
1176 for (int i
= 0; i
< 3; i
++) {
1177 result
[i
] = vc4_blend_func(c
,
1178 src_blend
[i
], dst_blend
[i
],
1181 result
[3] = vc4_blend_func(c
,
1182 src_blend
[3], dst_blend
[3],
1187 emit_frag_end(struct vc4_compile
*c
)
1189 enum pipe_format color_format
= c
->fs_key
->color_format
;
1190 const uint8_t *format_swiz
= vc4_get_format_swizzle(color_format
);
1191 struct qreg tlb_read_color
[4] = { c
->undef
, c
->undef
, c
->undef
, c
->undef
};
1192 struct qreg dst_color
[4] = { c
->undef
, c
->undef
, c
->undef
, c
->undef
};
1193 if (c
->fs_key
->blend
.blend_enable
||
1194 c
->fs_key
->blend
.colormask
!= 0xf) {
1195 struct qreg r4
= qir_TLB_COLOR_READ(c
);
1196 for (int i
= 0; i
< 4; i
++)
1197 tlb_read_color
[i
] = qir_R4_UNPACK(c
, r4
, i
);
1198 for (int i
= 0; i
< 4; i
++)
1199 dst_color
[i
] = get_swizzled_channel(c
,
1204 struct qreg blend_color
[4];
1205 struct qreg undef_array
[4] = {
1206 c
->undef
, c
->undef
, c
->undef
, c
->undef
1208 vc4_blend(c
, blend_color
, dst_color
,
1209 c
->outputs
? c
->outputs
: undef_array
);
1211 /* If the bit isn't set in the color mask, then just return the
1212 * original dst color, instead.
1214 for (int i
= 0; i
< 4; i
++) {
1215 if (!(c
->fs_key
->blend
.colormask
& (1 << i
))) {
1216 blend_color
[i
] = dst_color
[i
];
1220 /* Debug: Sometimes you're getting a black output and just want to see
1221 * if the FS is getting executed at all. Spam magenta into the color
1225 blend_color
[0] = qir_uniform_f(c
, 1.0);
1226 blend_color
[1] = qir_uniform_f(c
, 0.0);
1227 blend_color
[2] = qir_uniform_f(c
, 1.0);
1228 blend_color
[3] = qir_uniform_f(c
, 0.5);
1231 struct qreg swizzled_outputs
[4];
1232 for (int i
= 0; i
< 4; i
++) {
1233 swizzled_outputs
[i
] = get_swizzled_channel(c
, blend_color
,
1237 if (c
->discard
.file
!= QFILE_NULL
)
1238 qir_TLB_DISCARD_SETUP(c
, c
->discard
);
1240 if (c
->fs_key
->depth_enabled
) {
1241 qir_TLB_Z_WRITE(c
, qir_FRAG_Z(c
));
1244 bool color_written
= false;
1245 for (int i
= 0; i
< 4; i
++) {
1246 if (swizzled_outputs
[i
].file
!= QFILE_NULL
)
1247 color_written
= true;
1250 struct qreg packed_color
;
1251 if (color_written
) {
1252 /* Fill in any undefined colors. The simulator will assertion
1253 * fail if we read something that wasn't written, and I don't
1254 * know what hardware does.
1256 for (int i
= 0; i
< 4; i
++) {
1257 if (swizzled_outputs
[i
].file
== QFILE_NULL
)
1258 swizzled_outputs
[i
] = qir_uniform_f(c
, 0.0);
1260 packed_color
= qir_get_temp(c
);
1261 qir_emit(c
, qir_inst4(QOP_PACK_COLORS
, packed_color
,
1262 swizzled_outputs
[0],
1263 swizzled_outputs
[1],
1264 swizzled_outputs
[2],
1265 swizzled_outputs
[3]));
1267 packed_color
= qir_uniform_ui(c
, 0);
1270 qir_emit(c
, qir_inst(QOP_TLB_COLOR_WRITE
, c
->undef
,
1271 packed_color
, c
->undef
));
1275 emit_scaled_viewport_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1279 for (int i
= 0; i
< 2; i
++) {
1281 add_uniform(c
, QUNIFORM_VIEWPORT_X_SCALE
+ i
, 0);
1283 xyi
[i
] = qir_FTOI(c
, qir_FMUL(c
,
1290 qir_VPM_WRITE(c
, qir_PACK_SCALED(c
, xyi
[0], xyi
[1]));
1294 emit_zs_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1296 struct qreg zscale
= add_uniform(c
, QUNIFORM_VIEWPORT_Z_SCALE
, 0);
1297 struct qreg zoffset
= add_uniform(c
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0);
1299 qir_VPM_WRITE(c
, qir_FMUL(c
, qir_FADD(c
, qir_FMUL(c
,
1307 emit_rcp_wc_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1309 qir_VPM_WRITE(c
, rcp_w
);
1313 emit_vert_end(struct vc4_compile
*c
)
1315 struct qreg rcp_w
= qir_RCP(c
, c
->outputs
[3]);
1317 emit_scaled_viewport_write(c
, rcp_w
);
1318 emit_zs_write(c
, rcp_w
);
1319 emit_rcp_wc_write(c
, rcp_w
);
1321 for (int i
= 4; i
< c
->num_outputs
; i
++) {
1322 qir_VPM_WRITE(c
, c
->outputs
[i
]);
1327 emit_coord_end(struct vc4_compile
*c
)
1329 struct qreg rcp_w
= qir_RCP(c
, c
->outputs
[3]);
1331 for (int i
= 0; i
< 4; i
++)
1332 qir_VPM_WRITE(c
, c
->outputs
[i
]);
1334 emit_scaled_viewport_write(c
, rcp_w
);
1335 emit_zs_write(c
, rcp_w
);
1336 emit_rcp_wc_write(c
, rcp_w
);
1339 static struct vc4_compile
*
1340 vc4_shader_tgsi_to_qir(struct vc4_compiled_shader
*shader
, enum qstage stage
,
1341 struct vc4_key
*key
)
1343 struct vc4_compile
*c
= qir_compile_init();
1348 c
->uniform_data
= ralloc_array(c
, uint32_t, 1024);
1349 c
->uniform_contents
= ralloc_array(c
, enum quniform_contents
, 1024);
1351 c
->shader_state
= key
->shader_state
;
1352 ret
= tgsi_parse_init(&c
->parser
, c
->shader_state
->tokens
);
1353 assert(ret
== TGSI_PARSE_OK
);
1355 if (vc4_debug
& VC4_DEBUG_TGSI
) {
1356 fprintf(stderr
, "TGSI:\n");
1357 tgsi_dump(c
->shader_state
->tokens
, 0);
1363 c
->fs_key
= (struct vc4_fs_key
*)key
;
1364 if (c
->fs_key
->is_points
) {
1365 c
->point_x
= emit_fragment_varying(c
, 0);
1366 c
->point_y
= emit_fragment_varying(c
, 0);
1367 } else if (c
->fs_key
->is_lines
) {
1368 c
->line_x
= emit_fragment_varying(c
, 0);
1372 c
->vs_key
= (struct vc4_vs_key
*)key
;
1375 c
->vs_key
= (struct vc4_vs_key
*)key
;
1379 while (!tgsi_parse_end_of_tokens(&c
->parser
)) {
1380 tgsi_parse_token(&c
->parser
);
1382 switch (c
->parser
.FullToken
.Token
.Type
) {
1383 case TGSI_TOKEN_TYPE_DECLARATION
:
1384 emit_tgsi_declaration(c
,
1385 &c
->parser
.FullToken
.FullDeclaration
);
1388 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1389 emit_tgsi_instruction(c
,
1390 &c
->parser
.FullToken
.FullInstruction
);
1393 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1394 parse_tgsi_immediate(c
,
1395 &c
->parser
.FullToken
.FullImmediate
);
1412 tgsi_parse_free(&c
->parser
);
1416 if (vc4_debug
& VC4_DEBUG_QIR
) {
1417 fprintf(stderr
, "QIR:\n");
1420 vc4_generate_code(c
);
1422 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
1423 fprintf(stderr
, "SHADER-DB: %s: %d instructions\n",
1424 qir_get_stage_name(c
->stage
), c
->qpu_inst_count
);
1425 fprintf(stderr
, "SHADER-DB: %s: %d uniforms\n",
1426 qir_get_stage_name(c
->stage
), c
->num_uniforms
);
1433 vc4_shader_state_create(struct pipe_context
*pctx
,
1434 const struct pipe_shader_state
*cso
)
1436 struct pipe_shader_state
*so
= CALLOC_STRUCT(pipe_shader_state
);
1440 so
->tokens
= tgsi_dup_tokens(cso
->tokens
);
1446 copy_uniform_state_to_shader(struct vc4_compiled_shader
*shader
,
1448 struct vc4_compile
*c
)
1450 int count
= c
->num_uniforms
;
1451 struct vc4_shader_uniform_info
*uinfo
= &shader
->uniforms
[shader_index
];
1453 uinfo
->count
= count
;
1454 uinfo
->data
= malloc(count
* sizeof(*uinfo
->data
));
1455 memcpy(uinfo
->data
, c
->uniform_data
,
1456 count
* sizeof(*uinfo
->data
));
1457 uinfo
->contents
= malloc(count
* sizeof(*uinfo
->contents
));
1458 memcpy(uinfo
->contents
, c
->uniform_contents
,
1459 count
* sizeof(*uinfo
->contents
));
1460 uinfo
->num_texture_samples
= c
->num_texture_samples
;
1464 vc4_fs_compile(struct vc4_context
*vc4
, struct vc4_compiled_shader
*shader
,
1465 struct vc4_fs_key
*key
)
1467 struct vc4_compile
*c
= vc4_shader_tgsi_to_qir(shader
, QSTAGE_FRAG
,
1469 shader
->num_inputs
= c
->num_inputs
;
1470 copy_uniform_state_to_shader(shader
, 0, c
);
1471 shader
->bo
= vc4_bo_alloc_mem(vc4
->screen
, c
->qpu_insts
,
1472 c
->qpu_inst_count
* sizeof(uint64_t),
1475 qir_compile_destroy(c
);
1479 vc4_vs_compile(struct vc4_context
*vc4
, struct vc4_compiled_shader
*shader
,
1480 struct vc4_vs_key
*key
)
1482 struct vc4_compile
*vs_c
= vc4_shader_tgsi_to_qir(shader
,
1485 copy_uniform_state_to_shader(shader
, 0, vs_c
);
1487 struct vc4_compile
*cs_c
= vc4_shader_tgsi_to_qir(shader
,
1490 copy_uniform_state_to_shader(shader
, 1, cs_c
);
1492 uint32_t vs_size
= vs_c
->qpu_inst_count
* sizeof(uint64_t);
1493 uint32_t cs_size
= cs_c
->qpu_inst_count
* sizeof(uint64_t);
1494 shader
->coord_shader_offset
= vs_size
; /* XXX: alignment? */
1495 shader
->bo
= vc4_bo_alloc(vc4
->screen
,
1496 shader
->coord_shader_offset
+ cs_size
,
1499 void *map
= vc4_bo_map(shader
->bo
);
1500 memcpy(map
, vs_c
->qpu_insts
, vs_size
);
1501 memcpy(map
+ shader
->coord_shader_offset
,
1502 cs_c
->qpu_insts
, cs_size
);
1504 qir_compile_destroy(vs_c
);
1505 qir_compile_destroy(cs_c
);
1509 vc4_setup_shared_key(struct vc4_key
*key
, struct vc4_texture_stateobj
*texstate
)
1511 for (int i
= 0; i
< texstate
->num_textures
; i
++) {
1512 struct pipe_sampler_view
*sampler
= texstate
->textures
[i
];
1513 struct pipe_sampler_state
*sampler_state
=
1514 texstate
->samplers
[i
];
1517 struct pipe_resource
*prsc
= sampler
->texture
;
1518 key
->tex
[i
].format
= prsc
->format
;
1519 key
->tex
[i
].swizzle
[0] = sampler
->swizzle_r
;
1520 key
->tex
[i
].swizzle
[1] = sampler
->swizzle_g
;
1521 key
->tex
[i
].swizzle
[2] = sampler
->swizzle_b
;
1522 key
->tex
[i
].swizzle
[3] = sampler
->swizzle_a
;
1523 key
->tex
[i
].compare_mode
= sampler_state
->compare_mode
;
1524 key
->tex
[i
].compare_func
= sampler_state
->compare_func
;
1530 vc4_update_compiled_fs(struct vc4_context
*vc4
, uint8_t prim_mode
)
1532 struct vc4_fs_key local_key
;
1533 struct vc4_fs_key
*key
= &local_key
;
1535 memset(key
, 0, sizeof(*key
));
1536 vc4_setup_shared_key(&key
->base
, &vc4
->fragtex
);
1537 key
->base
.shader_state
= vc4
->prog
.bind_fs
;
1538 key
->is_points
= (prim_mode
== PIPE_PRIM_POINTS
);
1539 key
->is_lines
= (prim_mode
>= PIPE_PRIM_LINES
&&
1540 prim_mode
<= PIPE_PRIM_LINE_STRIP
);
1541 key
->blend
= vc4
->blend
->rt
[0];
1543 if (vc4
->framebuffer
.cbufs
[0])
1544 key
->color_format
= vc4
->framebuffer
.cbufs
[0]->format
;
1546 key
->depth_enabled
= vc4
->zsa
->base
.depth
.enabled
;
1548 vc4
->prog
.fs
= util_hash_table_get(vc4
->fs_cache
, key
);
1552 key
= malloc(sizeof(*key
));
1553 memcpy(key
, &local_key
, sizeof(*key
));
1555 struct vc4_compiled_shader
*shader
= CALLOC_STRUCT(vc4_compiled_shader
);
1556 vc4_fs_compile(vc4
, shader
, key
);
1557 util_hash_table_set(vc4
->fs_cache
, key
, shader
);
1559 vc4
->prog
.fs
= shader
;
1563 vc4_update_compiled_vs(struct vc4_context
*vc4
)
1565 struct vc4_vs_key local_key
;
1566 struct vc4_vs_key
*key
= &local_key
;
1568 memset(key
, 0, sizeof(*key
));
1569 vc4_setup_shared_key(&key
->base
, &vc4
->verttex
);
1570 key
->base
.shader_state
= vc4
->prog
.bind_vs
;
1572 for (int i
= 0; i
< ARRAY_SIZE(key
->attr_formats
); i
++)
1573 key
->attr_formats
[i
] = vc4
->vtx
->pipe
[i
].src_format
;
1575 vc4
->prog
.vs
= util_hash_table_get(vc4
->vs_cache
, key
);
1579 key
= malloc(sizeof(*key
));
1580 memcpy(key
, &local_key
, sizeof(*key
));
1582 struct vc4_compiled_shader
*shader
= CALLOC_STRUCT(vc4_compiled_shader
);
1583 vc4_vs_compile(vc4
, shader
, key
);
1584 util_hash_table_set(vc4
->vs_cache
, key
, shader
);
1586 vc4
->prog
.vs
= shader
;
1590 vc4_update_compiled_shaders(struct vc4_context
*vc4
, uint8_t prim_mode
)
1592 vc4_update_compiled_fs(vc4
, prim_mode
);
1593 vc4_update_compiled_vs(vc4
);
1597 fs_cache_hash(void *key
)
1599 return util_hash_crc32(key
, sizeof(struct vc4_fs_key
));
1603 vs_cache_hash(void *key
)
1605 return util_hash_crc32(key
, sizeof(struct vc4_vs_key
));
1609 fs_cache_compare(void *key1
, void *key2
)
1611 return memcmp(key1
, key2
, sizeof(struct vc4_fs_key
));
1615 vs_cache_compare(void *key1
, void *key2
)
1617 return memcmp(key1
, key2
, sizeof(struct vc4_vs_key
));
1620 struct delete_state
{
1621 struct vc4_context
*vc4
;
1622 struct pipe_shader_state
*shader_state
;
1625 static enum pipe_error
1626 fs_delete_from_cache(void *in_key
, void *in_value
, void *data
)
1628 struct delete_state
*del
= data
;
1629 struct vc4_fs_key
*key
= in_key
;
1630 struct vc4_compiled_shader
*shader
= in_value
;
1632 if (key
->base
.shader_state
== data
) {
1633 util_hash_table_remove(del
->vc4
->fs_cache
, key
);
1634 vc4_bo_unreference(&shader
->bo
);
1641 static enum pipe_error
1642 vs_delete_from_cache(void *in_key
, void *in_value
, void *data
)
1644 struct delete_state
*del
= data
;
1645 struct vc4_vs_key
*key
= in_key
;
1646 struct vc4_compiled_shader
*shader
= in_value
;
1648 if (key
->base
.shader_state
== data
) {
1649 util_hash_table_remove(del
->vc4
->vs_cache
, key
);
1650 vc4_bo_unreference(&shader
->bo
);
1658 vc4_shader_state_delete(struct pipe_context
*pctx
, void *hwcso
)
1660 struct vc4_context
*vc4
= vc4_context(pctx
);
1661 struct pipe_shader_state
*so
= hwcso
;
1662 struct delete_state del
;
1665 del
.shader_state
= so
;
1666 util_hash_table_foreach(vc4
->fs_cache
, fs_delete_from_cache
, &del
);
1667 util_hash_table_foreach(vc4
->vs_cache
, vs_delete_from_cache
, &del
);
1669 free((void *)so
->tokens
);
1673 static uint32_t translate_wrap(uint32_t p_wrap
)
1676 case PIPE_TEX_WRAP_REPEAT
:
1678 case PIPE_TEX_WRAP_CLAMP
:
1679 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1681 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1683 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1686 fprintf(stderr
, "Unknown wrap mode %d\n", p_wrap
);
1687 assert(!"not reached");
1693 write_texture_p0(struct vc4_context
*vc4
,
1694 struct vc4_texture_stateobj
*texstate
,
1697 struct pipe_sampler_view
*texture
= texstate
->textures
[unit
];
1698 struct vc4_resource
*rsc
= vc4_resource(texture
->texture
);
1700 cl_reloc(vc4
, &vc4
->uniforms
, rsc
->bo
,
1701 rsc
->slices
[0].offset
| texture
->u
.tex
.last_level
|
1702 ((rsc
->vc4_format
& 7) << 4));
1706 write_texture_p1(struct vc4_context
*vc4
,
1707 struct vc4_texture_stateobj
*texstate
,
1710 struct pipe_sampler_view
*texture
= texstate
->textures
[unit
];
1711 struct vc4_resource
*rsc
= vc4_resource(texture
->texture
);
1712 struct pipe_sampler_state
*sampler
= texstate
->samplers
[unit
];
1713 static const uint32_t mipfilter_map
[] = {
1714 [PIPE_TEX_MIPFILTER_NEAREST
] = 2,
1715 [PIPE_TEX_MIPFILTER_LINEAR
] = 4,
1716 [PIPE_TEX_MIPFILTER_NONE
] = 0
1718 static const uint32_t imgfilter_map
[] = {
1719 [PIPE_TEX_FILTER_NEAREST
] = 1,
1720 [PIPE_TEX_FILTER_LINEAR
] = 0,
1723 cl_u32(&vc4
->uniforms
,
1724 ((rsc
->vc4_format
>> 4) << 31) |
1725 (texture
->texture
->height0
<< 20) |
1726 (texture
->texture
->width0
<< 8) |
1727 (imgfilter_map
[sampler
->mag_img_filter
] << 7) |
1728 ((imgfilter_map
[sampler
->min_img_filter
] +
1729 mipfilter_map
[sampler
->min_mip_filter
]) << 4) |
1730 (translate_wrap(sampler
->wrap_t
) << 2) |
1731 (translate_wrap(sampler
->wrap_s
) << 0));
1735 get_texrect_scale(struct vc4_texture_stateobj
*texstate
,
1736 enum quniform_contents contents
,
1739 struct pipe_sampler_view
*texture
= texstate
->textures
[data
];
1742 if (contents
== QUNIFORM_TEXRECT_SCALE_X
)
1743 dim
= texture
->texture
->width0
;
1745 dim
= texture
->texture
->height0
;
1747 return fui(1.0f
/ dim
);
1751 vc4_write_uniforms(struct vc4_context
*vc4
, struct vc4_compiled_shader
*shader
,
1752 struct vc4_constbuf_stateobj
*cb
,
1753 struct vc4_texture_stateobj
*texstate
,
1756 struct vc4_shader_uniform_info
*uinfo
= &shader
->uniforms
[shader_index
];
1757 const uint32_t *gallium_uniforms
= cb
->cb
[0].user_buffer
;
1759 cl_start_shader_reloc(&vc4
->uniforms
, uinfo
->num_texture_samples
);
1761 for (int i
= 0; i
< uinfo
->count
; i
++) {
1763 switch (uinfo
->contents
[i
]) {
1764 case QUNIFORM_CONSTANT
:
1765 cl_u32(&vc4
->uniforms
, uinfo
->data
[i
]);
1767 case QUNIFORM_UNIFORM
:
1768 cl_u32(&vc4
->uniforms
,
1769 gallium_uniforms
[uinfo
->data
[i
]]);
1771 case QUNIFORM_VIEWPORT_X_SCALE
:
1772 cl_f(&vc4
->uniforms
, vc4
->viewport
.scale
[0] * 16.0f
);
1774 case QUNIFORM_VIEWPORT_Y_SCALE
:
1775 cl_f(&vc4
->uniforms
, vc4
->viewport
.scale
[1] * 16.0f
);
1778 case QUNIFORM_VIEWPORT_Z_OFFSET
:
1779 cl_f(&vc4
->uniforms
, vc4
->viewport
.translate
[2]);
1781 case QUNIFORM_VIEWPORT_Z_SCALE
:
1782 cl_f(&vc4
->uniforms
, vc4
->viewport
.scale
[2]);
1785 case QUNIFORM_TEXTURE_CONFIG_P0
:
1786 write_texture_p0(vc4
, texstate
, uinfo
->data
[i
]);
1789 case QUNIFORM_TEXTURE_CONFIG_P1
:
1790 write_texture_p1(vc4
, texstate
, uinfo
->data
[i
]);
1793 case QUNIFORM_TEXRECT_SCALE_X
:
1794 case QUNIFORM_TEXRECT_SCALE_Y
:
1795 cl_u32(&vc4
->uniforms
,
1796 get_texrect_scale(texstate
,
1801 case QUNIFORM_BLEND_CONST_COLOR
:
1802 cl_f(&vc4
->uniforms
,
1803 vc4
->blend_color
.color
[uinfo
->data
[i
]]);
1807 uint32_t written_val
= *(uint32_t *)(vc4
->uniforms
.next
- 4);
1808 fprintf(stderr
, "%p/%d: %d: 0x%08x (%f)\n",
1809 shader
, shader_index
, i
, written_val
, uif(written_val
));
1815 vc4_fp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
1817 struct vc4_context
*vc4
= vc4_context(pctx
);
1818 vc4
->prog
.bind_fs
= hwcso
;
1819 vc4
->prog
.dirty
|= VC4_SHADER_DIRTY_FP
;
1820 vc4
->dirty
|= VC4_DIRTY_PROG
;
1824 vc4_vp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
1826 struct vc4_context
*vc4
= vc4_context(pctx
);
1827 vc4
->prog
.bind_vs
= hwcso
;
1828 vc4
->prog
.dirty
|= VC4_SHADER_DIRTY_VP
;
1829 vc4
->dirty
|= VC4_DIRTY_PROG
;
1833 vc4_program_init(struct pipe_context
*pctx
)
1835 struct vc4_context
*vc4
= vc4_context(pctx
);
1837 pctx
->create_vs_state
= vc4_shader_state_create
;
1838 pctx
->delete_vs_state
= vc4_shader_state_delete
;
1840 pctx
->create_fs_state
= vc4_shader_state_create
;
1841 pctx
->delete_fs_state
= vc4_shader_state_delete
;
1843 pctx
->bind_fs_state
= vc4_fp_state_bind
;
1844 pctx
->bind_vs_state
= vc4_vp_state_bind
;
1846 vc4
->fs_cache
= util_hash_table_create(fs_cache_hash
, fs_cache_compare
);
1847 vc4
->vs_cache
= util_hash_table_create(vs_cache_hash
, vs_cache_compare
);