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vc4: Add support for 8-bit unorm/snorm vertex inputs.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "util/ralloc.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_info.h"
34
35 #include "vc4_context.h"
36 #include "vc4_qpu.h"
37 #include "vc4_qir.h"
38 #ifdef USE_VC4_SIMULATOR
39 #include "simpenrose/simpenrose.h"
40 #endif
41
42 struct vc4_key {
43 struct pipe_shader_state *shader_state;
44 struct {
45 enum pipe_format format;
46 unsigned compare_mode:1;
47 unsigned compare_func:3;
48 uint8_t swizzle[4];
49 } tex[VC4_MAX_TEXTURE_SAMPLERS];
50 };
51
52 struct vc4_fs_key {
53 struct vc4_key base;
54 enum pipe_format color_format;
55 bool depth_enabled;
56 bool stencil_enabled;
57 bool stencil_twoside;
58 bool stencil_full_writemasks;
59 bool is_points;
60 bool is_lines;
61
62 struct pipe_rt_blend_state blend;
63 };
64
65 struct vc4_vs_key {
66 struct vc4_key base;
67 enum pipe_format attr_formats[8];
68 };
69
70 static void
71 resize_qreg_array(struct vc4_compile *c,
72 struct qreg **regs,
73 uint32_t *size,
74 uint32_t decl_size)
75 {
76 if (*size >= decl_size)
77 return;
78
79 uint32_t old_size = *size;
80 *size = MAX2(*size * 2, decl_size);
81 *regs = reralloc(c, *regs, struct qreg, *size);
82 if (!*regs) {
83 fprintf(stderr, "Malloc failure\n");
84 abort();
85 }
86
87 for (uint32_t i = old_size; i < *size; i++)
88 (*regs)[i] = c->undef;
89 }
90
91 static struct qreg
92 add_uniform(struct vc4_compile *c,
93 enum quniform_contents contents,
94 uint32_t data)
95 {
96 uint32_t uniform = c->num_uniforms++;
97 struct qreg u = { QFILE_UNIF, uniform };
98
99 c->uniform_contents[uniform] = contents;
100 c->uniform_data[uniform] = data;
101
102 return u;
103 }
104
105 static struct qreg
106 get_temp_for_uniform(struct vc4_compile *c, enum quniform_contents contents,
107 uint32_t data)
108 {
109 for (int i = 0; i < c->num_uniforms; i++) {
110 if (c->uniform_contents[i] == contents &&
111 c->uniform_data[i] == data)
112 return c->uniforms[i];
113 }
114
115 struct qreg u = add_uniform(c, contents, data);
116 struct qreg t = qir_MOV(c, u);
117
118 resize_qreg_array(c, &c->uniforms, &c->uniforms_array_size,
119 u.index + 1);
120
121 c->uniforms[u.index] = t;
122 return t;
123 }
124
125 static struct qreg
126 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
127 {
128 return get_temp_for_uniform(c, QUNIFORM_CONSTANT, ui);
129 }
130
131 static struct qreg
132 qir_uniform_f(struct vc4_compile *c, float f)
133 {
134 return qir_uniform_ui(c, fui(f));
135 }
136
137 static struct qreg
138 get_src(struct vc4_compile *c, unsigned tgsi_op,
139 struct tgsi_src_register *src, int i)
140 {
141 struct qreg r = c->undef;
142
143 uint32_t s = i;
144 switch (i) {
145 case TGSI_SWIZZLE_X:
146 s = src->SwizzleX;
147 break;
148 case TGSI_SWIZZLE_Y:
149 s = src->SwizzleY;
150 break;
151 case TGSI_SWIZZLE_Z:
152 s = src->SwizzleZ;
153 break;
154 case TGSI_SWIZZLE_W:
155 s = src->SwizzleW;
156 break;
157 default:
158 abort();
159 }
160
161 assert(!src->Indirect);
162
163 switch (src->File) {
164 case TGSI_FILE_NULL:
165 return r;
166 case TGSI_FILE_TEMPORARY:
167 r = c->temps[src->Index * 4 + s];
168 break;
169 case TGSI_FILE_IMMEDIATE:
170 r = c->consts[src->Index * 4 + s];
171 break;
172 case TGSI_FILE_CONSTANT:
173 r = get_temp_for_uniform(c, QUNIFORM_UNIFORM,
174 src->Index * 4 + s);
175 break;
176 case TGSI_FILE_INPUT:
177 r = c->inputs[src->Index * 4 + s];
178 break;
179 case TGSI_FILE_SAMPLER:
180 case TGSI_FILE_SAMPLER_VIEW:
181 r = c->undef;
182 break;
183 default:
184 fprintf(stderr, "unknown src file %d\n", src->File);
185 abort();
186 }
187
188 if (src->Absolute)
189 r = qir_FMAXABS(c, r, r);
190
191 if (src->Negate) {
192 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
193 case TGSI_TYPE_SIGNED:
194 case TGSI_TYPE_UNSIGNED:
195 r = qir_SUB(c, qir_uniform_ui(c, 0), r);
196 break;
197 default:
198 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);
199 break;
200 }
201 }
202
203 return r;
204 };
205
206
207 static void
208 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,
209 int i, struct qreg val)
210 {
211 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
212
213 assert(!tgsi_dst->Indirect);
214
215 switch (tgsi_dst->File) {
216 case TGSI_FILE_TEMPORARY:
217 c->temps[tgsi_dst->Index * 4 + i] = val;
218 break;
219 case TGSI_FILE_OUTPUT:
220 c->outputs[tgsi_dst->Index * 4 + i] = val;
221 c->num_outputs = MAX2(c->num_outputs,
222 tgsi_dst->Index * 4 + i + 1);
223 break;
224 default:
225 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
226 abort();
227 }
228 };
229
230 static struct qreg
231 get_swizzled_channel(struct vc4_compile *c,
232 struct qreg *srcs, int swiz)
233 {
234 switch (swiz) {
235 default:
236 case UTIL_FORMAT_SWIZZLE_NONE:
237 fprintf(stderr, "warning: unknown swizzle\n");
238 /* FALLTHROUGH */
239 case UTIL_FORMAT_SWIZZLE_0:
240 return qir_uniform_f(c, 0.0);
241 case UTIL_FORMAT_SWIZZLE_1:
242 return qir_uniform_f(c, 1.0);
243 case UTIL_FORMAT_SWIZZLE_X:
244 case UTIL_FORMAT_SWIZZLE_Y:
245 case UTIL_FORMAT_SWIZZLE_Z:
246 case UTIL_FORMAT_SWIZZLE_W:
247 return srcs[swiz];
248 }
249 }
250
251 static struct qreg
252 tgsi_to_qir_alu(struct vc4_compile *c,
253 struct tgsi_full_instruction *tgsi_inst,
254 enum qop op, struct qreg *src, int i)
255 {
256 struct qreg dst = qir_get_temp(c);
257 qir_emit(c, qir_inst4(op, dst,
258 src[0 * 4 + i],
259 src[1 * 4 + i],
260 src[2 * 4 + i],
261 c->undef));
262 return dst;
263 }
264
265 static struct qreg
266 tgsi_to_qir_umul(struct vc4_compile *c,
267 struct tgsi_full_instruction *tgsi_inst,
268 enum qop op, struct qreg *src, int i)
269 {
270 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],
271 qir_uniform_ui(c, 16));
272 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],
273 qir_uniform_ui(c, 0xffff));
274 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],
275 qir_uniform_ui(c, 16));
276 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],
277 qir_uniform_ui(c, 0xffff));
278
279 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);
280 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);
281 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);
282
283 return qir_ADD(c, lolo, qir_SHL(c,
284 qir_ADD(c, hilo, lohi),
285 qir_uniform_ui(c, 16)));
286 }
287
288 static struct qreg
289 tgsi_to_qir_idiv(struct vc4_compile *c,
290 struct tgsi_full_instruction *tgsi_inst,
291 enum qop op, struct qreg *src, int i)
292 {
293 return qir_FTOI(c, qir_FMUL(c,
294 qir_ITOF(c, src[0 * 4 + i]),
295 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
296 }
297
298 static struct qreg
299 tgsi_to_qir_ineg(struct vc4_compile *c,
300 struct tgsi_full_instruction *tgsi_inst,
301 enum qop op, struct qreg *src, int i)
302 {
303 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);
304 }
305
306 static struct qreg
307 tgsi_to_qir_seq(struct vc4_compile *c,
308 struct tgsi_full_instruction *tgsi_inst,
309 enum qop op, struct qreg *src, int i)
310 {
311 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
312 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
313 }
314
315 static struct qreg
316 tgsi_to_qir_sne(struct vc4_compile *c,
317 struct tgsi_full_instruction *tgsi_inst,
318 enum qop op, struct qreg *src, int i)
319 {
320 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
321 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
322 }
323
324 static struct qreg
325 tgsi_to_qir_slt(struct vc4_compile *c,
326 struct tgsi_full_instruction *tgsi_inst,
327 enum qop op, struct qreg *src, int i)
328 {
329 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
330 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
331 }
332
333 static struct qreg
334 tgsi_to_qir_sge(struct vc4_compile *c,
335 struct tgsi_full_instruction *tgsi_inst,
336 enum qop op, struct qreg *src, int i)
337 {
338 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
339 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
340 }
341
342 static struct qreg
343 tgsi_to_qir_fseq(struct vc4_compile *c,
344 struct tgsi_full_instruction *tgsi_inst,
345 enum qop op, struct qreg *src, int i)
346 {
347 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
348 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
349 }
350
351 static struct qreg
352 tgsi_to_qir_fsne(struct vc4_compile *c,
353 struct tgsi_full_instruction *tgsi_inst,
354 enum qop op, struct qreg *src, int i)
355 {
356 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
357 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
358 }
359
360 static struct qreg
361 tgsi_to_qir_fslt(struct vc4_compile *c,
362 struct tgsi_full_instruction *tgsi_inst,
363 enum qop op, struct qreg *src, int i)
364 {
365 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
366 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
367 }
368
369 static struct qreg
370 tgsi_to_qir_fsge(struct vc4_compile *c,
371 struct tgsi_full_instruction *tgsi_inst,
372 enum qop op, struct qreg *src, int i)
373 {
374 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
375 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
376 }
377
378 static struct qreg
379 tgsi_to_qir_useq(struct vc4_compile *c,
380 struct tgsi_full_instruction *tgsi_inst,
381 enum qop op, struct qreg *src, int i)
382 {
383 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
384 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
385 }
386
387 static struct qreg
388 tgsi_to_qir_usne(struct vc4_compile *c,
389 struct tgsi_full_instruction *tgsi_inst,
390 enum qop op, struct qreg *src, int i)
391 {
392 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
393 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
394 }
395
396 static struct qreg
397 tgsi_to_qir_islt(struct vc4_compile *c,
398 struct tgsi_full_instruction *tgsi_inst,
399 enum qop op, struct qreg *src, int i)
400 {
401 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
402 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
403 }
404
405 static struct qreg
406 tgsi_to_qir_isge(struct vc4_compile *c,
407 struct tgsi_full_instruction *tgsi_inst,
408 enum qop op, struct qreg *src, int i)
409 {
410 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
411 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
412 }
413
414 static struct qreg
415 tgsi_to_qir_cmp(struct vc4_compile *c,
416 struct tgsi_full_instruction *tgsi_inst,
417 enum qop op, struct qreg *src, int i)
418 {
419 qir_SF(c, src[0 * 4 + i]);
420 return qir_SEL_X_Y_NS(c,
421 src[1 * 4 + i],
422 src[2 * 4 + i]);
423 }
424
425 static struct qreg
426 tgsi_to_qir_mad(struct vc4_compile *c,
427 struct tgsi_full_instruction *tgsi_inst,
428 enum qop op, struct qreg *src, int i)
429 {
430 return qir_FADD(c,
431 qir_FMUL(c,
432 src[0 * 4 + i],
433 src[1 * 4 + i]),
434 src[2 * 4 + i]);
435 }
436
437 static struct qreg
438 tgsi_to_qir_lit(struct vc4_compile *c,
439 struct tgsi_full_instruction *tgsi_inst,
440 enum qop op, struct qreg *src, int i)
441 {
442 struct qreg x = src[0 * 4 + 0];
443 struct qreg y = src[0 * 4 + 1];
444 struct qreg w = src[0 * 4 + 3];
445
446 switch (i) {
447 case 0:
448 case 3:
449 return qir_uniform_f(c, 1.0);
450 case 1:
451 return qir_FMAX(c, src[0 * 4 + 0], qir_uniform_f(c, 0.0));
452 case 2: {
453 struct qreg zero = qir_uniform_f(c, 0.0);
454
455 qir_SF(c, x);
456 /* XXX: Clamp w to -128..128 */
457 return qir_SEL_X_0_NC(c,
458 qir_EXP2(c, qir_FMUL(c,
459 w,
460 qir_LOG2(c,
461 qir_FMAX(c,
462 y,
463 zero)))));
464 }
465 default:
466 assert(!"not reached");
467 return c->undef;
468 }
469 }
470
471 static struct qreg
472 tgsi_to_qir_lrp(struct vc4_compile *c,
473 struct tgsi_full_instruction *tgsi_inst,
474 enum qop op, struct qreg *src, int i)
475 {
476 struct qreg src0 = src[0 * 4 + i];
477 struct qreg src1 = src[1 * 4 + i];
478 struct qreg src2 = src[2 * 4 + i];
479
480 /* LRP is:
481 * src0 * src1 + (1 - src0) * src2.
482 * -> src0 * src1 + src2 - src0 * src2
483 * -> src2 + src0 * (src1 - src2)
484 */
485 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
486
487 }
488
489 static void
490 tgsi_to_qir_tex(struct vc4_compile *c,
491 struct tgsi_full_instruction *tgsi_inst,
492 enum qop op, struct qreg *src)
493 {
494 assert(!tgsi_inst->Instruction.Saturate);
495
496 struct qreg s = src[0 * 4 + 0];
497 struct qreg t = src[0 * 4 + 1];
498 uint32_t unit = tgsi_inst->Src[1].Register.Index;
499
500 struct qreg proj = c->undef;
501 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
502 proj = qir_RCP(c, src[0 * 4 + 3]);
503 s = qir_FMUL(c, s, proj);
504 t = qir_FMUL(c, t, proj);
505 }
506
507 /* There is no native support for GL texture rectangle coordinates, so
508 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
509 * 1]).
510 */
511 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT ||
512 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
513 s = qir_FMUL(c, s,
514 get_temp_for_uniform(c,
515 QUNIFORM_TEXRECT_SCALE_X,
516 unit));
517 t = qir_FMUL(c, t,
518 get_temp_for_uniform(c,
519 QUNIFORM_TEXRECT_SCALE_Y,
520 unit));
521 }
522
523 qir_TEX_T(c, t, add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit));
524
525 struct qreg sampler_p1 = add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1,
526 unit);
527 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
528 qir_TEX_B(c, src[0 * 4 + 3], sampler_p1);
529 qir_TEX_S(c, s, add_uniform(c, QUNIFORM_CONSTANT, 0));
530 } else {
531 qir_TEX_S(c, s, sampler_p1);
532 }
533
534 c->num_texture_samples++;
535 struct qreg r4 = qir_TEX_RESULT(c);
536
537 enum pipe_format format = c->key->tex[unit].format;
538
539 struct qreg unpacked[4];
540 if (util_format_is_depth_or_stencil(format)) {
541 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
542 qir_uniform_ui(c, 8)));
543 struct qreg normalized = qir_FMUL(c, depthf,
544 qir_uniform_f(c, 1.0f/0xffffff));
545
546 struct qreg depth_output;
547
548 struct qreg compare = src[0 * 4 + 2];
549
550 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP)
551 compare = qir_FMUL(c, compare, proj);
552
553 struct qreg one = qir_uniform_f(c, 1.0f);
554 if (c->key->tex[unit].compare_mode) {
555 switch (c->key->tex[unit].compare_func) {
556 case PIPE_FUNC_NEVER:
557 depth_output = qir_uniform_f(c, 0.0f);
558 break;
559 case PIPE_FUNC_ALWAYS:
560 depth_output = one;
561 break;
562 case PIPE_FUNC_EQUAL:
563 qir_SF(c, qir_FSUB(c, compare, normalized));
564 depth_output = qir_SEL_X_0_ZS(c, one);
565 break;
566 case PIPE_FUNC_NOTEQUAL:
567 qir_SF(c, qir_FSUB(c, compare, normalized));
568 depth_output = qir_SEL_X_0_ZC(c, one);
569 break;
570 case PIPE_FUNC_GREATER:
571 qir_SF(c, qir_FSUB(c, compare, normalized));
572 depth_output = qir_SEL_X_0_NC(c, one);
573 break;
574 case PIPE_FUNC_GEQUAL:
575 qir_SF(c, qir_FSUB(c, normalized, compare));
576 depth_output = qir_SEL_X_0_NS(c, one);
577 break;
578 case PIPE_FUNC_LESS:
579 qir_SF(c, qir_FSUB(c, compare, normalized));
580 depth_output = qir_SEL_X_0_NS(c, one);
581 break;
582 case PIPE_FUNC_LEQUAL:
583 qir_SF(c, qir_FSUB(c, normalized, compare));
584 depth_output = qir_SEL_X_0_NC(c, one);
585 break;
586 }
587 } else {
588 depth_output = normalized;
589 }
590
591 for (int i = 0; i < 4; i++)
592 unpacked[i] = depth_output;
593 } else {
594 for (int i = 0; i < 4; i++)
595 unpacked[i] = qir_R4_UNPACK(c, r4, i);
596 }
597
598 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
599 uint8_t swiz[4];
600 util_format_compose_swizzles(format_swiz, c->key->tex[unit].swizzle, swiz);
601 for (int i = 0; i < 4; i++) {
602 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
603 continue;
604
605 update_dst(c, tgsi_inst, i,
606 get_swizzled_channel(c, unpacked, swiz[i]));
607 }
608 }
609
610 static struct qreg
611 tgsi_to_qir_pow(struct vc4_compile *c,
612 struct tgsi_full_instruction *tgsi_inst,
613 enum qop op, struct qreg *src, int i)
614 {
615 /* Note that this instruction replicates its result from the x channel
616 */
617 return qir_EXP2(c, qir_FMUL(c,
618 src[1 * 4 + 0],
619 qir_LOG2(c, src[0 * 4 + 0])));
620 }
621
622 static struct qreg
623 tgsi_to_qir_trunc(struct vc4_compile *c,
624 struct tgsi_full_instruction *tgsi_inst,
625 enum qop op, struct qreg *src, int i)
626 {
627 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
628 }
629
630 /**
631 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
632 * to zero).
633 */
634 static struct qreg
635 tgsi_to_qir_frc(struct vc4_compile *c,
636 struct tgsi_full_instruction *tgsi_inst,
637 enum qop op, struct qreg *src, int i)
638 {
639 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
640 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
641 qir_SF(c, diff);
642 return qir_SEL_X_Y_NS(c,
643 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
644 diff);
645 }
646
647 /**
648 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
649 * zero).
650 */
651 static struct qreg
652 tgsi_to_qir_flr(struct vc4_compile *c,
653 struct tgsi_full_instruction *tgsi_inst,
654 enum qop op, struct qreg *src, int i)
655 {
656 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
657
658 /* This will be < 0 if we truncated and the truncation was of a value
659 * that was < 0 in the first place.
660 */
661 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
662
663 return qir_SEL_X_Y_NS(c,
664 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
665 trunc);
666 }
667
668 static struct qreg
669 tgsi_to_qir_dp(struct vc4_compile *c,
670 struct tgsi_full_instruction *tgsi_inst,
671 int num, struct qreg *src, int i)
672 {
673 struct qreg sum = qir_FMUL(c, src[0 * 4 + 0], src[1 * 4 + 0]);
674 for (int j = 1; j < num; j++) {
675 sum = qir_FADD(c, sum, qir_FMUL(c,
676 src[0 * 4 + j],
677 src[1 * 4 + j]));
678 }
679 return sum;
680 }
681
682 static struct qreg
683 tgsi_to_qir_dp2(struct vc4_compile *c,
684 struct tgsi_full_instruction *tgsi_inst,
685 enum qop op, struct qreg *src, int i)
686 {
687 return tgsi_to_qir_dp(c, tgsi_inst, 2, src, i);
688 }
689
690 static struct qreg
691 tgsi_to_qir_dp3(struct vc4_compile *c,
692 struct tgsi_full_instruction *tgsi_inst,
693 enum qop op, struct qreg *src, int i)
694 {
695 return tgsi_to_qir_dp(c, tgsi_inst, 3, src, i);
696 }
697
698 static struct qreg
699 tgsi_to_qir_dp4(struct vc4_compile *c,
700 struct tgsi_full_instruction *tgsi_inst,
701 enum qop op, struct qreg *src, int i)
702 {
703 return tgsi_to_qir_dp(c, tgsi_inst, 4, src, i);
704 }
705
706 static struct qreg
707 tgsi_to_qir_abs(struct vc4_compile *c,
708 struct tgsi_full_instruction *tgsi_inst,
709 enum qop op, struct qreg *src, int i)
710 {
711 struct qreg arg = src[0 * 4 + i];
712 return qir_FMAXABS(c, arg, arg);
713 }
714
715 /* Note that this instruction replicates its result from the x channel */
716 static struct qreg
717 tgsi_to_qir_sin(struct vc4_compile *c,
718 struct tgsi_full_instruction *tgsi_inst,
719 enum qop op, struct qreg *src, int i)
720 {
721 float coeff[] = {
722 2.0 * M_PI,
723 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
724 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
725 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
726 };
727
728 struct qreg scaled_x =
729 qir_FMUL(c,
730 src[0 * 4 + 0],
731 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
732
733
734 struct qreg x = tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0);
735 struct qreg x2 = qir_FMUL(c, x, x);
736 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
737 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
738 x = qir_FMUL(c, x, x2);
739 sum = qir_FADD(c,
740 sum,
741 qir_FMUL(c,
742 x,
743 qir_uniform_f(c, coeff[i])));
744 }
745 return sum;
746 }
747
748 /* Note that this instruction replicates its result from the x channel */
749 static struct qreg
750 tgsi_to_qir_cos(struct vc4_compile *c,
751 struct tgsi_full_instruction *tgsi_inst,
752 enum qop op, struct qreg *src, int i)
753 {
754 float coeff[] = {
755 1.0f,
756 -pow(2.0 * M_PI, 2) / (2 * 1),
757 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
758 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
759 };
760
761 struct qreg scaled_x =
762 qir_FMUL(c, src[0 * 4 + 0],
763 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
764 struct qreg x_frac = tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0);
765
766 struct qreg sum = qir_uniform_f(c, coeff[0]);
767 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
768 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
769 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
770 if (i != 1)
771 x = qir_FMUL(c, x, x2);
772
773 struct qreg mul = qir_FMUL(c,
774 x,
775 qir_uniform_f(c, coeff[i]));
776 if (i == 0)
777 sum = mul;
778 else
779 sum = qir_FADD(c, sum, mul);
780 }
781 return sum;
782 }
783
784 static void
785 emit_vertex_input(struct vc4_compile *c, int attr)
786 {
787 enum pipe_format format = c->vs_key->attr_formats[attr];
788 struct qreg vpm_reads[4];
789
790 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
791 * time, so we always read 4 32-bit VPM entries.
792 */
793 for (int i = 0; i < 4; i++) {
794 vpm_reads[i] = qir_get_temp(c);
795 qir_emit(c, qir_inst(QOP_VPM_READ,
796 vpm_reads[i],
797 c->undef,
798 c->undef));
799 c->num_inputs++;
800 }
801
802 bool format_warned = false;
803 const struct util_format_description *desc =
804 util_format_description(format);
805
806 for (int i = 0; i < 4; i++) {
807 uint8_t swiz = desc->swizzle[i];
808 struct qreg result;
809
810 if (swiz > UTIL_FORMAT_SWIZZLE_W)
811 result = get_swizzled_channel(c, vpm_reads, swiz);
812 else if (desc->channel[swiz].size == 32 &&
813 desc->channel[swiz].type == UTIL_FORMAT_TYPE_FLOAT) {
814 result = get_swizzled_channel(c, vpm_reads, swiz);
815 } else if (desc->channel[swiz].size == 8 &&
816 (desc->channel[swiz].type == UTIL_FORMAT_TYPE_UNSIGNED ||
817 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) &&
818 desc->channel[swiz].normalized) {
819 struct qreg vpm = vpm_reads[0];
820 if (desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED)
821 vpm = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
822 result = qir_UNPACK_8(c, vpm, swiz);
823 } else {
824 if (!format_warned) {
825 fprintf(stderr,
826 "vtx element %d unsupported type: %s\n",
827 attr, util_format_name(format));
828 format_warned = true;
829 }
830 result = qir_uniform_f(c, 0.0);
831 }
832
833 if (desc->channel[swiz].normalized &&
834 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) {
835 result = qir_FSUB(c,
836 qir_FMUL(c,
837 result,
838 qir_uniform_f(c, 2.0)),
839 qir_uniform_f(c, 1.0));
840 }
841
842 c->inputs[attr * 4 + i] = result;
843 }
844 }
845
846 static void
847 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)
848 {
849 if (c->discard.file == QFILE_NULL)
850 c->discard = qir_uniform_f(c, 0.0);
851 qir_SF(c, src[0 * 4 + i]);
852 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
853 c->discard);
854 }
855
856 static void
857 emit_fragcoord_input(struct vc4_compile *c, int attr)
858 {
859 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
860 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
861 c->inputs[attr * 4 + 2] =
862 qir_FMUL(c,
863 qir_ITOF(c, qir_FRAG_Z(c)),
864 qir_uniform_f(c, 1.0 / 0xffffff));
865 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
866 }
867
868 static struct qreg
869 emit_fragment_varying(struct vc4_compile *c, int index)
870 {
871 struct qreg vary = {
872 QFILE_VARY,
873 index
874 };
875
876 /* XXX: multiply by W */
877 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
878 }
879
880 static void
881 emit_fragment_input(struct vc4_compile *c, int attr)
882 {
883 for (int i = 0; i < 4; i++) {
884 c->inputs[attr * 4 + i] =
885 emit_fragment_varying(c, attr * 4 + i);
886 c->num_inputs++;
887 }
888 }
889
890 static void
891 emit_tgsi_declaration(struct vc4_compile *c,
892 struct tgsi_full_declaration *decl)
893 {
894 switch (decl->Declaration.File) {
895 case TGSI_FILE_TEMPORARY:
896 resize_qreg_array(c, &c->temps, &c->temps_array_size,
897 (decl->Range.Last + 1) * 4);
898 break;
899
900 case TGSI_FILE_INPUT:
901 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
902 (decl->Range.Last + 1) * 4);
903
904 for (int i = decl->Range.First;
905 i <= decl->Range.Last;
906 i++) {
907 if (c->stage == QSTAGE_FRAG) {
908 if (decl->Semantic.Name ==
909 TGSI_SEMANTIC_POSITION) {
910 emit_fragcoord_input(c, i);
911 } else {
912 emit_fragment_input(c, i);
913 }
914 } else {
915 emit_vertex_input(c, i);
916 }
917 }
918 break;
919
920 case TGSI_FILE_OUTPUT:
921 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
922 (decl->Range.Last + 1) * 4);
923
924 switch (decl->Semantic.Name) {
925 case TGSI_SEMANTIC_POSITION:
926 c->output_position_index = decl->Range.First * 4;
927 break;
928 case TGSI_SEMANTIC_COLOR:
929 c->output_color_index = decl->Range.First * 4;
930 break;
931 }
932
933 break;
934 }
935 }
936
937 static void
938 emit_tgsi_instruction(struct vc4_compile *c,
939 struct tgsi_full_instruction *tgsi_inst)
940 {
941 struct {
942 enum qop op;
943 struct qreg (*func)(struct vc4_compile *c,
944 struct tgsi_full_instruction *tgsi_inst,
945 enum qop op,
946 struct qreg *src, int i);
947 } op_trans[] = {
948 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
949 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
950 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
951 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
952 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
953 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
954 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
955 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
956 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
957 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
958 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
959 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
960 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
961 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
962 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
963 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
964 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
965 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
966 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
967
968 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
969 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
970 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
971
972 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
973 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
974 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
975 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
976 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
977 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
978 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
979 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
980 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
981 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
982 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
983 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
984 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
985
986 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
987 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
988 [TGSI_OPCODE_DP2] = { 0, tgsi_to_qir_dp2 },
989 [TGSI_OPCODE_DP3] = { 0, tgsi_to_qir_dp3 },
990 [TGSI_OPCODE_DP4] = { 0, tgsi_to_qir_dp4 },
991 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_alu },
992 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
993 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_alu },
994 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_alu },
995 [TGSI_OPCODE_LIT] = { 0, tgsi_to_qir_lit },
996 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
997 [TGSI_OPCODE_POW] = { 0, tgsi_to_qir_pow },
998 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
999 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
1000 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
1001 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
1002 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
1003 };
1004 static int asdf = 0;
1005 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
1006
1007 if (tgsi_op == TGSI_OPCODE_END)
1008 return;
1009
1010 struct qreg src_regs[12];
1011 for (int s = 0; s < 3; s++) {
1012 for (int i = 0; i < 4; i++) {
1013 src_regs[4 * s + i] =
1014 get_src(c, tgsi_inst->Instruction.Opcode,
1015 &tgsi_inst->Src[s].Register, i);
1016 }
1017 }
1018
1019 switch (tgsi_op) {
1020 case TGSI_OPCODE_TEX:
1021 case TGSI_OPCODE_TXP:
1022 case TGSI_OPCODE_TXB:
1023 tgsi_to_qir_tex(c, tgsi_inst,
1024 op_trans[tgsi_op].op, src_regs);
1025 return;
1026 case TGSI_OPCODE_KILL:
1027 c->discard = qir_uniform_f(c, 1.0);
1028 return;
1029 case TGSI_OPCODE_KILL_IF:
1030 for (int i = 0; i < 4; i++)
1031 tgsi_to_qir_kill_if(c, src_regs, i);
1032 return;
1033 default:
1034 break;
1035 }
1036
1037 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
1038 fprintf(stderr, "unknown tgsi inst: ");
1039 tgsi_dump_instruction(tgsi_inst, asdf++);
1040 fprintf(stderr, "\n");
1041 abort();
1042 }
1043
1044 for (int i = 0; i < 4; i++) {
1045 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
1046 continue;
1047
1048 struct qreg result;
1049
1050 result = op_trans[tgsi_op].func(c, tgsi_inst,
1051 op_trans[tgsi_op].op,
1052 src_regs, i);
1053
1054 if (tgsi_inst->Instruction.Saturate) {
1055 float low = (tgsi_inst->Instruction.Saturate ==
1056 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
1057 result = qir_FMAX(c,
1058 qir_FMIN(c,
1059 result,
1060 qir_uniform_f(c, 1.0)),
1061 qir_uniform_f(c, low));
1062 }
1063
1064 update_dst(c, tgsi_inst, i, result);
1065 }
1066 }
1067
1068 static void
1069 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)
1070 {
1071 for (int i = 0; i < 4; i++) {
1072 unsigned n = c->num_consts++;
1073 resize_qreg_array(c, &c->consts, &c->consts_array_size, n + 1);
1074 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);
1075 }
1076 }
1077
1078 static struct qreg
1079 vc4_blend_channel(struct vc4_compile *c,
1080 struct qreg *dst,
1081 struct qreg *src,
1082 struct qreg val,
1083 unsigned factor,
1084 int channel)
1085 {
1086 switch(factor) {
1087 case PIPE_BLENDFACTOR_ONE:
1088 return val;
1089 case PIPE_BLENDFACTOR_SRC_COLOR:
1090 return qir_FMUL(c, val, src[channel]);
1091 case PIPE_BLENDFACTOR_SRC_ALPHA:
1092 return qir_FMUL(c, val, src[3]);
1093 case PIPE_BLENDFACTOR_DST_ALPHA:
1094 return qir_FMUL(c, val, dst[3]);
1095 case PIPE_BLENDFACTOR_DST_COLOR:
1096 return qir_FMUL(c, val, dst[channel]);
1097 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1098 return qir_FMIN(c, src[3], qir_FSUB(c,
1099 qir_uniform_f(c, 1.0),
1100 dst[3]));
1101 case PIPE_BLENDFACTOR_CONST_COLOR:
1102 return qir_FMUL(c, val,
1103 get_temp_for_uniform(c,
1104 QUNIFORM_BLEND_CONST_COLOR,
1105 channel));
1106 case PIPE_BLENDFACTOR_CONST_ALPHA:
1107 return qir_FMUL(c, val,
1108 get_temp_for_uniform(c,
1109 QUNIFORM_BLEND_CONST_COLOR,
1110 3));
1111 case PIPE_BLENDFACTOR_ZERO:
1112 return qir_uniform_f(c, 0.0);
1113 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1114 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1115 src[channel]));
1116 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1117 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1118 src[3]));
1119 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1120 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1121 dst[3]));
1122 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1123 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1124 dst[channel]));
1125 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1126 return qir_FMUL(c, val,
1127 qir_FSUB(c, qir_uniform_f(c, 1.0),
1128 get_temp_for_uniform(c,
1129 QUNIFORM_BLEND_CONST_COLOR,
1130 channel)));
1131 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1132 return qir_FMUL(c, val,
1133 qir_FSUB(c, qir_uniform_f(c, 1.0),
1134 get_temp_for_uniform(c,
1135 QUNIFORM_BLEND_CONST_COLOR,
1136 3)));
1137
1138 default:
1139 case PIPE_BLENDFACTOR_SRC1_COLOR:
1140 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1141 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1142 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1143 /* Unsupported. */
1144 fprintf(stderr, "Unknown blend factor %d\n", factor);
1145 return val;
1146 }
1147 }
1148
1149 static struct qreg
1150 vc4_blend_func(struct vc4_compile *c,
1151 struct qreg src, struct qreg dst,
1152 unsigned func)
1153 {
1154 switch (func) {
1155 case PIPE_BLEND_ADD:
1156 return qir_FADD(c, src, dst);
1157 case PIPE_BLEND_SUBTRACT:
1158 return qir_FSUB(c, src, dst);
1159 case PIPE_BLEND_REVERSE_SUBTRACT:
1160 return qir_FSUB(c, dst, src);
1161 case PIPE_BLEND_MIN:
1162 return qir_FMIN(c, src, dst);
1163 case PIPE_BLEND_MAX:
1164 return qir_FMAX(c, src, dst);
1165
1166 default:
1167 /* Unsupported. */
1168 fprintf(stderr, "Unknown blend func %d\n", func);
1169 return src;
1170
1171 }
1172 }
1173
1174 /**
1175 * Implements fixed function blending in shader code.
1176 *
1177 * VC4 doesn't have any hardware support for blending. Instead, you read the
1178 * current contents of the destination from the tile buffer after having
1179 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1180 * math using your output color and that destination value, and update the
1181 * output color appropriately.
1182 */
1183 static void
1184 vc4_blend(struct vc4_compile *c, struct qreg *result,
1185 struct qreg *dst_color, struct qreg *src_color)
1186 {
1187 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1188
1189 if (!blend->blend_enable) {
1190 for (int i = 0; i < 4; i++)
1191 result[i] = src_color[i];
1192 return;
1193 }
1194
1195 struct qreg src_blend[4], dst_blend[4];
1196 for (int i = 0; i < 3; i++) {
1197 src_blend[i] = vc4_blend_channel(c,
1198 dst_color, src_color,
1199 src_color[i],
1200 blend->rgb_src_factor, i);
1201 dst_blend[i] = vc4_blend_channel(c,
1202 dst_color, src_color,
1203 dst_color[i],
1204 blend->rgb_dst_factor, i);
1205 }
1206 src_blend[3] = vc4_blend_channel(c,
1207 dst_color, src_color,
1208 src_color[3],
1209 blend->alpha_src_factor, 3);
1210 dst_blend[3] = vc4_blend_channel(c,
1211 dst_color, src_color,
1212 dst_color[3],
1213 blend->alpha_dst_factor, 3);
1214
1215 for (int i = 0; i < 3; i++) {
1216 result[i] = vc4_blend_func(c,
1217 src_blend[i], dst_blend[i],
1218 blend->rgb_func);
1219 }
1220 result[3] = vc4_blend_func(c,
1221 src_blend[3], dst_blend[3],
1222 blend->alpha_func);
1223 }
1224
1225 static void
1226 emit_frag_end(struct vc4_compile *c)
1227 {
1228 enum pipe_format color_format = c->fs_key->color_format;
1229 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1230 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1231 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1232 if (c->fs_key->blend.blend_enable ||
1233 c->fs_key->blend.colormask != 0xf) {
1234 struct qreg r4 = qir_TLB_COLOR_READ(c);
1235 for (int i = 0; i < 4; i++)
1236 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1237 for (int i = 0; i < 4; i++)
1238 dst_color[i] = get_swizzled_channel(c,
1239 tlb_read_color,
1240 format_swiz[i]);
1241 }
1242
1243 struct qreg blend_color[4];
1244 struct qreg undef_array[4] = {
1245 c->undef, c->undef, c->undef, c->undef
1246 };
1247 vc4_blend(c, blend_color, dst_color,
1248 (c->output_color_index != -1 ?
1249 c->outputs + c->output_color_index :
1250 undef_array));
1251
1252 /* If the bit isn't set in the color mask, then just return the
1253 * original dst color, instead.
1254 */
1255 for (int i = 0; i < 4; i++) {
1256 if (!(c->fs_key->blend.colormask & (1 << i))) {
1257 blend_color[i] = dst_color[i];
1258 }
1259 }
1260
1261 /* Debug: Sometimes you're getting a black output and just want to see
1262 * if the FS is getting executed at all. Spam magenta into the color
1263 * output.
1264 */
1265 if (0) {
1266 blend_color[0] = qir_uniform_f(c, 1.0);
1267 blend_color[1] = qir_uniform_f(c, 0.0);
1268 blend_color[2] = qir_uniform_f(c, 1.0);
1269 blend_color[3] = qir_uniform_f(c, 0.5);
1270 }
1271
1272 struct qreg swizzled_outputs[4];
1273 for (int i = 0; i < 4; i++) {
1274 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1275 format_swiz[i]);
1276 }
1277
1278 if (c->discard.file != QFILE_NULL)
1279 qir_TLB_DISCARD_SETUP(c, c->discard);
1280
1281 if (c->fs_key->stencil_enabled) {
1282 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 0));
1283 if (c->fs_key->stencil_twoside) {
1284 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 1));
1285 }
1286 if (c->fs_key->stencil_full_writemasks) {
1287 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 2));
1288 }
1289 }
1290
1291 if (c->fs_key->depth_enabled) {
1292 struct qreg z;
1293 if (c->output_position_index != -1) {
1294 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1295 qir_uniform_f(c, 0xffffff)));
1296 } else {
1297 z = qir_FRAG_Z(c);
1298 }
1299 qir_TLB_Z_WRITE(c, z);
1300 }
1301
1302 bool color_written = false;
1303 for (int i = 0; i < 4; i++) {
1304 if (swizzled_outputs[i].file != QFILE_NULL)
1305 color_written = true;
1306 }
1307
1308 struct qreg packed_color;
1309 if (color_written) {
1310 /* Fill in any undefined colors. The simulator will assertion
1311 * fail if we read something that wasn't written, and I don't
1312 * know what hardware does.
1313 */
1314 for (int i = 0; i < 4; i++) {
1315 if (swizzled_outputs[i].file == QFILE_NULL)
1316 swizzled_outputs[i] = qir_uniform_f(c, 0.0);
1317 }
1318 packed_color = qir_get_temp(c);
1319 qir_emit(c, qir_inst4(QOP_PACK_COLORS, packed_color,
1320 swizzled_outputs[0],
1321 swizzled_outputs[1],
1322 swizzled_outputs[2],
1323 swizzled_outputs[3]));
1324 } else {
1325 packed_color = qir_uniform_ui(c, 0);
1326 }
1327
1328 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1329 packed_color, c->undef));
1330 }
1331
1332 static void
1333 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1334 {
1335 struct qreg xyi[2];
1336
1337 for (int i = 0; i < 2; i++) {
1338 struct qreg scale =
1339 add_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1340
1341 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1342 qir_FMUL(c,
1343 c->outputs[i],
1344 scale),
1345 rcp_w));
1346 }
1347
1348 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1349 }
1350
1351 static void
1352 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1353 {
1354 struct qreg zscale = add_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1355 struct qreg zoffset = add_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1356
1357 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1358 c->outputs[2],
1359 zscale),
1360 zoffset),
1361 rcp_w));
1362 }
1363
1364 static void
1365 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1366 {
1367 qir_VPM_WRITE(c, rcp_w);
1368 }
1369
1370 static void
1371 emit_vert_end(struct vc4_compile *c)
1372 {
1373 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1374
1375 emit_scaled_viewport_write(c, rcp_w);
1376 emit_zs_write(c, rcp_w);
1377 emit_rcp_wc_write(c, rcp_w);
1378
1379 for (int i = 4; i < c->num_outputs; i++) {
1380 qir_VPM_WRITE(c, c->outputs[i]);
1381 }
1382 }
1383
1384 static void
1385 emit_coord_end(struct vc4_compile *c)
1386 {
1387 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1388
1389 for (int i = 0; i < 4; i++)
1390 qir_VPM_WRITE(c, c->outputs[i]);
1391
1392 emit_scaled_viewport_write(c, rcp_w);
1393 emit_zs_write(c, rcp_w);
1394 emit_rcp_wc_write(c, rcp_w);
1395 }
1396
1397 static struct vc4_compile *
1398 vc4_shader_tgsi_to_qir(struct vc4_context *vc4,
1399 struct vc4_compiled_shader *shader, enum qstage stage,
1400 struct vc4_key *key)
1401 {
1402 struct vc4_compile *c = qir_compile_init();
1403 int ret;
1404
1405 c->stage = stage;
1406
1407 c->uniform_data = ralloc_array(c, uint32_t, 1024);
1408 c->uniform_contents = ralloc_array(c, enum quniform_contents, 1024);
1409
1410 c->shader_state = key->shader_state;
1411 ret = tgsi_parse_init(&c->parser, c->shader_state->tokens);
1412 assert(ret == TGSI_PARSE_OK);
1413
1414 if (vc4_debug & VC4_DEBUG_TGSI) {
1415 fprintf(stderr, "TGSI:\n");
1416 tgsi_dump(c->shader_state->tokens, 0);
1417 }
1418
1419 c->key = key;
1420 switch (stage) {
1421 case QSTAGE_FRAG:
1422 c->fs_key = (struct vc4_fs_key *)key;
1423 if (c->fs_key->is_points) {
1424 c->point_x = emit_fragment_varying(c, 0);
1425 c->point_y = emit_fragment_varying(c, 0);
1426 } else if (c->fs_key->is_lines) {
1427 c->line_x = emit_fragment_varying(c, 0);
1428 }
1429 break;
1430 case QSTAGE_VERT:
1431 c->vs_key = (struct vc4_vs_key *)key;
1432 break;
1433 case QSTAGE_COORD:
1434 c->vs_key = (struct vc4_vs_key *)key;
1435 break;
1436 }
1437
1438 while (!tgsi_parse_end_of_tokens(&c->parser)) {
1439 tgsi_parse_token(&c->parser);
1440
1441 switch (c->parser.FullToken.Token.Type) {
1442 case TGSI_TOKEN_TYPE_DECLARATION:
1443 emit_tgsi_declaration(c,
1444 &c->parser.FullToken.FullDeclaration);
1445 break;
1446
1447 case TGSI_TOKEN_TYPE_INSTRUCTION:
1448 emit_tgsi_instruction(c,
1449 &c->parser.FullToken.FullInstruction);
1450 break;
1451
1452 case TGSI_TOKEN_TYPE_IMMEDIATE:
1453 parse_tgsi_immediate(c,
1454 &c->parser.FullToken.FullImmediate);
1455 break;
1456 }
1457 }
1458
1459 switch (stage) {
1460 case QSTAGE_FRAG:
1461 emit_frag_end(c);
1462 break;
1463 case QSTAGE_VERT:
1464 emit_vert_end(c);
1465 break;
1466 case QSTAGE_COORD:
1467 emit_coord_end(c);
1468 break;
1469 }
1470
1471 tgsi_parse_free(&c->parser);
1472
1473 qir_optimize(c);
1474
1475 if (vc4_debug & VC4_DEBUG_QIR) {
1476 fprintf(stderr, "QIR:\n");
1477 qir_dump(c);
1478 }
1479 qir_reorder_uniforms(c);
1480 vc4_generate_code(vc4, c);
1481
1482 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1483 fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
1484 qir_get_stage_name(c->stage), c->qpu_inst_count);
1485 fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
1486 qir_get_stage_name(c->stage), c->num_uniforms);
1487 }
1488
1489 return c;
1490 }
1491
1492 static void *
1493 vc4_shader_state_create(struct pipe_context *pctx,
1494 const struct pipe_shader_state *cso)
1495 {
1496 struct pipe_shader_state *so = CALLOC_STRUCT(pipe_shader_state);
1497 if (!so)
1498 return NULL;
1499
1500 so->tokens = tgsi_dup_tokens(cso->tokens);
1501
1502 return so;
1503 }
1504
1505 static void
1506 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1507 int shader_index,
1508 struct vc4_compile *c)
1509 {
1510 int count = c->num_uniforms;
1511 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1512
1513 uinfo->count = count;
1514 uinfo->data = malloc(count * sizeof(*uinfo->data));
1515 memcpy(uinfo->data, c->uniform_data,
1516 count * sizeof(*uinfo->data));
1517 uinfo->contents = malloc(count * sizeof(*uinfo->contents));
1518 memcpy(uinfo->contents, c->uniform_contents,
1519 count * sizeof(*uinfo->contents));
1520 uinfo->num_texture_samples = c->num_texture_samples;
1521 }
1522
1523 static void
1524 vc4_fs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1525 struct vc4_fs_key *key)
1526 {
1527 struct vc4_compile *c = vc4_shader_tgsi_to_qir(vc4, shader,
1528 QSTAGE_FRAG,
1529 &key->base);
1530 shader->num_inputs = c->num_inputs;
1531 copy_uniform_state_to_shader(shader, 0, c);
1532 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
1533 c->qpu_inst_count * sizeof(uint64_t),
1534 "fs_code");
1535
1536 qir_compile_destroy(c);
1537 }
1538
1539 static void
1540 vc4_vs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1541 struct vc4_vs_key *key)
1542 {
1543 struct vc4_compile *vs_c = vc4_shader_tgsi_to_qir(vc4, shader,
1544 QSTAGE_VERT,
1545 &key->base);
1546 copy_uniform_state_to_shader(shader, 0, vs_c);
1547
1548 struct vc4_compile *cs_c = vc4_shader_tgsi_to_qir(vc4, shader,
1549 QSTAGE_COORD,
1550 &key->base);
1551 copy_uniform_state_to_shader(shader, 1, cs_c);
1552
1553 uint32_t vs_size = vs_c->qpu_inst_count * sizeof(uint64_t);
1554 uint32_t cs_size = cs_c->qpu_inst_count * sizeof(uint64_t);
1555 shader->coord_shader_offset = vs_size; /* XXX: alignment? */
1556 shader->bo = vc4_bo_alloc(vc4->screen,
1557 shader->coord_shader_offset + cs_size,
1558 "vs_code");
1559
1560 void *map = vc4_bo_map(shader->bo);
1561 memcpy(map, vs_c->qpu_insts, vs_size);
1562 memcpy(map + shader->coord_shader_offset,
1563 cs_c->qpu_insts, cs_size);
1564
1565 qir_compile_destroy(vs_c);
1566 qir_compile_destroy(cs_c);
1567 }
1568
1569 static void
1570 vc4_setup_shared_key(struct vc4_key *key, struct vc4_texture_stateobj *texstate)
1571 {
1572 for (int i = 0; i < texstate->num_textures; i++) {
1573 struct pipe_sampler_view *sampler = texstate->textures[i];
1574 struct pipe_sampler_state *sampler_state =
1575 texstate->samplers[i];
1576
1577 if (sampler) {
1578 struct pipe_resource *prsc = sampler->texture;
1579 key->tex[i].format = prsc->format;
1580 key->tex[i].swizzle[0] = sampler->swizzle_r;
1581 key->tex[i].swizzle[1] = sampler->swizzle_g;
1582 key->tex[i].swizzle[2] = sampler->swizzle_b;
1583 key->tex[i].swizzle[3] = sampler->swizzle_a;
1584 key->tex[i].compare_mode = sampler_state->compare_mode;
1585 key->tex[i].compare_func = sampler_state->compare_func;
1586 }
1587 }
1588 }
1589
1590 static void
1591 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
1592 {
1593 struct vc4_fs_key local_key;
1594 struct vc4_fs_key *key = &local_key;
1595
1596 memset(key, 0, sizeof(*key));
1597 vc4_setup_shared_key(&key->base, &vc4->fragtex);
1598 key->base.shader_state = vc4->prog.bind_fs;
1599 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
1600 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
1601 prim_mode <= PIPE_PRIM_LINE_STRIP);
1602 key->blend = vc4->blend->rt[0];
1603
1604 if (vc4->framebuffer.cbufs[0])
1605 key->color_format = vc4->framebuffer.cbufs[0]->format;
1606
1607 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
1608 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
1609 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
1610 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
1611 key->stencil_enabled);
1612
1613 vc4->prog.fs = util_hash_table_get(vc4->fs_cache, key);
1614 if (vc4->prog.fs)
1615 return;
1616
1617 key = malloc(sizeof(*key));
1618 memcpy(key, &local_key, sizeof(*key));
1619
1620 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1621 vc4_fs_compile(vc4, shader, key);
1622 util_hash_table_set(vc4->fs_cache, key, shader);
1623
1624 vc4->prog.fs = shader;
1625 }
1626
1627 static void
1628 vc4_update_compiled_vs(struct vc4_context *vc4)
1629 {
1630 struct vc4_vs_key local_key;
1631 struct vc4_vs_key *key = &local_key;
1632
1633 memset(key, 0, sizeof(*key));
1634 vc4_setup_shared_key(&key->base, &vc4->verttex);
1635 key->base.shader_state = vc4->prog.bind_vs;
1636
1637 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
1638 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
1639
1640 vc4->prog.vs = util_hash_table_get(vc4->vs_cache, key);
1641 if (vc4->prog.vs)
1642 return;
1643
1644 key = malloc(sizeof(*key));
1645 memcpy(key, &local_key, sizeof(*key));
1646
1647 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1648 vc4_vs_compile(vc4, shader, key);
1649 util_hash_table_set(vc4->vs_cache, key, shader);
1650
1651 vc4->prog.vs = shader;
1652 }
1653
1654 void
1655 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
1656 {
1657 vc4_update_compiled_fs(vc4, prim_mode);
1658 vc4_update_compiled_vs(vc4);
1659 }
1660
1661 static unsigned
1662 fs_cache_hash(void *key)
1663 {
1664 return util_hash_crc32(key, sizeof(struct vc4_fs_key));
1665 }
1666
1667 static unsigned
1668 vs_cache_hash(void *key)
1669 {
1670 return util_hash_crc32(key, sizeof(struct vc4_vs_key));
1671 }
1672
1673 static int
1674 fs_cache_compare(void *key1, void *key2)
1675 {
1676 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
1677 }
1678
1679 static int
1680 vs_cache_compare(void *key1, void *key2)
1681 {
1682 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
1683 }
1684
1685 struct delete_state {
1686 struct vc4_context *vc4;
1687 struct pipe_shader_state *shader_state;
1688 };
1689
1690 static enum pipe_error
1691 fs_delete_from_cache(void *in_key, void *in_value, void *data)
1692 {
1693 struct delete_state *del = data;
1694 struct vc4_fs_key *key = in_key;
1695 struct vc4_compiled_shader *shader = in_value;
1696
1697 if (key->base.shader_state == data) {
1698 util_hash_table_remove(del->vc4->fs_cache, key);
1699 vc4_bo_unreference(&shader->bo);
1700 free(shader);
1701 }
1702
1703 return 0;
1704 }
1705
1706 static enum pipe_error
1707 vs_delete_from_cache(void *in_key, void *in_value, void *data)
1708 {
1709 struct delete_state *del = data;
1710 struct vc4_vs_key *key = in_key;
1711 struct vc4_compiled_shader *shader = in_value;
1712
1713 if (key->base.shader_state == data) {
1714 util_hash_table_remove(del->vc4->vs_cache, key);
1715 vc4_bo_unreference(&shader->bo);
1716 free(shader);
1717 }
1718
1719 return 0;
1720 }
1721
1722 static void
1723 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1724 {
1725 struct vc4_context *vc4 = vc4_context(pctx);
1726 struct pipe_shader_state *so = hwcso;
1727 struct delete_state del;
1728
1729 del.vc4 = vc4;
1730 del.shader_state = so;
1731 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
1732 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
1733
1734 free((void *)so->tokens);
1735 free(so);
1736 }
1737
1738 static uint32_t translate_wrap(uint32_t p_wrap)
1739 {
1740 switch (p_wrap) {
1741 case PIPE_TEX_WRAP_REPEAT:
1742 return 0;
1743 case PIPE_TEX_WRAP_CLAMP:
1744 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1745 return 1;
1746 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1747 return 2;
1748 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1749 return 3;
1750 default:
1751 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
1752 assert(!"not reached");
1753 return 0;
1754 }
1755 }
1756
1757 static void
1758 write_texture_p0(struct vc4_context *vc4,
1759 struct vc4_texture_stateobj *texstate,
1760 uint32_t unit)
1761 {
1762 struct pipe_sampler_view *texture = texstate->textures[unit];
1763 struct vc4_resource *rsc = vc4_resource(texture->texture);
1764
1765 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
1766 rsc->slices[0].offset | texture->u.tex.last_level |
1767 ((rsc->vc4_format & 7) << 4));
1768 }
1769
1770 static void
1771 write_texture_p1(struct vc4_context *vc4,
1772 struct vc4_texture_stateobj *texstate,
1773 uint32_t unit)
1774 {
1775 struct pipe_sampler_view *texture = texstate->textures[unit];
1776 struct vc4_resource *rsc = vc4_resource(texture->texture);
1777 struct pipe_sampler_state *sampler = texstate->samplers[unit];
1778 static const uint32_t mipfilter_map[] = {
1779 [PIPE_TEX_MIPFILTER_NEAREST] = 2,
1780 [PIPE_TEX_MIPFILTER_LINEAR] = 4,
1781 [PIPE_TEX_MIPFILTER_NONE] = 0
1782 };
1783 static const uint32_t imgfilter_map[] = {
1784 [PIPE_TEX_FILTER_NEAREST] = 1,
1785 [PIPE_TEX_FILTER_LINEAR] = 0,
1786 };
1787
1788 cl_u32(&vc4->uniforms,
1789 ((rsc->vc4_format >> 4) << 31) |
1790 (texture->texture->height0 << 20) |
1791 (texture->texture->width0 << 8) |
1792 (imgfilter_map[sampler->mag_img_filter] << 7) |
1793 ((imgfilter_map[sampler->min_img_filter] +
1794 mipfilter_map[sampler->min_mip_filter]) << 4) |
1795 (translate_wrap(sampler->wrap_t) << 2) |
1796 (translate_wrap(sampler->wrap_s) << 0));
1797 }
1798
1799 static uint32_t
1800 get_texrect_scale(struct vc4_texture_stateobj *texstate,
1801 enum quniform_contents contents,
1802 uint32_t data)
1803 {
1804 struct pipe_sampler_view *texture = texstate->textures[data];
1805 uint32_t dim;
1806
1807 if (contents == QUNIFORM_TEXRECT_SCALE_X)
1808 dim = texture->texture->width0;
1809 else
1810 dim = texture->texture->height0;
1811
1812 return fui(1.0f / dim);
1813 }
1814
1815 void
1816 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1817 struct vc4_constbuf_stateobj *cb,
1818 struct vc4_texture_stateobj *texstate,
1819 int shader_index)
1820 {
1821 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1822 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
1823
1824 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
1825
1826 for (int i = 0; i < uinfo->count; i++) {
1827
1828 switch (uinfo->contents[i]) {
1829 case QUNIFORM_CONSTANT:
1830 cl_u32(&vc4->uniforms, uinfo->data[i]);
1831 break;
1832 case QUNIFORM_UNIFORM:
1833 cl_u32(&vc4->uniforms,
1834 gallium_uniforms[uinfo->data[i]]);
1835 break;
1836 case QUNIFORM_VIEWPORT_X_SCALE:
1837 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
1838 break;
1839 case QUNIFORM_VIEWPORT_Y_SCALE:
1840 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
1841 break;
1842
1843 case QUNIFORM_VIEWPORT_Z_OFFSET:
1844 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
1845 break;
1846 case QUNIFORM_VIEWPORT_Z_SCALE:
1847 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
1848 break;
1849
1850 case QUNIFORM_TEXTURE_CONFIG_P0:
1851 write_texture_p0(vc4, texstate, uinfo->data[i]);
1852 break;
1853
1854 case QUNIFORM_TEXTURE_CONFIG_P1:
1855 write_texture_p1(vc4, texstate, uinfo->data[i]);
1856 break;
1857
1858 case QUNIFORM_TEXRECT_SCALE_X:
1859 case QUNIFORM_TEXRECT_SCALE_Y:
1860 cl_u32(&vc4->uniforms,
1861 get_texrect_scale(texstate,
1862 uinfo->contents[i],
1863 uinfo->data[i]));
1864 break;
1865
1866 case QUNIFORM_BLEND_CONST_COLOR:
1867 cl_f(&vc4->uniforms,
1868 vc4->blend_color.color[uinfo->data[i]]);
1869 break;
1870
1871 case QUNIFORM_STENCIL:
1872 cl_u32(&vc4->uniforms,
1873 vc4->zsa->stencil_uniforms[uinfo->data[i]] |
1874 (uinfo->data[i] <= 1 ?
1875 (vc4->stencil_ref.ref_value[uinfo->data[i]] << 8) :
1876 0));
1877 break;
1878 }
1879 #if 0
1880 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
1881 fprintf(stderr, "%p/%d: %d: 0x%08x (%f)\n",
1882 shader, shader_index, i, written_val, uif(written_val));
1883 #endif
1884 }
1885 }
1886
1887 static void
1888 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
1889 {
1890 struct vc4_context *vc4 = vc4_context(pctx);
1891 vc4->prog.bind_fs = hwcso;
1892 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
1893 vc4->dirty |= VC4_DIRTY_PROG;
1894 }
1895
1896 static void
1897 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
1898 {
1899 struct vc4_context *vc4 = vc4_context(pctx);
1900 vc4->prog.bind_vs = hwcso;
1901 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
1902 vc4->dirty |= VC4_DIRTY_PROG;
1903 }
1904
1905 void
1906 vc4_program_init(struct pipe_context *pctx)
1907 {
1908 struct vc4_context *vc4 = vc4_context(pctx);
1909
1910 pctx->create_vs_state = vc4_shader_state_create;
1911 pctx->delete_vs_state = vc4_shader_state_delete;
1912
1913 pctx->create_fs_state = vc4_shader_state_create;
1914 pctx->delete_fs_state = vc4_shader_state_delete;
1915
1916 pctx->bind_fs_state = vc4_fp_state_bind;
1917 pctx->bind_vs_state = vc4_vp_state_bind;
1918
1919 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
1920 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
1921 }