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vc4: Allow copy propagation of uniforms.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "util/ralloc.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_info.h"
34
35 #include "vc4_context.h"
36 #include "vc4_qpu.h"
37 #include "vc4_qir.h"
38 #ifdef USE_VC4_SIMULATOR
39 #include "simpenrose/simpenrose.h"
40 #endif
41
42 struct vc4_key {
43 struct pipe_shader_state *shader_state;
44 struct {
45 enum pipe_format format;
46 unsigned compare_mode:1;
47 unsigned compare_func:3;
48 uint8_t swizzle[4];
49 } tex[VC4_MAX_TEXTURE_SAMPLERS];
50 };
51
52 struct vc4_fs_key {
53 struct vc4_key base;
54 enum pipe_format color_format;
55 bool depth_enabled;
56 bool is_points;
57 bool is_lines;
58
59 struct pipe_rt_blend_state blend;
60 };
61
62 struct vc4_vs_key {
63 struct vc4_key base;
64 enum pipe_format attr_formats[8];
65 };
66
67 static void
68 resize_qreg_array(struct vc4_compile *c,
69 struct qreg **regs,
70 uint32_t *size,
71 uint32_t decl_size)
72 {
73 if (*size >= decl_size)
74 return;
75
76 uint32_t old_size = *size;
77 *size = MAX2(*size * 2, decl_size);
78 *regs = reralloc(c, *regs, struct qreg, *size);
79 if (!*regs) {
80 fprintf(stderr, "Malloc failure\n");
81 abort();
82 }
83
84 for (uint32_t i = old_size; i < *size; i++)
85 (*regs)[i] = c->undef;
86 }
87
88 static struct qreg
89 add_uniform(struct vc4_compile *c,
90 enum quniform_contents contents,
91 uint32_t data)
92 {
93 uint32_t uniform = c->num_uniforms++;
94 struct qreg u = { QFILE_UNIF, uniform };
95
96 c->uniform_contents[uniform] = contents;
97 c->uniform_data[uniform] = data;
98
99 return u;
100 }
101
102 static struct qreg
103 get_temp_for_uniform(struct vc4_compile *c, enum quniform_contents contents,
104 uint32_t data)
105 {
106 for (int i = 0; i < c->num_uniforms; i++) {
107 if (c->uniform_contents[i] == contents &&
108 c->uniform_data[i] == data)
109 return c->uniforms[i];
110 }
111
112 struct qreg u = add_uniform(c, contents, data);
113 struct qreg t = qir_MOV(c, u);
114
115 resize_qreg_array(c, &c->uniforms, &c->uniforms_array_size,
116 u.index + 1);
117
118 c->uniforms[u.index] = t;
119 return t;
120 }
121
122 static struct qreg
123 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
124 {
125 return get_temp_for_uniform(c, QUNIFORM_CONSTANT, ui);
126 }
127
128 static struct qreg
129 qir_uniform_f(struct vc4_compile *c, float f)
130 {
131 return qir_uniform_ui(c, fui(f));
132 }
133
134 static struct qreg
135 get_src(struct vc4_compile *c, unsigned tgsi_op,
136 struct tgsi_src_register *src, int i)
137 {
138 struct qreg r = c->undef;
139
140 uint32_t s = i;
141 switch (i) {
142 case TGSI_SWIZZLE_X:
143 s = src->SwizzleX;
144 break;
145 case TGSI_SWIZZLE_Y:
146 s = src->SwizzleY;
147 break;
148 case TGSI_SWIZZLE_Z:
149 s = src->SwizzleZ;
150 break;
151 case TGSI_SWIZZLE_W:
152 s = src->SwizzleW;
153 break;
154 default:
155 abort();
156 }
157
158 assert(!src->Indirect);
159
160 switch (src->File) {
161 case TGSI_FILE_NULL:
162 return r;
163 case TGSI_FILE_TEMPORARY:
164 r = c->temps[src->Index * 4 + s];
165 break;
166 case TGSI_FILE_IMMEDIATE:
167 r = c->consts[src->Index * 4 + s];
168 break;
169 case TGSI_FILE_CONSTANT:
170 r = get_temp_for_uniform(c, QUNIFORM_UNIFORM,
171 src->Index * 4 + s);
172 break;
173 case TGSI_FILE_INPUT:
174 r = c->inputs[src->Index * 4 + s];
175 break;
176 case TGSI_FILE_SAMPLER:
177 case TGSI_FILE_SAMPLER_VIEW:
178 r = c->undef;
179 break;
180 default:
181 fprintf(stderr, "unknown src file %d\n", src->File);
182 abort();
183 }
184
185 if (src->Absolute)
186 r = qir_FMAXABS(c, r, r);
187
188 if (src->Negate) {
189 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
190 case TGSI_TYPE_SIGNED:
191 case TGSI_TYPE_UNSIGNED:
192 r = qir_SUB(c, qir_uniform_ui(c, 0), r);
193 break;
194 default:
195 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);
196 break;
197 }
198 }
199
200 return r;
201 };
202
203
204 static void
205 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,
206 int i, struct qreg val)
207 {
208 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
209
210 assert(!tgsi_dst->Indirect);
211
212 switch (tgsi_dst->File) {
213 case TGSI_FILE_TEMPORARY:
214 c->temps[tgsi_dst->Index * 4 + i] = val;
215 break;
216 case TGSI_FILE_OUTPUT:
217 c->outputs[tgsi_dst->Index * 4 + i] = val;
218 c->num_outputs = MAX2(c->num_outputs,
219 tgsi_dst->Index * 4 + i + 1);
220 break;
221 default:
222 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
223 abort();
224 }
225 };
226
227 static struct qreg
228 get_swizzled_channel(struct vc4_compile *c,
229 struct qreg *srcs, int swiz)
230 {
231 switch (swiz) {
232 default:
233 case UTIL_FORMAT_SWIZZLE_NONE:
234 fprintf(stderr, "warning: unknown swizzle\n");
235 /* FALLTHROUGH */
236 case UTIL_FORMAT_SWIZZLE_0:
237 return qir_uniform_f(c, 0.0);
238 case UTIL_FORMAT_SWIZZLE_1:
239 return qir_uniform_f(c, 1.0);
240 case UTIL_FORMAT_SWIZZLE_X:
241 case UTIL_FORMAT_SWIZZLE_Y:
242 case UTIL_FORMAT_SWIZZLE_Z:
243 case UTIL_FORMAT_SWIZZLE_W:
244 return srcs[swiz];
245 }
246 }
247
248 static struct qreg
249 tgsi_to_qir_alu(struct vc4_compile *c,
250 struct tgsi_full_instruction *tgsi_inst,
251 enum qop op, struct qreg *src, int i)
252 {
253 struct qreg dst = qir_get_temp(c);
254 qir_emit(c, qir_inst4(op, dst,
255 src[0 * 4 + i],
256 src[1 * 4 + i],
257 src[2 * 4 + i],
258 c->undef));
259 return dst;
260 }
261
262 static struct qreg
263 tgsi_to_qir_umul(struct vc4_compile *c,
264 struct tgsi_full_instruction *tgsi_inst,
265 enum qop op, struct qreg *src, int i)
266 {
267 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],
268 qir_uniform_ui(c, 16));
269 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],
270 qir_uniform_ui(c, 0xffff));
271 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],
272 qir_uniform_ui(c, 16));
273 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],
274 qir_uniform_ui(c, 0xffff));
275
276 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);
277 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);
278 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);
279
280 return qir_ADD(c, lolo, qir_SHL(c,
281 qir_ADD(c, hilo, lohi),
282 qir_uniform_ui(c, 16)));
283 }
284
285 static struct qreg
286 tgsi_to_qir_idiv(struct vc4_compile *c,
287 struct tgsi_full_instruction *tgsi_inst,
288 enum qop op, struct qreg *src, int i)
289 {
290 return qir_FTOI(c, qir_FMUL(c,
291 qir_ITOF(c, src[0 * 4 + i]),
292 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
293 }
294
295 static struct qreg
296 tgsi_to_qir_ineg(struct vc4_compile *c,
297 struct tgsi_full_instruction *tgsi_inst,
298 enum qop op, struct qreg *src, int i)
299 {
300 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);
301 }
302
303 static struct qreg
304 tgsi_to_qir_seq(struct vc4_compile *c,
305 struct tgsi_full_instruction *tgsi_inst,
306 enum qop op, struct qreg *src, int i)
307 {
308 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
309 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
310 }
311
312 static struct qreg
313 tgsi_to_qir_sne(struct vc4_compile *c,
314 struct tgsi_full_instruction *tgsi_inst,
315 enum qop op, struct qreg *src, int i)
316 {
317 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
318 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
319 }
320
321 static struct qreg
322 tgsi_to_qir_slt(struct vc4_compile *c,
323 struct tgsi_full_instruction *tgsi_inst,
324 enum qop op, struct qreg *src, int i)
325 {
326 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
327 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
328 }
329
330 static struct qreg
331 tgsi_to_qir_sge(struct vc4_compile *c,
332 struct tgsi_full_instruction *tgsi_inst,
333 enum qop op, struct qreg *src, int i)
334 {
335 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
336 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
337 }
338
339 static struct qreg
340 tgsi_to_qir_fseq(struct vc4_compile *c,
341 struct tgsi_full_instruction *tgsi_inst,
342 enum qop op, struct qreg *src, int i)
343 {
344 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
345 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
346 }
347
348 static struct qreg
349 tgsi_to_qir_fsne(struct vc4_compile *c,
350 struct tgsi_full_instruction *tgsi_inst,
351 enum qop op, struct qreg *src, int i)
352 {
353 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
354 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
355 }
356
357 static struct qreg
358 tgsi_to_qir_fslt(struct vc4_compile *c,
359 struct tgsi_full_instruction *tgsi_inst,
360 enum qop op, struct qreg *src, int i)
361 {
362 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
363 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
364 }
365
366 static struct qreg
367 tgsi_to_qir_fsge(struct vc4_compile *c,
368 struct tgsi_full_instruction *tgsi_inst,
369 enum qop op, struct qreg *src, int i)
370 {
371 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
372 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
373 }
374
375 static struct qreg
376 tgsi_to_qir_useq(struct vc4_compile *c,
377 struct tgsi_full_instruction *tgsi_inst,
378 enum qop op, struct qreg *src, int i)
379 {
380 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
381 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
382 }
383
384 static struct qreg
385 tgsi_to_qir_usne(struct vc4_compile *c,
386 struct tgsi_full_instruction *tgsi_inst,
387 enum qop op, struct qreg *src, int i)
388 {
389 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
390 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
391 }
392
393 static struct qreg
394 tgsi_to_qir_islt(struct vc4_compile *c,
395 struct tgsi_full_instruction *tgsi_inst,
396 enum qop op, struct qreg *src, int i)
397 {
398 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
399 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
400 }
401
402 static struct qreg
403 tgsi_to_qir_isge(struct vc4_compile *c,
404 struct tgsi_full_instruction *tgsi_inst,
405 enum qop op, struct qreg *src, int i)
406 {
407 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
408 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
409 }
410
411 static struct qreg
412 tgsi_to_qir_cmp(struct vc4_compile *c,
413 struct tgsi_full_instruction *tgsi_inst,
414 enum qop op, struct qreg *src, int i)
415 {
416 qir_SF(c, src[0 * 4 + i]);
417 return qir_SEL_X_Y_NS(c,
418 src[1 * 4 + i],
419 src[2 * 4 + i]);
420 }
421
422 static struct qreg
423 tgsi_to_qir_mad(struct vc4_compile *c,
424 struct tgsi_full_instruction *tgsi_inst,
425 enum qop op, struct qreg *src, int i)
426 {
427 return qir_FADD(c,
428 qir_FMUL(c,
429 src[0 * 4 + i],
430 src[1 * 4 + i]),
431 src[2 * 4 + i]);
432 }
433
434 static struct qreg
435 tgsi_to_qir_lit(struct vc4_compile *c,
436 struct tgsi_full_instruction *tgsi_inst,
437 enum qop op, struct qreg *src, int i)
438 {
439 struct qreg x = src[0 * 4 + 0];
440 struct qreg y = src[0 * 4 + 1];
441 struct qreg w = src[0 * 4 + 3];
442
443 switch (i) {
444 case 0:
445 case 3:
446 return qir_uniform_f(c, 1.0);
447 case 1:
448 return qir_FMAX(c, src[0 * 4 + 0], qir_uniform_f(c, 0.0));
449 case 2: {
450 struct qreg zero = qir_uniform_f(c, 0.0);
451
452 qir_SF(c, x);
453 /* XXX: Clamp w to -128..128 */
454 return qir_SEL_X_0_NC(c,
455 qir_EXP2(c, qir_FMUL(c,
456 w,
457 qir_LOG2(c,
458 qir_FMAX(c,
459 y,
460 zero)))));
461 }
462 default:
463 assert(!"not reached");
464 return c->undef;
465 }
466 }
467
468 static struct qreg
469 tgsi_to_qir_lrp(struct vc4_compile *c,
470 struct tgsi_full_instruction *tgsi_inst,
471 enum qop op, struct qreg *src, int i)
472 {
473 struct qreg src0 = src[0 * 4 + i];
474 struct qreg src1 = src[1 * 4 + i];
475 struct qreg src2 = src[2 * 4 + i];
476
477 /* LRP is:
478 * src0 * src1 + (1 - src0) * src2.
479 * -> src0 * src1 + src2 - src0 * src2
480 * -> src2 + src0 * (src1 - src2)
481 */
482 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
483
484 }
485
486 static void
487 tgsi_to_qir_tex(struct vc4_compile *c,
488 struct tgsi_full_instruction *tgsi_inst,
489 enum qop op, struct qreg *src)
490 {
491 assert(!tgsi_inst->Instruction.Saturate);
492
493 struct qreg s = src[0 * 4 + 0];
494 struct qreg t = src[0 * 4 + 1];
495 uint32_t unit = tgsi_inst->Src[1].Register.Index;
496
497 struct qreg proj = c->undef;
498 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
499 proj = qir_RCP(c, src[0 * 4 + 3]);
500 s = qir_FMUL(c, s, proj);
501 t = qir_FMUL(c, t, proj);
502 }
503
504 /* There is no native support for GL texture rectangle coordinates, so
505 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
506 * 1]).
507 */
508 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT ||
509 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
510 s = qir_FMUL(c, s,
511 get_temp_for_uniform(c,
512 QUNIFORM_TEXRECT_SCALE_X,
513 unit));
514 t = qir_FMUL(c, t,
515 get_temp_for_uniform(c,
516 QUNIFORM_TEXRECT_SCALE_Y,
517 unit));
518 }
519
520 qir_TEX_T(c, t, add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit));
521
522 struct qreg sampler_p1 = add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1,
523 unit);
524 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
525 qir_TEX_B(c, src[0 * 4 + 3], sampler_p1);
526 qir_TEX_S(c, s, add_uniform(c, QUNIFORM_CONSTANT, 0));
527 } else {
528 qir_TEX_S(c, s, sampler_p1);
529 }
530
531 c->num_texture_samples++;
532 struct qreg r4 = qir_TEX_RESULT(c);
533
534 enum pipe_format format = c->key->tex[unit].format;
535
536 struct qreg unpacked[4];
537 if (util_format_is_depth_or_stencil(format)) {
538 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
539 qir_uniform_ui(c, 8)));
540 struct qreg normalized = qir_FMUL(c, depthf,
541 qir_uniform_f(c, 1.0f/0xffffff));
542
543 struct qreg depth_output;
544
545 struct qreg compare = src[0 * 4 + 2];
546
547 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP)
548 compare = qir_FMUL(c, compare, proj);
549
550 struct qreg one = qir_uniform_f(c, 1.0f);
551 if (c->key->tex[unit].compare_mode) {
552 switch (c->key->tex[unit].compare_func) {
553 case PIPE_FUNC_NEVER:
554 depth_output = qir_uniform_f(c, 0.0f);
555 break;
556 case PIPE_FUNC_ALWAYS:
557 depth_output = one;
558 break;
559 case PIPE_FUNC_EQUAL:
560 qir_SF(c, qir_FSUB(c, compare, normalized));
561 depth_output = qir_SEL_X_0_ZS(c, one);
562 break;
563 case PIPE_FUNC_NOTEQUAL:
564 qir_SF(c, qir_FSUB(c, compare, normalized));
565 depth_output = qir_SEL_X_0_ZC(c, one);
566 break;
567 case PIPE_FUNC_GREATER:
568 qir_SF(c, qir_FSUB(c, compare, normalized));
569 depth_output = qir_SEL_X_0_NC(c, one);
570 break;
571 case PIPE_FUNC_GEQUAL:
572 qir_SF(c, qir_FSUB(c, normalized, compare));
573 depth_output = qir_SEL_X_0_NS(c, one);
574 break;
575 case PIPE_FUNC_LESS:
576 qir_SF(c, qir_FSUB(c, compare, normalized));
577 depth_output = qir_SEL_X_0_NS(c, one);
578 break;
579 case PIPE_FUNC_LEQUAL:
580 qir_SF(c, qir_FSUB(c, normalized, compare));
581 depth_output = qir_SEL_X_0_NC(c, one);
582 break;
583 }
584 } else {
585 depth_output = normalized;
586 }
587
588 for (int i = 0; i < 4; i++)
589 unpacked[i] = depth_output;
590 } else {
591 for (int i = 0; i < 4; i++)
592 unpacked[i] = qir_R4_UNPACK(c, r4, i);
593 }
594
595 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
596 uint8_t swiz[4];
597 util_format_compose_swizzles(format_swiz, c->key->tex[unit].swizzle, swiz);
598 for (int i = 0; i < 4; i++) {
599 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
600 continue;
601
602 update_dst(c, tgsi_inst, i,
603 get_swizzled_channel(c, unpacked, swiz[i]));
604 }
605 }
606
607 static struct qreg
608 tgsi_to_qir_pow(struct vc4_compile *c,
609 struct tgsi_full_instruction *tgsi_inst,
610 enum qop op, struct qreg *src, int i)
611 {
612 /* Note that this instruction replicates its result from the x channel
613 */
614 return qir_EXP2(c, qir_FMUL(c,
615 src[1 * 4 + 0],
616 qir_LOG2(c, src[0 * 4 + 0])));
617 }
618
619 static struct qreg
620 tgsi_to_qir_trunc(struct vc4_compile *c,
621 struct tgsi_full_instruction *tgsi_inst,
622 enum qop op, struct qreg *src, int i)
623 {
624 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
625 }
626
627 /**
628 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
629 * to zero).
630 */
631 static struct qreg
632 tgsi_to_qir_frc(struct vc4_compile *c,
633 struct tgsi_full_instruction *tgsi_inst,
634 enum qop op, struct qreg *src, int i)
635 {
636 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
637 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
638 qir_SF(c, diff);
639 return qir_SEL_X_Y_NS(c,
640 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
641 diff);
642 }
643
644 /**
645 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
646 * zero).
647 */
648 static struct qreg
649 tgsi_to_qir_flr(struct vc4_compile *c,
650 struct tgsi_full_instruction *tgsi_inst,
651 enum qop op, struct qreg *src, int i)
652 {
653 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
654
655 /* This will be < 0 if we truncated and the truncation was of a value
656 * that was < 0 in the first place.
657 */
658 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
659
660 return qir_SEL_X_Y_NS(c,
661 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
662 trunc);
663 }
664
665 static struct qreg
666 tgsi_to_qir_dp(struct vc4_compile *c,
667 struct tgsi_full_instruction *tgsi_inst,
668 int num, struct qreg *src, int i)
669 {
670 struct qreg sum = qir_FMUL(c, src[0 * 4 + 0], src[1 * 4 + 0]);
671 for (int j = 1; j < num; j++) {
672 sum = qir_FADD(c, sum, qir_FMUL(c,
673 src[0 * 4 + j],
674 src[1 * 4 + j]));
675 }
676 return sum;
677 }
678
679 static struct qreg
680 tgsi_to_qir_dp2(struct vc4_compile *c,
681 struct tgsi_full_instruction *tgsi_inst,
682 enum qop op, struct qreg *src, int i)
683 {
684 return tgsi_to_qir_dp(c, tgsi_inst, 2, src, i);
685 }
686
687 static struct qreg
688 tgsi_to_qir_dp3(struct vc4_compile *c,
689 struct tgsi_full_instruction *tgsi_inst,
690 enum qop op, struct qreg *src, int i)
691 {
692 return tgsi_to_qir_dp(c, tgsi_inst, 3, src, i);
693 }
694
695 static struct qreg
696 tgsi_to_qir_dp4(struct vc4_compile *c,
697 struct tgsi_full_instruction *tgsi_inst,
698 enum qop op, struct qreg *src, int i)
699 {
700 return tgsi_to_qir_dp(c, tgsi_inst, 4, src, i);
701 }
702
703 static struct qreg
704 tgsi_to_qir_abs(struct vc4_compile *c,
705 struct tgsi_full_instruction *tgsi_inst,
706 enum qop op, struct qreg *src, int i)
707 {
708 struct qreg arg = src[0 * 4 + i];
709 return qir_FMAXABS(c, arg, arg);
710 }
711
712 /* Note that this instruction replicates its result from the x channel */
713 static struct qreg
714 tgsi_to_qir_sin(struct vc4_compile *c,
715 struct tgsi_full_instruction *tgsi_inst,
716 enum qop op, struct qreg *src, int i)
717 {
718 float coeff[] = {
719 2.0 * M_PI,
720 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
721 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
722 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
723 };
724
725 struct qreg scaled_x =
726 qir_FMUL(c,
727 src[0 * 4 + 0],
728 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
729
730
731 struct qreg x = tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0);
732 struct qreg x2 = qir_FMUL(c, x, x);
733 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
734 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
735 x = qir_FMUL(c, x, x2);
736 sum = qir_FADD(c,
737 sum,
738 qir_FMUL(c,
739 x,
740 qir_uniform_f(c, coeff[i])));
741 }
742 return sum;
743 }
744
745 /* Note that this instruction replicates its result from the x channel */
746 static struct qreg
747 tgsi_to_qir_cos(struct vc4_compile *c,
748 struct tgsi_full_instruction *tgsi_inst,
749 enum qop op, struct qreg *src, int i)
750 {
751 float coeff[] = {
752 1.0f,
753 -pow(2.0 * M_PI, 2) / (2 * 1),
754 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
755 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
756 };
757
758 struct qreg scaled_x =
759 qir_FMUL(c, src[0 * 4 + 0],
760 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
761 struct qreg x_frac = tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0);
762
763 struct qreg sum = qir_uniform_f(c, coeff[0]);
764 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
765 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
766 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
767 if (i != 1)
768 x = qir_FMUL(c, x, x2);
769
770 struct qreg mul = qir_FMUL(c,
771 x,
772 qir_uniform_f(c, coeff[i]));
773 if (i == 0)
774 sum = mul;
775 else
776 sum = qir_FADD(c, sum, mul);
777 }
778 return sum;
779 }
780
781 static void
782 emit_vertex_input(struct vc4_compile *c, int attr)
783 {
784 enum pipe_format format = c->vs_key->attr_formats[attr];
785 struct qreg vpm_reads[4];
786
787 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
788 * time, so we always read 4 32-bit VPM entries.
789 */
790 for (int i = 0; i < 4; i++) {
791 vpm_reads[i] = qir_get_temp(c);
792 qir_emit(c, qir_inst(QOP_VPM_READ,
793 vpm_reads[i],
794 c->undef,
795 c->undef));
796 c->num_inputs++;
797 }
798
799 bool format_warned = false;
800 const struct util_format_description *desc =
801 util_format_description(format);
802
803 for (int i = 0; i < 4; i++) {
804 uint8_t swiz = desc->swizzle[i];
805
806 if (swiz <= UTIL_FORMAT_SWIZZLE_W &&
807 !format_warned &&
808 (desc->channel[swiz].type != UTIL_FORMAT_TYPE_FLOAT ||
809 desc->channel[swiz].size != 32)) {
810 fprintf(stderr,
811 "vtx element %d unsupported type: %s\n",
812 attr, util_format_name(format));
813 format_warned = true;
814 }
815
816 c->inputs[attr * 4 + i] =
817 get_swizzled_channel(c, vpm_reads, swiz);
818 }
819 }
820
821 static void
822 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)
823 {
824 if (c->discard.file == QFILE_NULL)
825 c->discard = qir_uniform_f(c, 0.0);
826 qir_SF(c, src[0 * 4 + i]);
827 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
828 c->discard);
829 }
830
831 static void
832 emit_fragcoord_input(struct vc4_compile *c, int attr)
833 {
834 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
835 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
836 c->inputs[attr * 4 + 2] =
837 qir_FMUL(c,
838 qir_ITOF(c, qir_FRAG_Z(c)),
839 qir_uniform_f(c, 1.0 / 0xffffff));
840 c->inputs[attr * 4 + 3] = qir_FRAG_RCP_W(c);
841 }
842
843 static struct qreg
844 emit_fragment_varying(struct vc4_compile *c, int index)
845 {
846 struct qreg vary = {
847 QFILE_VARY,
848 index
849 };
850
851 /* XXX: multiply by W */
852 return qir_VARY_ADD_C(c, qir_MOV(c, vary));
853 }
854
855 static void
856 emit_fragment_input(struct vc4_compile *c, int attr)
857 {
858 for (int i = 0; i < 4; i++) {
859 c->inputs[attr * 4 + i] =
860 emit_fragment_varying(c, attr * 4 + i);
861 c->num_inputs++;
862 }
863 }
864
865 static void
866 emit_tgsi_declaration(struct vc4_compile *c,
867 struct tgsi_full_declaration *decl)
868 {
869 switch (decl->Declaration.File) {
870 case TGSI_FILE_TEMPORARY:
871 resize_qreg_array(c, &c->temps, &c->temps_array_size,
872 (decl->Range.Last + 1) * 4);
873 break;
874
875 case TGSI_FILE_INPUT:
876 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
877 (decl->Range.Last + 1) * 4);
878
879 for (int i = decl->Range.First;
880 i <= decl->Range.Last;
881 i++) {
882 if (c->stage == QSTAGE_FRAG) {
883 if (decl->Semantic.Name ==
884 TGSI_SEMANTIC_POSITION) {
885 emit_fragcoord_input(c, i);
886 } else {
887 emit_fragment_input(c, i);
888 }
889 } else {
890 emit_vertex_input(c, i);
891 }
892 }
893 break;
894
895 case TGSI_FILE_OUTPUT:
896 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
897 (decl->Range.Last + 1) * 4);
898
899 switch (decl->Semantic.Name) {
900 case TGSI_SEMANTIC_POSITION:
901 c->output_position_index = decl->Range.First * 4;
902 break;
903 case TGSI_SEMANTIC_COLOR:
904 c->output_color_index = decl->Range.First * 4;
905 break;
906 }
907
908 break;
909 }
910 }
911
912 static void
913 emit_tgsi_instruction(struct vc4_compile *c,
914 struct tgsi_full_instruction *tgsi_inst)
915 {
916 struct {
917 enum qop op;
918 struct qreg (*func)(struct vc4_compile *c,
919 struct tgsi_full_instruction *tgsi_inst,
920 enum qop op,
921 struct qreg *src, int i);
922 } op_trans[] = {
923 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
924 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
925 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
926 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
927 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
928 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
929 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
930 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
931 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
932 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
933 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
934 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
935 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
936 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
937 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
938 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
939 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
940 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
941 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
942
943 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
944 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
945 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
946
947 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
948 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
949 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
950 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
951 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
952 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
953 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
954 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
955 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
956 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
957 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
958 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
959 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
960
961 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
962 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
963 [TGSI_OPCODE_DP2] = { 0, tgsi_to_qir_dp2 },
964 [TGSI_OPCODE_DP3] = { 0, tgsi_to_qir_dp3 },
965 [TGSI_OPCODE_DP4] = { 0, tgsi_to_qir_dp4 },
966 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_alu },
967 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
968 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_alu },
969 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_alu },
970 [TGSI_OPCODE_LIT] = { 0, tgsi_to_qir_lit },
971 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
972 [TGSI_OPCODE_POW] = { 0, tgsi_to_qir_pow },
973 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
974 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
975 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
976 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
977 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
978 };
979 static int asdf = 0;
980 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
981
982 if (tgsi_op == TGSI_OPCODE_END)
983 return;
984
985 struct qreg src_regs[12];
986 for (int s = 0; s < 3; s++) {
987 for (int i = 0; i < 4; i++) {
988 src_regs[4 * s + i] =
989 get_src(c, tgsi_inst->Instruction.Opcode,
990 &tgsi_inst->Src[s].Register, i);
991 }
992 }
993
994 switch (tgsi_op) {
995 case TGSI_OPCODE_TEX:
996 case TGSI_OPCODE_TXP:
997 case TGSI_OPCODE_TXB:
998 tgsi_to_qir_tex(c, tgsi_inst,
999 op_trans[tgsi_op].op, src_regs);
1000 return;
1001 case TGSI_OPCODE_KILL:
1002 c->discard = qir_uniform_f(c, 1.0);
1003 return;
1004 case TGSI_OPCODE_KILL_IF:
1005 for (int i = 0; i < 4; i++)
1006 tgsi_to_qir_kill_if(c, src_regs, i);
1007 return;
1008 default:
1009 break;
1010 }
1011
1012 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
1013 fprintf(stderr, "unknown tgsi inst: ");
1014 tgsi_dump_instruction(tgsi_inst, asdf++);
1015 fprintf(stderr, "\n");
1016 abort();
1017 }
1018
1019 for (int i = 0; i < 4; i++) {
1020 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
1021 continue;
1022
1023 struct qreg result;
1024
1025 result = op_trans[tgsi_op].func(c, tgsi_inst,
1026 op_trans[tgsi_op].op,
1027 src_regs, i);
1028
1029 if (tgsi_inst->Instruction.Saturate) {
1030 float low = (tgsi_inst->Instruction.Saturate ==
1031 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
1032 result = qir_FMAX(c,
1033 qir_FMIN(c,
1034 result,
1035 qir_uniform_f(c, 1.0)),
1036 qir_uniform_f(c, low));
1037 }
1038
1039 update_dst(c, tgsi_inst, i, result);
1040 }
1041 }
1042
1043 static void
1044 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)
1045 {
1046 for (int i = 0; i < 4; i++) {
1047 unsigned n = c->num_consts++;
1048 resize_qreg_array(c, &c->consts, &c->consts_array_size, n + 1);
1049 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);
1050 }
1051 }
1052
1053 static struct qreg
1054 vc4_blend_channel(struct vc4_compile *c,
1055 struct qreg *dst,
1056 struct qreg *src,
1057 struct qreg val,
1058 unsigned factor,
1059 int channel)
1060 {
1061 switch(factor) {
1062 case PIPE_BLENDFACTOR_ONE:
1063 return val;
1064 case PIPE_BLENDFACTOR_SRC_COLOR:
1065 return qir_FMUL(c, val, src[channel]);
1066 case PIPE_BLENDFACTOR_SRC_ALPHA:
1067 return qir_FMUL(c, val, src[3]);
1068 case PIPE_BLENDFACTOR_DST_ALPHA:
1069 return qir_FMUL(c, val, dst[3]);
1070 case PIPE_BLENDFACTOR_DST_COLOR:
1071 return qir_FMUL(c, val, dst[channel]);
1072 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1073 return qir_FMIN(c, src[3], qir_FSUB(c,
1074 qir_uniform_f(c, 1.0),
1075 dst[3]));
1076 case PIPE_BLENDFACTOR_CONST_COLOR:
1077 return qir_FMUL(c, val,
1078 get_temp_for_uniform(c,
1079 QUNIFORM_BLEND_CONST_COLOR,
1080 channel));
1081 case PIPE_BLENDFACTOR_CONST_ALPHA:
1082 return qir_FMUL(c, val,
1083 get_temp_for_uniform(c,
1084 QUNIFORM_BLEND_CONST_COLOR,
1085 3));
1086 case PIPE_BLENDFACTOR_ZERO:
1087 return qir_uniform_f(c, 0.0);
1088 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1089 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1090 src[channel]));
1091 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1092 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1093 src[3]));
1094 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1095 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1096 dst[3]));
1097 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1098 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1099 dst[channel]));
1100 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1101 return qir_FMUL(c, val,
1102 qir_FSUB(c, qir_uniform_f(c, 1.0),
1103 get_temp_for_uniform(c,
1104 QUNIFORM_BLEND_CONST_COLOR,
1105 channel)));
1106 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1107 return qir_FMUL(c, val,
1108 qir_FSUB(c, qir_uniform_f(c, 1.0),
1109 get_temp_for_uniform(c,
1110 QUNIFORM_BLEND_CONST_COLOR,
1111 3)));
1112
1113 default:
1114 case PIPE_BLENDFACTOR_SRC1_COLOR:
1115 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1116 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1117 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1118 /* Unsupported. */
1119 fprintf(stderr, "Unknown blend factor %d\n", factor);
1120 return val;
1121 }
1122 }
1123
1124 static struct qreg
1125 vc4_blend_func(struct vc4_compile *c,
1126 struct qreg src, struct qreg dst,
1127 unsigned func)
1128 {
1129 switch (func) {
1130 case PIPE_BLEND_ADD:
1131 return qir_FADD(c, src, dst);
1132 case PIPE_BLEND_SUBTRACT:
1133 return qir_FSUB(c, src, dst);
1134 case PIPE_BLEND_REVERSE_SUBTRACT:
1135 return qir_FSUB(c, dst, src);
1136 case PIPE_BLEND_MIN:
1137 return qir_FMIN(c, src, dst);
1138 case PIPE_BLEND_MAX:
1139 return qir_FMAX(c, src, dst);
1140
1141 default:
1142 /* Unsupported. */
1143 fprintf(stderr, "Unknown blend func %d\n", func);
1144 return src;
1145
1146 }
1147 }
1148
1149 /**
1150 * Implements fixed function blending in shader code.
1151 *
1152 * VC4 doesn't have any hardware support for blending. Instead, you read the
1153 * current contents of the destination from the tile buffer after having
1154 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1155 * math using your output color and that destination value, and update the
1156 * output color appropriately.
1157 */
1158 static void
1159 vc4_blend(struct vc4_compile *c, struct qreg *result,
1160 struct qreg *dst_color, struct qreg *src_color)
1161 {
1162 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1163
1164 if (!blend->blend_enable) {
1165 for (int i = 0; i < 4; i++)
1166 result[i] = src_color[i];
1167 return;
1168 }
1169
1170 struct qreg src_blend[4], dst_blend[4];
1171 for (int i = 0; i < 3; i++) {
1172 src_blend[i] = vc4_blend_channel(c,
1173 dst_color, src_color,
1174 src_color[i],
1175 blend->rgb_src_factor, i);
1176 dst_blend[i] = vc4_blend_channel(c,
1177 dst_color, src_color,
1178 dst_color[i],
1179 blend->rgb_dst_factor, i);
1180 }
1181 src_blend[3] = vc4_blend_channel(c,
1182 dst_color, src_color,
1183 src_color[3],
1184 blend->alpha_src_factor, 3);
1185 dst_blend[3] = vc4_blend_channel(c,
1186 dst_color, src_color,
1187 dst_color[3],
1188 blend->alpha_dst_factor, 3);
1189
1190 for (int i = 0; i < 3; i++) {
1191 result[i] = vc4_blend_func(c,
1192 src_blend[i], dst_blend[i],
1193 blend->rgb_func);
1194 }
1195 result[3] = vc4_blend_func(c,
1196 src_blend[3], dst_blend[3],
1197 blend->alpha_func);
1198 }
1199
1200 static void
1201 emit_frag_end(struct vc4_compile *c)
1202 {
1203 enum pipe_format color_format = c->fs_key->color_format;
1204 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1205 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1206 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1207 if (c->fs_key->blend.blend_enable ||
1208 c->fs_key->blend.colormask != 0xf) {
1209 struct qreg r4 = qir_TLB_COLOR_READ(c);
1210 for (int i = 0; i < 4; i++)
1211 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1212 for (int i = 0; i < 4; i++)
1213 dst_color[i] = get_swizzled_channel(c,
1214 tlb_read_color,
1215 format_swiz[i]);
1216 }
1217
1218 struct qreg blend_color[4];
1219 struct qreg undef_array[4] = {
1220 c->undef, c->undef, c->undef, c->undef
1221 };
1222 vc4_blend(c, blend_color, dst_color,
1223 (c->output_color_index != -1 ?
1224 c->outputs + c->output_color_index :
1225 undef_array));
1226
1227 /* If the bit isn't set in the color mask, then just return the
1228 * original dst color, instead.
1229 */
1230 for (int i = 0; i < 4; i++) {
1231 if (!(c->fs_key->blend.colormask & (1 << i))) {
1232 blend_color[i] = dst_color[i];
1233 }
1234 }
1235
1236 /* Debug: Sometimes you're getting a black output and just want to see
1237 * if the FS is getting executed at all. Spam magenta into the color
1238 * output.
1239 */
1240 if (0) {
1241 blend_color[0] = qir_uniform_f(c, 1.0);
1242 blend_color[1] = qir_uniform_f(c, 0.0);
1243 blend_color[2] = qir_uniform_f(c, 1.0);
1244 blend_color[3] = qir_uniform_f(c, 0.5);
1245 }
1246
1247 struct qreg swizzled_outputs[4];
1248 for (int i = 0; i < 4; i++) {
1249 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1250 format_swiz[i]);
1251 }
1252
1253 if (c->discard.file != QFILE_NULL)
1254 qir_TLB_DISCARD_SETUP(c, c->discard);
1255
1256 if (c->fs_key->depth_enabled) {
1257 struct qreg z;
1258 if (c->output_position_index != -1) {
1259 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1260 qir_uniform_f(c, 0xffffff)));
1261 } else {
1262 z = qir_FRAG_Z(c);
1263 }
1264 qir_TLB_Z_WRITE(c, z);
1265 }
1266
1267 bool color_written = false;
1268 for (int i = 0; i < 4; i++) {
1269 if (swizzled_outputs[i].file != QFILE_NULL)
1270 color_written = true;
1271 }
1272
1273 struct qreg packed_color;
1274 if (color_written) {
1275 /* Fill in any undefined colors. The simulator will assertion
1276 * fail if we read something that wasn't written, and I don't
1277 * know what hardware does.
1278 */
1279 for (int i = 0; i < 4; i++) {
1280 if (swizzled_outputs[i].file == QFILE_NULL)
1281 swizzled_outputs[i] = qir_uniform_f(c, 0.0);
1282 }
1283 packed_color = qir_get_temp(c);
1284 qir_emit(c, qir_inst4(QOP_PACK_COLORS, packed_color,
1285 swizzled_outputs[0],
1286 swizzled_outputs[1],
1287 swizzled_outputs[2],
1288 swizzled_outputs[3]));
1289 } else {
1290 packed_color = qir_uniform_ui(c, 0);
1291 }
1292
1293 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1294 packed_color, c->undef));
1295 }
1296
1297 static void
1298 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1299 {
1300 struct qreg xyi[2];
1301
1302 for (int i = 0; i < 2; i++) {
1303 struct qreg scale =
1304 add_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1305
1306 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1307 qir_FMUL(c,
1308 c->outputs[i],
1309 scale),
1310 rcp_w));
1311 }
1312
1313 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1314 }
1315
1316 static void
1317 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1318 {
1319 struct qreg zscale = add_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1320 struct qreg zoffset = add_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1321
1322 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1323 c->outputs[2],
1324 zscale),
1325 zoffset),
1326 rcp_w));
1327 }
1328
1329 static void
1330 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1331 {
1332 qir_VPM_WRITE(c, rcp_w);
1333 }
1334
1335 static void
1336 emit_vert_end(struct vc4_compile *c)
1337 {
1338 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1339
1340 emit_scaled_viewport_write(c, rcp_w);
1341 emit_zs_write(c, rcp_w);
1342 emit_rcp_wc_write(c, rcp_w);
1343
1344 for (int i = 4; i < c->num_outputs; i++) {
1345 qir_VPM_WRITE(c, c->outputs[i]);
1346 }
1347 }
1348
1349 static void
1350 emit_coord_end(struct vc4_compile *c)
1351 {
1352 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1353
1354 for (int i = 0; i < 4; i++)
1355 qir_VPM_WRITE(c, c->outputs[i]);
1356
1357 emit_scaled_viewport_write(c, rcp_w);
1358 emit_zs_write(c, rcp_w);
1359 emit_rcp_wc_write(c, rcp_w);
1360 }
1361
1362 static struct vc4_compile *
1363 vc4_shader_tgsi_to_qir(struct vc4_compiled_shader *shader, enum qstage stage,
1364 struct vc4_key *key)
1365 {
1366 struct vc4_compile *c = qir_compile_init();
1367 int ret;
1368
1369 c->stage = stage;
1370
1371 c->uniform_data = ralloc_array(c, uint32_t, 1024);
1372 c->uniform_contents = ralloc_array(c, enum quniform_contents, 1024);
1373
1374 c->shader_state = key->shader_state;
1375 ret = tgsi_parse_init(&c->parser, c->shader_state->tokens);
1376 assert(ret == TGSI_PARSE_OK);
1377
1378 if (vc4_debug & VC4_DEBUG_TGSI) {
1379 fprintf(stderr, "TGSI:\n");
1380 tgsi_dump(c->shader_state->tokens, 0);
1381 }
1382
1383 c->key = key;
1384 switch (stage) {
1385 case QSTAGE_FRAG:
1386 c->fs_key = (struct vc4_fs_key *)key;
1387 if (c->fs_key->is_points) {
1388 c->point_x = emit_fragment_varying(c, 0);
1389 c->point_y = emit_fragment_varying(c, 0);
1390 } else if (c->fs_key->is_lines) {
1391 c->line_x = emit_fragment_varying(c, 0);
1392 }
1393 break;
1394 case QSTAGE_VERT:
1395 c->vs_key = (struct vc4_vs_key *)key;
1396 break;
1397 case QSTAGE_COORD:
1398 c->vs_key = (struct vc4_vs_key *)key;
1399 break;
1400 }
1401
1402 while (!tgsi_parse_end_of_tokens(&c->parser)) {
1403 tgsi_parse_token(&c->parser);
1404
1405 switch (c->parser.FullToken.Token.Type) {
1406 case TGSI_TOKEN_TYPE_DECLARATION:
1407 emit_tgsi_declaration(c,
1408 &c->parser.FullToken.FullDeclaration);
1409 break;
1410
1411 case TGSI_TOKEN_TYPE_INSTRUCTION:
1412 emit_tgsi_instruction(c,
1413 &c->parser.FullToken.FullInstruction);
1414 break;
1415
1416 case TGSI_TOKEN_TYPE_IMMEDIATE:
1417 parse_tgsi_immediate(c,
1418 &c->parser.FullToken.FullImmediate);
1419 break;
1420 }
1421 }
1422
1423 switch (stage) {
1424 case QSTAGE_FRAG:
1425 emit_frag_end(c);
1426 break;
1427 case QSTAGE_VERT:
1428 emit_vert_end(c);
1429 break;
1430 case QSTAGE_COORD:
1431 emit_coord_end(c);
1432 break;
1433 }
1434
1435 tgsi_parse_free(&c->parser);
1436
1437 qir_optimize(c);
1438
1439 if (vc4_debug & VC4_DEBUG_QIR) {
1440 fprintf(stderr, "QIR:\n");
1441 qir_dump(c);
1442 }
1443 qir_reorder_uniforms(c);
1444 vc4_generate_code(c);
1445
1446 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1447 fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
1448 qir_get_stage_name(c->stage), c->qpu_inst_count);
1449 fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
1450 qir_get_stage_name(c->stage), c->num_uniforms);
1451 }
1452
1453 return c;
1454 }
1455
1456 static void *
1457 vc4_shader_state_create(struct pipe_context *pctx,
1458 const struct pipe_shader_state *cso)
1459 {
1460 struct pipe_shader_state *so = CALLOC_STRUCT(pipe_shader_state);
1461 if (!so)
1462 return NULL;
1463
1464 so->tokens = tgsi_dup_tokens(cso->tokens);
1465
1466 return so;
1467 }
1468
1469 static void
1470 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1471 int shader_index,
1472 struct vc4_compile *c)
1473 {
1474 int count = c->num_uniforms;
1475 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1476
1477 uinfo->count = count;
1478 uinfo->data = malloc(count * sizeof(*uinfo->data));
1479 memcpy(uinfo->data, c->uniform_data,
1480 count * sizeof(*uinfo->data));
1481 uinfo->contents = malloc(count * sizeof(*uinfo->contents));
1482 memcpy(uinfo->contents, c->uniform_contents,
1483 count * sizeof(*uinfo->contents));
1484 uinfo->num_texture_samples = c->num_texture_samples;
1485 }
1486
1487 static void
1488 vc4_fs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1489 struct vc4_fs_key *key)
1490 {
1491 struct vc4_compile *c = vc4_shader_tgsi_to_qir(shader, QSTAGE_FRAG,
1492 &key->base);
1493 shader->num_inputs = c->num_inputs;
1494 copy_uniform_state_to_shader(shader, 0, c);
1495 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
1496 c->qpu_inst_count * sizeof(uint64_t),
1497 "fs_code");
1498
1499 qir_compile_destroy(c);
1500 }
1501
1502 static void
1503 vc4_vs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1504 struct vc4_vs_key *key)
1505 {
1506 struct vc4_compile *vs_c = vc4_shader_tgsi_to_qir(shader,
1507 QSTAGE_VERT,
1508 &key->base);
1509 copy_uniform_state_to_shader(shader, 0, vs_c);
1510
1511 struct vc4_compile *cs_c = vc4_shader_tgsi_to_qir(shader,
1512 QSTAGE_COORD,
1513 &key->base);
1514 copy_uniform_state_to_shader(shader, 1, cs_c);
1515
1516 uint32_t vs_size = vs_c->qpu_inst_count * sizeof(uint64_t);
1517 uint32_t cs_size = cs_c->qpu_inst_count * sizeof(uint64_t);
1518 shader->coord_shader_offset = vs_size; /* XXX: alignment? */
1519 shader->bo = vc4_bo_alloc(vc4->screen,
1520 shader->coord_shader_offset + cs_size,
1521 "vs_code");
1522
1523 void *map = vc4_bo_map(shader->bo);
1524 memcpy(map, vs_c->qpu_insts, vs_size);
1525 memcpy(map + shader->coord_shader_offset,
1526 cs_c->qpu_insts, cs_size);
1527
1528 qir_compile_destroy(vs_c);
1529 qir_compile_destroy(cs_c);
1530 }
1531
1532 static void
1533 vc4_setup_shared_key(struct vc4_key *key, struct vc4_texture_stateobj *texstate)
1534 {
1535 for (int i = 0; i < texstate->num_textures; i++) {
1536 struct pipe_sampler_view *sampler = texstate->textures[i];
1537 struct pipe_sampler_state *sampler_state =
1538 texstate->samplers[i];
1539
1540 if (sampler) {
1541 struct pipe_resource *prsc = sampler->texture;
1542 key->tex[i].format = prsc->format;
1543 key->tex[i].swizzle[0] = sampler->swizzle_r;
1544 key->tex[i].swizzle[1] = sampler->swizzle_g;
1545 key->tex[i].swizzle[2] = sampler->swizzle_b;
1546 key->tex[i].swizzle[3] = sampler->swizzle_a;
1547 key->tex[i].compare_mode = sampler_state->compare_mode;
1548 key->tex[i].compare_func = sampler_state->compare_func;
1549 }
1550 }
1551 }
1552
1553 static void
1554 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
1555 {
1556 struct vc4_fs_key local_key;
1557 struct vc4_fs_key *key = &local_key;
1558
1559 memset(key, 0, sizeof(*key));
1560 vc4_setup_shared_key(&key->base, &vc4->fragtex);
1561 key->base.shader_state = vc4->prog.bind_fs;
1562 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
1563 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
1564 prim_mode <= PIPE_PRIM_LINE_STRIP);
1565 key->blend = vc4->blend->rt[0];
1566
1567 if (vc4->framebuffer.cbufs[0])
1568 key->color_format = vc4->framebuffer.cbufs[0]->format;
1569
1570 key->depth_enabled = vc4->zsa->base.depth.enabled;
1571
1572 vc4->prog.fs = util_hash_table_get(vc4->fs_cache, key);
1573 if (vc4->prog.fs)
1574 return;
1575
1576 key = malloc(sizeof(*key));
1577 memcpy(key, &local_key, sizeof(*key));
1578
1579 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1580 vc4_fs_compile(vc4, shader, key);
1581 util_hash_table_set(vc4->fs_cache, key, shader);
1582
1583 vc4->prog.fs = shader;
1584 }
1585
1586 static void
1587 vc4_update_compiled_vs(struct vc4_context *vc4)
1588 {
1589 struct vc4_vs_key local_key;
1590 struct vc4_vs_key *key = &local_key;
1591
1592 memset(key, 0, sizeof(*key));
1593 vc4_setup_shared_key(&key->base, &vc4->verttex);
1594 key->base.shader_state = vc4->prog.bind_vs;
1595
1596 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
1597 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
1598
1599 vc4->prog.vs = util_hash_table_get(vc4->vs_cache, key);
1600 if (vc4->prog.vs)
1601 return;
1602
1603 key = malloc(sizeof(*key));
1604 memcpy(key, &local_key, sizeof(*key));
1605
1606 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1607 vc4_vs_compile(vc4, shader, key);
1608 util_hash_table_set(vc4->vs_cache, key, shader);
1609
1610 vc4->prog.vs = shader;
1611 }
1612
1613 void
1614 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
1615 {
1616 vc4_update_compiled_fs(vc4, prim_mode);
1617 vc4_update_compiled_vs(vc4);
1618 }
1619
1620 static unsigned
1621 fs_cache_hash(void *key)
1622 {
1623 return util_hash_crc32(key, sizeof(struct vc4_fs_key));
1624 }
1625
1626 static unsigned
1627 vs_cache_hash(void *key)
1628 {
1629 return util_hash_crc32(key, sizeof(struct vc4_vs_key));
1630 }
1631
1632 static int
1633 fs_cache_compare(void *key1, void *key2)
1634 {
1635 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
1636 }
1637
1638 static int
1639 vs_cache_compare(void *key1, void *key2)
1640 {
1641 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
1642 }
1643
1644 struct delete_state {
1645 struct vc4_context *vc4;
1646 struct pipe_shader_state *shader_state;
1647 };
1648
1649 static enum pipe_error
1650 fs_delete_from_cache(void *in_key, void *in_value, void *data)
1651 {
1652 struct delete_state *del = data;
1653 struct vc4_fs_key *key = in_key;
1654 struct vc4_compiled_shader *shader = in_value;
1655
1656 if (key->base.shader_state == data) {
1657 util_hash_table_remove(del->vc4->fs_cache, key);
1658 vc4_bo_unreference(&shader->bo);
1659 free(shader);
1660 }
1661
1662 return 0;
1663 }
1664
1665 static enum pipe_error
1666 vs_delete_from_cache(void *in_key, void *in_value, void *data)
1667 {
1668 struct delete_state *del = data;
1669 struct vc4_vs_key *key = in_key;
1670 struct vc4_compiled_shader *shader = in_value;
1671
1672 if (key->base.shader_state == data) {
1673 util_hash_table_remove(del->vc4->vs_cache, key);
1674 vc4_bo_unreference(&shader->bo);
1675 free(shader);
1676 }
1677
1678 return 0;
1679 }
1680
1681 static void
1682 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1683 {
1684 struct vc4_context *vc4 = vc4_context(pctx);
1685 struct pipe_shader_state *so = hwcso;
1686 struct delete_state del;
1687
1688 del.vc4 = vc4;
1689 del.shader_state = so;
1690 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
1691 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
1692
1693 free((void *)so->tokens);
1694 free(so);
1695 }
1696
1697 static uint32_t translate_wrap(uint32_t p_wrap)
1698 {
1699 switch (p_wrap) {
1700 case PIPE_TEX_WRAP_REPEAT:
1701 return 0;
1702 case PIPE_TEX_WRAP_CLAMP:
1703 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1704 return 1;
1705 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1706 return 2;
1707 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1708 return 3;
1709 default:
1710 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
1711 assert(!"not reached");
1712 return 0;
1713 }
1714 }
1715
1716 static void
1717 write_texture_p0(struct vc4_context *vc4,
1718 struct vc4_texture_stateobj *texstate,
1719 uint32_t unit)
1720 {
1721 struct pipe_sampler_view *texture = texstate->textures[unit];
1722 struct vc4_resource *rsc = vc4_resource(texture->texture);
1723
1724 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
1725 rsc->slices[0].offset | texture->u.tex.last_level |
1726 ((rsc->vc4_format & 7) << 4));
1727 }
1728
1729 static void
1730 write_texture_p1(struct vc4_context *vc4,
1731 struct vc4_texture_stateobj *texstate,
1732 uint32_t unit)
1733 {
1734 struct pipe_sampler_view *texture = texstate->textures[unit];
1735 struct vc4_resource *rsc = vc4_resource(texture->texture);
1736 struct pipe_sampler_state *sampler = texstate->samplers[unit];
1737 static const uint32_t mipfilter_map[] = {
1738 [PIPE_TEX_MIPFILTER_NEAREST] = 2,
1739 [PIPE_TEX_MIPFILTER_LINEAR] = 4,
1740 [PIPE_TEX_MIPFILTER_NONE] = 0
1741 };
1742 static const uint32_t imgfilter_map[] = {
1743 [PIPE_TEX_FILTER_NEAREST] = 1,
1744 [PIPE_TEX_FILTER_LINEAR] = 0,
1745 };
1746
1747 cl_u32(&vc4->uniforms,
1748 ((rsc->vc4_format >> 4) << 31) |
1749 (texture->texture->height0 << 20) |
1750 (texture->texture->width0 << 8) |
1751 (imgfilter_map[sampler->mag_img_filter] << 7) |
1752 ((imgfilter_map[sampler->min_img_filter] +
1753 mipfilter_map[sampler->min_mip_filter]) << 4) |
1754 (translate_wrap(sampler->wrap_t) << 2) |
1755 (translate_wrap(sampler->wrap_s) << 0));
1756 }
1757
1758 static uint32_t
1759 get_texrect_scale(struct vc4_texture_stateobj *texstate,
1760 enum quniform_contents contents,
1761 uint32_t data)
1762 {
1763 struct pipe_sampler_view *texture = texstate->textures[data];
1764 uint32_t dim;
1765
1766 if (contents == QUNIFORM_TEXRECT_SCALE_X)
1767 dim = texture->texture->width0;
1768 else
1769 dim = texture->texture->height0;
1770
1771 return fui(1.0f / dim);
1772 }
1773
1774 void
1775 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1776 struct vc4_constbuf_stateobj *cb,
1777 struct vc4_texture_stateobj *texstate,
1778 int shader_index)
1779 {
1780 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1781 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
1782
1783 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
1784
1785 for (int i = 0; i < uinfo->count; i++) {
1786
1787 switch (uinfo->contents[i]) {
1788 case QUNIFORM_CONSTANT:
1789 cl_u32(&vc4->uniforms, uinfo->data[i]);
1790 break;
1791 case QUNIFORM_UNIFORM:
1792 cl_u32(&vc4->uniforms,
1793 gallium_uniforms[uinfo->data[i]]);
1794 break;
1795 case QUNIFORM_VIEWPORT_X_SCALE:
1796 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
1797 break;
1798 case QUNIFORM_VIEWPORT_Y_SCALE:
1799 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
1800 break;
1801
1802 case QUNIFORM_VIEWPORT_Z_OFFSET:
1803 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
1804 break;
1805 case QUNIFORM_VIEWPORT_Z_SCALE:
1806 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
1807 break;
1808
1809 case QUNIFORM_TEXTURE_CONFIG_P0:
1810 write_texture_p0(vc4, texstate, uinfo->data[i]);
1811 break;
1812
1813 case QUNIFORM_TEXTURE_CONFIG_P1:
1814 write_texture_p1(vc4, texstate, uinfo->data[i]);
1815 break;
1816
1817 case QUNIFORM_TEXRECT_SCALE_X:
1818 case QUNIFORM_TEXRECT_SCALE_Y:
1819 cl_u32(&vc4->uniforms,
1820 get_texrect_scale(texstate,
1821 uinfo->contents[i],
1822 uinfo->data[i]));
1823 break;
1824
1825 case QUNIFORM_BLEND_CONST_COLOR:
1826 cl_f(&vc4->uniforms,
1827 vc4->blend_color.color[uinfo->data[i]]);
1828 break;
1829 }
1830 #if 0
1831 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
1832 fprintf(stderr, "%p/%d: %d: 0x%08x (%f)\n",
1833 shader, shader_index, i, written_val, uif(written_val));
1834 #endif
1835 }
1836 }
1837
1838 static void
1839 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
1840 {
1841 struct vc4_context *vc4 = vc4_context(pctx);
1842 vc4->prog.bind_fs = hwcso;
1843 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
1844 vc4->dirty |= VC4_DIRTY_PROG;
1845 }
1846
1847 static void
1848 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
1849 {
1850 struct vc4_context *vc4 = vc4_context(pctx);
1851 vc4->prog.bind_vs = hwcso;
1852 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
1853 vc4->dirty |= VC4_DIRTY_PROG;
1854 }
1855
1856 void
1857 vc4_program_init(struct pipe_context *pctx)
1858 {
1859 struct vc4_context *vc4 = vc4_context(pctx);
1860
1861 pctx->create_vs_state = vc4_shader_state_create;
1862 pctx->delete_vs_state = vc4_shader_state_delete;
1863
1864 pctx->create_fs_state = vc4_shader_state_create;
1865 pctx->delete_fs_state = vc4_shader_state_delete;
1866
1867 pctx->bind_fs_state = vc4_fp_state_bind;
1868 pctx->bind_vs_state = vc4_vp_state_bind;
1869
1870 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
1871 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
1872 }