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vc4: Clear padding of ioctl arguments.
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "tgsi/tgsi_parse.h"
32 #include "tgsi/tgsi_dump.h"
33
34 #include "vc4_context.h"
35 #include "vc4_qpu.h"
36 #include "vc4_qir.h"
37 #ifdef USE_VC4_SIMULATOR
38 #include "simpenrose/simpenrose.h"
39 #endif
40
41 struct tgsi_to_qir {
42 struct tgsi_parse_context parser;
43 struct qcompile *c;
44 struct qreg *temps;
45 struct qreg *inputs;
46 struct qreg *outputs;
47 struct qreg *uniforms;
48 struct qreg *consts;
49 struct qreg line_x, point_x, point_y;
50 struct qreg discard;
51
52 uint32_t num_consts;
53
54 struct pipe_shader_state *shader_state;
55 struct vc4_key *key;
56 struct vc4_fs_key *fs_key;
57 struct vc4_vs_key *vs_key;
58
59 uint32_t *uniform_data;
60 enum quniform_contents *uniform_contents;
61 uint32_t num_uniforms;
62 uint32_t num_outputs;
63 uint32_t num_texture_samples;
64 };
65
66 struct vc4_key {
67 struct pipe_shader_state *shader_state;
68 enum pipe_format tex_format[VC4_MAX_TEXTURE_SAMPLERS];
69 };
70
71 struct vc4_fs_key {
72 struct vc4_key base;
73 enum pipe_format color_format;
74 bool depth_enabled;
75 bool is_points;
76 bool is_lines;
77
78 struct pipe_rt_blend_state blend;
79 };
80
81 struct vc4_vs_key {
82 struct vc4_key base;
83 enum pipe_format attr_formats[8];
84 };
85
86 static struct qreg
87 add_uniform(struct tgsi_to_qir *trans,
88 enum quniform_contents contents,
89 uint32_t data)
90 {
91 uint32_t uniform = trans->num_uniforms++;
92 struct qreg u = { QFILE_UNIF, uniform };
93
94 trans->uniform_contents[uniform] = contents;
95 trans->uniform_data[uniform] = data;
96
97 return u;
98 }
99
100 static struct qreg
101 get_temp_for_uniform(struct tgsi_to_qir *trans, enum quniform_contents contents,
102 uint32_t data)
103 {
104 struct qcompile *c = trans->c;
105
106 for (int i = 0; i < trans->num_uniforms; i++) {
107 if (trans->uniform_contents[i] == contents &&
108 trans->uniform_data[i] == data)
109 return trans->uniforms[i];
110 }
111
112 struct qreg u = add_uniform(trans, contents, data);
113 struct qreg t = qir_MOV(c, u);
114
115 trans->uniforms[u.index] = t;
116 return t;
117 }
118
119 static struct qreg
120 qir_uniform_ui(struct tgsi_to_qir *trans, uint32_t ui)
121 {
122 return get_temp_for_uniform(trans, QUNIFORM_CONSTANT, ui);
123 }
124
125 static struct qreg
126 qir_uniform_f(struct tgsi_to_qir *trans, float f)
127 {
128 return qir_uniform_ui(trans, fui(f));
129 }
130
131 static struct qreg
132 get_src(struct tgsi_to_qir *trans, struct tgsi_src_register *src, int i)
133 {
134 struct qcompile *c = trans->c;
135 struct qreg r = c->undef;
136
137 uint32_t s = i;
138 switch (i) {
139 case TGSI_SWIZZLE_X:
140 s = src->SwizzleX;
141 break;
142 case TGSI_SWIZZLE_Y:
143 s = src->SwizzleY;
144 break;
145 case TGSI_SWIZZLE_Z:
146 s = src->SwizzleZ;
147 break;
148 case TGSI_SWIZZLE_W:
149 s = src->SwizzleW;
150 break;
151 default:
152 abort();
153 }
154
155 assert(!src->Indirect);
156
157 switch (src->File) {
158 case TGSI_FILE_NULL:
159 return r;
160 case TGSI_FILE_TEMPORARY:
161 r = trans->temps[src->Index * 4 + s];
162 break;
163 case TGSI_FILE_IMMEDIATE:
164 r = trans->consts[src->Index * 4 + s];
165 break;
166 case TGSI_FILE_CONSTANT:
167 r = get_temp_for_uniform(trans, QUNIFORM_UNIFORM,
168 src->Index * 4 + s);
169 break;
170 case TGSI_FILE_INPUT:
171 r = trans->inputs[src->Index * 4 + s];
172 break;
173 case TGSI_FILE_SAMPLER:
174 case TGSI_FILE_SAMPLER_VIEW:
175 r = c->undef;
176 break;
177 default:
178 fprintf(stderr, "unknown src file %d\n", src->File);
179 abort();
180 }
181
182 if (src->Absolute)
183 r = qir_FMAXABS(c, r, r);
184
185 if (src->Negate)
186 r = qir_FSUB(c, qir_uniform_f(trans, 0), r);
187
188 return r;
189 };
190
191
192 static void
193 update_dst(struct tgsi_to_qir *trans, struct tgsi_full_instruction *tgsi_inst,
194 int i, struct qreg val)
195 {
196 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
197
198 assert(!tgsi_dst->Indirect);
199
200 switch (tgsi_dst->File) {
201 case TGSI_FILE_TEMPORARY:
202 trans->temps[tgsi_dst->Index * 4 + i] = val;
203 break;
204 case TGSI_FILE_OUTPUT:
205 trans->outputs[tgsi_dst->Index * 4 + i] = val;
206 trans->num_outputs = MAX2(trans->num_outputs,
207 tgsi_dst->Index * 4 + i + 1);
208 break;
209 default:
210 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
211 abort();
212 }
213 };
214
215 static struct qreg
216 get_swizzled_channel(struct tgsi_to_qir *trans,
217 struct qreg *srcs, int swiz)
218 {
219 switch (swiz) {
220 default:
221 case UTIL_FORMAT_SWIZZLE_NONE:
222 fprintf(stderr, "warning: unknown swizzle\n");
223 /* FALLTHROUGH */
224 case UTIL_FORMAT_SWIZZLE_0:
225 return qir_uniform_f(trans, 0.0);
226 case UTIL_FORMAT_SWIZZLE_1:
227 return qir_uniform_f(trans, 1.0);
228 case UTIL_FORMAT_SWIZZLE_X:
229 case UTIL_FORMAT_SWIZZLE_Y:
230 case UTIL_FORMAT_SWIZZLE_Z:
231 case UTIL_FORMAT_SWIZZLE_W:
232 return srcs[swiz];
233 }
234 }
235
236 static struct qreg
237 tgsi_to_qir_alu(struct tgsi_to_qir *trans,
238 struct tgsi_full_instruction *tgsi_inst,
239 enum qop op, struct qreg *src, int i)
240 {
241 struct qcompile *c = trans->c;
242 struct qreg dst = qir_get_temp(c);
243 qir_emit(c, qir_inst4(op, dst,
244 src[0 * 4 + i],
245 src[1 * 4 + i],
246 src[2 * 4 + i],
247 c->undef));
248 return dst;
249 }
250
251 static struct qreg
252 tgsi_to_qir_mad(struct tgsi_to_qir *trans,
253 struct tgsi_full_instruction *tgsi_inst,
254 enum qop op, struct qreg *src, int i)
255 {
256 struct qcompile *c = trans->c;
257 return qir_FADD(c,
258 qir_FMUL(c,
259 src[0 * 4 + i],
260 src[1 * 4 + i]),
261 src[2 * 4 + i]);
262 }
263
264 static struct qreg
265 tgsi_to_qir_lit(struct tgsi_to_qir *trans,
266 struct tgsi_full_instruction *tgsi_inst,
267 enum qop op, struct qreg *src, int i)
268 {
269 struct qcompile *c = trans->c;
270 struct qreg x = src[0 * 4 + 0];
271 struct qreg y = src[0 * 4 + 1];
272 struct qreg w = src[0 * 4 + 3];
273
274 switch (i) {
275 case 0:
276 case 3:
277 return qir_uniform_f(trans, 1.0);
278 case 1:
279 return qir_FMAX(c, src[0 * 4 + 0], qir_uniform_f(trans, 0.0));
280 case 2: {
281 struct qreg zero = qir_uniform_f(trans, 0.0);
282
283 /* XXX: Clamp w to -128..128 */
284 return qir_CMP(c,
285 x,
286 zero,
287 qir_EXP2(c, qir_FMUL(c,
288 w,
289 qir_LOG2(c,
290 qir_FMAX(c,
291 y,
292 zero)))));
293 }
294 default:
295 assert(!"not reached");
296 return c->undef;
297 }
298 }
299
300 static struct qreg
301 tgsi_to_qir_lrp(struct tgsi_to_qir *trans,
302 struct tgsi_full_instruction *tgsi_inst,
303 enum qop op, struct qreg *src, int i)
304 {
305 struct qcompile *c = trans->c;
306 struct qreg src0 = src[0 * 4 + i];
307 struct qreg src1 = src[1 * 4 + i];
308 struct qreg src2 = src[2 * 4 + i];
309
310 /* LRP is:
311 * src0 * src1 + (1 - src0) * src2.
312 * -> src0 * src1 + src2 - src0 * src2
313 * -> src2 + src0 * (src1 - src2)
314 */
315 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
316
317 }
318
319 static void
320 tgsi_to_qir_tex(struct tgsi_to_qir *trans,
321 struct tgsi_full_instruction *tgsi_inst,
322 enum qop op, struct qreg *src)
323 {
324 struct qcompile *c = trans->c;
325
326 assert(!tgsi_inst->Instruction.Saturate);
327
328 struct qreg s = src[0 * 4 + 0];
329 struct qreg t = src[0 * 4 + 1];
330 uint32_t unit = tgsi_inst->Src[1].Register.Index;
331
332 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
333 struct qreg proj = qir_RCP(c, src[0 * 4 + 3]);
334 s = qir_FMUL(c, s, proj);
335 t = qir_FMUL(c, t, proj);
336 }
337
338 /* There is no native support for GL texture rectangle coordinates, so
339 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
340 * 1]).
341 */
342 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT) {
343 s = qir_FMUL(c, s,
344 get_temp_for_uniform(trans,
345 QUNIFORM_TEXRECT_SCALE_X,
346 unit));
347 t = qir_FMUL(c, t,
348 get_temp_for_uniform(trans,
349 QUNIFORM_TEXRECT_SCALE_Y,
350 unit));
351 }
352
353 qir_TEX_T(c, t, add_uniform(trans, QUNIFORM_TEXTURE_CONFIG_P0,
354 unit));
355
356 struct qreg sampler_p1 = add_uniform(trans, QUNIFORM_TEXTURE_CONFIG_P1,
357 unit);
358 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
359 qir_TEX_B(c, src[0 * 4 + 3], sampler_p1);
360 qir_TEX_S(c, s, add_uniform(trans, QUNIFORM_CONSTANT, 0));
361 } else {
362 qir_TEX_S(c, s, sampler_p1);
363 }
364
365 trans->num_texture_samples++;
366 qir_emit(c, qir_inst(QOP_TEX_RESULT, c->undef, c->undef, c->undef));
367
368 struct qreg unpacked[4];
369 for (int i = 0; i < 4; i++)
370 unpacked[i] = qir_R4_UNPACK(c, i);
371
372 enum pipe_format format = trans->key->tex_format[unit];
373 const uint8_t *swiz = vc4_get_format_swizzle(format);
374 for (int i = 0; i < 4; i++) {
375 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
376 continue;
377
378 update_dst(trans, tgsi_inst, i,
379 get_swizzled_channel(trans, unpacked, swiz[i]));
380 }
381 }
382
383 static struct qreg
384 tgsi_to_qir_pow(struct tgsi_to_qir *trans,
385 struct tgsi_full_instruction *tgsi_inst,
386 enum qop op, struct qreg *src, int i)
387 {
388 struct qcompile *c = trans->c;
389
390 /* Note that this instruction replicates its result from the x channel
391 */
392 return qir_EXP2(c, qir_FMUL(c,
393 src[1 * 4 + 0],
394 qir_LOG2(c, src[0 * 4 + 0])));
395 }
396
397 static struct qreg
398 tgsi_to_qir_trunc(struct tgsi_to_qir *trans,
399 struct tgsi_full_instruction *tgsi_inst,
400 enum qop op, struct qreg *src, int i)
401 {
402 struct qcompile *c = trans->c;
403 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
404 }
405
406 /**
407 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
408 * to zero).
409 */
410 static struct qreg
411 tgsi_to_qir_frc(struct tgsi_to_qir *trans,
412 struct tgsi_full_instruction *tgsi_inst,
413 enum qop op, struct qreg *src, int i)
414 {
415 struct qcompile *c = trans->c;
416 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
417 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
418 return qir_CMP(c,
419 diff,
420 qir_FADD(c, diff, qir_uniform_f(trans, 1.0)),
421 diff);
422 }
423
424 /**
425 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
426 * zero).
427 */
428 static struct qreg
429 tgsi_to_qir_flr(struct tgsi_to_qir *trans,
430 struct tgsi_full_instruction *tgsi_inst,
431 enum qop op, struct qreg *src, int i)
432 {
433 struct qcompile *c = trans->c;
434 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
435
436 /* This will be < 0 if we truncated and the truncation was of a value
437 * that was < 0 in the first place.
438 */
439 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
440
441 return qir_CMP(c,
442 diff,
443 qir_FSUB(c, trunc, qir_uniform_f(trans, 1.0)),
444 trunc);
445 }
446
447 static struct qreg
448 tgsi_to_qir_dp(struct tgsi_to_qir *trans,
449 struct tgsi_full_instruction *tgsi_inst,
450 int num, struct qreg *src, int i)
451 {
452 struct qcompile *c = trans->c;
453
454 struct qreg sum = qir_FMUL(c, src[0 * 4 + 0], src[1 * 4 + 0]);
455 for (int j = 1; j < num; j++) {
456 sum = qir_FADD(c, sum, qir_FMUL(c,
457 src[0 * 4 + j],
458 src[1 * 4 + j]));
459 }
460 return sum;
461 }
462
463 static struct qreg
464 tgsi_to_qir_dp2(struct tgsi_to_qir *trans,
465 struct tgsi_full_instruction *tgsi_inst,
466 enum qop op, struct qreg *src, int i)
467 {
468 return tgsi_to_qir_dp(trans, tgsi_inst, 2, src, i);
469 }
470
471 static struct qreg
472 tgsi_to_qir_dp3(struct tgsi_to_qir *trans,
473 struct tgsi_full_instruction *tgsi_inst,
474 enum qop op, struct qreg *src, int i)
475 {
476 return tgsi_to_qir_dp(trans, tgsi_inst, 3, src, i);
477 }
478
479 static struct qreg
480 tgsi_to_qir_dp4(struct tgsi_to_qir *trans,
481 struct tgsi_full_instruction *tgsi_inst,
482 enum qop op, struct qreg *src, int i)
483 {
484 return tgsi_to_qir_dp(trans, tgsi_inst, 4, src, i);
485 }
486
487 static struct qreg
488 tgsi_to_qir_abs(struct tgsi_to_qir *trans,
489 struct tgsi_full_instruction *tgsi_inst,
490 enum qop op, struct qreg *src, int i)
491 {
492 struct qcompile *c = trans->c;
493 struct qreg arg = src[0 * 4 + i];
494 return qir_FMAXABS(c, arg, arg);
495 }
496
497 /* Note that this instruction replicates its result from the x channel */
498 static struct qreg
499 tgsi_to_qir_sin(struct tgsi_to_qir *trans,
500 struct tgsi_full_instruction *tgsi_inst,
501 enum qop op, struct qreg *src, int i)
502 {
503 struct qcompile *c = trans->c;
504 float coeff[] = {
505 2.0 * M_PI,
506 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
507 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
508 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
509 };
510
511 struct qreg scaled_x =
512 qir_FMUL(c,
513 src[0 * 4 + 0],
514 qir_uniform_f(trans, 1.0f / (M_PI * 2.0f)));
515
516
517 struct qreg x = tgsi_to_qir_frc(trans, NULL, 0, &scaled_x, 0);
518 struct qreg x2 = qir_FMUL(c, x, x);
519 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(trans, coeff[0]));
520 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
521 x = qir_FMUL(c, x, x2);
522 sum = qir_FADD(c,
523 sum,
524 qir_FMUL(c,
525 x,
526 qir_uniform_f(trans, coeff[i])));
527 }
528 return sum;
529 }
530
531 /* Note that this instruction replicates its result from the x channel */
532 static struct qreg
533 tgsi_to_qir_cos(struct tgsi_to_qir *trans,
534 struct tgsi_full_instruction *tgsi_inst,
535 enum qop op, struct qreg *src, int i)
536 {
537 struct qcompile *c = trans->c;
538 float coeff[] = {
539 1.0f,
540 -pow(2.0 * M_PI, 2) / (2 * 1),
541 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
542 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
543 };
544
545 struct qreg scaled_x =
546 qir_FMUL(c, src[0 * 4 + 0],
547 qir_uniform_f(trans, 1.0f / (M_PI * 2.0f)));
548 struct qreg x_frac = tgsi_to_qir_frc(trans, NULL, 0, &scaled_x, 0);
549
550 struct qreg sum = qir_uniform_f(trans, coeff[0]);
551 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
552 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
553 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
554 if (i != 1)
555 x = qir_FMUL(c, x, x2);
556
557 struct qreg mul = qir_FMUL(c,
558 x,
559 qir_uniform_f(trans, coeff[i]));
560 if (i == 0)
561 sum = mul;
562 else
563 sum = qir_FADD(c, sum, mul);
564 }
565 return sum;
566 }
567
568 static void
569 emit_vertex_input(struct tgsi_to_qir *trans, int attr)
570 {
571 enum pipe_format format = trans->vs_key->attr_formats[attr];
572 struct qcompile *c = trans->c;
573 struct qreg vpm_reads[4];
574
575 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
576 * time, so we always read 4 32-bit VPM entries.
577 */
578 for (int i = 0; i < 4; i++) {
579 vpm_reads[i] = qir_get_temp(c);
580 qir_emit(c, qir_inst(QOP_VPM_READ,
581 vpm_reads[i],
582 c->undef,
583 c->undef));
584 c->num_inputs++;
585 }
586
587 bool format_warned = false;
588 const struct util_format_description *desc =
589 util_format_description(format);
590
591 for (int i = 0; i < 4; i++) {
592 uint8_t swiz = desc->swizzle[i];
593
594 if (swiz <= UTIL_FORMAT_SWIZZLE_W &&
595 !format_warned &&
596 (desc->channel[swiz].type != UTIL_FORMAT_TYPE_FLOAT ||
597 desc->channel[swiz].size != 32)) {
598 fprintf(stderr,
599 "vtx element %d unsupported type: %s\n",
600 attr, util_format_name(format));
601 format_warned = true;
602 }
603
604 trans->inputs[attr * 4 + i] =
605 get_swizzled_channel(trans, vpm_reads, swiz);
606 }
607 }
608
609 static void
610 tgsi_to_qir_kill_if(struct tgsi_to_qir *trans, struct qreg *src, int i)
611 {
612 struct qcompile *c = trans->c;
613
614 if (trans->discard.file == QFILE_NULL)
615 trans->discard = qir_uniform_f(trans, 0.0);
616 trans->discard = qir_CMP(c,
617 src[0 * 4 + i],
618 qir_uniform_f(trans, 1.0),
619 trans->discard);
620 }
621
622 static void
623 emit_fragcoord_input(struct tgsi_to_qir *trans, int attr)
624 {
625 struct qcompile *c = trans->c;
626
627 trans->inputs[attr * 4 + 0] = qir_FRAG_X(c);
628 trans->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
629 trans->inputs[attr * 4 + 2] =
630 qir_FMUL(c,
631 qir_FRAG_Z(c),
632 qir_uniform_f(trans, 1.0 / 0xffffff));
633 trans->inputs[attr * 4 + 3] = qir_FRAG_RCP_W(c);
634 }
635
636 static struct qreg
637 emit_fragment_varying(struct tgsi_to_qir *trans, int index)
638 {
639 struct qcompile *c = trans->c;
640
641 struct qreg vary = {
642 QFILE_VARY,
643 index
644 };
645
646 /* XXX: multiply by W */
647 return qir_VARY_ADD_C(c, qir_MOV(c, vary));
648 }
649
650 static void
651 emit_fragment_input(struct tgsi_to_qir *trans, int attr)
652 {
653 struct qcompile *c = trans->c;
654
655 for (int i = 0; i < 4; i++) {
656 trans->inputs[attr * 4 + i] =
657 emit_fragment_varying(trans, attr * 4 + i);
658 c->num_inputs++;
659 }
660 }
661
662 static void
663 emit_tgsi_declaration(struct tgsi_to_qir *trans,
664 struct tgsi_full_declaration *decl)
665 {
666 struct qcompile *c = trans->c;
667
668 switch (decl->Declaration.File) {
669 case TGSI_FILE_INPUT:
670 for (int i = decl->Range.First;
671 i <= decl->Range.Last;
672 i++) {
673 if (c->stage == QSTAGE_FRAG) {
674 if (decl->Semantic.Name ==
675 TGSI_SEMANTIC_POSITION) {
676 emit_fragcoord_input(trans, i);
677 } else {
678 emit_fragment_input(trans, i);
679 }
680 } else {
681 emit_vertex_input(trans, i);
682 }
683 }
684 break;
685 }
686 }
687
688 static void
689 emit_tgsi_instruction(struct tgsi_to_qir *trans,
690 struct tgsi_full_instruction *tgsi_inst)
691 {
692 struct qcompile *c = trans->c;
693 struct {
694 enum qop op;
695 struct qreg (*func)(struct tgsi_to_qir *trans,
696 struct tgsi_full_instruction *tgsi_inst,
697 enum qop op,
698 struct qreg *src, int i);
699 } op_trans[] = {
700 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
701 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
702 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
703 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
704 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
705 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
706 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
707 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
708 [TGSI_OPCODE_SEQ] = { QOP_SEQ, tgsi_to_qir_alu },
709 [TGSI_OPCODE_SNE] = { QOP_SNE, tgsi_to_qir_alu },
710 [TGSI_OPCODE_SGE] = { QOP_SGE, tgsi_to_qir_alu },
711 [TGSI_OPCODE_SLT] = { QOP_SLT, tgsi_to_qir_alu },
712 [TGSI_OPCODE_CMP] = { QOP_CMP, tgsi_to_qir_alu },
713 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
714 [TGSI_OPCODE_DP2] = { 0, tgsi_to_qir_dp2 },
715 [TGSI_OPCODE_DP3] = { 0, tgsi_to_qir_dp3 },
716 [TGSI_OPCODE_DP4] = { 0, tgsi_to_qir_dp4 },
717 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_alu },
718 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_alu },
719 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_alu },
720 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_alu },
721 [TGSI_OPCODE_LIT] = { 0, tgsi_to_qir_lit },
722 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
723 [TGSI_OPCODE_POW] = { 0, tgsi_to_qir_pow },
724 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
725 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
726 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
727 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
728 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
729 };
730 static int asdf = 0;
731 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
732
733 if (tgsi_op == TGSI_OPCODE_END)
734 return;
735
736 struct qreg src_regs[12];
737 for (int s = 0; s < 3; s++) {
738 for (int i = 0; i < 4; i++) {
739 src_regs[4 * s + i] =
740 get_src(trans, &tgsi_inst->Src[s].Register, i);
741 }
742 }
743
744 switch (tgsi_op) {
745 case TGSI_OPCODE_TEX:
746 case TGSI_OPCODE_TXP:
747 case TGSI_OPCODE_TXB:
748 tgsi_to_qir_tex(trans, tgsi_inst,
749 op_trans[tgsi_op].op, src_regs);
750 return;
751 case TGSI_OPCODE_KILL:
752 trans->discard = qir_uniform_f(trans, 1.0);
753 return;
754 case TGSI_OPCODE_KILL_IF:
755 for (int i = 0; i < 4; i++)
756 tgsi_to_qir_kill_if(trans, src_regs, i);
757 return;
758 default:
759 break;
760 }
761
762 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
763 fprintf(stderr, "unknown tgsi inst: ");
764 tgsi_dump_instruction(tgsi_inst, asdf++);
765 fprintf(stderr, "\n");
766 abort();
767 }
768
769 for (int i = 0; i < 4; i++) {
770 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
771 continue;
772
773 struct qreg result;
774
775 result = op_trans[tgsi_op].func(trans, tgsi_inst,
776 op_trans[tgsi_op].op,
777 src_regs, i);
778
779 if (tgsi_inst->Instruction.Saturate) {
780 float low = (tgsi_inst->Instruction.Saturate ==
781 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
782 result = qir_FMAX(c,
783 qir_FMIN(c,
784 result,
785 qir_uniform_f(trans, 1.0)),
786 qir_uniform_f(trans, low));
787 }
788
789 update_dst(trans, tgsi_inst, i, result);
790 }
791 }
792
793 static void
794 parse_tgsi_immediate(struct tgsi_to_qir *trans, struct tgsi_full_immediate *imm)
795 {
796 for (int i = 0; i < 4; i++) {
797 unsigned n = trans->num_consts++;
798 trans->consts[n] = qir_uniform_ui(trans, imm->u[i].Uint);
799 }
800 }
801
802 static struct qreg
803 vc4_blend_channel(struct tgsi_to_qir *trans,
804 struct qreg *dst,
805 struct qreg *src,
806 struct qreg val,
807 unsigned factor,
808 int channel)
809 {
810 struct qcompile *c = trans->c;
811
812 switch(factor) {
813 case PIPE_BLENDFACTOR_ONE:
814 return val;
815 case PIPE_BLENDFACTOR_SRC_COLOR:
816 return qir_FMUL(c, val, src[channel]);
817 case PIPE_BLENDFACTOR_SRC_ALPHA:
818 return qir_FMUL(c, val, src[3]);
819 case PIPE_BLENDFACTOR_DST_ALPHA:
820 return qir_FMUL(c, val, dst[3]);
821 case PIPE_BLENDFACTOR_DST_COLOR:
822 return qir_FMUL(c, val, dst[channel]);
823 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
824 return qir_FMIN(c, src[3], qir_FSUB(c,
825 qir_uniform_f(trans, 1.0),
826 dst[3]));
827 case PIPE_BLENDFACTOR_CONST_COLOR:
828 return qir_FMUL(c, val,
829 get_temp_for_uniform(trans,
830 QUNIFORM_BLEND_CONST_COLOR,
831 channel));
832 case PIPE_BLENDFACTOR_CONST_ALPHA:
833 return qir_FMUL(c, val,
834 get_temp_for_uniform(trans,
835 QUNIFORM_BLEND_CONST_COLOR,
836 3));
837 case PIPE_BLENDFACTOR_ZERO:
838 return qir_uniform_f(trans, 0.0);
839 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
840 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
841 src[channel]));
842 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
843 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
844 src[3]));
845 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
846 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
847 dst[3]));
848 case PIPE_BLENDFACTOR_INV_DST_COLOR:
849 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(trans, 1.0),
850 dst[channel]));
851 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
852 return qir_FMUL(c, val,
853 qir_FSUB(c, qir_uniform_f(trans, 1.0),
854 get_temp_for_uniform(trans,
855 QUNIFORM_BLEND_CONST_COLOR,
856 channel)));
857 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
858 return qir_FMUL(c, val,
859 qir_FSUB(c, qir_uniform_f(trans, 1.0),
860 get_temp_for_uniform(trans,
861 QUNIFORM_BLEND_CONST_COLOR,
862 3)));
863
864 default:
865 case PIPE_BLENDFACTOR_SRC1_COLOR:
866 case PIPE_BLENDFACTOR_SRC1_ALPHA:
867 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
868 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
869 /* Unsupported. */
870 fprintf(stderr, "Unknown blend factor %d\n", factor);
871 return val;
872 }
873 }
874
875 static struct qreg
876 vc4_blend_func(struct tgsi_to_qir *trans,
877 struct qreg src, struct qreg dst,
878 unsigned func)
879 {
880 struct qcompile *c = trans->c;
881
882 switch (func) {
883 case PIPE_BLEND_ADD:
884 return qir_FADD(c, src, dst);
885 case PIPE_BLEND_SUBTRACT:
886 return qir_FSUB(c, src, dst);
887 case PIPE_BLEND_REVERSE_SUBTRACT:
888 return qir_FSUB(c, dst, src);
889 case PIPE_BLEND_MIN:
890 return qir_FMIN(c, src, dst);
891 case PIPE_BLEND_MAX:
892 return qir_FMAX(c, src, dst);
893
894 default:
895 /* Unsupported. */
896 fprintf(stderr, "Unknown blend func %d\n", func);
897 return src;
898
899 }
900 }
901
902 /**
903 * Implements fixed function blending in shader code.
904 *
905 * VC4 doesn't have any hardware support for blending. Instead, you read the
906 * current contents of the destination from the tile buffer after having
907 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
908 * math using your output color and that destination value, and update the
909 * output color appropriately.
910 */
911 static void
912 vc4_blend(struct tgsi_to_qir *trans, struct qreg *result,
913 struct qreg *dst_color, struct qreg *src_color)
914 {
915 struct pipe_rt_blend_state *blend = &trans->fs_key->blend;
916
917 if (!blend->blend_enable) {
918 for (int i = 0; i < 4; i++)
919 result[i] = src_color[i];
920 return;
921 }
922
923 struct qreg src_blend[4], dst_blend[4];
924 for (int i = 0; i < 3; i++) {
925 src_blend[i] = vc4_blend_channel(trans,
926 dst_color, src_color,
927 src_color[i],
928 blend->rgb_src_factor, i);
929 dst_blend[i] = vc4_blend_channel(trans,
930 dst_color, src_color,
931 dst_color[i],
932 blend->rgb_dst_factor, i);
933 }
934 src_blend[3] = vc4_blend_channel(trans,
935 dst_color, src_color,
936 src_color[3],
937 blend->alpha_src_factor, 3);
938 dst_blend[3] = vc4_blend_channel(trans,
939 dst_color, src_color,
940 dst_color[3],
941 blend->alpha_dst_factor, 3);
942
943 for (int i = 0; i < 3; i++) {
944 result[i] = vc4_blend_func(trans,
945 src_blend[i], dst_blend[i],
946 blend->rgb_func);
947 }
948 result[3] = vc4_blend_func(trans,
949 src_blend[3], dst_blend[3],
950 blend->alpha_func);
951 }
952
953 static void
954 emit_frag_end(struct tgsi_to_qir *trans)
955 {
956 struct qcompile *c = trans->c;
957
958 struct qreg src_color[4] = {
959 trans->outputs[0], trans->outputs[1],
960 trans->outputs[2], trans->outputs[3],
961 };
962
963 enum pipe_format color_format = trans->fs_key->color_format;
964 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
965 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
966 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
967 if (trans->fs_key->blend.blend_enable ||
968 trans->fs_key->blend.colormask != 0xf) {
969 qir_emit(c, qir_inst(QOP_TLB_COLOR_READ, c->undef,
970 c->undef, c->undef));
971 for (int i = 0; i < 4; i++)
972 tlb_read_color[i] = qir_R4_UNPACK(c, i);
973 for (int i = 0; i < 4; i++)
974 dst_color[i] = get_swizzled_channel(trans,
975 tlb_read_color,
976 format_swiz[i]);
977 }
978
979 struct qreg blend_color[4];
980 vc4_blend(trans, blend_color, dst_color, src_color);
981
982 /* If the bit isn't set in the color mask, then just return the
983 * original dst color, instead.
984 */
985 for (int i = 0; i < 4; i++) {
986 if (!(trans->fs_key->blend.colormask & (1 << i))) {
987 blend_color[i] = dst_color[i];
988 }
989 }
990
991 /* Debug: Sometimes you're getting a black output and just want to see
992 * if the FS is getting executed at all. Spam magenta into the color
993 * output.
994 */
995 if (0) {
996 blend_color[0] = qir_uniform_f(trans, 1.0);
997 blend_color[1] = qir_uniform_f(trans, 0.0);
998 blend_color[2] = qir_uniform_f(trans, 1.0);
999 blend_color[3] = qir_uniform_f(trans, 0.5);
1000 }
1001
1002 struct qreg swizzled_outputs[4];
1003 for (int i = 0; i < 4; i++) {
1004 swizzled_outputs[i] = get_swizzled_channel(trans, blend_color,
1005 format_swiz[i]);
1006 }
1007
1008 if (trans->discard.file != QFILE_NULL)
1009 qir_TLB_DISCARD_SETUP(c, trans->discard);
1010
1011 if (trans->fs_key->depth_enabled) {
1012 qir_emit(c, qir_inst(QOP_TLB_PASSTHROUGH_Z_WRITE, c->undef,
1013 c->undef, c->undef));
1014 }
1015
1016 bool color_written = false;
1017 for (int i = 0; i < 4; i++) {
1018 if (swizzled_outputs[i].file != QFILE_NULL)
1019 color_written = true;
1020 }
1021
1022 struct qreg packed_color;
1023 if (color_written) {
1024 /* Fill in any undefined colors. The simulator will assertion
1025 * fail if we read something that wasn't written, and I don't
1026 * know what hardware does.
1027 */
1028 for (int i = 0; i < 4; i++) {
1029 if (swizzled_outputs[i].file == QFILE_NULL)
1030 swizzled_outputs[i] = qir_uniform_f(trans, 0.0);
1031 }
1032 packed_color = qir_get_temp(c);
1033 qir_emit(c, qir_inst4(QOP_PACK_COLORS, packed_color,
1034 swizzled_outputs[0],
1035 swizzled_outputs[1],
1036 swizzled_outputs[2],
1037 swizzled_outputs[3]));
1038 } else {
1039 packed_color = qir_uniform_ui(trans, 0);
1040 }
1041
1042 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1043 packed_color, c->undef));
1044 }
1045
1046 static void
1047 emit_scaled_viewport_write(struct tgsi_to_qir *trans, struct qreg rcp_w)
1048 {
1049 struct qcompile *c = trans->c;
1050 struct qreg xyi[2];
1051
1052 for (int i = 0; i < 2; i++) {
1053 struct qreg scale =
1054 add_uniform(trans, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1055
1056 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1057 qir_FMUL(c,
1058 trans->outputs[i],
1059 scale),
1060 rcp_w));
1061 }
1062
1063 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1064 }
1065
1066 static void
1067 emit_zs_write(struct tgsi_to_qir *trans, struct qreg rcp_w)
1068 {
1069 struct qcompile *c = trans->c;
1070
1071 struct qreg zscale = add_uniform(trans, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1072 struct qreg zoffset = add_uniform(trans, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1073
1074 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1075 trans->outputs[2],
1076 zscale),
1077 zoffset),
1078 rcp_w));
1079 }
1080
1081 static void
1082 emit_rcp_wc_write(struct tgsi_to_qir *trans, struct qreg rcp_w)
1083 {
1084 struct qcompile *c = trans->c;
1085
1086 qir_VPM_WRITE(c, rcp_w);
1087 }
1088
1089 static void
1090 emit_vert_end(struct tgsi_to_qir *trans)
1091 {
1092 struct qcompile *c = trans->c;
1093
1094 struct qreg rcp_w = qir_RCP(c, trans->outputs[3]);
1095
1096 emit_scaled_viewport_write(trans, rcp_w);
1097 emit_zs_write(trans, rcp_w);
1098 emit_rcp_wc_write(trans, rcp_w);
1099
1100 for (int i = 4; i < trans->num_outputs; i++) {
1101 qir_VPM_WRITE(c, trans->outputs[i]);
1102 }
1103 }
1104
1105 static void
1106 emit_coord_end(struct tgsi_to_qir *trans)
1107 {
1108 struct qcompile *c = trans->c;
1109
1110 struct qreg rcp_w = qir_RCP(c, trans->outputs[3]);
1111
1112 for (int i = 0; i < 4; i++)
1113 qir_VPM_WRITE(c, trans->outputs[i]);
1114
1115 emit_scaled_viewport_write(trans, rcp_w);
1116 emit_zs_write(trans, rcp_w);
1117 emit_rcp_wc_write(trans, rcp_w);
1118 }
1119
1120 static struct tgsi_to_qir *
1121 vc4_shader_tgsi_to_qir(struct vc4_compiled_shader *shader, enum qstage stage,
1122 struct vc4_key *key)
1123 {
1124 struct tgsi_to_qir *trans = CALLOC_STRUCT(tgsi_to_qir);
1125 struct qcompile *c;
1126 int ret;
1127
1128 c = qir_compile_init();
1129 c->stage = stage;
1130
1131 memset(trans, 0, sizeof(*trans));
1132 /* XXX sizing */
1133 trans->temps = calloc(sizeof(struct qreg), 1024);
1134 trans->inputs = calloc(sizeof(struct qreg), 8 * 4);
1135 trans->outputs = calloc(sizeof(struct qreg), 1024);
1136 trans->uniforms = calloc(sizeof(struct qreg), 1024);
1137 trans->consts = calloc(sizeof(struct qreg), 1024);
1138
1139 trans->uniform_data = calloc(sizeof(uint32_t), 1024);
1140 trans->uniform_contents = calloc(sizeof(enum quniform_contents), 1024);
1141
1142 trans->shader_state = key->shader_state;
1143 trans->c = c;
1144 ret = tgsi_parse_init(&trans->parser, trans->shader_state->tokens);
1145 assert(ret == TGSI_PARSE_OK);
1146
1147 if (vc4_debug & VC4_DEBUG_TGSI) {
1148 fprintf(stderr, "TGSI:\n");
1149 tgsi_dump(trans->shader_state->tokens, 0);
1150 }
1151
1152 trans->key = key;
1153 switch (stage) {
1154 case QSTAGE_FRAG:
1155 trans->fs_key = (struct vc4_fs_key *)key;
1156 if (trans->fs_key->is_points) {
1157 trans->point_x = emit_fragment_varying(trans, 0);
1158 trans->point_y = emit_fragment_varying(trans, 0);
1159 } else if (trans->fs_key->is_lines) {
1160 trans->line_x = emit_fragment_varying(trans, 0);
1161 }
1162 break;
1163 case QSTAGE_VERT:
1164 trans->vs_key = (struct vc4_vs_key *)key;
1165 break;
1166 case QSTAGE_COORD:
1167 trans->vs_key = (struct vc4_vs_key *)key;
1168 break;
1169 }
1170
1171 while (!tgsi_parse_end_of_tokens(&trans->parser)) {
1172 tgsi_parse_token(&trans->parser);
1173
1174 switch (trans->parser.FullToken.Token.Type) {
1175 case TGSI_TOKEN_TYPE_DECLARATION:
1176 emit_tgsi_declaration(trans,
1177 &trans->parser.FullToken.FullDeclaration);
1178 break;
1179
1180 case TGSI_TOKEN_TYPE_INSTRUCTION:
1181 emit_tgsi_instruction(trans,
1182 &trans->parser.FullToken.FullInstruction);
1183 break;
1184
1185 case TGSI_TOKEN_TYPE_IMMEDIATE:
1186 parse_tgsi_immediate(trans,
1187 &trans->parser.FullToken.FullImmediate);
1188 break;
1189 }
1190 }
1191
1192 switch (stage) {
1193 case QSTAGE_FRAG:
1194 emit_frag_end(trans);
1195 break;
1196 case QSTAGE_VERT:
1197 emit_vert_end(trans);
1198 break;
1199 case QSTAGE_COORD:
1200 emit_coord_end(trans);
1201 break;
1202 }
1203
1204 tgsi_parse_free(&trans->parser);
1205 free(trans->temps);
1206
1207 qir_optimize(c);
1208
1209 if (vc4_debug & VC4_DEBUG_QIR) {
1210 fprintf(stderr, "QIR:\n");
1211 qir_dump(c);
1212 }
1213 vc4_generate_code(c);
1214
1215 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1216 fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
1217 qir_get_stage_name(c->stage), c->qpu_inst_count);
1218 fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
1219 qir_get_stage_name(c->stage), trans->num_uniforms);
1220 }
1221
1222 return trans;
1223 }
1224
1225 static void *
1226 vc4_shader_state_create(struct pipe_context *pctx,
1227 const struct pipe_shader_state *cso)
1228 {
1229 struct pipe_shader_state *so = CALLOC_STRUCT(pipe_shader_state);
1230 if (!so)
1231 return NULL;
1232
1233 so->tokens = tgsi_dup_tokens(cso->tokens);
1234
1235 return so;
1236 }
1237
1238 static void
1239 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1240 int shader_index,
1241 struct tgsi_to_qir *trans)
1242 {
1243 int count = trans->num_uniforms;
1244 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1245
1246 uinfo->count = count;
1247 uinfo->data = malloc(count * sizeof(*uinfo->data));
1248 memcpy(uinfo->data, trans->uniform_data,
1249 count * sizeof(*uinfo->data));
1250 uinfo->contents = malloc(count * sizeof(*uinfo->contents));
1251 memcpy(uinfo->contents, trans->uniform_contents,
1252 count * sizeof(*uinfo->contents));
1253 uinfo->num_texture_samples = trans->num_texture_samples;
1254 }
1255
1256 static void
1257 vc4_fs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1258 struct vc4_fs_key *key)
1259 {
1260 struct tgsi_to_qir *trans = vc4_shader_tgsi_to_qir(shader, QSTAGE_FRAG,
1261 &key->base);
1262 shader->num_inputs = trans->c->num_inputs;
1263 copy_uniform_state_to_shader(shader, 0, trans);
1264 shader->bo = vc4_bo_alloc_mem(vc4->screen, trans->c->qpu_insts,
1265 trans->c->qpu_inst_count * sizeof(uint64_t),
1266 "fs_code");
1267
1268 qir_compile_destroy(trans->c);
1269 free(trans);
1270 }
1271
1272 static void
1273 vc4_vs_compile(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1274 struct vc4_vs_key *key)
1275 {
1276 struct tgsi_to_qir *vs_trans = vc4_shader_tgsi_to_qir(shader,
1277 QSTAGE_VERT,
1278 &key->base);
1279 copy_uniform_state_to_shader(shader, 0, vs_trans);
1280
1281 struct tgsi_to_qir *cs_trans = vc4_shader_tgsi_to_qir(shader,
1282 QSTAGE_COORD,
1283 &key->base);
1284 copy_uniform_state_to_shader(shader, 1, cs_trans);
1285
1286 uint32_t vs_size = vs_trans->c->qpu_inst_count * sizeof(uint64_t);
1287 uint32_t cs_size = cs_trans->c->qpu_inst_count * sizeof(uint64_t);
1288 shader->coord_shader_offset = vs_size; /* XXX: alignment? */
1289 shader->bo = vc4_bo_alloc(vc4->screen,
1290 shader->coord_shader_offset + cs_size,
1291 "vs_code");
1292
1293 void *map = vc4_bo_map(shader->bo);
1294 memcpy(map, vs_trans->c->qpu_insts, vs_size);
1295 memcpy(map + shader->coord_shader_offset,
1296 cs_trans->c->qpu_insts, cs_size);
1297
1298 qir_compile_destroy(vs_trans->c);
1299 qir_compile_destroy(cs_trans->c);
1300 }
1301
1302 static void
1303 vc4_setup_shared_key(struct vc4_key *key, struct vc4_texture_stateobj *texstate)
1304 {
1305 for (int i = 0; i < texstate->num_textures; i++) {
1306 struct pipe_sampler_view *sampler = texstate->textures[i];
1307 if (sampler) {
1308 struct pipe_resource *prsc = sampler->texture;
1309 key->tex_format[i] = prsc->format;
1310 }
1311 }
1312 }
1313
1314 static void
1315 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
1316 {
1317 struct vc4_fs_key local_key;
1318 struct vc4_fs_key *key = &local_key;
1319
1320 memset(key, 0, sizeof(*key));
1321 vc4_setup_shared_key(&key->base, &vc4->fragtex);
1322 key->base.shader_state = vc4->prog.bind_fs;
1323 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
1324 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
1325 prim_mode <= PIPE_PRIM_LINE_STRIP);
1326 key->blend = vc4->blend->rt[0];
1327
1328 if (vc4->framebuffer.cbufs[0])
1329 key->color_format = vc4->framebuffer.cbufs[0]->format;
1330
1331 key->depth_enabled = vc4->zsa->base.depth.enabled;
1332
1333 vc4->prog.fs = util_hash_table_get(vc4->fs_cache, key);
1334 if (vc4->prog.fs)
1335 return;
1336
1337 key = malloc(sizeof(*key));
1338 memcpy(key, &local_key, sizeof(*key));
1339
1340 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1341 vc4_fs_compile(vc4, shader, key);
1342 util_hash_table_set(vc4->fs_cache, key, shader);
1343
1344 vc4->prog.fs = shader;
1345 }
1346
1347 static void
1348 vc4_update_compiled_vs(struct vc4_context *vc4)
1349 {
1350 struct vc4_vs_key local_key;
1351 struct vc4_vs_key *key = &local_key;
1352
1353 memset(key, 0, sizeof(*key));
1354 vc4_setup_shared_key(&key->base, &vc4->verttex);
1355 key->base.shader_state = vc4->prog.bind_vs;
1356
1357 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
1358 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
1359
1360 vc4->prog.vs = util_hash_table_get(vc4->vs_cache, key);
1361 if (vc4->prog.vs)
1362 return;
1363
1364 key = malloc(sizeof(*key));
1365 memcpy(key, &local_key, sizeof(*key));
1366
1367 struct vc4_compiled_shader *shader = CALLOC_STRUCT(vc4_compiled_shader);
1368 vc4_vs_compile(vc4, shader, key);
1369 util_hash_table_set(vc4->vs_cache, key, shader);
1370
1371 vc4->prog.vs = shader;
1372 }
1373
1374 void
1375 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
1376 {
1377 vc4_update_compiled_fs(vc4, prim_mode);
1378 vc4_update_compiled_vs(vc4);
1379 }
1380
1381 static unsigned
1382 fs_cache_hash(void *key)
1383 {
1384 return util_hash_crc32(key, sizeof(struct vc4_fs_key));
1385 }
1386
1387 static unsigned
1388 vs_cache_hash(void *key)
1389 {
1390 return util_hash_crc32(key, sizeof(struct vc4_vs_key));
1391 }
1392
1393 static int
1394 fs_cache_compare(void *key1, void *key2)
1395 {
1396 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
1397 }
1398
1399 static int
1400 vs_cache_compare(void *key1, void *key2)
1401 {
1402 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
1403 }
1404
1405 struct delete_state {
1406 struct vc4_context *vc4;
1407 struct pipe_shader_state *shader_state;
1408 };
1409
1410 static enum pipe_error
1411 fs_delete_from_cache(void *in_key, void *in_value, void *data)
1412 {
1413 struct delete_state *del = data;
1414 struct vc4_fs_key *key = in_key;
1415 struct vc4_compiled_shader *shader = in_value;
1416
1417 if (key->base.shader_state == data) {
1418 util_hash_table_remove(del->vc4->fs_cache, key);
1419 vc4_bo_unreference(&shader->bo);
1420 free(shader);
1421 }
1422
1423 return 0;
1424 }
1425
1426 static enum pipe_error
1427 vs_delete_from_cache(void *in_key, void *in_value, void *data)
1428 {
1429 struct delete_state *del = data;
1430 struct vc4_vs_key *key = in_key;
1431 struct vc4_compiled_shader *shader = in_value;
1432
1433 if (key->base.shader_state == data) {
1434 util_hash_table_remove(del->vc4->vs_cache, key);
1435 vc4_bo_unreference(&shader->bo);
1436 free(shader);
1437 }
1438
1439 return 0;
1440 }
1441
1442 static void
1443 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1444 {
1445 struct vc4_context *vc4 = vc4_context(pctx);
1446 struct pipe_shader_state *so = hwcso;
1447 struct delete_state del;
1448
1449 del.vc4 = vc4;
1450 del.shader_state = so;
1451 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
1452 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
1453
1454 free((void *)so->tokens);
1455 free(so);
1456 }
1457
1458 static uint32_t translate_wrap(uint32_t p_wrap)
1459 {
1460 switch (p_wrap) {
1461 case PIPE_TEX_WRAP_REPEAT:
1462 return 0;
1463 case PIPE_TEX_WRAP_CLAMP:
1464 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1465 return 1;
1466 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1467 return 2;
1468 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1469 return 3;
1470 default:
1471 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
1472 assert(!"not reached");
1473 return 0;
1474 }
1475 }
1476
1477 static void
1478 write_texture_p0(struct vc4_context *vc4,
1479 struct vc4_texture_stateobj *texstate,
1480 uint32_t unit)
1481 {
1482 struct pipe_sampler_view *texture = texstate->textures[unit];
1483 struct vc4_resource *rsc = vc4_resource(texture->texture);
1484
1485 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
1486 rsc->slices[0].offset | texture->u.tex.last_level |
1487 ((rsc->vc4_format & 7) << 4));
1488 }
1489
1490 static void
1491 write_texture_p1(struct vc4_context *vc4,
1492 struct vc4_texture_stateobj *texstate,
1493 uint32_t unit)
1494 {
1495 struct pipe_sampler_view *texture = texstate->textures[unit];
1496 struct vc4_resource *rsc = vc4_resource(texture->texture);
1497 struct pipe_sampler_state *sampler = texstate->samplers[unit];
1498 static const uint32_t mipfilter_map[] = {
1499 [PIPE_TEX_MIPFILTER_NEAREST] = 2,
1500 [PIPE_TEX_MIPFILTER_LINEAR] = 4,
1501 [PIPE_TEX_MIPFILTER_NONE] = 0
1502 };
1503 static const uint32_t imgfilter_map[] = {
1504 [PIPE_TEX_FILTER_NEAREST] = 1,
1505 [PIPE_TEX_FILTER_LINEAR] = 0,
1506 };
1507
1508 cl_u32(&vc4->uniforms,
1509 ((rsc->vc4_format >> 4) << 31) |
1510 (texture->texture->height0 << 20) |
1511 (texture->texture->width0 << 8) |
1512 (imgfilter_map[sampler->mag_img_filter] << 7) |
1513 ((imgfilter_map[sampler->min_img_filter] +
1514 mipfilter_map[sampler->min_mip_filter]) << 4) |
1515 (translate_wrap(sampler->wrap_t) << 2) |
1516 (translate_wrap(sampler->wrap_s) << 0));
1517 }
1518
1519 static uint32_t
1520 get_texrect_scale(struct vc4_texture_stateobj *texstate,
1521 enum quniform_contents contents,
1522 uint32_t data)
1523 {
1524 struct pipe_sampler_view *texture = texstate->textures[data];
1525 uint32_t dim;
1526
1527 if (contents == QUNIFORM_TEXRECT_SCALE_X)
1528 dim = texture->texture->width0;
1529 else
1530 dim = texture->texture->height0;
1531
1532 return fui(1.0f / dim);
1533 }
1534
1535 void
1536 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
1537 struct vc4_constbuf_stateobj *cb,
1538 struct vc4_texture_stateobj *texstate,
1539 int shader_index)
1540 {
1541 struct vc4_shader_uniform_info *uinfo = &shader->uniforms[shader_index];
1542 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
1543
1544 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
1545
1546 for (int i = 0; i < uinfo->count; i++) {
1547
1548 switch (uinfo->contents[i]) {
1549 case QUNIFORM_CONSTANT:
1550 cl_u32(&vc4->uniforms, uinfo->data[i]);
1551 break;
1552 case QUNIFORM_UNIFORM:
1553 cl_u32(&vc4->uniforms,
1554 gallium_uniforms[uinfo->data[i]]);
1555 break;
1556 case QUNIFORM_VIEWPORT_X_SCALE:
1557 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
1558 break;
1559 case QUNIFORM_VIEWPORT_Y_SCALE:
1560 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
1561 break;
1562
1563 case QUNIFORM_VIEWPORT_Z_OFFSET:
1564 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
1565 break;
1566 case QUNIFORM_VIEWPORT_Z_SCALE:
1567 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
1568 break;
1569
1570 case QUNIFORM_TEXTURE_CONFIG_P0:
1571 write_texture_p0(vc4, texstate, uinfo->data[i]);
1572 break;
1573
1574 case QUNIFORM_TEXTURE_CONFIG_P1:
1575 write_texture_p1(vc4, texstate, uinfo->data[i]);
1576 break;
1577
1578 case QUNIFORM_TEXRECT_SCALE_X:
1579 case QUNIFORM_TEXRECT_SCALE_Y:
1580 cl_u32(&vc4->uniforms,
1581 get_texrect_scale(texstate,
1582 uinfo->contents[i],
1583 uinfo->data[i]));
1584 break;
1585
1586 case QUNIFORM_BLEND_CONST_COLOR:
1587 cl_f(&vc4->uniforms,
1588 vc4->blend_color.color[uinfo->data[i]]);
1589 break;
1590 }
1591 #if 0
1592 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
1593 fprintf(stderr, "%p/%d: %d: 0x%08x (%f)\n",
1594 shader, shader_index, i, written_val, uif(written_val));
1595 #endif
1596 }
1597 }
1598
1599 static void
1600 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
1601 {
1602 struct vc4_context *vc4 = vc4_context(pctx);
1603 vc4->prog.bind_fs = hwcso;
1604 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
1605 vc4->dirty |= VC4_DIRTY_PROG;
1606 }
1607
1608 static void
1609 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
1610 {
1611 struct vc4_context *vc4 = vc4_context(pctx);
1612 vc4->prog.bind_vs = hwcso;
1613 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
1614 vc4->dirty |= VC4_DIRTY_PROG;
1615 }
1616
1617 void
1618 vc4_program_init(struct pipe_context *pctx)
1619 {
1620 struct vc4_context *vc4 = vc4_context(pctx);
1621
1622 pctx->create_vs_state = vc4_shader_state_create;
1623 pctx->delete_vs_state = vc4_shader_state_delete;
1624
1625 pctx->create_fs_state = vc4_shader_state_create;
1626 pctx->delete_fs_state = vc4_shader_state_delete;
1627
1628 pctx->bind_fs_state = vc4_fp_state_bind;
1629 pctx->bind_vs_state = vc4_vp_state_bind;
1630
1631 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
1632 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
1633 }